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Stanley C. Lorette, 62
BELMONT — Stanley C. Lorette, 62, of 400 Jamestown Road, died at Lakes Region General Hospital, Laconia on Sunday, September 28, 2014.
Mr. Lorette was born September 3, 1952 in Nashua, N.H., the son of the late Jean F. and Geraldine F. (Dunn) Lorette. He resided in San Diego, Calif. and Lynn, Mass. for several years before moving to Belmont, N.H. three months ago. He had been a self-employed carpenter for many years.
Survivors include his son, Micah Ciampi and his wife, Sharon, of Belmont; one grandchild, Jeffrey Lorette of Tilton, three brothers, Richard F. Lorette, Sr. and his wife, Stephanie, of Lowell, Mass., Gerald Lorette, of Lynn, Mass., and Russell Lorette and his wife, Cynthia, of Lynn, Mass. In addition to his parents, Mr. Lorette was predeceased by a grandchild, Nicholas Lorette.
There will be no calling hours or funeral services.
For those who wish, the family suggests that memorial donations be made to The Belmont Police Explorers, P.O. Box 320, Belmont, NH 03220.
Wilkinson-Beane-Simoneau-Paquette Funeral Home & Cremation Services, 164 Pleasant Street, Laconia, N.H. is assisting the family with the arrangements. For more information and to view an online memorial, please go to www.wilkinsonbeane.com.
Last Updated on Monday, 13 October 2014 08:00
Hits: 274
Vera G. Prescott, 71
TILTON — Vera G. (Lepelley) Prescott, 71, a longtime resident of the Tilton-Northfield areas for over 50 years, passed away, surrounded by family on Sunday, October 12, 2014. She was born in Somerville, Mass., September 3, 1943, daughter of the late, John and Margaret (McPhee) Lepelley. She was a graduate of Laconia High School with the class of 1962. A homemaker, Vera also worked for several years as a clerk and bookkeeper at the Park'n Go Market in Northfield. She was a member of the American Legion Ladies Auxiliary, Post # 49 in Northfield and VFW Ladies Auxiliary, Post # 1698 in Franklin. She will be remembered for her caring and outgoing personality.
She was predeceased by a brother, Bradford Lepelley.
Her family includes two daughters, Mary Elizabeth Steady and her husband Matt of Northfield, Pammy Jean McLaughlan of Laconia; two sons, Shannon Eric Prescott and his wife Rachel Luksic of Loudon, Peter William Prescott of Tilton; six grandchildren, Aleasha Marie Martin, Eric James Prescott, Mariah Elizabeth Bolla, Camden Elizabeth Steady, Isabelle, Kathleen Prescott and Nahum George Prescott; brothers: John Lepelley and his wife Josephine of Northfield, Harold Lepelley and his wife Caryl of Valley Springs, Calif.; sisters, Mildred Jameson and her husband Ronald of Tilton, Barbara Chretien and her husband Chris of Franklin, Dorothy Prentiss and her husband Raymond of Belmont; sister-in-law Judith Lepelley of Prince George, Va.; numerous nieces and nephews.
Calling hours will be on Sunday, October 19, 2014 from 11 a.m. to 1 p.m. at the William F. Smart Sr. Memorial Home, Franklin-Tilton Road (584 West Main St.) in Tilton. A graveside service will follow at Park Cemetery in Tilton.
Those wishing may make contributions in Vera's name to the "Activities Fund", Genesis Center, 7 Baldwin St., Franklin, NH 03235.
For more information go to www.smartfuneralhome.com
Last Updated on Monday, 13 October 2014 07:56
Hits: 509
Marjorie H. Norell, 101
NORTHFIELD — Marjorie H. Norell, 101, of 190 Shaker Road, died Sunday, October 12, 2014 at Lakes Region General Hospital.
She was born on September 29, 1913 in Jamestown, N.Y., the daughter of Charles and Grace (Mack) Hale. She was a 1935 graduate of the Women's Christian Association Hospital in Jamestown, N.Y. Marjorie was a Registered Nurse and she worked for 38 years as the Office Nurse for Dr. Hamel in Laconia. She loved stamp collecting and researching family genealogy. Marjorie also enjoyed cross stitching and crafts.
She is survived by one son, William C. Norell of Gilmanton, one daughter, Lois J. Wilson of Laconia, five grandchildren; Michael Glines of Sanbornton, Roger Glines of Tilton, Carol Beck of Gilmanton, Karen Woodward of Northfield and Robert K. Norell of Phoenix, Arizona, 4 great grandchildren and 4 great-great grandchildren. In addition to her parents, she was predeceased by her husband, Robert W. Norell in 1994.
Calling hours will be held from 4 p.m. to 6 p.m. on Thursday, October 16, 2014 at the Wilkinson-Beane-Simoneau-Paquette Funeral Home, 164 Pleasant Street, Laconia, using the Carriage House entrance.
A private graveside service will be held at Smith Meeting House Cemetery, Gilmanton, N.H.
For those who wish, memorial contributions may be made to the charity of one's choice.
Wilkinson-Beane-Simoneau-Paquette Funeral Home & Cremation Services, 164 Pleasant Street, Laconia, N.H. is assisting the family with the arrangements. For more information and to view an online memorial go to www.wilkinsonbeane.com.
Last Updated on Monday, 13 October 2014 07:53
Hits: 235
C. Arthur Rosenberger, 87
CONCORD — C. Arthur Rosenberger, Jr,. 87, died peacefully October 7, 2014 after an illness, his wife of 64 years, Jeanette, by his side.
Born in Sellersville, Penn.,, Art grew up in Tottenville, Staten Island, N.Y. He served in the U.S. Navy during WWII and graduated from Cornell University in 1949 with a degree in Mechanical Engineering.
Art worked for Link Belt Div., FMC Technologies in Penn. for 30 years before retiring to N.H. He was a member of Lions Club International and the Freemasons, and First Congregational Church, U.C.C. of Meredith, N.H., and was active in community life at Havenwood and Heritage Heights in Concord, where he and Jean lived for over 15 years. Art enjoyed singing with his church choir, the HHH Singers, especially their Barbershop Ensemble, and was a past member of the Pemigewasset Choral Society. He loved trains since childhood, and enjoyed international travel and relaxing at the lake with Jean during retirement.
Survivors include his wife Jeanette Gordon Rosenberger; sisters Joyce Slaight of Va., and Dorothy Jensen and husband Howard of Penn.; daughters Susan J. Andersen and husband Ronald of N.H., Aileen Hobaugh and husband William of Penn., and Barbara Lammert of Mass.; 8 grandchildren, 8 great-grandchildren, and many nieces and nephews.
There are no calling hours.
A celebration of Art's life will be held at 2 p.m. Friday, Oct. 24, 2014 at Havenwood Auditorium, 33 Christian Ave., Concord, N.H. In lieu of flowers, memorial contributions may be made to the Havenwood General Fund at the above address.
Mayhew Funeral Homes and Meredith Bay Crematorium are assisting the family with arrangements. To view Chester's on line book of memories go to; www.mayhewfuneralhomes.com
Last Updated on Monday, 13 October 2014 07:50
Hits: 276


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ClassicsOnline Home » Guitar Duo Recital: Athens Guitar Duo - SAY, F. / DUARTE, J. / LIEBERMANN, L. / FRANCAIX, J. (Magellan's Playlist, Vol. 1: On Tour in China)
By DM96074
Good players, odd songlist
"Magellan's Playlist" – On Tour in China – The Athens Guitar Duo - CLAUDIO
The Athens Guitar Duo (Dusty Woodruff and Mathew Anderson) are two talented American musicians whose new recording of 20th century guitar music is oddly titled "Magellan's Playlist". Adding further to the conceptual confusion is the subtitle 'On Tour in China', a strange name for a recording done entirely in England; presumably the repertoire had been performed on their tour of China, though the liner notes never make this clear.
While both gentlemen are more than skilled as guitarists, one might question some of their repertoire choices. By ignoring the standard, Segovia-inspired recital format (i.e. modern compositions mixed with classical, romantic and baroque era pieces) and, instead, featuring an all-contemporary playlist, they've not done themselves nor the listeners any favors.
While the composers whose work is performed do come from divergent backgrounds (US, UK, Turkey, France and China), there is nevertheless a curious sameness to the sound of much of this music. Eventually even the most avant garde music can start to feel predictable; though there are some genuinely beautiful moments in some of these compositions (notably John Duarte's "Greek Suite" and "Evening Dance" by Andrew York"), too much of it sounds like modal noodling around in search of a melodic idea.
While we're at it, what exactly will it take to convince composers and guitarists alike that they should refrain from beating on a beautiful, handmade guitar as though it were a bongo drum?
So, this is a technically well played and recorded grouping of compositions that will probably appeal to guitar students and fans of the avant garde; one can only wonder what the Chinese thought. 7 out of 10
- Oscar O. Veteranomore....
Last Albums Viewed
Guitar Duo Recital: Athens Guitar Duo - SAY, F. / ...

subset: commoncrawl


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BOISE -- U.S. Rep. Mike Simpson is shifting Appropriations Committee assignments, taking on new chairmanship that puts him a key position to help determine funding for facilities including the Department of Energy's Idaho National Laboratory.
Simpson's move Wednesday to become chairman of the Appropriations Subcommittee on Energy and Water Development was precipitated by the death of Rep. Bill Young of Florida.
Young's passing caused a reshuffling of leadership assignments among majority House Republicans.
Previously, Simpson headed the Interior and Environment Appropriations Subcommittee.
In addition to helping set funding for the Department of Energy, Simpson's new committee also helps control the purse strings for the National Nuclear Security Administration and dam managers at the Army Corps of Engineers.
Next May, Simpson faces a challenge from GOP rival Bryan Smith in Idaho's Republican primary.


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Frances Harriet Kelly as Juliet
1 portrait of Frances Harriet Kelly
© National Portrait Gallery, London
Frances Harriet Kelly as Juliet
by Thomas Woolnoth, published by John Cumberland, after Thomas Charles Wageman
stipple engraving, published 1829
5 3/8 in. x 3 1/4 in. (135 mm x 84 mm) paper size
Given by Bonnie and Robert Meech, 2010
Reference Collection
Click on the links below to find out more:
Sitterback to top
- Frances Harriet Kelly (born 1800), Actress. Sitter associated with 5 portraits.
Artistsback to top
- John Cumberland (active 1827-1840), Publisher. Artist associated with 24 portraits.
- Thomas Charles Wageman (1787-1863), Painter, printmaker and draughtsman. Artist associated with 259 portraits, Sitter associated with 2 portraits.
- Thomas Woolnoth (1785-1857), Painter and engraver. Artist associated with 120 portraits.


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Mexicans of Detroit
Wayne State University, Center for Urban Studies, 1979 - Detroit (Mich.) - 89 pages
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Asthma Overview Center - Greenville, NC
Greenville Asthma & Allergy Specialist Doctors for Asthma Overview
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LITTLE ROCK, Ark. (KTHV) - Wrestling legend Dan Gable spoke Tuesday afternoon at the Rotary Club in Little Rock. Dan Gable named the third greatest Athlete of all-time by ESPN.
Gable won 21 consecutive Big Ten titles, coached Iowa to 15 NCAA titles, and is a three time NCAA coach of the year. The Arkansas state tournament set to start this Friday at the Jack Stephens Center.
Read or Share this story: http://on.kthv.com/1gn4A1t


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You will enjoy:
Mobile Massage
Beauty and massage service in Golders Green. Temporary is not available.
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If you purchase an eVoucher you will need to book with the venue directly.
Our old Wahanda Gift Vouchers can still be redeemed at over 3,000 locations. Use them to pay as you would with cash. Please note, the Wahanda Gift Voucher's successor – the Wahanda Gift Card – can only be used for online purchases.


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Hey, ladies. Just to let you all know after this post I plan on taking a break for a week or so. I need some time to replenish my funnies cache. So don't be surprised if you don't see a new Giggles post for a while. Now let's get our laugh on!
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Woohoo! I've never been this early before!
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Shop now and get Free Value Shipping on most orders over $49 to the contiguous 48 states, DC and to all U.S. Military APO/FPO/DPO addresses.
We want to ensure that making a return is as easy and hassle-free as possible! If for any reason you decide that your purchase just isn't for you, simply return the item within 30 days of receipt and we'll cover the cost of return shipping. Learn more about our Return Policy.
Good for any kind of cooking area, the CVA APEX Premium Tool Kit in Soft Case has been designed to be an important tool for virtually every chef. An exceptional kitchen utensil can make your cooking experience much more straight forward. And thanks to the CVA APEX Premium Tool Kit in Soft Case, there's never been a much better time for you to get one of these amazing kitchen tools. This bit of Camping Gear from CVA is made using tough and consistent resources, in an attempt to ensure that you end up with a long lasting and dependable choice for your food preparation requirements. For a very long time, CVA has been popular in the food prep community, and the CVA APEX Premium Tool Kit in Soft Case is the outcome of their time and dedication to ensuring cooks are working with some of the most useful conceivable tools on the market. For a great way to ensure your kitchen is equipped with some of the best gear the kitchen industry is offering, pick the CVA APEX Premium Tool Kit in Soft Case.
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Rejecting Karnataka's charge of boundary violation by Tamil Nadu in the implementation of Hogenakkal drinking water scheme, Tamil Nadu Deputy Chief Minister M. K. Stalin on Monday said the project site is within the State's limits.
"The work on the Rs 1,928 crore Japanese-aided project is being taken up only within Tamil Nadu's territory and there is no violation of the border," Mr. Stalin told reporters at Hogenakkal, 58 km from here, after inspecting the ongoing phase-I work of the scheme.
He said the Karnataka government and other political parties in that State are indulging in a false propaganda on the issue.
"Karnataka has been claiming that the land where the project is being executed belonged to it and also accused Tamil Nadu of deviating from the original plan, saying the scheme would involve 2.5 tmc ft of water, whereas we would draw only 1.4 tmc of Cauvery water for the scheme with the Centre's permission", Mr. Stalin said.
The Hogenakkal scheme would cater to drinking water needs of water-starved Dharmapuri and Krishnagiri districts bordering Karnataka, he said, adding that the project would be completed before the targeted schedule of December 2012.


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Space Escape!
100 - 500 downloadsAdd this app to your listsTweets por @Appszoom
Fly your ship by tilting your phone or tablet, and navigate your way through procedurally generated levels, wrack up high scores, and unlock new ships!
Recently changed in this version
Send bug reports to firstname.lastname@example.com
-Added to Google Play store!
-Fixed bugs causing errors on some devices
-Added player death sound
-Increased rate at which space station is spawned
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Good value and Easy installation
Reviewed By James G (Fairbanks, AK) Reviewed for a 2014 GMC Sierra —4/25/2015 11:21 PM
Received the cover and noticed it was well packed. FedEx is pretty rough on packages here but it had no damage. Unpacked it and had it installed in about a half an hour. I'm very happy with this cover.


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DMV to Internet-less New Yorkers: Get in Line
By Jared Chausow
By Katie Toth
By Elizabeth Flock
City Hid Facts From Feds About Rikers
By Albert Samaha
Flood Wall Street Gets Pepper Sprayed and Arrested
By Anna Merlan
By Jon Campbell
Report Sheds Light on Anti-Muslim Bias
By Jon Campbell
Rikers Island Lawsuits Over Diabetic Care
By Albert Samaha
Re Tall Tales of a Mob Mistress' [October 31November 6]: Please pass on to Tom Robbins my appreciation for his sense of justice in the Lindley DeVecchio case.
I am a 1977 graduate of Southern Methodist University, where I received my degree in broadcast journalism. As time went on, journalism became all about demonizing conservatives and their causes while carrying the rally flag for liberal causes and the Democratic Party, regardless of the facts. I decided I couldn't support that hypocrisy and made my career elsewhere.
Every once in a while, though, someone from the old school steps up to remind us that the principles of journalistic ethics that I was taught 30 years ago came attached with a conscience that demands speaking up for what is right, not what will sell books and newspapers or get your friends elected.
Scott Noris
How can a paper with such important, well-researched, and well-written articles be so sloppy in its presentation to the point that it seems no one checks the pages before sending them to print! How could you possibly pass on the first page of your 'Secret Agent Schmuck' article [Chris Thompson, October 2430] and allow your layout/art directors to use such small white typeor was it gray!on a black background when almost anyone in graphics knows the ultimate result: almost unreadable! What a waste! I strained at the first line and then chucked the whole thing out of sheer anger and frustration. Why couldn't you have simply used black text on a white box inset and made it easy on everyone?! Or did your design team think it wouldn't be artistic enough?! The Voice often does this and for what reason I can't imagine, since the information in the articles is what your readers come back for, not some art director's idea of what looks exciting on the page.
T. Kanter
Re Michael Feingold's review of Die Mommie Die! ['Back to Camp,' October 31November 6]: Thank you for your nice mention of our costumes for Charles Busch ("in drag . . . a lady of infinite aplomb"). It is most appreciated.
Michael Bottari and Ronald Case
I am rather forgiving than bloodthirsty as some others, as Musto's 'Apocalypse Musto' testifies, and every time I leave New York it might be my last seeing this great lovely place definitely. Perhaps, an accident with a subway ticket machine I spent after midnight more than an hour wandering under Times Square around automatic and living staff cashiers while attempting to acquire a valid ticket, was a sure but just single really naughty nuisance fixed already to date.
I know someone there at the "new" Voice thought it would be clever to assume what restaurants famous people may frequent at the end of the world [Robert Sietsema's 'Best of New YorkEats & Treats,' October 1723]. It wasn't. It was the elitist kind of crap that the old Voice would have mocked, and rightfully. Oh, and by the way, if you're going to report on "best ofs in NYC," get real New Yorkers to write them: The United Palace Theatre, a/k/a Rev. Ike's theater, is in Washington Heights, not Harlem. Strictly amateur.
J. Stone
Your 'Diplomats and Guns' article [Adam Weinstein, October 2430], with the subhead "Chinatown mystery: Why did officials from the bloodiest country on earth stock up at a local gun shop?" made it seem as though it was indeed a Chinatown mystery, with maybe some Chinese diplomats involved in gun smuggling. It turned out that "the bloodiest country on earth" was "the Democratic Republic of Congo," and that the "John Joving Gun Shop has been a fixture of the Grand Street block that connects Chinatown and Little Italy since it opened in 1911." You could also easily have made it "Little Italy Saga."
Your editorial dishonesty is amazing. No wonder people are saying the Voice has changed; it is no longer the old Voice.
Timothy Tung
Re Letters [October 2430]: Daniel Goldstein responded to your "Best of New York" issue's award of Best Noble Failure to his organization, Develop Don't Destroy Brooklyn, by claiming that the award was premature. Some of us in Brooklyn agree that Goldstein's group is a failure, but for a completely differentand less noblereason. I view Goldstein and his absolutist views as responsible for the failure of the opposition to Atlantic Yards. While his organization is called Develop Don't Destroy, it should have been called Don't Develop Brooklyn. It never engaged in a serious effort to negotiate the size and bulk of Atlantic Yards and permit a reasonable development of that long-neglected neighborhood to go forward. There's no way to know whether a good-faith effort to negotiate a scaled-back version of Atlantic Yards might have succeeded, but Goldstein's absolutist opposition made serious negotiation impossible. You might as well blame him for the fact that Atlantic Yards will proceed as planned, without any real community input.
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Dave Hartmann
Original recipe yields 6 servings
Amount per serving ({{servings}} total)
Based on a 2,000 calorie diet
Ready In
I sprinkled a little of the Kraft 3-cheese blend (parmesan, romano, & something)while it was grilling. Yummy without killing the taste of the vegetable.
I put all of the slices in a baggie and just added enough dressing to lightly cover them. So easy and great.


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Barely two weeks after 21-year-old engineering student Tushar Jadhav died following a brutal attack inside a moving train in Ghansoli, his father Arun passed away in a private hospital in Mulund on Tuesday evening.
Jadhav, whose kidneys had stopped functioning, had been on dialysis for the past couple of months. His condition deteriorated after Tushar's death and he was admitted to the hospital on Monday. He worked with a sales tax office in Thane.
Tushar, a third-year student of Rajendra Mane College of Engineering and Technology in Ratnagiri, was attacked by two people when he was returning home after writing his last paper on June 12. He was stabbed seven times with a knife and died on his way to hospital.
Talking to dna after his son's death, Arun had said, "Tushar was my only son, the only hope for my future. But he too has been killed. I have donated his eyes to the eye bank of Thane Civil Hospital. At least, some poor patient will use his eyes and remember my son."


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Woman Arrested For Not Returning Movie Rental
By editor
Originally published on Tue February 18, 2014 8:03 am
Good morning. I'm David Greene. Kayla Finley is finally paying for her crime. Back in 2005, the South Carolina woman rented a movie. It was "Monster-In-Law," starring Jane Fonda and JLo on VHS. She never returned it. The movie store is now closed but there was still a warrant out for her arrest and police nabbed her last week. She spent a night in jail. Given the reviews of the movie, she should've been given time served for the 101 minutes she spent watching that film. It's MORNING EDITION. Transcript provided by NPR, Copyright NPR.


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Man drowns in Looc
A MAN drowned last Monday afternoon in Cabahug wharf in barangay Looc, Mandaue City.
The body of Roberto Capiznon, 22, of barangay Mantuyong, was found under a barge moored at the wharf.
His cousins and friends called the police after he went under at past 2 p.m.
His body was found three hours later floating under the barge./Reporter Jucell Marie M. Cuyos
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The Corner Alley features 16 lanes of upscale bowling action. Designed for people who want to have fun and bowl at all skill levels, guests can live Life In The Fast Lane. The state-of-the-art, custom designed scoring system delivers attention-grabbing multimedia content. Satellite music gets our crowd pumping, but our myTouchTunes Jukebox let's you be the DJ. Download the iPhone or Droid app and play your music from your smartphone while earning credits for free music play!
Hungry or thirsty while you bowl? Experienced servers come to you for lane-side service, filling your food and beverage needs.
Rates for Open Bowling
- Sunday - Thursday: $4.25 per game +$3.00 Shoe Rental per person
- Friday - Saturday (4pm till close ): Walk in guest: $35.00 per hour per lane (up to 6 guest). Reservations: $50 per lane per hour (this Guarantees the lane)
- Happy Hour: Monday through Friday 2-7 PM Free Shoe Rental
Reserving a Lane
- Reservation are taken beginning Monday at noon for the remainder of the week.
- The Cost is $50 per lane, per hour, this includes tax and shoes for up to 6 people.
- Bowling Reservations are taken by the hour only.
- You can Reserve up to 2 hours maximum.
- 6 people on 1 lane.
- Can only Reserve 4 lanes per reservation.
- The Corner Alley holds Reservations for 15 minutes, then releases the reservation.
- A reservation is a guarantee, thus any promotions that day or during your time period are not applicable.
In order to ensure proper service for all of our guests, on event and weekend nights we will provide one check per lane. Thank you for your understanding.
Please Note: Groups of 15 or larger wishing to book through our Group Sales Department will be able to make their reservations as far in advance as they wish with the purchase of a food and beverage package. Groups size 14 or smaller will be able to book their lanes according to the Reservation Policy listed above. The Corner Alley frequently hosts large groups which may affect availability for bowling or dining. We strongly recommend reservations when possible.
We are certified by the United States Bowling Congress.


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"[We were] happy cause wow, we did it, and sad because it's our last year," said Brem. "I won't miss the cold nights though, not at all."
Senior Kaleb Coffie, tuba player, also expressed his happiness for winning the competition.
Both agreed they joined band because all of their friends were in it and they have become like a family with fellow band members.
"I just have a lot of friends in band and it makes it enjoyable," said Coffie.
Brem agreed and said, "Pretty much all of my friends are in band."
During the last two weeks of August the band practiced intensely and in September through October the band meets from Monday to Wednesday, 6 to 9 p.m. and Saturday from 1 p.m. to 5 p.m. Brem said sometimes the day of competitions for the band stretches from 5 a.m. to midnight.
In all of their smaller competitions, Coffie said they came in first place except for one where they came in second; so being on top is nothing new to the band.
"The other [competitions] are like stepping stones to get to this big competitions at the end to see how you do statewide instead of just the little competitions," said Brem.
Getting out on the field of the Carrier Dome was a exciting and daunting experience, said Brem, but after the excitement begins to settle for a little bit the focus goes right back to trying to win.
"You just focus for those seven minutes and all that practice and all that time we did all that practice for seven and a half minutes," said Brem.""
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Mirkarimi v. Nevada Property 1 LLC et al
|Sasan Mirkarimi
|Nevada Property 1 LLC and Does 1-50
|Case Number:
|August 31, 2012
|California Southern District Court
|San Diego Office
|San Diego
|Referring Judge:
|David H. Bartick
|Presiding Judge:
|Barry Ted Moskowitz
|Nature of Suit:
|Other Contract
|Cause of Action:
|Jury Demanded By:
Available Case Documents
The following documents for this case are available for you to view or download:
|Date Filed
|Document Text
|July 15, 2013
|ORDER Denying as moot Defendant's 7 Motion to Dismiss for Failure to State a Claim; Denying 15 Motion to Dismiss; and Denying 15 Motion to strike class action allegations without prejudice. Defendant has twenty (20) days from the filing of this order to answer Plaintiff's First Amended Complaint. Signed by Judge Barry Ted Moskowitz on 7/15/2013. (rlu)
|October 22, 2014
|ORDER Regarding 75 Joint Motion for Determination of Discovery Dispute. It is Ordered that Plaintiff's motion to compel is Granted. Defendant shall produce all documents responsive to Plaintiff's outstanding Requests for Production for wh ich Defendant agreed to produce documents, including RFP Nos. 5, 18-20, 35, 36, 44, 47, 48, 50, 122-124, 128, and 133-136, and shall provide supplemental responses to Interrogatories Nos. 17 and 25, and RFP No. 128 on or before October 31, 2014. Signed by Magistrate Judge David H. Bartick on 10/22/2014. (rlu)
|November 18, 2014
|ORDER Regarding Plaintiff's Ex Parte Application for Discovery Orders. It is Ordered that Plaintiff's motion for leave to conduct additional discovery is Granted, in part. Plaintiff may take up to 5 additional depositions. Plaintiff may also propound up to 15 additional interrogatories. Defendant shall respond to the interrogatories within 15 days from the date of service of the interrogatories. Signed by Magistrate Judge David H. Bartick on 11/18/14.(rlu)
|November 21, 2014
|ORDER Resolving 78 Joint Motion for Determination of Discovery Dispute. It is Ordered that the temporary stay on communications with putative class members is lifted. It is further Ordered that before Plaintiff may mail any questionnaire to the putative class members, Plaintiff must submit the proposed questionnaire to the Court for an in camera review. Signed by Magistrate Judge David H. Bartick on 11/21/14. (rlu)
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Cannondale CAAD8 5 105 - 2014
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Cannondale Trail SL 29er 3 - 2014
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From the Publisher'Anthony Elliott is quickly emerging as a one-person industry, intent in all his writings to demonstrate both the relevance and the importance of psychoanalytic theory for social analysis.' - Thesis Eleven
'Anthony Elliott has once again provided a lucid and critical examination of the relationship between psychoanalysis and social theory. While many writers are still catching up with Lacan's work, Elliott explains the major advances to be found in post-Lacanian theory, and shows how it offers a new view of subjectivity and the 'imagination' attuned to the complexities of contemporary social life.' - Stephen Frosh, Birkbeck College, London
'Comprehensive and challenging, Social Theory Since Freud explores major developments in western thought since Freud mapped out the unconscious. It is an authoritative synopsis of the Frankfurt School, Castoriadis, Lacan, Laplanche and Kristeva. In pursuing the legacy of Freud, Anthony Elliott shows convincingly that the imagination is central to rethinking the relationship between social theory and psychoanalysis.' - Bryan Turner, Cambridge University


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Looking at a boat tomorrow
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Tim R.
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Re: Looking at a boat tomorrow
Originally Posted by
in my opinion (and keep in mind I am prob the least experienced here) on a boat that costs less then 4 grand I would not get a survey. take it for a sail, if it works and looks ok and 4 large won't hurt your wallet then buy it. I would survey more spendy boats but not something this inexpensive. Again take it for what it's worth from inexperienced sailor. I make no claims to know more then others here, just my opinion when spending my money.
Unless the OP is an experienced boat owner with skills, A survey is a good idea for safety reasons. $4k may not be a lot of money to lose by ones life is certainly worth something.
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An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.
1. In a data processing system including a central processor having an addressable read/write memory, a plurality of addressable working registers, an arithmetic and logical processing unit, a first internal bus, a second internal bus, and an instruction register said data processing system further including a plurality of external input/output devices connectable to said central processor by way of a bidirectional input/output (I/O) bus containing a plurality of data lines and a plurality of control lines, the improvement which comprises:
an input/output port control subsystem including port control means in said central processor, for controlling bidirectional data flow over said data lines between selected ones of said external devices and said processor, by the controllable assignment of said data and control lines to perform the necessary transfer of input/output service requests, addresses, commands and data, said subsystem including
adaptor means for connecting individual external devices to said bidirectional bus including control means for receiving device commands from the port control means and for transferring said commands between said external devices and said port control means,
said adaptor means further including a first command word register means for storing lower priority commands utilized for controlling the operation of said external devices and a second command word register means for storing commands to be transferred to said central processor on a high priority basis, means for initiating a high priority microprogram sequence in response to a command in said second command word register, means for sequentially gating a predetermined block of data between said central processor and a particular external device without checking for pending service requests between each read transfer operation and means for returning control to normal interrupt procedures upon the completion of the transmission of said block of data;
said port control means further including a first control driver gate means for selectively connecting said I/O data lines to said first internal bus to effect a data transfer in a first direction,
a second control driver gate means for selectively connecting said I/O data lines to said second internal bus to effect data transfer in the opposite direction,
microprogram sequence control means including a series of selectively accessible microprogram sequences stored in said central processor and means responsive to a particular I/O service request for accessing and decoding a particular microprogram sequence to perform a desired I/O operation, said, means responsive further including,
means operative under the control of said microprogram sequences accessed in response to service commands received from either the processor or the external devices for selectively actuating either of said control driver gates and selecting inputs to and outputs from said addressable working registers and memory in order to perform specified input/output operations.
2. A data processing system as set forth in claim 1, wherein said system includes a plurality of further adaptors connected in parallel to said I/O bus and wherein each adaptor has at least one external device connected thereto,
means in said input/output port control subsystem for selectively addressing a particular adaptor and external device connected thereto, when a service request relating to said external device is detected by the system,
each said adaptor further including an interrupt control mechanism including setable latch circuit means for each external device connected to said adaptor wherein an interrupt request from a given external device will cause a particular latch to be set, and means for periodically monitoring said latches to determine which external device is to receive service at a particular time.
In computer systems in general and in small systems in particular, it is desirable to reduce the total amount of hardware required for the system consistent with some specified level of machine performance. Data lines connecting various external devices such as keyboard terminals, CRT displays, credit card readers, etc., to a central processor would normally require separate I/O pin connections for each data line. In modern computers, large scale integrated circuitry (LSI) is widely used and, as is well known, these circuit modules are limited in the number of external circuit connections or pins which can be placed on an LSI module. Hence, by utilizing the same data lines for both input and output, the number of pins required is cut in half. In large, high speed computing systems, it generally has not been feasible to utilize the same data lines for both reading data into and out of the system, as many operations are held up pending the termination of an existing operation. While such waiting is necessary with a central memory or other shared functional unit, it is not so critical within the CPU as modern computers have extremely high speed memory circuits, etc., capable of performing required operations in extremely short periods of time. However, with smaller lower speed computers where both cost and manufacturing feasibility are primary factors, and time is somewhat secondary, it becomes possible to consider bidirectional data lines or half-duplex type of operations.
With the advent of modern integrated circuits and micro electronic technology, it has been possible to construct relatively small inexpensive computers utilizing separate source and destination buses within the computers which allows for considerably higher speed operations without greatly increasing the cost of construction. However, in the past, such two bus computers required large numbers of terminal pins for connecting the computer to both the input and output data lines. As stated previously, this causes severe pin connection problems when LSI is used in the host computer. It is the purpose of the present invention to provide a solution to the terminal or pin connection problem.
It has been found that satisfactory overall system performance is possible with a bidirectional data bus connected to a small two separate internal bus computer system by providing internal gating and control means for selectively connecting the I/O bus to the source and destination bus of said computer utilizing internal control circuitry together with a special adaptor connecting I/O devices to the I/O bus and for effecting requisite I/O control.
It has been further found that the requisite control functions can be efficiently and inexpensively performed by the use of micro programs stored in a read only memory having special decoding and control circuitry for effecting the desired gating operations.
It is accordingly a primary object of the present invention to provide an input output port control subsystem for allowing the connection of a bidirectional data I/O bus to a central computing system having separate source and destination buses.
It is a further object of the invention to provide such a subsystem whose operation is controlled by a set of microinstructions stored in the central computer's microprogram memory.
It is yet a further object to provide such a subsystem including two primary gates for gating data from the system destination bus out to the bidirectional I/O bus and for connecting the data from the bidirectional I/O bus to the system source bus.
It is a still further object of the invention to provide such a subsystem wherein said two primary gates are controlled by decoding circuitry connected to the output of said microprogram memory, the appropriate instructions of which are accessed under cycle steal or programmed I/O modes of operation.
These and other objects of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings.
FIG. 1 comprises a high level functional block diagram illustrating the overall configuration of the present I/O port control subsystem with a plurality of adaptors attached to the bidirectional I/O bus wherein a plurality of separate devices are shown attached to each adaptor.
FIG. 2 comprises an organizational drawing for FIGS. 2A and 2B.
FIGS. 2A and 2B comprise a combination logical schematic and functional block diagram of the preferred embodiment of the present invention showing the details of the hardware necessary to effect the present input/output port control subsystem.
The objects of the present invention are accomplished in general by a data processing system comprising a plurality of input-output devices connected to a central processor by a bus containing a plurality of bidirectional data lines and a plurality of control lines, means for effecting the bidirectional operation of said data lines between selected ones of said devices and said controller by controllable assignment of the data function of said data lines to perform addressing and transfer of commands and data comprising a first controlled driver gate for selectively connecting said I/O data lines to a source bus internal to said central processor to provide selected inputs to functional units therein. A second controlled driver gate is provided for selectively connecting a destination bus internal to said processor to said I/O data lines, said internal functional unit outputs being selectively connected to said destination bus. Input/output control subsystem means are provided internal to said processor responsive to I/O programmed instructions or external device generated interrupts or cycle steal requests for operating said driver gates and the selection of said inputs to and outputs from said functional units of said system and said external devices to perform the desired I/O operations.
The present input-output port control subsystem concept may be incorporated in at least two data bus central computing system and it is to be understood that the present invention is limited thereto. Accordingly, only as much detail of the general hardware of the central system as is needed will be shown and discussed. These include, as stated before, a read only memory utilized as a microprogram store in the present embodiment and associated decoding circuitry therefor as well as the central system memory from and into which I/O data is read as well as the source and destination buses.
The disclosed embodiment illustrates a terminal driven system. In such a system, the various terminals, such as keyboards, credit card readers, etc., actually initiate operation of the system by signalling interrupts or requests for cycle steal at predetermined priority levels.
The present I/O port control interface operates in program controlled mode or in cycle steal mode wherein it is controlled by hardware in the external devices which can use memory faster than normal programmed I/O.
The following is a general overview of the system organization referring to FIG. 1 in which the central memory 10 is shown connected generally to the central processor 12 which, should be clearly understood, defines a two internal data bus system having separate source and destination buses. At the lower portion of block 12, the I/O port control 14 is indicated as being a portion of the central processor, since the I/O port control will use the system microprogram store which in the disclosed embodiment is a read only store (ROS). Similarly, the output from the main ROS decoder and control unit will cause the requisite control latches of the present port control subsystem to be brought up to set the various tag lines going out to the external device adaptor units 16 through which the external devices 18 are connected to the main data bus 20. Additionally, a control bus 22 is shown connected between the I/O port control 14 and the various adaptors 16. As will be explained subsequently with respect to the description of FIG. 2, this control bus comprises a series of fixed lines going to the various adaptors in parallel. In the present embodiment, these are unidirectional lines and are not operated bidirectionally as with the data bus 20.
By use of the disclosed system, the I/O port control allows the central processor to communicate with designated devices and certain devices to communicate with the central processor thru the necessary gating circuits over the I/O data bus onto the source bus or from the destination bus onto the data bus as required by a particular operation being processed. It also includes controls required to prevent conflicts from occurring, i.e., one device trying to transmit while another one is trying to transmit or when the processor is attempting to communicate with a device.
Before proceeding with a detailed description of the operation of the specifically disclosed functional hardware elements shown in the block diagram of FIG. 2, there follows a general description of the operation of the system.
The objective of the present I/O port control design is to accomplish the following two functions. The first is to perform the control of I/O in an asynchronous manner. The second is to allow sharing of I/O control mechanisms and the I/O bus for programmed I/O, UC cycle steal, and interrupt signalling.
FIGS. 2 (2A and 2B) shows the I/O port control circuitry of the central processor and the I/O bus with one adaptor attached. The I/O bus contains 16 bidirectional lines, a high byte and a low byte, each 8 bits wide. When the system is not performing a cycle steal or programmed I/O operation, the low byte of the I/O bus is used to send interrupt requests from the adaptor to the central processor. When the I/O bus is being sampled for interrupts by the system, the TD tag is used to inhibit changing the interrupt request latches during the sampling interval. In order to begin a programmed I/O instruction or cycle steal operation, the I/O tag is raised early in these operations to free the I/O bus (i.e., the interrupt requests are inhibited).
The central processor is a microcoded machine in which each operation has a beginning address (instruction decode) in ROS which can only be followed by a fixed number of other ROS patterns until the instruction is completed. The ROS REG output sends out control signals over the tag lines within the machine for fixed intervals of time except for I/O and cycle steal operations. For these operations, the set ROS REG line is inhibited from gating the ROS REG out within specified patterns until certain conditions are satisfied by the adaptor. This allows these operations to be carried out faster by faster adaptors and slower by slower adaptors. There is a limit to how long the system will wait for a response from an adaptor and when this time limit is reached, the central processor will go into its machine check stop sequence (MCK). The halt tag will be raised to signal the adaptor when this occurs. This is a diagnostic which detects a malfunction of some sort and may do any one of many things including something as simple as a `retry` of the last operation.
The central processor can operate over the I/O bus with either one byte or two bytes of data depending on the type of device and/or the operation. There are two programmed I/O instructions: IO and IOH. IO can be used to read or write bytes of data to a byte or halfword (HW) device while IOH can only be used with a HW device. An IO write operation takes data out of memory and sends it to the adaptor over the IO bus. An IO read takes data from the IO bus and stores it in memory.
In both instructions, IO and IOH it is necessary to send the address of the device and the command (read or write) to the external device before data is read or written. The address and command are each byte information and therefore must be sent individually to byte devices whereas they can be sent at the same time for HW devices. As an example of how the procedure works, assume an IO write instruction to a byte device is required. The instruction decode sends out the initial ROS pattern for the IO instruction. During this initial pattern the I/O and byte tags are activated to free the I/O bus and the gate to the IO bus from the buffer output is opened. The contents of memory at a location specified by the instruction are being sent out of memory to the buffer and the output of the buffer is connected to the I/O bus. The memory content has the address of the device on the high byte (bits 0-7) and the command on the low byte (bits 8-15). The adaptor responds to the I/O tag by dropping VB (valid byte-byte adaptor) to signal that interrupts have been removed from the I/O bus and that the adaptor is a byte adaptor. The central processor then raises the TA tag to tell the adaptor that the address of a device is on the high byte of the I/O bus (and also that the command is on the low byte for a HW adaptor). The adaptor then responds by raising VB to indicate that a valid address was transmitted by the central processor. This return of valid resets the TA tag and now the command is transferred to the high byte out of the buffer and out to the I/O bus. Also, the adaptor must deactivate VB as a result of the TA tag being reset. When VB is deactivated, the TC tag is raised to tell the adaptor that the command is on the high byte of the I/O bus. VB is activated to tell the central processor that the command has been stored in the command REG and that TC tag can be reset. Bit 15 out of the buffer is checked to see whether the command is read or write so that the correct microcode pattern is decoded.
As a result of the TC tag being reset, VB is deactivated. Now data is read from a memory location specified by the instruction decode and is sent through the buffer out to the high byte of the I/O bus. TD tag can be raised after VB is deactivated to tell the adaptor that the data is on the high byte of the I/O bus. When the data is stored in the `data in` REG by the adaptor, VB is activated to signal the central processor that the adaptor has the data. Next the I/O and byte tags are reset to signal that the I/O instruction is completed and the IRP line if used is deactivated to signal that interrupts are back on the bus.
For HW devices, the TC tag is not required since the device can read the address and command at the same time. Timeout can only occur while the central processor is waiting for a response from VB tag, VH tag, IRP tag, and EOC tag. The exception line is used during cycle steal to inhibit timeout.
The only extra lines required to accomplish cycle steal are CS request, CSG tag, and EOC tag. Cycle steal is initiated by the adaptor and therefore does not require an address. Instead a control word is sent from the adaptor to the central processor. This control word contains information to tell the central processor whether a read or write should be done, and a starting address for the address control, and for direct byte transfer, which byte to begin reading or writing. The purpose of cycle steal is to read or write many bytes or halfwords of data at a rapid rate. The cycle steal request line can be activated at any time, but is ignored until the completion of the present instruction being executed in the central processor. When this instruction is finished, the central processor is ready to begin cycle steal and the cycle steal initial ROS pattern causes the I/O tag to activate. This frees the I/O bus and a valid (byte or HW) must deactivate to indicate this is done. Then the central processor raises cycle steal grant (CSG tag) to indicate it is ready to receive the control word. The valid tag (VB or VH) must be returned to indicate that the control word is on the bus.
After the initial address is stored in the address control, the address is updated by one for byte data transfers or by two for HW data transfers until EOC tag (end of chain) activates to signal that the adaptor has completed cycle steal. Before this, the TD tag was used in the same manner as programmed I/O for data. The end of cycle steal is similar to the end of programmed I/O. Another cycle steal request can follow a cycle steal operation or the central processor will return to its next instruction.
The AC latches for input tags from the adaptor to the central processor are used to prevent the central processor from responding to noise pulses which might appear on these lines.
In summary, a fairly extensive description has been given to show how two objectives have been accomplished. The diagram only shows one adaptor for simplicity which can have several devices attached, but the machine can have several adaptors each with several devices and therefore it is necessary for a particular system configuration to determine how it will use the address information.
Referring to FIG. 2 (FIGS. 2A and 2B), the individual blocks will be described relative to the functions performed thereby. In the upper portion of FIG. 2A, there appears the source and destination bus of the host computer system. Similarly, the memory 10 is the same as that shown in FIG. 1. The address control 30 performs conventional addressing routines and includes the memory address register. It additionally has features for doing indexing operations. The cycle steal CW buffer 32 is a conventional control word buffer wherein this control word is transferred from the cycle steal CW buffer 62 in the adaptor and utilized to control the cycle steal operations.
The buffer 34 is a conventional memory buffer for receiving data from and storing data in the memory 10. Interrupt mechanism 36 receives and analyzes interrupt requests and contains the necessary logic controls for selecting the interrupt request with the highest priority. It will be readily understood that there are many types of interrupt systems available in the computer arts and could be as simple as a prewired interrupt priority wherein particular devices will have priority over all other devices or some other more complex scheme. The type envisioned in the present system is a simple prewired priority wherein the raising of particular data lines during an interrupt call indicates priority designations of particular external device connected to the data bus through its particular adaptor.
The gates 38 and 40 are the primary data gates for transferring data from the destination bus to the I/O bus or from the I/O bus to the source bus respectively. The instruction decoder 42 is a conventional instruction decoder connected to the instruction register (not shown) and as far as the present invention is concerned only those functions applying to the present invention are shown. The line shown going from the instruction decoder 42 to the ROS address decoder 44 is active when a programmed I/O operation is called for. This, as will be apparent from the subsequent description, selects a particular beginning address in the ROS which address is accessed and subsequent commands are read out until the particular I/O operation called for is completed. The ROS address decoder is similarly activated when a cycle steal type of operation is required. The ROS 46 is completely conventional and reads out into the ROS register 48. The output of this register goes into the ROS decoder 50, the output lines of which in turn are connected to the block marked latches 52 which will raise or lower one or more of the output tag lines from this block. The two output lines from block 50 labelled Set and Reset would set or reset all of the latches whereas the intermediate lines, indicated by the dotted lines, set selected ones of the tag lines which in turn are fed into the adaptor control block 54. The adaptor control block operates in a conventional manner to perform the usual handshaking operations between the external devices and the central processor and also contains the controls to set up the cycle steal mode of operation in the preferred embodiment disclosed herein. In other words, when one of the tag lines comes up from the latches 52, the adaptor control signals that a certain operation is to be performed by the external device and when this operation has been performed, the device notifies the adaptor control and the VH or VB tag is raised indicating the particular operation has been performed and notifies the ROS control 56 that the next instruction is needed. The adaptor control block consists essentially of latches and timing circuitry which accept and pass on the various control signals from the control system and the devices, and automatically provides for the requisite time to complete the called for operations. The two blocks 58 and 60 at the bottom of FIG. 2A, designated the AC latches, are for the purpose of holding their outputs up when a specific signal is received on the one of the four tag lines going into these blocks from the adaptor control and are designed such that random noise appearing on these lines cannot cause erroneous operation of the ROS control 56.
As will be apparent from the subsequent description, the presently disclosed system includes an operation called cycle steal wherein a particular device requests a rather lengthy chain of data from memory at consecutive address locations. Under the cycle steal operation, it is not required that each data word transferred from memory go through a complete access request but instead the complete chain of data is either read into or out of memory until the chain is completed at which point the cycle steal operation is terminated and the system returns presumably to standard programmed I/O. This will however be discussed in further detail subsequently. The cycle steal CW buffer 62 comprises part of the cycle steal mechanism just mentioned and is utilized during the cycle steal operation.
The address decoder 64 stores an address and decodes the address to identify the particular device which is being addressed by the system. An output line goes from the address decoder to each individual device indicating that it has been selected. The command register 66 is for the purpose of storing a particular command for the devices. The command may include a read/write particular command, goes thru the adaptor control 54 and then to the data in and data out registers 68 and 70 which could either be located in the individual external devices or be common to the adaptor. However as will be apparent a single pair of such registers could be utilized with appropriate gating utilized in conjuction with the address decoder so that any given device could utilize these data registers and thus avoid a duplication. The command may include a number of other device dependent operations, which may or may not include data transfer per se. However, for the purpose of explaining the overall operation of the present I/O port control subsystem, the read/write operation is the most general. The dotted block marked 72 comprises the interrupt request mechanism where it will be noted that the gates 74 will be energized when a particular external device requests an interrupt from the system. It will further be noted that there are as many of the gates 74 as there are devices. The gates 74 feed into the interrupt request latches 76 for the obvious purpose of holding the lines up for a predetermined time. It should be noted that one or more of the interrupt request latches could be set at a given time and in accordance with the present embodiment a particular one of the data lines in the I/O bus is energized. Thereby, the system will decide which of the external devices is to receive service at a particular time.
The preceding description of the detailed hardware of FIGS. 2A and 2B clearly describes the particular functions performed by each of the disclosed blocks. The following description of the operation of this system and the control line table will more clearly set forth the interrupt operation and cycle steal sequences included therein.
The following table shows the function of each of the control lines which directly connect the adaptor devices with the central processor. These lines are dedicated to one way communication in the disclosed embodiment although they could be made bidirectional with the addition of appropriate program support and hardware gating controls. However, the disclosed embodiment is preferred. The direction of the signal flow on these lines is clearly shown in the table (i.e., central processor to adaptor or vice versa).
It should be understood that the circuitry of the adaptor controls are configured in a conventional manner so that various operations may occur on either the rise or fall of the control tag and valid lines. This is conventionally accomplished by taking control from either the `set` or `reset` side of a flip-flop.
__________________________________________________________________________TABLE OF CONTROL LINE FUNCTIONS__________________________________________________________________________Lines Functions Served__________________________________________________________________________I/O TAG (Central Processor Frees I/O bus of signals from→ Adaptor) interrupt request latches. Opens gate from destination bus to I/O bus for "write" Indicates I/O instruction completed. Indicates starting of CS instruction.BYTE TAG (Central Processor Indicates byte operation.→ Adaptor)TA TAG (Central Processor Tells adaptor that high data→ Adaptor) byte contains an address (and that command is on low byte for a HW adaptor). Indicates that command is shifted to "high byte" data lines (for a byte adaptor.TC TAG (Central Processor Indicates command is on "high→ Adaptor) byte". Indicates command is stored. (Not required for HW adaptors which can read address and command at same line.)TD TAG (Central Processor Inhibits changing of interrupt→ Adaptor) request latches in adaptor during sampling of interrupt lines. Indicates data is on high byte. In cycle steal, indicates data is on bus.HALT TAG (Central Processor Tells adaptor that the count→ Adaptor) limit has been exceeded for VB or VH or IRP or EOC response from adaptor, or internal latch (any MACH CHK that would cause a level of interrupt).IRP TAG (Adaptor → Central Indicates that interrupts areProcessor) on bus.VH TAG (Adaptor → Central Same as VB for a half word device.Processor)VB TAG (Adaptor → Central Indicates interrupts are removedProcessor) and device is a byte device. Indicates receipt of a valid address. Indicates command stored in command register 66. Indicates adaptor has stored data. In cycle steal, indicates that control word is on I/O bus.CS REQ (Adaptor → Central Indicates a request for cycleProcessor) steal. (Initiated by adaptor - ignored until an instruction has been completed)CSG TAG (Central Processor Indicates processor is ready to→ Adaptor) receive cycle steal control word (CSCW).EOC TAG (Adaptor → Central Indicates end of cycle stealProcessor) chain.EXC (Adaptor → Central Inhibits timeout during CS.Processor)__________________________________________________________________________
__________________________________________________________________________TABLE OF DATA LINE FUNCTIONS (I/O BUS)__________________________________________________________________________Lines Functions Served__________________________________________________________________________HIGH 0 - 7 "data" High byte "write" data to HW(Central Processor → Adaptor) adaptor. Device address for byte operation. Byte data to byte adaptor.HIGH 0 - 7 "data" High byte "read" data from HWAdaptor → Central Processor) adaptor. Byte data from byte adaptor.LOW 8 - 15 "data" Low byte "write" data to HW(Central Processor → Adaptor) adaptor command for byte operation.LOW 8 - 15 "data" Interrupt requests from adaptor(Adaptor → Central Processor) (when not in CS or I/O mode). Low byte "write" data from HW adaptor.__________________________________________________________________________
The following are brief descriptions of the interrupt system utilized to give service to requesting external devices and the cycle start operation itself which allows relatively large strings of data to be read into or out of the system without individual hand shaking operations between memory cycles.
The following description assumes one possible wired in interrupt priority scheme where the raising of a particular data line (lines) automatically signals the level of the interrupt. This I/O interrupt scheme works in two steps assuming there are several devices on any given interrupt level. First, the I/O bus is examined to see which levels are up. There may be several devices requesting service on any given level. Determination of the highest requesting level is done in conventional decoding circuitry. A software routine is then invoked to poll the highest up level to find out which devices want service at that level. (If there is more than one device on any level, these devices must operate from "special" adaptors which will also use the I/O bus to indicate, during a polling interval, that they want service). If, for example, a 4 is the highest requesting level, the program is then switched to level 4 I/O, and an instruction is performed on the data lines. Any of the adaptors have the ability to put an adaptor identifying signal on a signal I/O line to identify that they want service under their interrupt. The data bus is read out and a further instruction determines which devices at level 4 want service. The devices are then taken in a predetermined sequence until all level 4 interrupts have been serviced and then lower level interrupts will be serviced.
When a Cycle Steal Adaptor raises the CS Request (CS Req) line, a latch is set at the EXIT of the instruction currently in process. This causes the ROS address register to be loaded with the CS microprogram initial address. The I/O line is raised which indicates to the adaptor that the controller has entered the CS routine. The adaptor raises a valid line (VB or VH) which is acknowledged by the Cycle Steal Grant (CSG) line.
The Adaptor then places the Cycle Steal Control Word (CSCW) on the I/O Bus. The CSCW is gated to the CSCW buffer 32 by an appropriate gating operation.
The CSCW identifies whether the operation is to be read or write (Address Bus Bit 8), it provides an initial address in memory 10. Subsequent read or write cycles are addressed by the memory address control 30 until the Adaptor has completed the desired number of cycles, at which time it raises the EOC line. This causes a termination of the cycle steal microprogram. The address of the last instruction completed before the cycle steal operation began is loaded back into the memory address register and normal programmed I/O may be resumed or another cycle operation may be initiated.
The preceding description of the present I/O port control system clearly illustrates the general applicability of the concept. While the disclosed embodiment shows a microprogrammed central processor with a read only store (ROS), it will be apparent that a conventional stored program central processor utilizing central memory for resident control programs could be suitably modified. Also, many variations of the interrupt mechanism and cycle steal operations could be used. The broad concept disclosed is that of the port control mechanism which provides suitable gating paths and controls internal to the central processor to allow the selective connection of the internal source and destination buses to the I/O data lines for the required transfer of both data and command information as needed.
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Affymetrix will enter a research and service collaboration with the Centre for Proteomic and Genomic Research (CPGR) in South Africa. CPGR will provide gene expression and Axiom® genotyping services to African researchers using GeneTitan® Multi-Channel (MC) Instrument. The Affymetrix and CPGR partnership aims to enable high-throughput genomics research and personalized medicine projects across Africa.
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text: No recent wiki edits to this page. The war for New York's soul escalates big time when Luke Cage and Iron Fist take on the all-new, all-different Power Man! Who is the kid that can mop the floor with them both? And if that wasn't bad enough, the worst villains from Luke and Danny's past are crawling out of the woodwork en masse to take them on: Cockroach Hamilton! Comanche! Specs! Senor Muerte! Discuss! Stiletto! Why has this flash mob of colorful criminality suddenly swarmed against our heroes -- and what role does it play in the long-term schemes of The Hand?AThe book opens with another flashback as Victor Alvarez argues with his father over his parent's impending divorce. Just as Victor accuses his father of caring about the protest for the apartment building more than his family, the building blows up (due to Bullseye).In present day, Victor's mother comes to talk to him, but realizes he has snuck out. Picking up on the fight from last issue, the new Power Man continues to take on Luke Cage and Iron Fist. A nearby drug dealer recognizes Power Man as the one who took out his crew early last issue. He calls someone he refers to as "D.N.S.", who summons the Rivals. The fight continues as Power Man absorbs the chi from Iron Fist's signature punch, much to the surprise of Iron Fist. The Rivals arrive and take on a drained Power Man. Cage and Iron Fist join the fight and beat up several of the Rivals. They are briefly detained by Chemistro's alchemy gun which allows Power Man to leave the scene. We learn that Power Man is the son of the former Rival member Shades. Cage and Iron Fist can't pursue him any longer as they must get to Shadowland for Daredevil's intervention ( SL #2). During the ensuing Shadowland melee, Daredevil removes the ban on killing, prompting the ninjas who were beaten by Power Man (last issue) to plan their revenge.At home, Power Man/Victor reveals to his stepsister Sofia that he is Power Man. He confesses to her that he has no idea how he survived the apartment explosion and that he has intense dreams that seem like memories. He makes Sofia promise to keep his secret. His mother then barges in and Sofia tells her Victor was jumped by the Rivals and his mom believes her.On Riker's Island, a voice in a limo talks to a lawyer who tells her that half the Rivals will be released from jail and the other half will have to stay due to warrants. The voice turns out to be Deadly Nightshade ("D.N.S."), who is in pursuit of Power Man for an item that "Specs" stole from her months ago.