text:
A no start condition may be a result of an internal distributor fault. Our technicians tell us the replacement of the distributor may be necessary to correct this condition.
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ClassicsOnline Home » ALFVEN: Symphony No. 3 / Legend of the Skerries
Penguin Guide
Hugo Alfvén (1872-1960)
Symphony No.3 in E major
Dalecarlian Rhapsody
Legend of the Skerries
The music of Hugo Alfvén has always been close
to the hearts of the Swedish people. More than any other composer, he is
regarded as representing the spirit of the country. This might also be due to
the fact that for many years he lived in Dalecarlia, the province where genuine
folk-music tradition is at its strongest.
He spent the first part of his life in
Stockholm, however, and from the age of fifteen studied the violin at the
Conservatory. During the 1890s he also had private lessons in composition from
Johan Lindegren, the foremost master of counterpoint. At the same time he was
engaged as a violinist at the Opera. This gave him ample opportunities to acquaint
himself with the nature and possibilities of different instruments. His
colourful and virtuosic mode of orchestration has been favourably compared with
that of Richard Strauss.
From 1897 Alfvén spent ten years travelling in
Europe, partly financed by a Jenny Lind scholarship. In Brussels he polished
his violin technique and in Dresden he studied conducting. He declined a post
as a teacher of composition in Stockholm, settling instead in Uppsala where he
was appointed Director Musicesat
the University in 1910. He was to stay there for thirteen years.
In Uppsala Alfvén began a collaboration with
the male, mostly academic, choir Orphei
Drängar (Servants of Orpheus) known as OD, whose conductor he
remained until 1947, bringing the choir international renown through tours in
Europe and the United States. He also conducted other well-known choirs, such
as Allmänna Sängen and Siljanskören. Thus for half a century
Alfvén played a dominant rôle in Swedish choral tradition, not only as
conductor but also as composer and arranger.
Alfvén's talents were not solely restricted to
music. He was a fine water-colourist and in his youth seriously considered
taking up painting instead of music. He also wrote a lively and interesting
autobiography in four volumes in which you catch glimpses of his contemporaries
in music.
Many music-lovers know Alfvén best as the
popular, cheerful entertainer in compositions such as Midsommarvaka (Midsummer Vigil) (the
best-known piece of Swedish music outside Sweden), Vallflickans dans(Dance of the Shepherd Girl), the ballet Den förlorade sonen (The Prodigal Son) and
a great many choral songs. His five symphonies and his symphonic poems reveal a
different, more elegiac and often more dramatic aspect of his character. His First Symphony, composed in 1897, has a
melancholy Sturm und Drang mood
that is to recur at intervals throughout his life as a composer, but there is
also a buoyant vitality that was to flourish, two years later, in his Second Symphony. These two compositions
were radically to change the face of Swedish music. Following almost a century
of relative isolation from continental trends, they marked the beginning of a
greater international influence on orchestral music. Stenhammar, Natanael Berg,
Rangström, Atterberg, Peterson-Berger and others were to follow.
Alfvén spent much time in the Stockholm
archipelago, where he felt at home and where he found inspiration for many of
his principal works. As early as 1894, at a rural wedding on Svartnö, he had
heard a farm-hand sing some of the lunes that would, in time, be the frame-work
of Midsommarvaka, a depiction of
"the wanton merry-making and yearning love of Midsummer's Eve, an
apotheosis of the pure, serene poetry of the luminous Swedish summer's night,
the beautiful, happy festival of ail nature", as he himself described it.
After Midsommarvaka
Alfvén wanted to paint its counterpart "the skerries in the
darkness of the autumn night, the stonns and the elegiac moonlight". The
result was the emotionally charged tone-poem En
skärgårdssägen (Legend of the Skerries), completed in 1904 and
performed by the Royal Opera House Orchestra the following year, conducted by
the composer. "My innermost self belongs to the skerries" Alfven
writes. "I have had my best ideas when sailing on dark and stormy nights.
The wild autumn has been my greatest inspiration." His tone-poems are not
intended as detailed descriptions but he emphasizes that there is more to them
than the outward shape. 'The impressions of nature are constantly linked to the
dark joy of human passions". The constant changing of nature becomes a
metaphor for love, invigorating and ecstatic but even more desperate and sad.
Against the background of the dark and threatening sea a fateful drama of the
vanity of human love is enacted. Alfvén was to return to this theme in his Fourth Symphonyfifteen years later.
Following the completion of En skärgårdssägen, Alfvén began to plan a
new symphony, but he needed a change of surroundings and chose Italy, the
nature and culture of which had impressed him strongly during earlier visits.
It was there that he met his future wife Marie Kroyer, at the time married to
the alfresco painter Peter
In the summer of 1905 Hugo and Marie returned
to Italy. In Sori, just outside Genoa, the Third
Symphony began to take shape. Once again love was the inspiration,
only this time as a wholy positive force: the symphony became one of his most
brilliant and harmonious creations. Alfvén says. "The symphony has no
programme, it depicts neither concrete nor abstract. It is an expression of the
joy of living, an expression of the sun-lit happiness that filled my whole
being". The beauty of the Italian countryside and the presence of the
woman he loved - what could be more stimulating to a creative mind? Alfvén
conducted the first performance in December 1906 in Gothenburg. A few months
later he again conducted the symphony, now with the Royal Opera House Orchestra
in Stockholm.
The Dalarapsodi
(Dalecarlian Rhapsody) of 1931 belongs to the composer's later
years. Like so many other compositions from this period it is nostalgic and
rather sad. There is a muted feeling in this description of "the dark
nature and the melancholy temperament of the Swedes". As so often, the
artist Alfvén depicts a specific setting, this time the lonely woods and
majestic mountains north of Lake Siljan. The melodies are mostly from that part
of Dalecarlia.
"I imagine a shepherd-girl sitting on the
grass at her mountain farm in the quiet and deserted woodlands, blowing her horn.
I want to depict her dreams, her longing. In the distance she hears a bridal
procession pass by and in her dreams she is once more among her friends down in
the village. She remembers merry dances in the evenings and church on Sundays
and the exalted solemn hymns. She shivers as she remembers the night when a
strange man appeared among them, seized a fiddle and played wild and strange
tunes that made the people go mad. It was the Devil himself. The shepherd-girl
starts up with a cry of fear, then she wakes from her horrible dream and looks
around in confusion. Quietly she takes up her horn again. I hear the same
melody as in the beginning. And the woods answer her, sighing deeply."
Alfvén conducted the first performance of this, the last of his three Rhapsodies,
in Stockholm in 1932.
translation: Kerstin Swartling
Royal Scottish National Orchestra
Formed in 1891 as the Scottish Orchestra, in
1951 the ensemble, now full-time, took the name of the Scottish National
Orchestra, later assuming the title Royal, a recognition of its importance in
the musical life of Scotland. Distinguished conductors who have worked with the
orchestra include Karl Rankl, Hans Swarowsky, Walter Susskind, Bryden Thomson
and Sir Alexander Gibson, the last named becoming the first Scottish-born
principal conductor in 1959, Neeme Järvi, who was conductor from 1984 to 1988
is now Conductor Laureate and Alexander Lazarev succeeded Walter Weller as
Music Director in 1997. The orchestra has a busy schedule in Scotland, including
regular seasons in its home-town of Glasgow, annual appearances at the
Edinburgh Festival and regular performances in the BBC Promenade Concerts in
London. In addition to concerts in England, the orchestra has travelled to
other countries abroad, with tours of North America, Japan, Austria and
Switzerland. The wide repertoire of the Royal Scottish National Orchestra
extends from the Baroque to the contemporary. There have been two recent awards
from the Gramophone magazine and
the orchestra has embarked on a continuing collaboration with Naxos.
Niklas Willén
Niklas Willén studied conducting at the Royal
Conservatory in Stockholm with Kjell Ingebrektsen and Jorma Panula, graduating
in 1990. In 1988 he made his conducting debut with the Symphony Orchestra of
Gävle and has since appeared with all major Swedish orchestras In January 1992
he was appointed principal guest conductor of the Stockholm Royal Philharmonic
Orchestra, an appointment he held for three years, and from 1993 to 1997 he was
conductor in chief of the Chamber Orchestra of Sundsvall. In January 1990
Niklas Willén won second prize in the Nordic Conducting Competition in
Stockholm and in the autumn of 1990 made his debut at the Royal Opera House,
conducting the ballet A Midsummer Night's
Dream. He has since then returned several times, conducting both
opera and ballet. Niklas Willén's great interest in new music has made him a
favourite with today's composers and he has already directed the first
performances of a number of contemporary works. His recordings include
performances with the Radio Symphony Orchestra, the Gothenburg Symphony
Orchestra, the Chamber Orchestra of Sundsvall and the Swedish Chamber
Orchestra. His international career has brought appearances with important
orchestras throughout Europe.
Last Albums Viewed
ALFVEN: Symphony No. 3 / Legend of the Skerries


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Lets Go Lakers wrote:upgraded with Booz over Gasol (yes, it's an upgrade. Gasol was a joke).
I'm pretty sure THAT is a joke...or you just don't know anything about basketball. Beyond the simple fact that Gasol produced 2.7 more PPG, 1.4 more RPG, 1.2 more BPG, and a PER of 19.34 to Boozer's BELOW LEAGUE AVERAGE 14.48...Pau was the primary front court weapon for 3 straight finals appearances, and two championships...and Boozer hasn't even sniffed the finals. Oh, and Pau is 4 inches taller than Boozer also.
I understand being disappointed with our team's (and Gasol's) performance in the post season after our reign ended, and everyone after last season's debacle, but it's a bit ridiculous to go from that, to downplaying Gasol's value to the degree that is not even represented by factual reality.


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Classicsonline Home » Artists » » Yang, Amos
Amos Yang, cello, with the Seattle Symphony since 2002, has performed as soloist and chamber musician throughout the United States, Asia and Europe. He has collaborated with the Ying Quartet, pianists Ann Schein and Melvin Chen, violinist Earl Carlyss, and composer Bright Sheng, among others.
Yang's awards include the Eastman School of Music's Performer's Certificate, and first prizes in the American String Teacher's Association and Grace Vamos competitions. He has Bachelor and Master of Music degrees from The Juilliard School, and has served on the faculties of the Peabody Conservatory, University of Iowa, Grinnell College, and the Interlochen Advanced String Quartet Institute.


text:
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text:
BPL Community Profile
Ryan C (radio_guy) - BPL Lifetime Member
You cannot send this user a personal message (PM) because they have not specified a PM email address yet.
All Forum Posts by Ryan C
FS: SMD Wild Oasis
Wild Oasis is still available.
FS: SMD Wild Oasis
Six Moon Designs Wild Oasis. Like new condition, only setup in the backyard for fun and not used on any trips. Color is gray and I have short lengths of Triptease line attached to the tie outs. SOLD
PM sent about the Hexamid.
Re: Backpacking areas accesible by General Aviation
Thanks for the suggestions. Many of these options will require some sort of shuttle, lots of planning, and extra expense. Does not look like the quick and easy long weekend backpacking trip by air ...
Re: Backpacking areas accesible by General Aviation
Places such as the Black Forest Trail are exactly what I was looking for. I called the Black Forest Inn to inquire about the airstrip. They don't maintain it anymore and it has obstructions now...
Backpacking areas accesible by General Aviation
Strange question but figured it would get the most views in the Gear section. For those aviation gurus and other pilots out there, what are some good backpacking locations east of the Mississipp...
Wild Oasis, Solomid
Does anyone have a Solomid (gray preferred) to trade for a Wild Oasis? If not, I am willing to sell the Wild Oasis outright. $140 shipped.
WTT: SMD Wild Oasis for a MLD Solomid
Interested in trading a like new SMD Wild Oasis for a MLD Solomid. May be willing to pay extra if you have a matching net tent to go with it. Let me know what you got!
Re: Alaska Wish List
Out of all the places I have visited in Alaska thus far, Lake Clark National Park is very high on the list. It has been called the essence of Alaska and offers some of everything the state has ...
Re: Re: MSR Hoop????
I would for sure agree with Roger that the Hoop can be a challenge to setup in icky weather. I had the advantage of setting up the tents many times before the trip. Others had to learn the quirky s...
All Reader Reviews by Ryan C
Ryan C has posted no reviews.


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El Popo Apartments3228 S Union Ave, Tacoma, WA 98409 View On Map (253) 627-5746
For rates, availability, and other information fill out the availability request form and a representative from El Popo Apartments will contact you shortly
El Popo Apartments is located in the Tacoma Area in the 98409 zip code. View this apartment on a map.
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Academics . Liberal Arts . Faculty . Christopher Auerbach-Brown
Christopher Auerbach-Brown
Title Adjunct Faculty
Department Liberal Arts
Phone 216.421.7000
Courses John Cage: His Life, Work, and Influence | Sound Art + New Media | Sound Design | Survey of Contemporary Music
Christopher is an adjunct faculty member in Liberal Arts at The Cleveland Institute of Art. He received his Bachelor of Music in 1992 from Ithaca College. In 1995 he earned his Masters degree from The Cleveland Institute of Music in Composition. He was been a Music mentor with the Cleveland Opera and lecturer at The University of Akron and Cleveland State University. Christopher was the co-founder of Composers in the Shape of a Pear and the co-director of the Modern Arts Coalition of Cleveland.
Degree BA, Ithaca College; MFA, Cleveland Institute of Music
Get started here.
While at CIA, you'll learn from the masters through our rigorous, world-class curriculum and connect with working professionals to begin your career.


text:
Construction Injuries Lawyers and Law Firms in Schaumburg, IL
Construction Injuries Lawyers
Paul W. Grauer & Associates
Personal Injury & Workers' Compensation Attorneys in Schaumburg, IL(847) 240-9010
Paul W. Grauer & Associates is one of the most well-known and respected personal injury and workers' compensation law firms located in the northwest suburbs of Cook county Illinois. For over 35 years, we have concentrated our practice in Personal Injury and Workers Compensation...
Law Firm's Overview Free Consultation
Lloyd Law Group, Ltd.
Medical Malpractice Attorneys in Schaumburg, Illinois(312) 462-0363 or (888) 365-5481
The Lloyd Law Group, with more than 25 years of experience, has successfully represented many clients handling a number of cases that have led to changes in the laws or in the ways that hospitals or medical professionals provide care. We are dedicated to protecting the rights of...
Law Firm's Overview Free Consultation
Bellas & Wachowski
Full-Service Law Firm in Park Ridge, Illinois(847) 823-9030 or (800) 825-9260
Bellas and Wachowski in Park Ridge, IL, serves as trusted advisors on legal advice, regardless of the issue. The firm can represent clients with a number of issues from personal injury to class-action litigation. For more than 40 years, the firm has helped clients solve their legal...
Law Firm's Overview
Drost, Gilbert, Andrew & Apicella, LLC
Schaumburg, Illinois Civil Litigation Attorneys(847) 934-6000
Drost, Gilbert, Andrew & Apicella, LLC is a criminal defense, personal injury, estate and employment law firm located in Chicago, Illinois which serves Chicago and the surrounding suburbs in a full spectrum of matters related to each practice area. The firm's dedicated team understands...
Law Firm's Overview Free ConsultationCredit Cards
David W. Clark, PC
Wheaton, Illinois Personal Injury Attorney(630) 665-5678
The Law Offices of David W. Clark, P.C. is a personal injury and workers' compensation law firm located in Wheaton, Illinois. Attorney Clark's comprehensive knowledge of the intricacies of liability, and his practice is motivated by a desire to help those who are facing serious adversity...
Law Firm's Overview Free Consultation
Farooqi & Husain LLC
DuPage County Estate Planning & Business Law Attorneys(630) 909-9114
Farooql and Husain Law Office in Oak Brook, IL, can represent clients in a number of areas. Regardless of the issue, the firm provides high-quality legal advice for businesses and individuals. The firm can handle cases involving family law, business law, estate planning and criminal...
Law Firm's Overview Free Consultation
Mirabella, Kincaid, Frederick & Mirabella, LLC
DuPage County Divorce and Civil Litigation Attorneys(630) 665-7300
Mirabella, Kincaid, Frederick and Mirabella LLC in Wheaton, IL, helps those clients who need to resolve family disputes, business litigation or employment discrimination. The firm celebrates its 50 years of serving people of Illinois, which means it knows much about family law. The...
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Walsh, Knippen, Pollock & Cetina, Chartered
Chicago, Illinois Personal Injury Lawyers(630) 462-1980
Walsh, Knippen, Pollock & Cetina, Chartered is a personal injury law firm based in Wheaton, Illinois providing legal services to injured clients throughout the greater Chicagoland area and its surrounding cities and counties. The team of attorneys at the firm has well over a...
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Mevorah Law Offices LLC
Multi-Practice Law Firm in Illinois(630) 932-9100
Mevorah Law Offices, LLC has given Illinois residents over a century and a half of expertise in a full range of legal specialties, providing families, businesses, the injured, and the accused with the personal attention and tailored solutions that have given the firm its respected...
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Scott W. Sheen & Associates, PC
Criminal Defense and Personal Injury Attorneys in St. Charles, Illinois(630) 443-6200 or (800) 516-1387
Scott W. Sheen & Associates, P.C. is a law firm based in St. Charles, Illinois and specializes in personal injury, workers' compensation, criminal defense and family law. Our firm serves clients throughout the Chicagoland area in all matters of the law, led by our founding attorney,...
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Law Offices of R. F. Wittmeyer, Ltd.
Arlington Heights, Illinois Personal Injury Attorney(847) 577-1123
The Law Offices of R. F. Wittmeyer Ltd. in Arlington Heights, IL, handles personal injury cases. The firm can represent clients who are victims of any type of accident. For more than a quarter century, the firm has helped clients get the compensation they deserve.
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Mevorah Law Offices LLC
DuPage County Divorce, Personal Injury and Criminal Defense Attorneys(630) 932-9100
Mevorah Law Offices LLC is a multi-practice law firm serving Northern Illinois clients in a range of areas, including family law and divorce, personal injury and medical malpractice, bankruptcy, immigration, criminal defense, workers' compensation, employment law, and workplace discrimination....
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DuPage County Personal Injury and Workers' Compensation Attorneys(630) 574-2288 or (866) 926-9007
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Rolewick & Gutzke, P.C.
Wheaton, Illinois Estate Planning & Business Law Firm(630) 653-1577
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Mevorah Law Offices LLC
DuPage County, Illinois Divorce and Personal Injury Lawyers(630) 932-9100
Mevorah Law Offices is a full service law firm based in Lombard, Illinois with additional offices in Bloomingdale, St. Charles, Joliet, and Chicago serving clients throughout the greater Chicagoland area. The firm's large and talented staff combines over 150 years of legal experience...
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Kathryn L. Harry & Associates, PC
Illinois Criminal Defense Attorneys(630) 472-9700
The law office of Kathryn L. Harry and Associates, P.C. is a criminal defense law firm serving clients throughout Chicago, Illinois and the surrounding counties. Ms. Kathryn Harry first opened her own law firm in 1995, and since then she has worked with her experienced legal team...
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Newland & Newland, LLP
Illinois Personal Injury, Workers' Compensation, and Bankruptcy Attorneys(847) 797-8000
Newland and Newland LLP is a law practice dedicated to personal injury, bankruptcy, workers' compensation, estate planning, real estate and immigration cases in Illinois. The attorneys rely on their more than 20 years of experience to help clients resolve their issues and prevent...
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Chad M. Hayward, PC
Illinois Bankruptcy, Real Estate and Immigration Lawyers(312) 867-3640
At the Law Offices of Chad M.Hayward, P.C. in Illinois, our lawyers practice in several areas of law, including: Bankruptcy protection and home foreclosure defense; Immigration services; Real estate transactions; Property Tax Issues; and, Workers' compensation.
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Friedman & Bonebrake, PC
Chicago Personal Injury Attorneys(312) 466-8200
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Navy Using New Cyclopss Decontamination Technology.
The United States Navy is using a new decontamination technology developed by Cyclopss Corporation (OTC Bulletin Board: OZON). The Cyclopss systems are currently operating in Navy facilities in San Diego, California, and Pearl Harbor, Hawaii.
The ECO-WASH Cold Water Ozone Systems are being used to decontaminate and recycle rags containing oils, grease, solvents and other chemical contaminants when they are off-loaded from Navy ships returning to port after lengthy trips at sea. While the systems are currently being used solely for chemical decontamination, Cyclopss reports that they are capable of destroying Biological contamination as well.
"We have repeatedly demonstrated that the ECO-WASH Ozone Systems can effectively destroy all microorganisms including Bacillus Subtilis, a spore from the same genus as Bacillus Anthracis, the viral spore that causes Anthrax," says Dr. Durand Smith, President and Director of R&D at Cyclopss. He continues, "Our test results run in absolute parallel to the Los Alamos Laboratories data produced in their study on the effectiveness of Ozone on Anthrax 'look alike' spores."
The Cyclopss systems utilize the oxidation potential of ozone to destroy biological and chemical contaminants alike. Because the ECO-WASH products wash with cold water and neutral ph., the systems are perfect for use in the decontamination of Hazardous Materials Suits and other protective garments. These suits are made of plasticized and hydrophobic materials that react poorly to traditional ultra high temperature or harsh chemical decontamination treatments.
The company also announced earlier in the week that it had completed the installation of its first Ster-O-Zone Ozone Gas Decontamination Chamber in a nationally recognized, FDA certified biological testing laboratory, just outside of Salt Lake City. The chamber was designed and constructed at the Company's research and development facilities in Albuquerque, New Mexico. It will be used for the decontamination of laboratory carts and equipment between sterility studies. The chamber kills 99.9% of the Anthrax "look alike" Bacillus Subtilis in 30 minutes at room temperature and low pressure.
In its current design the chamber is capable of decontaminating mail carts and sorting equipment, and is currently being evaluated to determine what adaptations, if any, can be made to expand its use to the treatment of low volumes of mail or suspicious packages in small post offices, or office mail rooms where irradiation won't be practical.
Cyclopss is a world leader in the development of environmentally friendly technologies and applications that are used in the cleaning and disinfection of food, laundry, and surfaces for industries as well as consumers.
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A plurality of integrated circuit chips (12) are packaged in a stack of chips in which a number of individual chip layers (10,120,130,132,134) are physically and electrically interconnected to one another and are peripherally sealed to one another to form an hermetically sealed package having a number of input/output pads (137a,139a,141a,156,158,160) on the surface of the upper (132) and lower (134) layers. Each chip layer comprises a chip carrier substrate having a chip cavity (22) on a bottom side and having a plurality of electrically conductive vias (40,42,44) extending completely around the chip cavity. Each substrate is formed with a peripheral sealing strip (46,48) on its top and bottom sides and mounts on its top side a chip that has its connecting pads (14) wire bonded to exposed traces (32,34) of a pattern of traces that are formed on the top side of the substrate and on intermediate layers (16,18,20) of this multi-layer substrate. The traces interconnect with the vias (40,42,44) that extend completely through the substrate, and each via is provided at the top and bottom sides of the substrate with a via connecting pad (40a41b), with the via pads on top and bottom sides all being arranged in identical patterns. Solder on the via pads and on the sealing strips is reflowed to effect a completely sealed package and to interconnect vias in each layer with vias in each other layer.
1. A multi-die package comprising:
a plurality of stacked chip layers, each said chip layer comprising:
a carrier substrate having top and bottom sides,
a plurality of electrically conductive vias extending through said carrier substrate between said top and bottom sides, each said via having electrically conductive top and bottom via pads on the top and bottom sides of the carrier substrate, wherein each said via pad is oblong and has a major axis, and wherein the major axis of the pad of the top side of each via is angulated relative to the major axis of the pad of the bottom side of the same via,
a pattern of electrically conductive traces formed on the top side of said carrier substrate, at least some of said traces having an outer end connected to one of said via pads,
a chip mounted on said top side of said substrate and having a plurality of chip pads, and
an electrical connection between each of said chip pads and one of said traces,
said chip layers being arranged in a stack of chip layers with the vias of one carrier substrate aligned with the vias of an adjacent carrier substrate and with the via pads on top and bottom sides of each carrier substrate being electrically connected to via pads on respective bottom and top sides of adjacent carrier substrates.
2. The package of claim 1 wherein each said carrier substrate has a geometric center and wherein each includes at least three elongated alignment openings each having a longitudinal axis that intersects said geometric center, each said opening being positioned near the periphery of said carrier substrate, two of said openings being positioned on opposite sides of said geometric center and having mutually aligned axes and a third one of said openings having an axis that is angulated relative to the axes of said two openings.
3. The package of claim 1 wherein each said carrier substrate includes a continuous peripheral seal strip on both top and bottom sides, the seal strips on the top and bottom sides of each carrier being hermetically sealed to the seal strips on the bottom and top sides, respectively, of adjacent carrier substrates.
4. The package of claim 3 including a lid having a plurality of vias registered with the vias of said carrier substrates and electrically connected thereto, and a continuous peripheral sealing strip on the bottom side of said lid congruent with and sealed to a sealing strip on the top side of an uppermost one of said carrier substrates, thereby providing a fully hermetically sealed package of stacked dies.
5. The package of claim 1 wherein the major axis of the pad of the top side of each via is orthogonal to the major axis of the pad of the bottom side of the same via, and wherein the via pad of the top of one carrier substrate is electrically and mechanically connected to a via pad of the bottom of an adjacent carrier substrate to form a pair of interconnected via pads, and wherein the major axis of the via pad of one pad of said pair is orthogonal to the major axis of the via pad of the other pad of said pair.
6. The package of claim 3 wherein said via pads comprise reflow solder pads, and wherein each carrier substrate includes on its top side a solder flow barrier interposed between the inner end of said leads and said via pads.
7. The package of claim 6 wherein said barrier comprises a thin dielectric cover overlying some of said traces.
8. The package of claim 1 including a lid having a plurality of electrically conductive lid vias aligned with respective ones of the vias in said carrier substrates and extending from bottom to top sides of said lid, each of said lid vias having an electrically conductive lid via pad on top and bottom ends thereof, the bottom pads of the lid vias being electrically connected to top pads of the vias of the uppermost one of said group of carrier substrates.
9. The package of claim 1 wherein at least one of said carrier substrates comprises a plurality of dielectric laminations, at least some of said electrically conductive traces being formed on different ones of said laminations.
10. The package of claim 1 wherein each of a group of said carrier substrates includes a cavity on its bottom side and wherein the chip on the top side of one of said carrier substrates is at least partially received within the cavity on the bottom side of an adjacent carrier substrate.
11. A chip carrier for use in forming a hermetically sealed stacked chip package, said carrier comprising;
a carrier substrate having top and bottom sides,
a plurality of electrically conductive vias extending through said substrate between said top and bottom sides, each via of said plurality of vias having a respective electrically conductive top and bottom via pad at said top and bottom sides of said substrate,
a pattern of electrically conductive traces formed on the top side of said substrate, at least some traces of said pattern of electrically conductive traces having an outer end connected to one of said via pads and having an exposed chip-connecting end,
an electrical connection between each of said chip pads and one of said traces,
a respective continuous peripheral seal strip on both said top and bottom sides of said carrier substrate, and
a plurality of elongated alignment non-circular openings in said carrier substrate, each alignment opening of said plurality of alignment openings having a longitudinal axis that intersects the geometric center of said carrier substrate.
12. The chip carrier of claim 11 further including a chip mounted on said top side of said substrate and having a plurality of chip pads.
13. The chip carrier of claim 11 wherein said pattern of electrically conductive traces includes a plurality of electrically conductive traces, each trace of said plurality of electrically conductive traces having an exposed end configured and arranged for connection to a connecting pad of a chip to be mounted on said carrier substrate, and each one of said via pads includes a layer of reflow solder thereon, further including a solder barrier interposed between each of said via pads and the respective one of said exposed chip connecting ends of said plurality of traces.
14. The chip carrier of claim 13 wherein said solder barrier comprises a thin dielectric cover overlying at least some of said plurality of electrically conductive traces.
15. The chip carrier of claim 11 wherein said via pads on said top and bottom sides of said substrate are elongated and have longitudinal axes, and wherein said longitudinal axes of said top and bottom via pads at each via are mutually orthogonal.
16. The chip carrier of claim 11 wherein said carrier substrate includes a chip mounting area on one side, and defines a cavity in and opening to the other side of said substrate.
17. The chip carrier of claim 11 further including a lid member having a plurality of electrically conductive lid vias respectively aligned with vias of said carrier substrate and extending from bottom to top sides of said lid, each one of said plurality of electrically conductive lid vias having an electrically conductive lid via pad at respective top and bottom ends thereof, the bottom via pads of said lid vias being electrically connected to respective top pads of said vias of said carrier substrate.
18. The chip carrier of claim 11 wherein said carrier substrate includes a plurality of dielectric laminations, at least some traces of said pattern of electrically conductive traces being formed on different ones of said plurality of dielectric laminations.
The United States government has rights in the present invention pursuant to Contract No. DASG 60-90-C-0135, issued by the Department of the Army.
1. Field of the Invention
The present invention relates to packaging of integrated circuit chips and more particularly concerns an improved three-dimensional package of stacked integrated circuit chips.
2. Description of Related Art
As electronic circuits become larger and more complex, increased efforts continue to be directed toward the goal of decreasing size of circuit packages. In some types of multi-chip modules, many integrated circuit chips are mounted side by side in close proximity to one another on a multi-layered substrate so that adjacent chips may be connected to one another by means of connecting leads that extend in a number of different planes, thereby decreasing horizontal dimensions of the package at the expense of some increase in vertical dimension.
Integrated circuit chips have also been stacked vertically one upon another to provide decreased size, weight and power as compared to conventional single chip or multiple horizontally aligned chip packaging. However, because of the large number of chip connecting pads, which may be in excess of four hundred on a single chip, for example, it is difficult, in prior arrangements, for chip stacking to adequately provide interconnections from all of the chip pads to one another as desired, or to external circuitry. In prior chip stacking arrangements interconnecting leads between chips on different levels are provided at the sides of the stack. Leads are routed from each chip connecting pad to the side of the stack, and interconnections are made in the form of vertical connectors or vertical buses that extend along the exterior sides of the stack. Because the vertical surface area of the sides of the stack is limited, the number of input/output connections between the chip connecting pads of the chips of a stack and connecting elements at the outside of the stack is itself severely limited. In prior chip stacks, connecting leads from the chip connecting pads have been routed to one side of the stack so as to most conveniently form the vertical interconnects between stack layers and connections. This has been done in the past by adding metallization or additional leads on the chip or using other interconnect techniques, such as tape automated bonding. These techniques require special processing of the chips or wafers and add considerable cost to the stacking process. Without the use of special chip or wafer processing to allow stacking in the prior art, the input/output connections for interconnecting stack layers are limited in number. Thus, standard chips that are not specially processed for stacking cannot be stacked without severe limitations on input/output connections.
Accordingly, it is an object of the present invention to provide integrated circuit chip packaging that avoids or minimizes above mentioned problems.
In carrying out principles of the present invention in accordance with a preferred embodiment thereof, a plurality of stacked chip layers is provided wherein each chip layer comprises a substrate or chip carrier having a number of electrically conductive vias extending between its top and bottom sides, with via connecting pads formed on the top and bottom sides of each via. A pattern of electrically conductive traces is formed on one side of the substrate, at least some of which are connected to some of the via pads. An integrated circuit chip is mounted on the other side of the substrate with its connecting pads wire bonded to some of the electrically conductive traces. The chip layers are arranged in a stack with the vias of each layer aligned with the vias of an adjacent layer and with the via pads on top and bottom sides of each layer being electrically and mechanically connected to via pads on bottom and top sides, respectively, of adjacent layers.
In the accompanying drawings:
FIG. 1 is an enlarged sectional view of one half of a symmetrical single chip layer showing a chip and chip carrier embodying principles of the present invention;
FIG. 2 is a view of the bottom side of the chip carrier of the chip layer of FIG. 1;
FIG. 3 is a view of the top side of the chip carrier of FIG. 1, showing the chip in phantom lines;
FIG. 4 is a sectional view of an exemplary stack of chip layers; and
FIG. 5 illustrates the relative orientations of a pair of interconnected via pads on adjacent layers.
Illustrated in FIG. 1 is a single chip layer. The single chip layer in FIG. 1 shows a chip carrier, or substrate 10, carrying a single chip 12. FIG. 2, for convenience of illustration, shows only one half of the chip carrier and chip, which may be symmetrical about the center line 11. This layer is to be assembled in a stack of chip layers, each with a mounted chip, as illustrated in FIG. 4. This figure shows a sectional view of one half of a complete hermetically sealed stack of integrated circuit chips, for a stack that is symmetrical about centerline 11.
The single chip layer of FIG. 1 comprises a substrate or chip carrier, generally indicated at 10, upon which is mounted a conventional integrated circuit chip 12 having a plurality of chip connecting pads, such as pad 14 shown in FIG. 1. Chip carrier 10 may either be a single layer solid substrate or, as shown in FIG. 1, a multi-layer substrate formed of any suitable number of layers, such as first, second and third substrate layers 16,18 and 20. The carrier 10, in the embodiment illustrated in the drawings, is of generally rectangular configuration, as can be seen in FIGS. 2 and 3, and has a symmetrically and centrally located cavity 22 formed in its bottom. Each of the substrate layers has a pattern of electrically conductive traces formed thereon for interconnection of various elements, as will be described below. Thus, for example, traces 24 are formed on the upper surface of lower layer 22, traces 26 are formed on the upper surface of intermediate layer 18, and traces 28,30 are formed on the upper surface of upper layer 16. In this arrangement traces 28 and 30 have exposed bond finger portions 32 and 34, respectively (see FIGS. 1 and 3).
The various substrate layers are formed of very thin (from about 1 to 10 mil thickness) dielectric ceramic, such as alumina, aluminum oxide (Al2 O3), aluminum nitride (AlN), or other suitable nonconductive material.
Extending through the thicker part of the substrate, surrounding the cavity 22, are rows of vias, such as vias 40,42, and 44, filled with an electrically conductive material, such as a tungsten paste, for example, and extending continuously from the top side of the carrier to its bottom side. For convenience of exposition, the top side of the carrier is the side that is deemed to be uppermost as viewed in FIG. 1, and the bottom side is the side that is lowermost. Each of the vias has a via pad, such as pads 41a and 41b, 43a and 43b, and 45a and 45b, electrically and mechanically connected to the top and bottom ends of the via, respectively.
Running continuously around the peripheral edge of both the top side and bottom side of the carrier substrate 10 are a continuous top side seal strip 46 and a continuous bottom side seal strip 48. Additional vias, such as a via 50, extend through the thinner part of the substrate above cavity 22 to interconnect certain of the trace patterns on different layers of the single carrier, such as for interconnection of trace 30 with trace 26. A very thin (in the order of a fraction of a mil in thickness) dielectric protective inner cavity layer 52 is bonded to the bottom of the cavity 22, that is, to the lowermost portion of the thin inner portion of the carrier substrate, to shield leads running along the lower surface of this portion of the substrate. A similar thin dielectric outer cavity cover layer 54 of a rectangular configuration for this rectangular configuration chip carrier overlies and is bonded to the uppermost layer 16 of substrate 10. Cover layer 54 has a peripheral edge 55 (see also FIG. 3) which is positioned to expose free ends of all of the upper layer leads 34. Thus, outer cavity cover layer 54 protects inner portions of leads 30 but leaves an exposed portion 34 that is available for bonding to a bond wire 58 to connecting pads 14 of the chip 12. The latter is mounted by a suitable adhesive (not shown) on the upper surface of cover layer 54. The chip may have a size equal to but preferably not greater than the dimensions of the cover layer 54 so that edges of the chip do not extend beyond, and are preferably set back somewhat from, the peripheral edge 55 of the cover layer 54. Chip 12 is shown in phantom lines in FIG. 3.
All of the electrically conductive traces, all of the via pads, and all of the seal strips are preferably formed by the same process, using the same material. To form these elements, a tungsten paste is screened onto the substrate layer and then fired together with the individual substrate layer to cause the paste to solidify and to become bonded to the layer. Thereafter the fired tungsten paste is covered with a barrier layer of nickel and then a very thin outermost layer of gold (for at least the exposed areas). To all of the via pads and to all of the peripheral seal strips, but not to any of the other traces, is thereafter applied a thin coat of a high temperature reflowable solder. Certain pads or bumps on the bottom of a stack to be used to mount the stack may be formed of a relatively low temperature solder, as will be described below.
The via top and bottom pads are each elongated, having an aspect ratio of about 3:1, that is, a length of three times the width. The via pads are oriented so that when several carriers are stacked, as shown in FIG. 4, with the via pad at the top side of one carrier in contact with the via pad at the bottom side of an adjacent carrier to form a pair of contacting via pads, the two elongated pads of a single pair of contacting via pads are angulated with respect to one another, and preferably positioned at right angles to each other, as shown FIG. 5. In this figure is shown, for example, a via pad 41a that is positioned at the top side of via 40 of a lower layer and in contact with a via pad 137b at the bottom side of an immediately higher layer.
As can be seen in the carrier bottom view of FIG. 2, the vias (the via pads of the outer three rows of vias are seen in this figure) are arranged in parallel rows on each of the four sides of the carrier cavity 22. Thus, a row of via pads including lower side via pad 41b is identified in FIG. 2 as via pad row 62 (extending vertically in FIG. 2). A row including via pad 43b is identified as vertically extending row 64, and a row of via pads including via pad 45b is identified as vertically extending row 66. Thus, there are three parallel rows of vias extending along the left side of the cavity on the carrier (as viewed in FIG. 2) with the rows being parallel. In this case, all of the vias of these three rows have their longitudinal axes aligned in directions parallel to the extent of the several rows (e.g., vertically, as viewed in FIG. 2). A similar set of three via pad rows 68,70,72 (including the associated vias, of course) are arranged in an identical pattern along the right side of the cavity 22. Similarly, along the top and bottom side of the cavity are arranged groups of horizontally extending via rows 74,76,78 on the top side of the cavity, as viewed in FIG. 2, and horizontal via rows 80,82 and 84 on the bottom side of the cavity. Again, all the vias have their longitudinal axes parallel to one another in each row and in each group of rows and parallel to the extent of the rows. In the particular arrangement illustrated, however, the longitudinal axes of the vertically extending rows of vias 62,64,66,68,70,72 are all parallel to one another and perpendicular to the longitudinal axes of horizontally extending via rows 74-84.
Each of the vias of the inner pair of rows, such as rows 64,66,68,70,74,76,80,82, are connected to leads buried within the thin portion of the substrate layer above the cavity, such as lead 26 (FIGS. 1 and 2) which connects to via 40 (FIG. 1) and to one of the vias 50 (FIGS. 1 and 3) extending through the thin portion of the substrate above the cavity. For example, via pad 41b is connected via lead 26, on layer 18, and via 50 (through layer 16) to the lead 30 which has an end portion 34 exposed for connection to a bonding wire 58 and chip pad 14.
A group of the vias are designated herein as cavity vias and generally indicated in FIGS. 2 and 3 by numeral 86 (which include the via 50), which, like the via 50, extend through the thin portion of the upper layer 16 for connection to different ones of leads on the surface of the upper layer 16. The cavity vias 86 are each connected by buried leads analogous to lead 26 to a different one of the vias in the row of vias indicated at 62 (FIG. 2). Similarly, additional groups of cavity vias 88,90 and 92 are connected by buried leads to respective ones of the vias in outer via rows 78,72 and 84, respectively. To maintain clarity of the drawings, only some of these buried leads are shown, but the general pattern of leads is as illustrated. Cavity vias 86,90 and 92 all extend through the thinner portion of the substrate layer above the cavity 22 and are individually connected to respective ones of leads, such as leads 30, formed on the uppermost surface of the layer 16 above the cavity. To relatively orient FIGS. 2 and 3, the top of carrier 10, as illustrated in FIG. 3, merely is turned over so that the right side of the carrier, as viewed in FIG. 3, becomes the left side of the turned over carrier as viewed in FIG. 2, and the left side of the carrier as seen in FIG. 2 becomes right side of the carrier as seen in FIG. 3. For example, as seen in the carrier bottom view of FIG. 2, the carrier includes three registration openings 100,102, and 104 at three different corners of the carrier. In the carrier top view of FIG. 3, registration opening 100 is seen at the upper left corner, whereas the other side of this same opening is seen in the upper right corner of FIG. 2. Similarly, opening 102 is seen in the lower right corner of FIG. 2 and in the lower left corner of FIG. 3. The nature, purpose and function of these registration openings and the significant and important improvements accomplished thereby will be described in detail below.
As mentioned above and as seen in FIG. 3, the top side of each of the cavity vias 86,88,90 and 92 are covered by a very thin (a fraction of a mil) dielectric layer 54 which covers the cavity via groups and portions of the conductive leads on the upper surface of the upper carrier layer. Also shown in FIG. 3 in phantom lines is the outline of the integrated circuit chip 12 that will be adhesively bonded to the uppermost surface of the thin dielectric cover layer 54.
A generally rectangular ring shaped cover layer 110, also formed of a very thin dielectric material, such as a ceramic, alumina or the like, covers the uppermost surface of the upper layer of carrier 10 and extends completely around the outer cavity cover layer 54. The inner periphery 112 of the ring shaped cover layer is spaced from the outer periphery 114 of the outer cavity cover layer 54 so as to expose portions of the traces collectively indicated at 28 and 30. As indicated above, these exposed portions of the traces are arranged for connection of bond wires, such as wire bond 58, that are also bonded to the chip connecting pads 14. The exposed traces, such as trace 38, are connected by leads 28 (FIGS. 1 and 3), which are covered by the ring shaped cover layer 110 to respective ones of the via pads of via pad rows 64b,66b. FIG. 3 also shows the groups of three rows of vias on each side of the carrier (actually only the via pads on the upper sides of the vias are seen in the figure) with via rows 62b,64b,66b corresponding respectively to via rows 62,64, and 66 of FIG. 2.
It is to be noted, however, that the elongated via pads on the top side of vias in rows 62b,64b,66b, though all parallel to one another, have their longitudinal axes all perpendicular to the direction of the respective rows. Importantly, these longitudinal axes are perpendicular to the longitudinal axes of the corresponding via pads on the bottom side of the same via. That is, any one via of the vertically extending rows has a vertically oriented pad on its bottom side (vertical as seen in FIG. 2) and the same via has a horizontally oriented via (as seen in FIG. 3) on its top side.
The purpose of this orthogonal pad orientation is to provide overlapping connecting pairs of via pads overlapping as shown in the configuration illustrated in FIG. 5, as will be more particularly described below. Thus, each via has a top side pad oriented in one direction and a bottom side pad oriented in a perpendicular direction, as can be seen from the illustrations of FIGS. 2 and 3. The via pads of the inner rows of the top side pads of via rows 64 and 66 are connected by traces, such as trace 28, partially buried beneath the ring shaped cover layer 110 and having exposed end portions, such as exposed end portion 32 of trace 28. Wire bonds from the individual chip connecting pads 14 are connected respectively to different ones of the exposed ends 32,34, etc. of the partially buried traces, which are connected at their other ends to individual ones of the cavity vias that extend through the upper carrier layer.
As can be seen in each of FIGS. 2 and 3, the continuous seal strip 48, on the bottom side of the substrate, and strip 46, on the top side of the substrate, extend around the entire periphery of both top and bottom sides of the substrate.
Illustrated in FIG. 4 is an exemplary stack formed of three intermediate chip layers 10,120, and 130, each of which may be identical to the single chip layer shown in FIGS. 1, 2 and 3, and including a lid or uppermost layer 132 and a base or lower layer 134. The upper layer 132 is identical to the intermediate chip layers 10,120 and 130 except for the fact that no chip is mounted on its upper surface and none of the connecting leads necessary for connection of the chips pads are needed or used. However, this upper layer also includes electrically conductive tungsten filled vias 136,138 and 140, having top and bottom pads 137a and 137b, 139a and 139b, and 141a and 141b on top and bottom sides of the respective vias 136,138,140. The uppermost layer or lid 132 also is formed with a continuous peripheral seal 144 on its lower surface. No such seal is needed, of course, on its upper surface.
In a like manner, the lowermost layer or base 134 is identical to the intermediate layers 10,120 and 130. Its three electrically conductive tungsten filled vias 150,152, and 154 are provided with top side via pads just the same as are provided for the intermediate layers 10,120 and 130 but may be provided with smaller pin type via pads 156,158, and 160, respectively, that are specifically configured and arranged to be received in solder wells (not shown) on a PC board or other mounting substrate for making physical and electrical connection of the stack to the mounting substrate.
As can be seen in FIG. 4, the via pads of the successive layers are in physical, mechanical and electrical contact with one another in the stack. So too the peripheral seals on top and bottom sides of adjacent layers are in hermetically sealing contact with one another to provide a complete hermetic seal for the entire package.
An exemplary sequence of assembling procedures is as follows:
Each ceramic carrier of one or multiple layers with vias, traces and registration openings is formed. The several traces are formed by screened-on tungsten paste fired together with the layer and then covered with a nickel barrier and a thin gold layer, where appropriate. The vias are filled with a suitable conductive compound, such as a tungsten paste, which is fired together with the individual layers, the tungsten traces, seal strips and via pads. Thereafter the carrier substrate has applied to its upper surface the thin dielectric ceramic inner and outer cover layers 52,54 and ring shaped cover layer 110, which are suitably bonded thereto, and, as previously mentioned, may have a thickness of a fraction of a mil. The high temperature solder coats the continuous seal strips and via pads are then silk-screened on top and bottom sides of the carrier. Each carrier is now available for mounting of its die integrated circuit chip. The chip is adhesively secured to (as by an epoxy, for example) the cover layer 54 and its chip connecting pads wire bonded to different ones of the exposed traces 32,34. After completion of each chip layer, that is, after mounting of a chip of an individual carrier substrate, the chip and its carrier may be completely tested to ensure proper operation before the chip and its carrier are assembled in a stack. The several chip layers, comprising the carrier and chip, are then stacked on a stacking fixture or stacking base with all the sealing strips in contact with one another and with top via pads of one layer in contact with and orthogonally oriented relative to the bottom via pads of the next upper layer. The stack is assembled on a group of three mutually parallel vertical alignment pins (not shown) fixed on a fixed stacking fixture base and protruding vertically through the respective alignment openings 100,102 and 104 of each of the carriers and stack layers, including the lid 132 and the lower layer 134. The stack, held with its several carriers mutually aligned by the alignment pins, is placed in an oven and weighted to press the layers against one another. The assembly is heated to cause the solder to soften and/or melt and to form solder joints between connecting seal strips and mutually contacting via pads to provide strong, reliable, mechanical, electrical and thermal connections between the stacked carriers.
The various carriers are subject to thermal contraction and expansion as they are fired and thereafter cooled. Because the various layers may have different thermal coefficients of expansion than the base of the stacking fixture, and because even similar materials of the different carriers may themselves have slightly different coefficients of thermal expansion, the elongated registration apertures 100,102 and 104, extending in mutual vertical alignment through all of the stacked carriers are provided to enable accommodation of the assembled carriers to differentiate thermal expansion and contraction. As previously mentioned, each of these openings is elongated and has a longitudinal axis. The longitudinal axis of each opening intersects the geometric center of the carrier layer. Each carrier layer will thermally expand or contract equally in all directions from its geometric center, and thus the elongated registration openings, elongated in the direction of a line to the geometric center, allow such a thermally induced change in dimension without loss of alignment of one layer with the next. Since all of the openings are referenced to the geometric center of the layer rather than to any single edge, there is required a tolerance of only one-half of that which would be required if the registration openings are referenced from an edge of the layer. Thus, this unique arrangement of elongated registration openings, aligned with the geometric center of the carriers, greatly eases dimensional tolerance in manufacture of various layers, simplifies the assembly procedure and decreases cost of assembly.
Having fired the stack, it is removed from the oven and the complete hermetically sealed package is available for incorporation and/or mounting of the stacks by means of the solder bumps 156,158,160, etc. to another device, such as a printed wiring board or a multi-chip module or similar structure.
The reflow solder employed for the vias pads and seal strips is a high temperature solder, having melting point that is as much as 70� higher than the low temperature solder employed for the mounting solder bumps or pads 156,158,160 (FIG. 4). Accordingly, when the latter are softened or melted for connection and mounting of the entire stack, the integrity of the stack internal solder interconnections is not affected. The solder bumps 156,158,160 may be positioned in wells on the printed wiring board or the multi-chip module and reflowed to provide mechanical and electrical connection.
The solder interconnections also provide good thermal paths throughout the entire length of the stack from top to bottom and also from inside to outside because of the close proximity of one solder pad to another and to the perimetral hermetic seal.
Alternatively, tape automated bonding structures may be attached to the lower solder bumps 156,159,160, with the tape automated bonding structures extending past the edges of the stack so that outer leads of the bonding structure may then be connected to pads on a printed wiring board or multi-chip module.
The thin dielectric ring-shaped cover layer 110 that surrounds each of the via pads acts as a solder dam to prevent flowing or wicking of solder from one pad to another or from one pad to exposed leads of the traces. This dielectric ring-shaped layer 110 acts as a solder dam, at least in part because it effectively prevents flow of solder along its surface.
An important feature of the present invention is shown in FIGS. 2 and 3 and more conceptually illustrated in FIG. 5. FIG. 5 illustrates a via pad, such as pad 41a of the top side of via 40 of a lower carrier layer and a corresponding contacting via pad, such as pad 137b at the bottom side of an immediately adjacent relatively upper layer.
As can be seen in FIG. 5, each of the via pads has a length of approximately three times its width, with its width being approximately equal to the diameter of the associated via, which is in the order of about 5 mils. With the illustrated arrangement there is a contact area between the two mutually perpendicular pads, when precisely oriented, with the contact area being indicated by the shaded area 170. This contact area is nominally a square with an equal length of non-contacting via pad extending on all four sides of this square. These mutually orthogonal contacting pads greatly ease dimensional tolerance limitations because they allow for misalignment of one pad with a contacting pad by a distance equal to as much as one-third of its length in either direction without diminishing the contacting area indicated by shaded area 170. For example, even if there should be a misalignment to the right or to the left or up or down, as viewed in FIG. 5, the contacting area 170 still remains as a square having the same area, until the misalignment becomes greater than one-third the full length of the elongated pad. If the pads were of equal or comparable shape and size to one another, any such misalignment would cause an overlap in the contacting of the pads and at least a partial relative displacement, and thereby would significantly decrease the contacting area. Accordingly, the orthogonal orientation of each pair of contacting pads provides for a uniform area of contact, even in the presence of some misalignment, and thereby ensures that each contacting area provides a uniform electrically conductive area, mechanical bond strength, and thermal path area. Moreover, the areas of the pads outside of the contacting shaded area 170 will direct any excess flow of contacting solder and confine it to the area of the pad. In other words, any excess flowing solder which may occur during the reflow process will flow in the direction of the arrows shown in FIG. 5 and be confined to the pad area. The elongated pads do not significantly impact upon available area for positioning of traces since portions of some of the traces may be readily routed beneath the areas of the pads that project beyond the common contacting or shaded area. By maintaining uniformity of the contacting area, and thereby uniformity of thermal path area, of mechanical strength and of electrical path area at each via pad connection, the system is greatly improved. Mechanical strength is improved because mechanical failure generally occurs at the weakest mechanical point, that connecting area in which the solder interconnection from one via pad to the other has a decreased area because of misregistration. Electrical uniformity occurs because of the uniformity of the contacting area and similarly thermal conductivity from pad to pad, and thereby from top to bottom of the entire stack, is increased for each thermal path that extends through aligned vias from top to bottom of the stack.
Input/output connections to the stack are made through the via pads at the bottom 156,158 and 160, and further input/output connections are made to the via pads 137a,139a and 141a on the lid or uppermost layer 132. Each carrier is connected to all other carriers, and to external input/output connections (e.g., the outermost via pads) through the many vias which extend completely through the stack and all carriers. As can be readily seen from FIGS. 2 and 3, the number of these input/output connections, that is the total number of via pads available in any one horizontal outside layer (namely the uppermost and lowermost layers), is very large, and thus a significant increase in the number of input/output connections to the stacked chips is available with the arrangement of the present invention.
A stack embodying principles of the present invention will exhibit dramatic decreases in size, weight and power. The decrease in size and weight is due to the decreased overall volume of the stack, which allows utilization of all of the chip pads and provides a large number of input/output connections. The number of these connections is not constrained or restricted by the area of the side of the stack. Further, because of the compact arrangement and the mode of interconnection of chips from one layer to another, the total length of leads employed internally of the stack is less, and, importantly, the length of individual leads is less. Because of this decrease in lead length, the stray capacitance of the package is greatly reduced. Stray or distributed capacitance, as is well known, may cause power losses in excess of fifty percent. Because the power loss is related to the stray or distributed capacitance of the circuit, performance is enhanced by greatly decreased power loss. Further, the shorter length of leads not only decreases the stray capacitance, it decreases the travel time of signals within the package, thereby enhancing speed. Accordingly, circuit performance is enhanced because of the decrease in capacitance and the decreased time of travel of signals within the package allowing greater component and system operating speeds.
Total thickness of each individual carrier may vary between 18 and 70 mils depending upon the number of layers in the carrier substrate and the thickness of the integrated circuit chips which are mounted on each carrier substrate. Chips vary in size and thickness and may have a thickness of between 5 and 25 mils and a rectangular configuration of from about 0.50 to 1.0 inches or more per side. A total carrier thickness is in the order of about 10 to 12 mils greater than the thickness of the chip that it carries. Note that each cavity of one layer carrier partially receives the chip mounted on the top side of the next lower carrier and also provides some space for the bonding wire. Limits on the number of possible carriers (and chips) in a stack are not presently known, but it is contemplated that a stack may have a height of up to 50 layers (e.g., 50 carriers, each with a chip thereon), with about a total of 0.020 inches for each chip layer (e.g., carrier plus chip). If a stack is laid on its side, the total number of layers may be significantly greater. In an exemplary single chip carrier the carrier substrate has a total thickness of 0.027 inches, with the center portion of the substrate, above the cavity, having a thickness of 0.009 inches. The outer carrier dimensions, in one example, are 0.790�0.790, and the cavity is 0.535�0.485 inches.
Although a wire bond connection of the integrated circuit chip to the layer traces is illustrated, it will be readily understood that other types of mounting of the chip on the substrate may be employed. For example, flip-chip mounting may be employed in which the chip is turned upside-down with its connecting pads facing the substrate on which it is mounted. The substrate has appropriate connecting pads for electrically connecting to the flipped over chip. The various traces can either be screened on or plated on. The flip-chip may be connected using either tape automated bonding or solder bumps.
Preferably, the solder employed on the high temperature solder bumps is a fluxless solder to prevent parasitic effects that may result from the use of flux.
The stack of layers provides an alignment of vias that extends from top to bottom of the stack to provide a continuous electrical and thermal path. The various chip leads and traces on each carrier, and on each layer of each multi-layer carrier, may be connected to one or another or any group of the vias so that any chip of the stack may be connected to leads on its same carrier and also to leads connecting to chips on other carriers. Accordingly, chips in any one stack may be interconnected to one another as desired or may be simply coupled to input/output via connecting pads without connection to any other chip in the stack.
Because the sealing strip is essentially made in the same fashion as are all of the traces and via pads, excepting that it is additionally coated with a reflow solder that is not applied to the conductive traces, the sealing is greatly simplified without compromise of sealing effectivity. No special types of materials or sealing rings are needed to be fabricated or assembled.
There have been described methods and apparatus for forming a stack of integrated circuit chips to provide an hermetically sealed package of minimum size and weight and greatly decreased power loss. A maximized number of input/output connections is available from a plurality of aligned vias that collectively extend from top to bottom of the stack, providing arrays of input/output connections on upper and lower surfaces of a stack rather than merely on peripheral edges. Simple precision alignment of the layers of the stack, allowing thermally induced dimensional changes, is provided by use of elongated registration openings, each having an axis that intersects the geometric center of each of the associated layers.
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Korea Republic boss Cho Kwang-rae felt his side's display merited all three points against Australia after Mile Jedinak's second-half header salvaged a 1-1 draw for the Socceroos at Al Gharafa Stadium
Koo Jo-cheol's third goal of the tournament had put Korea in front after 24 minutes of the Asian Cup Group C clash, only for Jedinak to nod home an equaliser just after the hour mark. Both sides missed a number of decent opportunities in an entertaining game, but Cho believed his side should have come away with maximum reward for their efforts.
"We could have won the game if you see the general performance of our team. We could've won the game," he said. "It could've been better when it came to the result tonight. For the fans, it was a great game to watch and I am quite appreciative of the players' performance today.
"I think that we controlled the game and in that aspect, we've improved quite a lot," he went on. "With the fact that we can control the game with any other team in the tournament I am quite pleased about that, and if we can continue to develop that aspect of our game, it will be much better for us."
Australia boss Holger Osieck was delighted with the way his side battled back from a goal down to leave both sides level on four points at the top of the group with one round of games remaining. "I think we have seen a high standard match, both teams have great potential and we've seen that today," he said.
"It was end to end, both teams tried to play football. It was not just entertaining but from the technical point of view it was very good," the coach continued. "I'm very happy with our performance, our plan to close them down in midfield was mostly achieved. We knew about their strength and you could see that on a couple of occasions but what was most encouraging for me was that we created a lot of chances, in particular in the first-half that we could have converted.
"But we never gave up and got the goal, we came back into the game, we didn't just fight, we tried to play."


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Development will be the election plank, says party spokesperson
The Bharatiya Janata Party (BJP) will contest all the 189 seats across seven urban local bodies (ULBs) in Dakshina Kannada in the elections to be held on March 7, according to K. Monappa Bhandary, MLC and spokesperson of the district unit of the party.
He told presspersons here on Tuesday that in the election held for ULBs in the district in 2007, the party had contested 157 seats and had an alliance with the Janata Dal (Secular) in Moodbidri Town Municipal Council. Mr. Bhandary said the BJP candidates had won in 84 wards in the 2007 election and expressed confidence that the party would win 125 seats this year.
The BJP had won 34 wards out of 60 in the Mangalore City Corporation in the last election. Mr. Bhandary said that of the 27 wards in Puttur Town Municipality, the BJP had won 15 wards and in Bantwal Town Municipality the party had bagged 10 seats out of 34.
In Moodbidri Town Municipal Council, the party had won four seats out of 23 and won six seats in the 27-member Ullal Town Municipal Council. In Sullia Town Panchayat, the BJP had won nine out of 18 wards while in Belthangady Town Panchayat it had won four out of 11 wards.
Mr. Bhandary said the party gained power in Bantwal Town Municipal Council despite being in minority for "political reasons". The party ruled the Mangalore City Corporation, Puttur Town Municipal Council, and Sullia Town Panchayat.
He said the party would seek votes on the basis of development work carried out in the last five years. He claimed that there were no groups in the party at the State-level. The internal bickering had ended after some leaders quit the party and formed Karnataka Janata Paksha (KJP).
Keywords: Dakshina Kannada, BJP, Karnataka politics, ULB elections, KJP


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- Category: Hockey Rambling
- Written by Michael Amato
Heatley, Rinne, the Sharks getting younger, and more
So Bruce Boudreau wants to play Dany Heatley with Ryan Getzlaf and Corey Perry next season, making him a fairly valuable commodity to have on your roster. Dustin Penner had success there last year posting 13 goals in 49 games and then Patrick Maroon took advantage of ice time with the duo later in the season.
I'd expect Heatley to have similar success and he could be in for a 25-30 goal season. The question is how early should you draft him in a one-year league? Heatley probably falls into the category of a sleeper at this point, but with news like this he is going to start to get talked about more and more and he's likely going to vault up many people's draft board.
As an example, for those of you into fantasy football, Jay Cutler was in a similar position. Earlier in the summer he was looking like a nice sleeper that you could snag outside of the quarterback elites like Rodgers, Manning, and Brees, but as we got closer to draft time more and more buzz started to generate about the numbers Cutler could put up throwing to Brandon Marshall and an emerging Alshon Jeffery, he was going above his initial ADP (average draft position).
Something tells me if you want Heatley this year you are probably going to have to draft him a round or two ahead of where he should probably be taken, because come late September he's going to be on everybody's sleeper list. It's getting harder and harder to find real sleepers these days with all the information available.
Speaking of where players will be taken in drafts, where exactly does Pekka Rinne land? He might be an interesting one to look at because there should be some uncertainty in Nashville this season.
With Barry Trotz and his goalie friendly system no longer with the Preds, does that hurt Rinne at all? Also keep in mind he's going to be coming off the hip issue that cost him most of 2013-14.
Rinne played 43-of-48 games in the lockout shortened season and 73-of-82 the year before that, but I have a hard time believing he stays on that pace given last year's injury and his age. Carter Hutton also demonstrated himself to be serviceable at times last year, which might make Nashville more apt to give Rinne an extra night off here and there.
Still, Rinne is a great goaltender and the aforementioned factors might make a few poolies go in another direction when drafting this time around, meaning you might be able to get a bit of a bargain when drafting him. If you're able to wait an extra round or two before scooping Rinne you could bolster other areas of your roster first and give yourself a bit of an advantage.
Here's a nice piece from Jason Kay of The Hockey News looking at long-term deals and if the make sense based on when players hit their peak.
The answer depends on your perspective. If you're demanding equal value across all seasons, prepare to be disappointed. The evidence shows that, apart from notable exceptions, returns diminish on players beginning in their early 30s.
Anecdotally, if you retrace steps over an eight-season span (from the summer of 2006 to the summer of 2014), the tales mostly reflect the numbers. Joe Thornton, Brad Richards and Dany Heatley – all in their mid-20s back then – were three of the league's biggest stars. Today they range from declining cornerstone to question mark to last chance saloon.
The San Jose Sharks will be returning largely the same team that collapsed last spring against the Los Angeles Kings, but it could include some new youngsters in the lineup. The team plans to give some prospects a good look in training camp to see if they will make the team.
Keep an eye on Pittsburgh Penguins defenseman Derrick Pouliot during training camp. He played under new head coach Mike Johnston in Portland and the bench boss believes he is ready to make the jump to the NHL.
"Yeah, I do. For sure," Johnston said. "Not only his play in Portland, but the thing that convinced me the most was last year at the World Juniors. I really thought Derrick was the best defenseman in the tournament. If you can play at that level on the world stage, yeah, you're ready."
St. Louis Blues head coach Ken Hitchcock thinks Ian Cole could be in the team's top six full-time next season.
"This is a real opportunity for Ian," Hitchcock said. "He's paid his dues. He spent time in the minors. He's spent time as the seventh defenseman. He's matured as a person and as a player. It's his time. There's an open spot, a regular shift. There's everything there waiting for him, just step up and grab it."
Some of Pouliot's work
Michael Amato is an Associate Editor for DobberHockey and a News Editor for theScore. You can follow him on Twitter at @amato_mike
If you draft him for his true purpose, assists, +/- and reasonable PPP, he's still a pretty valuable fantasy asset that is above and beyond "declining cornerstone"
He finished 2nd to Crosby in assists last season, which is absolutely great value for the assists column given that on average he was taken 50 some odd picks after Crosby...
One thing that you have to keep in mind is that it's relative to league scoring too... You can't necessarily look at raw numbers and say well first five years he produced this, last 4 seasons he's produced this and then generalize that he's declining...
A factor that you have to take into account is that in those first five years 05-10... those were the "glory days" of NHL scoring with elevated PP opportunities/s coring was up/goalie sv% was down, now that it's regressed back to "stalemate hockey", so you have to take that into consideration if you're going to draw a conclusions about differences in scoring.
05-06- 1st
06-07- 2nd
07-08- 5th
08-09- 11th
09-10- 8th
10-11- 24th
11-12- 14th
12-13- 32nd
13-14- 13th
His last 4 seasons he's had 263 points in 292 games.
Are you arguing that he's not 'declining'?


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Scotiabank today announced that it will launch the Scotiabank Mobile Banking app on the Apple Watch.
Customers of Canada's Scotiabank can now check their account balances with a quick glance at their wrists, as the bank unveils a new app for the Samsung Gear range of smartwatches.
Canadian digital bank Tangerine is revamping its mobile app to enable customers to log in using Apple's Touch ID technology and issue commands through speech.
Wells Fargo & Company (WFC) announced today that it has added SCOTIABANK and Remesas BAC Credomatic to its network of ExpressSend® payout locations in El Salvador. The new remittance network members will bring the total number of payout locations in El Salvador to more than 500, along with more than 1,200 ATMs.
Startup Lenddo has launched a 'social network' credit card in Colombia that will see applicants approved or declined based on their reputations on Facebook and Twitter.
ING Direct has changed its name to Tangerine. The name change is the result of ING Direct's sale by ING Groep to Scotiabank in 2012. Tangerine will continue to operate as a wholly-owned subsidiary of Scotiabank.
Fenergo today announced that the firm's Regulatory Onboarding solution has been launched by Scotiabank, Canada's most international bank.
ING Direct announced today that, effective spring 2014, it will operate under the new name Tangerine. The Bank also revealed its new visual identity at a unique unveiling event held today at the Toronto Centre for the Arts for employees, partners and media, and via live stream for clients.
CGI (NYSE: GIB) (TSX: GIB.A) today announced that Scotiabank, a leading multinational financial services provider, has completed the Canadian rollout of CGI's cloud-based, customizable SaaS solution, CGI Trade360.
Scotiabank, the Canadian-based bank providing a complete range of retail, commercial, corporate, investment and international banking services, has appointed Red Box Recorders as its preferred partner for call and data recording for Scotiabank Trading floors.
© Finextra Research 2015


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I don't think the GOP is going to go in this direction on foreign policy
- By Daniel W. Drezner
Daniel W. Drezner is professor of international politics at the Fletcher School of Law and Diplomacy at Tufts University and a senior editor at The National Interest. Prior to Fletcher, he taught at the University of Chicago and the University of Colorado at Boulder. Drezner has received fellowships from the German Marshall Fund of the United States, the Council on Foreign Relations, and Harvard University. He has previously held positions with Civic Education Project, the RAND Corporation, and the Treasury Department.
Conor Friedersdorf has an provocative essay over at The Atlantic in which he states a few hard truths about the state of the GOP on foreign policy… and then goes to a very strange place. The hard truths first:
President Obama's foreign policy is vulnerable to all sorts of accurate attacks. But Mitt Romney, the Republican Party, and the conservative movement are totally unable to exploit them. This is partly because the last four years have been spent advancing critiques so self-evidently implausible to anyone outside the movement that calling attention to them seems impolite. There is no factual basis for the assertion that Obama rejects American exceptionalism or that he embarked on an apology tour or that he is allied with our Islamist enemy in a "grand jihad" against America; or that his every action is motivated by Kenyan anti-colonialism. And while those critiques are especially inane, they aren't cherry-picked to discredit conservatives; they're actually all critiques advanced by prominent people, publications, and/or Republican politicians.
The fact that the vast majority of conservatives give no indication of having learned anything from the Iraq War is an even more significant reason that the GOP has lost its traditional edge on national security issues, with a majority of Americans telling pollsters they trust Democrats more.
OK, I'm with him so far. But then we get to how Friedersdorf thinks the GOP should ground its criticism:
So what could an opposition party less dysfunctional than Republicans say about Obama's foreign policy?
1) The Afghan surge turned out to be a failure that cost a lot of American lives and money with little if any lasting benefit.
2) In the course of the successful Bin Laden raid, the Obama Administration ran a fake vaccination campaign that failed in its mission to get the fugitive's DNA, failed to stay secret, and undermined public health efforts in Pakistan and elsewhere for a generation — a catastrophic bungle that could conceivably make the world more vulnerable to a pandemic in the future.
3) Obama's main counterterrorism strategy, secretive CIA drone strikes in multiple Muslim countries, scatters terrorists to more countries than they'd otherwise be in, arguably creates more terrorists than it kills over time, and has definitely killed hundreds of innocent people at minimum.
4) Agree or disagree with the idea of intervening in Libya, the way President Obama went about it violated the U.S. Constitution, the War Powers Resolution, and an Obama campaign promise.
There are a lot more critiques of Obama's foreign policy. It's instructive to focus on these because they're just the sorts of things you can't attack if your party defines itself as most hawkish; totally discounts the importance of things like public health compared to military operations; doesn't pay any attention at all to dead innocents killed by America; and has totally abandoned Madisonian notions of checks and balances when it comes to national security policy (emphasis added).
I don't necessarily disagree that these lines of attacks exist — but I also don't think that Friedersdorf comprehends the history of the GOP on foreign policy — and I'm not just talking about the post-Cold War era. As Colin Dueck noted in his book Hard Right, the Republicans have been branding themselves as the more hawkish party since Thomas Dewey faded from the scene. Sure, the Ron Paul wing would love these lines of attack — but I don't think either the rest of the GOP or the rest of the country for that matter is gonna dislike the drone strategy.
I agree that the GOP has made its mistakes in its foreign policy critiques, but the kind of conceptual pivot that Friedersdorf expects Republicans to make strikes me as pretty absurd.
So what should the GOP do? I'm not entirely sure, but I do know two things:
1) The Republican Party can't summarily reject the hawk brand it's built for more than a half-century;
2) Unless and until the GOP acknowledges that Iraq was a tragedy and a mistake, it will be as enfeebled on foreign policy as the Democratic Party was on this issue for a generation after the Vietnam War went south.
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COLUMBUS GROVE – There were many momentum swings when the Lima Central Catholic girls basketball team traveled to meet Columbus Grove Thursday evening.
But the Bulldogs grabbed the swing that mattered and rode a big fourth period comeback to grab a 58-57 victory.
Columbus Grove (6-3) grabbed a quick 14-11 lead after one period of play and the two teams picked up the pace in the second quarter as the Thunderbirds outscored the Bulldogs 22-21 in the second quarter but still trailed at the half by a score of 35-33.
LCC (6-2) got a big first half from Meredith Shepherd who connected for 14 points that came on the strength of three 3-pointers.
The Bulldogs, meanwhile, got 11 first half points from freshman Jade Clement that also included three 3-point baskets.
"Jade doesn't play like a freshman," Grove coach Brian Schroeder said. "She did a nice job for us tonight but she has been clutch all year."
The Bulldogs opened the third period with five quick points that gave them a seven-point lead at 40-33. But, the T-Birds promptly regained the momentum and responded with a 19-5 run that gave them a 52-45 lead going to the final period of play.
And just as suddenly, the lid went on the LCC basket and they wouldn't hit the first bucket of the fourth quarter until only one minute remained in the game.
The Bulldogs Sydney McCluer then connected on a driving layup. A costly T-Birds turnover led to two free throws by McCluer and a last second 3-pointer by LCC's Natalie Snider made the final score a one-point margin and Grove had more wins before the end of December than they did all last season.
"This was an emotional win for us, we only won five games last year," Schroeder said. "We lost a lot of close games last year but we kept our poise tonight; we made plays when we needed to and had defensive stops when we needed them."
Grove was led on offensive by Clement and Rachel Schumacher who both finished with 13 points. The Bulldogs also got nine points from Sammy Stechschulte and Julia Wynn.
"We had that long stretch without scoring and you just can't do that against good teams," LCC coach Katie Krieg said. "Our shot choice wasn't good tonight, and we gave up too many offensive rebounds that led to put backs by their big girls."
LCC got a game high 17-point effort by Shepherd while Kayla Verhoff added 11 points and Madison Stolly chipped in with 10 points for the T-Birds.
Grove pulled down 30 rebounds in the game compared to only 21 for the T-Birds and both teams committed 13 turnovers in the contest.
LCC connected on 21-of-43 from the field and the Bulldogs knocked down 21-of-46 from the floor.
The difference may have been at the free throw as the T-Birds only made 6-of-11 in the game while the Bulldogs connected on 9-of-15 from the charity stripe.