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A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.
1. A method of operating a non-volatile memory system including an array of floating gate memory cells arranged in rows and columns and characterized by at least one type of defect in a column rendering inoperable all of the cells in that column, comprising:
operating the memory system with the rows of the array separated into unique blocks of cells that are individually addressable for simultaneous erasure of the cells within an addressed block,
maintaining a list identifying any inoperable columns,
designating a plurality of contiguous columns, not including a column on said list, for storage of at least one chunk of overhead data within the individual blocks and designating memory cells of columns other than those designated for overhead data for storage of a plurality of chunks of user data within the individual blocks,
writing user data to and reading user data from memory cells, at least one chunk at a time, of the individual blocks that lie in columns designated for the storage of user data, and
writing overhead data to and reading overhead data from memory cells, at least one chunk at a time, of the individual blocks that lie in columns designated for overhead data, said overhead data including information about the individual blocks themselves or any user data stored therein.
2. The method of claim 1 wherein the writing of user data to and reading user data from memory cells of the individual blocks includes addressing cells within said other columns by reference to said inoperable column list.
3. The method of claim 1 wherein the overhead data written to and read from individual blocks includes a flag that designates whether an addressed block is defective or not.
4. The method of claim 3 wherein the overhead data written to and read from individual blocks includes, when said flag indicates that an addressed block is defective, an address of a substitute block.
5. The method of claim 1 wherein the overhead data written to and read from individual blocks includes a count of a number of times that an addressed block has been erased.
6. The method of claim 1 wherein the overhead data written to and read from individual blocks includes an electrical parameter a previous erase cycle of an addressed block.
7. The method of claim 1 wherein the overhead data written to and read from individual blocks includes an error correction code calculated from the user data stored in memory cells within columns designated for storage of user data.
8. The method of claim 1 wherein the overhead data written to and read from individual blocks includes an error correction code calculated from the overhead data stored in memory cells within columns designated for storage of overhead data.
9. The method of claim 1 wherein the overhead data written to and read from individual blocks includes addresses of any defective cells within columns of respective individual blocks that are designated for storage of user data.
10. A method of formatting a flash EEPROM memory system having floating gate memory cells arranged in a two dimensional array of a plurality of columns and a plurality of rows thereacross, comprising:
grouping the rows of cells into unique blocks of cells which are individually addressable for simultaneous erasure of the cells within an addressed block,
identifying any columns within the array that include a defect and storing a list of such defective columns,
designating a plurality of contiguous cells in the individual rows of the array that do not include a defective column included on said list for receiving a chunk of a plurality of bits of overhead data, and
storing column addresses of said designated chunks, whereby overhead data about the individual blocks and any user data stored therein may be recorded in the chunks.
11. A non-volatile flash EEPROM system, comprising:
an array of floating gate memory cells arranged in rows and columns, the rows being separated into individual blocks that are addressable for erasure together of the memory cells in the individual blocks, and the columns being grouped together into a plurality of unique chunks of memory cells within the individual rows that are each positioned in a plurality of contiguous columns,
means for addressing the individual blocks by designating addresses of the chunks therein,
means for maintaining a list of any defective columns within the array,
means for maintaining an identification of at least one chunk of columns within the array that does not include a defective column noted on said list, and
means for addressing said at least one chunk of columns within the individual blocks for storing overhead data relating to the blocks.
This is a continuation of application Ser. No. 08/252,052, filed Jun. 1, 1994, now U.S. Pat. No. 5,438,573, which in turn is a continuation of application Ser. No. 07/759,497, filed Sep. 13, 1991, now abandoned.
This invention relates generally to solid state mass storage systems, and, more specifically, to a file structure for storing data in such systems.
Low cost mass computer storage systems have traditionally used mechanical devices employing magnetic storage media, such as hard disk drives, floppy disk drives and tape. Such memory systems have been very effective and have provided a large amount of data storage capacity at a low cost for use in computer systems. However, there are certain drawbacks to the mechanical/magnetic media systems that have limited development of computer systems and their applications. The mechanical systems lack desired ruggedness for certain applications, such as portable computers, have a limited life due to mechanical wear, and require significant amounts of power to operate them, again a disadvantage in portable computer systems.
As a result, large solid state memory systems have been proposed and have been developed for replacing hard and floppy disk drives. The most promising solid state technology is electrically erasable and programmable read only memory ("EEPROM"). This technology provides non-volatile memory that can be erased and reprogrammed tens of thousands of times. A flash EEPROM system allows erasure of the entire memory or designated portion of the memory at one time, i.e., in a "flash".
It is desirable that such a flash EEPROM memory system be able to communicate with a computer system of which it is a part as if the memory is a disk drive. That is, since computer circuitry and operating software for communicating with a hard disk drive, for example, has been fully developed as an industry standard interface for mass storage of data, it is desirable that a flash EEPROM memory system also communicate with the computer system in the same manner. Much of the control and status communication between a computer system and a hard disk drive is not applicable for a flash EEPROM system, while other control and status information is necessary but must be changed in form. An appropriate controller is provided as part of flash EEPROM system for providing that translation.
A usual disk drive records data from the computer system in physical sectors having a certain capacity, such as 512 bytes, plus a large number of bytes that go along with each sector of data as a header to identify control information about the sector of data and its disk location (address). It is also desirable in a flash EEPROM memory system to store data in blocks and provide header information as part of each block. Therefore, it is a principal object of the present invention to provide a data and header block file storage technique in a flash EEPROM mass storage system that takes full advantage of the capabilities of the EEPROM technology, but without retaining limitations of the disk storage technology.
This and other objects are accomplished by the various aspects of the present invention, wherein, briefly and generally, integral blocks that each contain a sector of data and header information are stored in blocks of memory cells which are simultaneously erasable upon the block itself being addressed. The header includes block identifying information in terms appropriate for a solid state memory and error detection/correction codes for the sector of data in the header information. Spare cells are provided as part of the header to replace any defective cells in the data sector portion of the block, pointers also being included in the header to identify the bad cell locations which are then replaced by one of the spare cells. Other header information includes a field containing a count of the number of times the block has been erased and the voltage level used during the last successful erase of the block. A header is also provided with a field containing a pointer to another block in the case where the current block has so many defective cells that it cannot store the required number of bits. Certain header information is read by the memory controller preceding a read, write or erase operation being performed on the block.
In a preferred form of the flash EEPROM file structure according to the present invention, the blocks are each formed from a plurality of contiguously addressable rows of memory cells extending across the same contiguously addressable columns of a two-dimensional array of cells. The header is formed from certain columns in each of the block's row. A number of spare cells are provided in each row of the header that are used to replace any defective cells of the data sector in that row. Additionally, an error correction code for each row of data is preferably stored as part of the header area in each of those rows. One or more error correction codes is also desirable for at least some of the header information itself and is also stored as part of the header. A few spare cells can also be provided as part of the header with pointers therein to bad cell addresses which are then replaced by the spare cells. In order to improve the probability that the header fields will be located in areas that do not have bad cells, the header is, according to a preferred embodiment, implemented in two narrow portions that can be separately positioned, one portion containing the spare cells for each data sector row and an error correction code for data of that row, while the other header portion contains various block identification information described above.
Additional objects, features and advantages of the various aspects of the present invention can be had from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.
FIG. 1 is a schematic block diagram illustrating a flash EEPROM system in which the file structure of the present invention may be utilized;
FIG. 2 shows a typical prior art hard disk drive data block structure;
FIG. 3 illustrates organization of the memory in the system of FIG. 1;
FIG. 4 shows further details of a preferred organization of the memory illustrated in FIGS. 1 and 3;
FIG. 5 illustrates the type of information stored in one of the header portions shown in FIG. 4;
FIG. 6 illustrates the type of information stored in another of the header portions shown in FIG. 4;
FIGS. 7A and 7B are a flow diagram that illustrates generally the operation of the controller module of the memory system of FIG. 1 when utilizing a file structure shown in FIGS. 3-6;
FIG. 8 is a flow diagram that amplifies a block of FIG. 7 to show the process of reading one of the header portions;
FIG. 9 is a flow diagram that shows the data reading process block of FIG. 7; and,
FIG. 10 is a flow diagram that shows the data writing process block of FIG. 7.
Before proceeding to describe the flash EEPROM memory file structure in detail, a typical memory system utilizing such a file structure is discussed with respect to FIG. 1. A computer system 101 has an architecture that includes a microprocessor 121 connected to a system bus 123, along with a random access, main system memory 125, and one or more input-output devices 127, such as utilized with a keyboard, monitor, modem and the like. Another main computer system component that is connected to a typical computer system bus 123 is a large amount of long-term, non-volatile memory 129. Conventionally, such mass data storage is provided by a hard disk drive having a capacity of tens of megabytes of data storage.
In this case, however, the mass memory 129 includes one or more solid state memory modules, such as modules 131 and 132, which are under the control of a controller module 133. Each of the memory modules 131, 132, etc., includes at least one, but preferably several, such as four, flash EEPROM integrated circuit chips. Addresses, data, commands and status signals are communicated between the memory modules 131, 132, etc., and the controller module 133 by way of a device bus 135. Individual modules are selected by control signals in respective circuits 151, 152, etc. The controller module 133 is connected to a bus interface circuit 137 by means of an interface bus 138. The interface circuits 137 are connected, on the other hand, to the computer system bus 123. For personal computer systems, the bus interface 135 preferably conforms to the integrated device electronics ("IDE") standard.
Additional details of the mass storage memory system 129 and variations of it are provided in a co-pending patent application Ser. No. 07/736,733, filed Jul. 26, 1991, entitled "Device and Method for Controlling Solid-State Memory System", and naming Robert D. Norman, Karl Lofgren, Jeff Stai, Anil Gupta and Sanjay Mehrotra as inventors, which is incorporated herein by this reference. The physical form of the mass storage memory 129 can be a very small memory card conforming to existing physical and electrical interface requirements, or in a package sized to be substantially the same as that of a hard disk drive, thereby being directly replaceable for the disk drive, or the like.
Before proceeding to a description of the preferred flash EEPROM file structure for use in the system of FIG. 1, a typical data structure for hard disks is summarized. Data is stored on magnetic surfaces of hard disk along a plurality of concentric tracks that are usually defined in terms of an intersection of a plurality of concentric cylinders with the disk surfaces. A specific track is usually specified by identifying the read/write head to be utilized and the cylinder in which the data is recorded. Each of the tracks is further divided around its circumference into blocks, such as 17 blocks per track, each of which includes a sector of data, such as 512 bytes according to the most popular standard, along with header information. A single data read or write operation generally involves access to a large number of sequential located blocks.
FIG. 2 illustrates the file structure for a typical hard drive block. A GAP1 field 161 is typically 16 bytes in length and is used for controller overhead and speed variations. A next field 163 includes the address mark ("AM") which is typically 4 bytes in size and is specially decoded to tell the controller that it is entering a field of zeros. A PLO SYNC field 165, typically 25-35 bytes in size, contains a special pattern, normally zeroes, which is used by the controller to turn on a phase lock loop for clock alignment and generation. A next field 167 is a SYNC one byte or two bytes that is used by the controller in obtaining bit alignment.
A next field 169 of a typical hard drive data block structure provides identification for use by the controller to verify positioning in the drive. It is typically 6 to 8 bytes in length. Subfields within the portion 169 include cylinder high and low fields 171 and 173 which together define the disk cylinder location of the present block. A subfield 177 specifies the head that is being used. Another subfield 179 defines the sector location of the subject block. Additional bytes 181 and 183 are used as flags to the controller. These flags carry information as to the usage of the sector block being read. Typical information is whether the block is good, is a spare, or if defective, and where the spare is located. These flags only point to block types of failures and do not allow for defect handling within the block itself.
A next field 185 of the hard block structure of FIG. 2 is an error detection/correction code ("ECC"), typically 2-8 bytes in length. Following that is a PAD field 187, typically 4 bytes, that is used for write splice turn on or off. A next portion 189 includes another PLO field used to resynchronize the phase lock loop after a write splice. Following that is a 1 or 2 byte SYNC field 191. The data being transferred, typically a 512 byte sector, is included in a portion 193, followed by another error correction code 195 and another PAD field 197 of 4 to 8 bytes in the usual case. The second PAD field 197 is used to support write splice turn off and spin speed variations. There are many variations of the format described with respect to FIG. 2 but this is being described as typical, by way of background.
Before describing the flash EEPROM file structure, which is significantly different than that described with respect to FIG. 2, it is interesting to note which parts of the hard drive block structure that are used to operate the solid state memory. The controller module 133 (FIG. 1) receives a block data transfer with such a format. The controller ignores, however, all of it except for the identification portion 169, the EECs 185 and 195, and, of course, the data 193. All other fields of the FIG. 2 block structure have something to do with mechanical aspects of the disk drive, and so are unnecessary in a solid state memory. The block identification information field 169, in effect, provides an address of the data block in disk drive terms which is received by the controller 133 and translated by it into a solid state memory block address, as described hereinafter. The ECCs 185 and 195 are used by the controller to check the accuracy of the data transferred into its buffer memory from the computer system bus, but then create and store in the solid state memory additional ECCs, as described hereinafter.
In a preferred physical arrangement, as schematically illustrated in FIG. 3, each of the individual EEPROM integrated circuit chips in the memory modules 131, 132, etc., has its memory cells arranged in four quadrants. The quadrants of a circuit chip 201 is indicated in FIG. 3. The organization of each of the chip quadrants is shown at 203, containing, in this example, 256 blocks. The organization of one of these blocks is indicated at 205. The EEPROM cells are logically arranged in addressable rows and columns, as is typical for solid state memories. The memory organization illustrated herein also provides the memory cells physically arranged in such a row and column configuration but such a physical arrangement is unnecessary so long as the individual cells can be addressed by applying appropriate voltages to the correct row drive lines and column bit lines of the array.
In a preferred arrangement 205 of a typical block, a plurality of rows of cells, in this case four rows, are used. Each row extends across the same group of columns. The block is divided into two major portions, a data sector 207 and an overhead portion 209. Each of the two portions 207 and 209 extends across all four rows of the block with common column addresses. The overhead portion 209 is divided into two stacks 211 and 213, each stack occupying a small number of the same columns of each of the rows of the block. The overhead groups of cells are said to be organized into a "stack" since portions of each row are stacked on each other. Each of the two stacks is preferably read separately, the cells in one row being read, followed by those in the next row, and so on. Data in the sector 207 is preferably read in a similar manner, one row at a time, the row portions included in the stacks being skipped.
The memory system of FIG. 1, in a preferred implementation, transfers data between the controller and EEPROM chip modules in eight byte chunks. Therefore, it is useful to show the organization of a block in terms of such chunks. With reference to FIG. 4, a memory block includes four rows of 18 chunks each. One chunk of each row at the same column address forms an overhead stack 215 and another vertically arranged group of chunks, one from each row, forms another stack 217. The remaining chunks shown unshaded in FIG. 4 hold the 512 bytes of sector data. By making the stacks 215 and 217 narrow, and by making them positionable away from each other in any of the chunk columns illustrated, it can be assured that at least the critical portions of the stacks are formed where there are no defective EEPROM cells. A primary characteristic of each of the blocks of the quadrant 203 (FIG. 3) is that all of the memory cells in that block are erasable at the same time by an erase pulse applied to a single addressed block.
It is unfortunately a fact of life that the memory will have certain defective cells upon manufacture and may develop others during use. In order to accommodate bad cells in the data sector region of a block, several spares are provided in each of the four rows of the block within the stack region 217. This is illustrated by spare cells 219, 221, 223 and 225 of FIG. 5. Also provided in each row is a field to store an ECC calculated from the data stored in the sector data cells of that same row. Referring to FIG. 5, a field 227 is provided for one of the rows, 229 for another, 231 for another and 233 for the last row of the block. The usual approach in mass storage systems is to calculate a single ECC for an entire sector of data of the size being discussed. The calculation and storage as part of the data block of four ECCs, one for each row, improves the system ability to determine when bad data exists and to then correct it.
In order to handle individual bad cells in the data sector portion of the block, seven bad bit pointer ("BBP") fields 235, 237, 239, 241, 243, 245 and 247 are provided. These fields are used to store the address of bad data sector cells within the same block. These pointers are loaded in the fields 235-247 in the same order as their corresponding bad cells are reached during sequentially addressing each of the cells, or pair of cells, in along each of the four rows of the data sector portion of the block. Their use is described more specifically hereinafter with respect to the process flow diagrams.
The stack 215 also has the ability to operate properly with a few bad cells in it. Fields 249, 251 and 253 can accept pointers to certain cell addresses within the stack 215. Six spare cells in an area 255 are provided in row 3. The stacks are read by addressing each cell, or a pair of cells simultaneously, in order from left to right across row 0, and then from left to right across row 1, and so forth. If a bad cell exists somewhere in rows 1-3, that cell is simply skipped during a reading or writing operation, and the bits thereafter are shifted a pair of cells in address, thereby using one of the spare cells of the area 255. If a second bad cell exists, a pointer is stored in the field 251 that indicates the bad cell address and the same bit mapping occurs.
The bad bit pointers stored in the stack 215 are loaded during a testing procedure of each EEPROM chip by the manufacturer. Any cells which are defective, because of an electrical short or for some other reason, are mapped out of the system by storing an appropriate pointer in one of the bad bit pointer fields described with respect to FIG. 6. It is important, however, for the file structure being described, that row 0 of stack 215 be located in a portion of the memory block where no defective cells exist. This is made possible because of the ability to move the stacks 215 and 217 from left to right (FIG. 4) by appropriately noting their chunk column addresses in the controller 133.
Another field 257 of row 0 of the stack 215 identifies whether the block in which the stack 215 exists is being used for data storage, or whether it has been reassigned. A field 259 of row 0 contains an ECC calculated from the remaining information stored in that row. The maximum possible care is taken to assure that the header bad bit pointers of fields 249-253 and the flag of field 257 are accurate.
Three additional fields are provided in row 1 of the stack 215. A field 261 contains either the address of the current block or, in case the flag in field 257 indicates that the current block is has been reassigned, contains the address of a substitute block that is to be used in its place. As pointed out below with respect to the flow chart of FIG. 7, the occurrence of an address of another block in the field 261 causes that other block to be accessed in its place.
A field 263 contains a number that indicates the erase voltage used during the last erase cycle on this particular block. In the process of being erased and rewritten tens of thousands of times, the EEPROM cells require the erase voltage to be increased over its lifetime. The voltage which was necessary for a complete erase during the most recent cycle is stored in the field 263.
Another field of row 1 of the stack 215, indicated at 265, stores the number of times that the block has been put through an erase and reprogramming cycle. This information can also be used to set operational parameters.
A final field 267 of the stack 215, located in its row 3, contains an ECC for the information stored in rows 1, 2 and fields 245 and 247 of row 3. This separate ECC allows careful monitoring of the accuracy of the bits read from rows 1-3 which affect operation of the memory.
In order to better understand the nature of the file structure described with respect to FIGS. 3-6, and the use of the information stored in the stacks, a general operational flow diagram is provided as FIG. 7. As indicated by a step 301, the controller module 133 (FIG. 1) is constantly monitoring any commands from the host computer received by it over the bus 138. When a READ or WRITE command is received, as indicated by a step 303, the controller 133 then reads the address of a data block or blocks presented in disk drive terms by the computer system and translates that address to a corresponding block or blocks of EEPROM memory, as indicated at 305. This address translation is preferably carried out by an algorithm, where there is a one-to-one correspondence between disk and EEPROM memory block addresses, or by use of an appropriate look-up table.
Once a given memory block is addressed, its stack 215 is read, as indicated by a step 307. The flags in the field 257 are checked in a step 309 to determine whether the addressed block is good or not. If so, then the field 261 is read, as indicated by a step 311, to make sure that the block which the controller thinks it has addressed is indeed the block addressed. The address in the field 261 is compared with the logical address of the block being addressed by the controller. If it does not compare, an error message is sent, as indicated at 313, and the host computer system then responds appropriately.
If a check of the flag bits in field 257 by the step 309 reveals that the block has been reassigned, then, in a step 315, the field 261 is accessed to read the address of the substitute block. A step 317 then substitutes that new address for that of the current block, and the process proceeds back to step 307 which occurs on the new block.
Once a good block has been addressed, after a proper comparison of block addresses in the step 311, a read operation 319 or a write operation 321 occurs, depending upon the nature of the command from the host computer system that is detected in a step 323. Once the commanded read or write operation occurs, as indicated in a step 325, it is determined from the commands sent from the host computer whether there are any other blocks involved in the current read or write operation. Since each block operation results in transferring only 512 bytes of data, in this specific example, there are generally many blocks transferred, one at a time in sequence. These blocks are arranged in address sequence in disk drives, so a translation of those addresses to the EEPROM memory blocks results in contiguous blocks of solid state memory also being used. Therefore, if additional blocks are being transferred, a step 327 increments the block address to the next in order block and the process is begun again with the step 307 for that new block. If, on the other hand, only one block is transferred, or after all blocks of a multiple block transfer have been handled, a step 329 occurs. This step tells the host computer that the transfer has been completed, and the controller then returns to steps 301 and 303 to look for any further read or write commands from the host computer. When one is received, the process is begun again at the top of FIG. 7.
Three of the process blocks of FIG. 7 are expanded in FIGS. 8-10. Referring to FIG. 8, the step 307 of FIG. 7 is shown in more detail. A step 331 first causes row 0 of the stack 215 (FIG. 6) to be read. As part of that reading operation, the ECC stored in the field 259 is expanded by running it through the ECC polynomial being used and the resulting data is compared in a step 333 with that of the other fields of row 0. If a mismatch of one or more bits occurs, a correction is attempted, as indicated in step 335, but, as indicated in a step 337, if the correction does not work, an error status flag is posted to the computer system, as shown in a step 339. The ECC technique utilized may be a standard forward and reverse polynomial of a common type used in hard disk drive data transfers.
If the data read from row 0 of the stack 215 is satisfactory, a next step 341 sets a compare function in the controller to include the pointer in the field 249 of row 0 of stack 215. A next step 343 then points to one or more bits in row 1 of the stack 215 which are to be read at the same time. In the example being described, data is transferred between the controller and the EEPROM chips a pair at a time. A comparison indicated at a step 345 looks to see if the addresses of the bit pair include that of the bad bit pointer in field 249 (FIG. 6). If not, the pair of bits is read, as indicated in a step 347. If, on the other hand, the addressed bits of row 1 include that of the field 249 pointer, a step 349 increments the bit address to the next bit pair in sequence along row 1. Since the bad bit indicated in field 241 has now been passed, the next bad bit pointer in a field 251 is, in a step 351, appropriately accessed and the process begins again with the step 345.
The result of incrementing the address is to skip over reading the bad bit, meaning that each of the bits in the rows 1-3 has been relocated one bit to the right of that indicated in FIG. 6, thus to include one of the spare bits in the field 255.
After each successful read of a pair of bits, a step 353 determines whether that read was the of the last bit pair of the stack 215. If not, the bit address is incremented in a step 355 and the process begins again with step 345 for that new address. Once all the bits have been read from the stack 215, however, a step 357 then expands the ECC in the field 267 and compares it with the data just read in rows 1, 2 and 3 of the stack 215. A step 359 indicates the usual attempt to correct that data, with a check at step 361 as to whether the data was corrected. If not, an error status is posted, in a step 363. If, of course, the result of the step 355 is a positive comparison of the data, the steps 359 and 361 are skipped.
Referring to FIG. 9, the process of reading sector data of the step 319 of FIG. 7 is shown in more detail. Certain common operations of the process of FIG. 9 with that described with respect to FIG. 8 will be referenced. A first step 365 sets the current controller compare circuitry to the first sector data bad bit pointer stored in the field 235 of the stack 215. In parallel with that, another portion of the current controller compare circuitry is set to a pointer that identifies the first bad column of the block being read, if any, as indicated by a step 367. Since it is not uncommon for an entire column of memory cells to be rendered inoperable by a short or other defect in its column bit line, it is easier to keep track of that column in a single pointer instead of storing a number of pointers to all of the individual cells in the defective column. The bad column pointers can be included as part of each block, as are the bad bit pointers, but in this example are stored in a separate group of sectors duplicated within the memory array for this purpose.
A next step 369 then points to the first bit pair of the first row of the addressed block in its data sector portion (that is, memory cells outside of the stacks). If that data address pointer compares with either of the bad bit or column pointers, as indicated by a decision step 371, then the address is incremented by one in a step 372 and the next bad bit or column pointer, depending upon which caused the match in step 371, is set in a step 373 for the next address comparison.
If, however, there is no such positive address compare in the step 371, the data in the addressed cells is read, as indicated at 375. At the end of a data sector row, having skipped the chunk within the stack, as determined by step 377, the ECC for that row, which is stored in the stack 217, is then compared with the data in a step 379. However, if there are additional bits of the data sector row that need to be read, the bit address is incremented, as indicated by a step 381, and the process returns to the decision block 371 for the new cell locations.
As is usual with an ECC, a step 383 follows if the expanded ECC does not compare with the data. A correction of that data is attempted in that step. If the data cannot be corrected, as indicated by a step 385, then an error status is sent to the host computer system, as indicated at 387. If the data is corrected, or if the expanded ECC does compare with the data in a step 379, a next step 389 determines whether all of the data sector rows of the current block have been read. If so, the read operation is complete and the process proceeds to the decision block 325 of FIG. 7. However, if all of the rows have not been read, then the bit pair address is incremented by a step 391 to the next row in sequence and the bad bit column pointer is reinitialized in a step 393 back to the first column in the block that will be encountered when incrementing along the row from column to column to read its data.
Referring to FIG. 10, a write operation 321 of FIG. 7 is shown in more detail. A first step 401 transfers the contents of the stack 215 into a buffer memory. The entire block is then erased, as indicated at 403, including the cells designated for the overhead stacks. This is preferably accomplished by a series of erase pulses simultaneously applied to each of the cells in the current block, with a read step occurring between the pulses to determine if the voltage of the cell has been reduced to an erased level. Once this occurs and all of the cells are erased, the erase level that was necessary to be used is written, in a step 405, into the field 263 of the stack 215 contents that are currently stored in buffer memory. As indicated by a step 407, the count in field 265 of the stack 215, as stored in the buffer, is also incremented to show this new cycle of erase and reprogramming. After that, the contents of the stack 215 are written back into the block of memory from the controller buffer memory, as indicated by a step 409.
The process of writing sector data into the block is then commenced. Steps 411, 413 and 415 correspond in function to steps 365, 367 and 369, respectively, described with respect to FIG. 9 for a read process. Similarly, a comparison step 417 and address and pointer steps 419 and 421 of the FIG. 10 write process correspond to respective steps 371, 372 and 373 of the FIG. 9 read process. When a bad bit or bad column is encountered in the sector data portion of the block as each pair of cells of a row are addressed in order, that defective cell or column is skipped. This results in the data sector then extending into the spare bits of the stack 217 for that row. The read process steps 371-373 of FIG. 9 then automatically result in skipping the same bad bits that are skipped by the steps 417-421 of the write process of FIG. 10.
Once a good sector data bit pair is found, data is written into it or them by a step 423. If all of the cells of a sector data row have not been written, as observed in a step 425, the row address is incremented in a step 427. Once all of the sector data cells in a row have been programmed, the ECC for that row of data has been calculated and now is written into the portion of the stack 217 for that row, per a step 429. The method step 429 for writing the ECC is the same as described above for data bits, wherein bad bit locations are skipped over during the write.
Once the ECC is calculated and stored for a given row of data, a decision 431 will cause the process to increment to the first bit pair of the next row, in a step 433, if all the rows have not yet been programmed. If this is the case, the bad bit column pointer is initialized, in a step 435, prior to beginning to write data into the next row.
Once all of the rows have been written, all of the sector data is read in a step 437 and compared with a copy of that data temporarily maintained in a controller buffer. Alternatively, this can be accomplished by a read with an ECC check. If the comparison is positive, a decision block 439 causes the process of writing data to end, the next step being indicated at 325 of FIG. 7. If the data does not compare, a step 441 identifies the bad cell or cells by address which are responsible for the bad bits, and then adds that address in the form of a bad bit pointer to the bad bit pointer fields 235-237 of the stack 215 in its proper order. This process dynamically and automatically takes a bad cell out of service without having to declare the entire block to be of out of service.
Although the various aspects of the present invention have been described with respect to a preferred embodiment, it will be understood that the invention is entitled to protection within the full scope of the appended claims.
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Judicial Branch & Supreme Court
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Marbury v. Madison and the Federalist Legacy
1803 case established principle of judicial reviewChief Justice John Marshall issued famous ruling Quite a bit can happen during an outgoing president's lame duck period—those days between th...
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1968 massacre at My Lai, Vietnam, led to controversial courts-martial of US soldiersWhat laws apply to warfare? How can they be enforced? A nation's rules of warfare—what are they? How are th...

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text: I get to try out a lot of cases for my iPad 2 and new iPad, but it's rare to find a case that protects the screen while in use, but doesn't add a ton of bulk. The Leisure Case from M-Edge is unique in that it is a rigid fabric shell that the iPad 2 or new iPad zips into, and has a clear cover that lets you use the touchscreen. In fact, I'm typing this review while my iPad is in the Leisure Jacket case!


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Imagine ... balmy summer breezes, gentle waves lapping against the shore. You're lying on your tummy with the smell of frangipani and jasmine wafting through the air. Gentle hands cast long strokes across your back in a repetitive kneading motion. Bliss.
If this sounds like your type of holiday, then an Asian Spa holiday may just be what the doctor ordered. Cast aside the atrocious New Zealand summer, tell the boss that the report can wait, and throw the bikini in the suitcase. Now is the time to book your spa escape.
Which country and how do I get there?
Most Asian holiday planning starts with the decision on which country to go to. Heres a quick snap shot of the most popular destinations:
THAILAND synonymous with Spas. The most popular destinations are the tourist mecca, Phuket or the more intimate, Koh Samui. Either way the accommodation options are excellent with a wide range of 4-5 star spa specialising beach resorts to choose from. There are no direct flights to either of these destinations, though plenty of Airlines fly to these destinations including Thai Airways, Singapore Airlines, and Jetstar.
BALI a new favourite for Kiwis. Here you can opt for a spa specialising beach resort, a villa complex with spa facilities, or Ubud the hillside resort that specialises in spa techniques (and only 45 mins from Bali). Air New Zealand offers direct services to Denpasar. Thai Airways, Singapore Airlines, other Asian carriers and Jetstar offer services via their respective hubs.
MALAYSIA Langkawi is a popular escape for couples, 30km northwest of Malaysia. For those looking for a cultural and spa experience, the Penang offers great resorts, pretty villages and amazing eating experiences. All Asian carriers and Jetstar offer services via their respective hubs.
VIETNAM a burgeoning Asian beach destination, Vietnams stunning coastline and luxury resort properties are increasingly popular for travellers. Hoi An; Nha Trang and Phan Thiet all offer beachside spa resort options. Thai Airways, Singapore Airlines, other Asian carriers and Jetstar offer services via their respective hubs.
When to travel?
Now is the time you will find good deals for travelling to Asia. We recommend that our Winter/Spring (May to October) is the ideal time to visit. Not only do you miss the peak travelling period for the European travellers, but more importantly, it means you can escape the gloomy New Zealand weather.
How long do I go for?
Given the 9 hour plus plane ride to Asia, we recommend that you take 6 days in Asia or more.
You can opt for a half day Spa treatment, through to a 4 day indulgence. So the options are abound. Almost all 4.5 to 5 star resorts will have inhouse Spas. The likes of Shangri-La have signature Spas that follow a specific ideologies of balancing the mind and body. We find that many of our spa" customers opt for 2-3 days indulging in a spa and then another 3-4 days enjoying the local culture and attractions.
What to pack?
We recommend that you pack light beach going gear, sunnies, flip flops, bikinis and board shorts. Most of these destinations have fantastic night markets within the vicinity, which are ideal for picking up extra beach going gear.
And all the Asian hubs (e.g. Singapore, Bangkok, Kuala Lumpur and Hong Kong) are renowned for their shopping, so leave room to spare in your suitcase.
The nights are a little cooler and the shopping malls often have air conditioning on full throttle, so bringing a light long sleeve top/cardigan is a good idea.
If you are visiting Malaysia and would like to experience the Mosques, we recommend that you pack light long sleeve tops and pants as you will need to cover yourself before you are allowed to enter.
We also recommend that you visit a travel doctor and take advice on the appropriate precautions for visiting South East Asian countries.
HOT recommendations on where to stay.
THAILAND Indigo Pearl Phuket is a stunning resort uniquely inspired by the Tin Mining era of the region. Beautiful suites are scattered through the landscaped gardens. The ultimate feature is the 'pièce de résistance of the Coqoon Spa, and the must-try for all spa enthusiasts is 'The Nest' - a luxurious spa suite suspended midair and accessed by a flying bridge, allowing guests to get up close and personal to nature.
The Nest - Coqoon Spa, Indigo Pearl Phuket
BALI At the Maya Ubud Resort & Spa, you are set in the rolling hills and misty mountains about 45 mins from the Bali beaches. Here they offer an array of Spa Packages including our favourite The Enchanting Ubud Experience which runs over 4 days and includes daily scheduled activities: yoga for beginners, introductory pilates, nature walks, and meditation; massage and flower baths; cycle tours; and some of your meals.
Maya Ubud Resort and Spa, 45 mins from Bali
MALAYSIA - Berjaya Langkawi Resort & Spa this 4 and a half star resort has a local Malay flavour with its beautiful beach & jungle setting, on the lovely island of Langkawi. You have the option of staying in wooden rainforest chalets or overwater bungalows. The Ayura Spa is in a dedicated area of the resort and offers its guests a private Plunge pool & Jacuzzi with a dedicated number of Spa treatments
Ayura Spa at Berjaya Langkawi Resort & Spa, Langkawi, Malaysia
VIETNAM - Six Senses Ninh Van Bay in Vietnam - where they have personal Spa Suites - actual rooms where instead of having to go to the resident Spa in the resort, they come to you, massage table set up within your room (usually like a Suite so it is separate) and in your daily massage in included in your room rate.
Six Senses Ninh Van Bay - Vietnam
Or the stunning Life Wellness Resort in Quy Nhon, where there is a focus on Yoga, Wellness, Meditation, Tai Chi and Cuisine & they offer 4 & 5 day Life Spa Packages with a range of treatments, therapies, activities and meal packages available


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Five things for pharma marketers to know: Friday, March 20March 20, 2015
A judge rules against Amgen in Neupogen case; FDA advisory panel recommends Breio Ellipta for adults with asthma; AstraZeneca partners with Daiichi Sankyo to sell Movantik
GSK shingles vax shaping up to compete with Merck'sDecember 22, 2014
The Herpes zoster vaccine candidate showed relatively strong efficacy in a Phase-III trial, but its dosing is less convenient than an older product sold by rival Merck.
Teva narrows focus, trims R&DOctober 07, 2014
The drugmaker is poised to cut 14 pipeline projects loose.
Allergan updates pipelineJuly 01, 2014
Allergan's latest pipeline news was a mix of the good and the bad. The good: a potential Lucentis competitor is progressing. The bad: migraine medication Semprana has stalled.
PhRMA uneasy about "right-to-try" lawsJune 18, 2014
Colorado's version of the FDA's compassionate use rule does not sit well with lobbying group Pharmaceutical Research and Manufacturers of America.
Merck Q1 sales fall, but diabetes risesApril 29, 2014
Sales of its big diabetes franchise rose 3% vs. the same period last year, while drops in Singulair and Nasonex revenue marked the quarter. The company is slated to reveal pipeline progress next week.
Roche wraps quarter with two fewer pipeline medicationsApril 15, 2014
Roche also announced first-quarter sales shrank 1%.
Lilly says 2014 will not be "trough year"January 30, 2014
Higher prices helped insulate Q4 and annual sales, which fell and rose 2%, respectively. Lilly said its insulin glargine biosimilar will go nowhere if it is not substantially different from the competition.
Pfizer's Q4 fails to wow, but palbo' news mayJanuary 28, 2014
The company said it may use Phase II data of a breast cancer drug for FDA review, part of an earnings presentation that also included its perspective on what a pre-2017 breakup would take.
The year's most popular storiesDecember 31, 2013
Our year-end list captures the 10 that sparked heaviest interest.
Analyst: Don't underestimate AbbVieDecember 04, 2013
Goldman Sachs's Jami Rubin says AbbVie's pipeline assets make it a stealth competitor.
Amgen PCSK9 drug passes safety testNovember 20, 2013
New results from its Phase II safety trial show the LDL-cholesterol lowerer was not associated with a major increase in adverse events vs. standard of care.
Xeljanz line extension could lift drug's profileOctober 09, 2013
An analyst notes that early Phase III results in a psoriasis clinical trial could change the drug's efficacy profile. It could also fill out the financial potential of a standalone innovative unit, should Pfizer divide.
Bayer: 5 new Phase III drugs expected in 2015October 08, 2013
The drug maker says it is accelerating development of new drugs and focusing on expanding indications of current ones.
AstraZeneca reinforces oncology pushAugust 26, 2013
The drug maker is adding Amplimunne's cancer portfolio to subsidiary MedImmune's oncology efforts, one of several recent deals to add heft.
Analyst gives Merck tough loveAugust 21, 2013
Analyst Seamus Fernandez writes that Merck needs to undergo a deep overhaul, continuing the summer narrative that has enveloped Pfizer and Novartis.
Sleeper in Lilly oncology pipeline surprises StreetAugust 13, 2013
Phase III results of Eli Lilly lung cancer drug necitumumab took analysts by surprise on two levels: by helping it avoid the dustbin and in succeeding where Erbitux had failed.
Higher prices drive Lilly's second-quarter earningsJuly 24, 2013
The Indiana drug maker logged a 6% sales increase over the same period last year. Higher prices were responsible for the majority of the growth.
Roche diabetes pipeline shrinks to twoJuly 10, 2013
A Data and Safety Monitoring Board recommendation has wiped aleglitazar from the drug maker's slate of possible diabetes medications.
FDA pushes Merck's suvorexant asideJuly 01, 2013
The regulator says Merck needs to focus on lower doses of the drug.
Which companies stand out post-ASCO?June 28, 2013
ASCO not only offered a peek at developing treatments likely to be commercialized. Its impact also put some companies in the limelight from a business-development perspective.
Victoza in its crosshairs, Lilly primes for marketing duelJune 25, 2013
Eli Lilly's GLP-1 drug is still in Phase III, but recently released data suggest it could be a formidable competitor to the already marketed GLP-1 drugs, including Novo's market-leading Victoza.
J&J expands pipeline in prostate cancerJune 17, 2013
The pharmaceutical behemoth is betting at least $650 million on the Aragon Pharmaceuticals Ph. II drug.
Novartis readying 2014 filing for lung cancer drugJune 04, 2013
Novartis is advancing its "breakthrough" lung cancer drug into Phase III based on promising Phase I data.
GSK gets 2 cancer pills approved, but a deeper question is left unansweredMay 30, 2013
GSK's newest cancer approvals highlight a problem that stalks progress with personalized medicines.
Business Briefs: Merck and Forest LabsMay 23, 2013
Merck's proposed insomnia drug scores a thumbs-up from an FDA advisory panel, and long-time Forest Labs CEO Howard Solomon announces his coming retirement.
J&J's Janssen looks to the margins with hep C agentMay 14, 2013
J&J scored an unexpected "priority review status" for its HCV agent simeprivir, whose initial approval is expected to be with interferon.
Data show Gilead's sofosbuvir has 'clean' safety profileApril 24, 2013
Phase III findings on sofosbuvir, released in a medical journal, suggest no cause for concern from a safety perspective.
Pfizer pipeline breast cancer drug gets fast trackedApril 11, 2013
FDA is accelerating review of Pfizer's experimental breast cancer drug palbociclib, which analysts say already has a fan base among KOLs.
Oncology lifts Roche's Q1, Lucentis finds new fansApril 11, 2013
Roche's oncology trifecta of Herceptin, Avastin and mabThera/Rituxan buoyed quarterly sales. Devices and diagnostics sales were solid, if less impressive.
Pharma continues to struggle with its image. Exhibit A is the public debate around the price of, and access to, new and innovative meds. As countless transformative technologies hit market, has industry done enough to anchor its permission to innovate? To provide a closer look at trends affecting trust over the past year, MM&M presents this e-book, "The 2015 Edelman Trust Barometer." Click here.


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On May 22, 2013, the New York State Department of Labor published its long overdue proposed regulations interpreting New York's permissible deductions from employee wages. As we covered previously in the September 2012 issue of the New York eAuthority, amendments to N.Y. Labor Law §193, which became effective on November 7, 2012, expanded New York's permissible deductions to include categories such as an employee's pre-authorized personal activities, inadvertent overpayments, and loans or pay advancements.
The proposed regulations, which are not yet effective and remain open to public comment until July 6, 2013, provide further guidance regarding the permissible scope of wage deductions under New York law. Of particular interest to employers are the following proposed interpretations:
The proposed regulations are available here. We will continue to monitor the proposed regulations pending any amendments and final passage.
Note: This article was published in the June 2013 issue of the New York eAuthority.
DISCLAIMER: Because of the generality of this update, the information provided herein may not be applicable in all situations and should not be acted upon without specific legal advice based on particular situations.
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Car Advertising Campaign of the Year 2015: VOTE NOW!
This week's issue of Auto Express
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Toyota has put one over the VW Group when it comes to profit
Skoda Rapid Spaceback takes a price cut
Things to do for car fans: family days out in summer 2015
New Vauxhall Viva 2015 review
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Six months in, what do you think of the new UK road tax system?
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A 25-year-old man was swept away today in the turbulent waters of Muhane river in Nalanda district while washing his car, police said.
Police said the young man identified as Chandan Kumar of Chandi Bazar area in the district accompanied by a friend took his vehicle to wash in the river. Kumar took the route of a diversion on which plying of vehicles is not allowed, and drove the car a little into the river, currently in spate, for easy access to water. He was washed away while washing the car, an official at the Chandi police station said.
The official said the current in the river was so swift that nobody dared to venture into it to save Kumar, who was tossed up and down by the waves. His friend, identified as Ramashish, also could not do anything.
A search has been launched by local people and divers, police said adding that divers were searching for Kumar in the river.


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Hoping to learn PHP?
Month July 2012
Envato's 6th Birthday: 70% Author Commission & Birthday Bundle!
We're excited to announce that we're rapidly approaching Envato's 6th year in operation!
Author Interview: Mackaymusic
Living in Kazakhstan, studying music in New York, being inspired by ambient music, and sitting on the roof to watch the sun rise and set.
Get Constructive Feedback
With Tuts+ Workshops
Iron sharpens iron.
Even Ex-Googlers Love Tim McMorris
The new Triposo App from Jon Tirsen on Vimeo.
Learn to Be Your Own Critic
How good are you at evaluating your own work?
WordPress 3.4 Compatible Themes
With WordPress being updated to version 3.4 on the 13th of June, we're pleased to announce that we've updated the Marketplaces to allow version 3.4 to be selected by theme authors as a compatibility option.
Want Some Exposure? Why Not Offer a Freebie?
The Envato Marketplaces are a fantastic way to earn money, but sometimes you may be looking for a way to draw extra attention to your portfolio of work.
Your Say: How do you sketch?
How do you sketch?
Killer Magento Themes on ThemeForest
Magento has been emerging as a feature rich eCommerce script that boasts an intuitive interface and scalable functionality.


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A brake pulsation or steering wheel vibration may be noted when braking, especially at highway speeds. Our technicians tell us that replacing the front brake backing plates, resurfacing or replacing the front brake rotors, and inspecting the front brake pads and caliper hardware and replacing as necessary will generally correct this concern.
2010 Infiniti EX35 Problem Reports
Most Reported 2010 Infiniti EX35 Problem Reports
Report A Problem
View:Most ReportedNewestRepairPal Verified
The Check Engine Light may illuminate due to an EVAP system charcoal canister purge control valve fault. Our technicians tell us that if the valve requires replacement, a revised part is available which should be installed.
Various GPS and Bluetooth system related malfunctions may develop. Our technicians recommend updating the GPS system software before attempting any other repairs.


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Filipina 5th Filipino drug mule to be put to death by China since 2011
More News from INQURER.net
MANILA, Philippines – The execution of a Filipina drug mule in China was the fifth Filipino nationals put to death for drug trafficking since the execution of four Filipinos in 2011.
The 35-year-old Filipina was caught trying to smuggle around six kilograms of heroin in Hangzhou international airport last January 2011.
She was executed Wednesday after the Supreme People's Court of China upheld the death sentence handed down by lower courts on June 26.
Philippine President Benigno Aquino III had sent an appeal letter to Chinese President Xi Jinping to have the death sentence commuted to life imprisonment but the Chinese government did not respond.
Last March 30, 2011, Sally Ordinario-Villanueva, 32, Ramon Credo, 42, and Elizabeth Batain, 38, were executed in China also for attempting to smuggle heroin into the country.
A fifth Filipino was executed in December 2011.
They were arrested separately in 2008 for possession of at least four kilos of heroin each and were handed down the death sentence the following year.
The Philippine government appealed repeatedly to have their death sentences commuted to life imprisonment, but the Chinese government turned down the appeals.
Most executions in the world
The Dui Hua Foundation, a non-profit organization that advocates for the human rights of detainees, said in a report last December 12, 2011 that China conducted an estimated 4,000 executions in that year.
In an earlier study released in 2010, Dui Hua Foundation said that the number of executions carried out in China were higher.
"Statistics on capital punishment in China are considered state secrets. Lacking official information, international observers are left to make educated guesses about the number of executions in China," it said.
"In past years, Dui Hua has based estimates of annual executions on discussions with knowledgeable sources. We have estimated that China carried out nearly 5,000 executions in 2009—a slight decrease from 2008," it said.
Dui Hua said in the same study that a separate research based on collated news reports of executions from October 1, 2009 to September 30, 2010 showed that there were at least 700 executions in China in 2009.
"After one year, ending on September 30, we recorded exactly 700 executions in China," the study said.
"This number serves as an absolute minimum number of executions carried out over the year, and tells us nothing about how many actual executions may have taken place. But even using this lowest figure, China still executed more people than any other country in 2009," it said.
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c/o Philippine Daily Inquirer Chino Roces Avenue corner Yague and Mascardo Streets, Makati City,Metro Manila, Philippines Or fax nos. +63 2 8974793 to 94


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Now this is what we call a sandwich, and we defy anyone to argue! You'll need both hands and a big apetite.
Mix together the balsamic vinegar, garlic, oregano and chilli in a shallow dish. Add the steaks and leave to marinate for up to 2 hours in the refrigerator.
To prepare the tomato salsa: gently heat the olive oil in a frying pan. Add the onion, garlic and chilli. Gently cook for 5 minutes until the onion is soft and golden.
Remove the steaks from the marinade and season with salt and pepper on each side. Add the marinade to the pan along with the tomatoes and cook on a high heat for 3-4 minutes until the tomatoes start to burst in the pan. Throw in the rocket to wilt, reserving some for the sandwich.
Cook the steaks on the barbecue or grill for 1 minute on each side. Slice the steaks and set aside.
Place the reserved rocket into a large bowl with a splash of olive oil and balsamic vinegar. Season and toss the leaves around the bowl.
Slice and oil the bread and place onto the barbecue or griddle, oiled side down for a few seconds to toast. Remove, rub with garlic and place onto a plate.
To assemble the sandwich: place the tomato salsa and wilted rocket onto the base of the bread. Place some of the steak slices on top. Spoon over more of the tomato salsa, gently squashing the mixture down. Top with the remaining beef and the other slice of ciabatta.
Cut each sandwich in half on the diagonal and serve immediately.
» Metric Converter
Shiraz, Cabernet Sauvignon and MALBEC are the best wines to pair with Seared Steak Sandwich with Warm Tomato Salsa.
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The meat in this taco is worth even less than the meat in a real taco. I'm broke as a joke.
Need a project? How about making your own amigurumi Link? You're welcome!
I've never been any good with actual yarn, perhaps I could master the art of icing crocheting in time for my cats and dogs to have babies. Wait, they're not having babies! WHO WILL I BE GRANNY FOR?
I might be able to handle a Big Mac if it's made itty bitty and crunchy. Sure I like a little grease now and then, but this is the perfect portion size.
considering how kids never really just pick up a sandwich and eat it like normal human beings, you can make them lunches that defy the norms of sandwich making for fun. They're going to decimate the thing anyway, why not get them excited about the beauty they are about to destroy?


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Secure the Promise is a comprehensive campaign that will directly benefit the lifeblood of our institution: our students. The purpose of Secure the Promise is to unlock each student's potential by offering scholarships for financial flexibility, a contemporary and safe campus environment to call home, academic programs and facilities to support academic excellence and to foster a passion for lifelong learning, and a new health and wellness center designed for student fitness and recreation.
The success of the campaign relies on the support of alumni, parents, and friends. We invite you to join others in making a commitment to the Secure the Promise Campaign.
220 N. Camden St.
Wingate University
Wingate, North Carolina 28174
Toll Free: 1-800-755-5550
Phone: 704-233-8000


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Tutorial PEST Courses
Download a comprehensive tutorial that shows you how to use PEST to undertake state-of-the-art model parameter and predictive uncertainty analysis. Two complete worked examples are provided, one involving a surface water model (HSPF) and the other involving a groundwater model (MODFLOW). Also provided is the background theory (explained in an easy-to-read manner) and suggestions on how modern methods of data processing and uncertainty analysis such as are provided by PEST can be used as critical components of the environmental decision-making process.
Topics covered include the following:
Many thanks to the South Florida Water Management District for making development of this tutorial possible.
A number of professional PEST courses are normally held each year. Planned courses are as follows.
A three-day PEST course will be held in Santiago, Chile starting 25th May, 2015.
A two-day PEST course featuring PEST usage with Groundwater Vistas will follow the MODFLOW conference in Golden, Colorado. Jim Rumbaugh (developer of Groundwater Vistas) will co-host this course. Dates are Jun 6-7 2015, following a two-day GV/PEST/MODFLOW-USG workshop.
A four day PEST course will be hosted by University of Neuchatel, Switzerland starting September 7, 2015.
A short, one-day introductory course on model calibration, uncertainty analysis and model-based decision-making will precede the IAH conference in Rome, Italy on September 12, 2015.
A four or five day PEST course will be hosted by SSPA in Bethesda, MD (just outside of Washington DC) over the week beginning 28th September 2015.
Contact us for further details on any of these courses.
In-house training is also offered. This can be tailored to your needs. Contact us if you are interested.
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Caroline Manzo declined to comment on that part of her family's past in a telephone interview. But she owned up to the parallels between her clan and New Jersey's first famous family.
"We are Italian Americans and you will see some similarities -- a love of family tradition, saying what's on our minds," she said. "But the similarities stop there."
The family ties on "The Real Housewives" don't stop with Caroline and Dina Manzo. Jacqueline Laurita, a former cosmetologist turned full-time stay-at-home-mom, is married to the Manzos' brother, Chris.
But Laurita doesn't quite fit into the "Sopranos" oeuvre. Having only recently left her hometown of Las Vegas to settle in New Jersey, she's still learning the ways of the queen bee and second-in-command. Like Margene Heffman, the third wife on HBO's "Big Love," Laurita's a little green, always upbeat and conflict-shy, which becomes clear when she tries to bring a new member into her Manzo-dominated circle.
Admittedly, it's a stretch. But if only because you can't help but laugh at her, Jersey native Teresa Giudice's TV character equivalent is Lucille Ball circa "I Love Lucy." Teaching her three young daughters how to be "fabulous" while augmenting her family's massive mansion isn't all Giudice does – she's also launching a line of hair accessories called TGfabulicious.
The other housewives admit Giudice is their comic relief, and how could they not? In the first episode, she talks about wanting to get breast implants, despite the fact that her husband "is more of an a** guy and he loves my bubbies." (Yes, "bubbies.")


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Roush Fenway Racing making noise
Updated: March 16, 2010, 2:22 PM ETBy Terry Blount | ESPN.com
Despite that little hiccup with the Carl Edwards sideshow at Atlanta, things are looking up for Roush Fenway Racing and the Ford group. Tempers and paybacks aside, RFR is back.
Matt Kenseth ranks second in the Sprint Cup standings, and Greg Biffle is third after the first four races. Edwards is a misleading 20th after his tussles with Brad Keselowski led to a 39th-place finish at Atlanta Motor Speedway, but Edwards hadn't finished worse than 13th before that incident.
Only ...
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Here is a thread for all Wicked fans! I haven't seen it yet but I really want to. Has anyone seen it yet?
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Here is a thread for all Wicked fans! I haven't seen it yet but I really want to. Has anyone seen it yet?
I have seen it and love it
I'm seeing it on April 28th...:)
I'm seeing it in 8 days!!!! :yea:
A bunch of Micechatters are going on the 28th....and I'm one of them!
OH I am going the 28th as well :)
I have seen Wicked three times. I saw it twice when it was here two summers ago and then in New York last summer. It is a really fun show. I love it.
Here's an old huge thread about Wicked....
I've been in NYC, LA, and three times in Portland. I'd go again in a heartbeat! :)
I'm going with the chatters at the end of this month. Come to think of it, the first and only other time I saw Wicked was with MiceChatters. :P
Hey the gay miceclub isn't called Friends of Elphaba for nothin ;)
Saw it once about 3 yrs ago in NYC with the original cast and fell in love with it. It's one of my absolute favorite musicals
I saw the traveling one when it came into town last year.
I'd see it many more times if I could.
when i got my tickets I had no idea mc was going on the 28th. I got my tickets through work for the night show...:)...
Saw it once recently at Pantages. Pretty cool. The only songs that stuck with me are "Popular" and "Defying Gravity" (then again, I heard them many times before the show). Still really neat.
Seen it. Loved it.
Am I the only person on the planet who has seen it and didn't love it?


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On March 12, Fannie Mae issued a notice postponing the April 1, 2014 implementation deadline for changes to its standard and streamlined modification programs announced in SVC-2013-28. Those changes expanded the programs to include loans with a pre-modification mark-to-market loan-to-value (MTMLTV) ratio of less than 80%. In the "near future," Fannie Mae will announce a new effective date and updated requirements for such loans. Until the new requirements become effective, loans with MTMLTVs of less than 80% will continue to be eligible for a standard or streamlined modification if the loan servicer has fully implemented the previously-announced changes. In a separate notice relating to its adjustable-rate mortgage (ARM) plans, Fannie Mae announced that it is requiring sellers and servicers to substitute certain LIBOR indices for the discontinued Federal Reserve Board CD index, and as a result it is retiring two standard ARM plans based on the discontinued index.
DISCLAIMER: Because of the generality of this update, the information provided herein may not be applicable in all situations and should not be acted upon without specific legal advice based on particular situations.
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Vivien D'Andrea, M.D., FACP
Internal Medicine
(Board Certified)
Not Accepting new patients
701 E. El Camino Real
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Mountain View, California 94040
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Assange seeks asylum in Ecuador
- By Elias GrollElias Groll is an assistant editor at Foreign Policy. A native of Stockholm, Sweden, he received his undergraduate degree from Harvard University, where he was the managing editor of The Harvard Crimson.
- elias.groll
- @eliasgroll
Julian Assange's legal battle in Britain to overturn an extradition order to Sweden may have come to an end, but the Wikileaks founder isn't giving up. Assange is now seeking asylum from Ecuador, and has taken refuge in Ecuador's London embassy according to Reuters.
Assange has been in Britain for the better part of the past year while fighting the extradition order to Sweden, where he is wanted for questioning in connection with alleged sex crimes. It is unclear whether Ecuador will accept Assange's request, but Reuters quoted Ricardo Patino, the country's foreign minister, as saying that officials are "studying and analyzing the request."
In a statement posted on the website of the Ecuadorian foreign ministry, Assange blasted his native Australia, which he said had abandoned him in the face of ongoing political persecution directed at Assange and his organization.
In the statement, Ecuador said that Assange had sought the protection of the Ecuadorean government after Australia failed to live up to its stated obligation to defend his "basic rights in front of any government and delegated to a foreign country whose constitution applies the death penalty for the crime of espionage and treason … ignoring its obligation to protect its citizen, who is being persecuted politically."
Sweden, of course, does not have the death penalty on the books, but Assange has long maintained that the extradition order is part of a conspiracy by the American government to have him extradited to the United States in order to face espionage charges, a crime for which he could face the death penalty. Swedish prosecutors have not charged Assange with a crime.
The choice to seek asylum in Ecuador may seem surprising, but Ecuador's president, Rafael Correa, has closely aligned himself with Hugo Chavez's Venezuela and Evo Morales' Bolivia, and like his South American compatriots, Correa preaches a political doctrine willing to crack down on press freedoms and political rights to preserve his particular brand of socialism. Additionally, Correa and Assange have something of a personal history-Assange interviewed Correa this year on his RT talk show, and Ecuador offered the Australian hacker-cum-provocateur residence in 2010.
Complicating matters, Ecuador has signed extradition treaties with both the United States and the European Union, but given Assange's decision to pursue asylum at the Ecuadorian embassy in London, it would appear unlikely that Ecuador will enforce those agreements.
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Will Ecuador have to smuggle Assange out of Britain? [Updated]Joshua Keating
Joshua Keating is associate editor at Foreign Policy and the editor of the Passport blog. He has worked as a researcher, editorial assistant, and deputy Web editor since joining the FP staff in 2007. In addition to being featured in Foreign Policy, his writing has been published by the Washington Post, Newsweek International, Radio Prague, the Center for Defense Information, and Romania's Adevarul newspaper. He has appeared as a commentator on CNN International, C-Span, ABC News, Al Jazeera, NPR, BBC radio, and others. A native of Brooklyn, New York, he studied comparative politics at Oberlin College.| Passport |
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State Department denies pressuring Brits to go in and get Julian AssangeJosh Rogin
Josh Rogin covers national security and foreign policy and writes the daily Web column The Cable. His column appears bi-weekly in the print edition of The Washington Post. He can be reached for comments or tips at email@example.com.
Previously, Josh covered defense and foreign policy as a staff writer for Congressional Quarterly, writing extensively on Iraq, Afghanistan, Guantánamo Bay, U.S.-Asia relations, defense budgeting and appropriations, and the defense lobbying and contracting industries. Prior to that, he covered military modernization, cyber warfare, space, and missile defense for Federal Computer Week Magazine. He has also served as Pentagon Staff Reporter for the Asahi Shimbun, Japan's leading daily newspaper, in its Washington, D.C., bureau, where he reported on U.S.-Japan relations, Chinese military modernization, the North Korean nuclear crisis, and more.
A graduate of George Washington University's Elliott School of International Affairs, Josh lived in Yokohama, Japan, and studied at Tokyo's Sophia University. He speaks conversational Japanese and has reported from the region. He has also worked at the House International Relations Committee, the Embassy of Japan, and the Brookings Institution.
Josh's reporting has been featured on CNN, MSNBC, C-Span, CBS, ABC, NPR, WTOP, and several other outlets. He was a 2008-2009 National Press Foundation's Paul Miller Washington Reporting Fellow, 2009 military reporting fellow with the Knight Center for Specialized Journalism and the 2011 recipient of the InterAction Award for Excellence in International Reporting. He hails from Philadelphia and lives in Washington, D.C.| The Cable |


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Steelseries Stratus iOS gaming controller flash review
The Steelseries Stratus is the company's first dedicated iOS gaming controller. The pocket-friendly Bluetooth 2.1 gadget utilizes the external gamepad support which debuted with Apple iOS 7 last year.
Headquartered in the Valby district of Copenhagen, Steelseries is currently among the premier designers and manufacturers of gaming gear and peripherals. Read on to find out all about its iOS-friendly offering! Read more »


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Marin tweeted: "Time to make ur voice heard. Unfortunately it's come to...
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Campus tensions are surfacing around ex-British MP George Galloway's upcoming visit to McMaster University this month.
Judy Schwartz, the director of the McMaster Jewish Students Association, said the campus group respects Galloway's right to his opinion and believes in the freedom of speech, but found it "hard to consider that any group with a conscience and who desire peace would want to have the presence of a gadfly radical like Galloway at McMaster, which degrades the university and diminishes its value."
"By extending an invitation to this individual, the sponsoring groups only reveal their true intentions — not real dialogue or sharing of information or educating people, but only to demonize Israel and to intimidate Israel's many supporters on campus," Schwartz said.
Galloway was banned from entering Canada last year because of his financial support to Palestinian group Hamas, which is considered a terrorist organization by Ottawa. But a Federal Court ruling was critical of the government and immigration officials eventually let Galloway into the country.
The former Labour member of Parliament, who is an outspoken supporter of the Palestinians in the Middle East conflict and a critic of the war in Iraq and Afghanistan, is visiting 10 cities on his Canadian tour this month.
Campus groups Solidarity for Palestinian Human Rights (SPHR), Students Resisting War and Occupation (SRWO), Independent Jewish Voices and Students for Social Justice, along with the Hamilton Coalition to Stop the War (HCSW), have come together to bring Galloway to the campus in what they are calling an educational opportunity.
Organizers are expecting about 600 people to attend the Nov. 21 event.
SPHR co-president Omar Saif, 20, said the purpose of the talk is to foster dialogue.
"The idea is not to just bring a controversial speaker," Saif said.
Galloway will mainly be speaking about Canada's role in the Afghanistan war, of which many Canadians are not supportive today, the third-year environmental sciences student said.
"For those people who might not share his viewpoints, that's totally acceptable," Saif said.
"Even for people who want to protest him coming, at the end of the day, that's within their rights to do so."
Schwartz said the group would not be taking any action against the talk, but there is an overall feeling of disappointment among the Jewish students.
"The truth is that any time that these types of speakers come to campus … there is always a fear," she said.
But Brendan Stone, HCSW co-chair, said the event will have a question-and-answer period and they welcome people with diverse opinions to attend.
"McMaster … as an academic space frequently brings in speakers that have opinions that are not always heard," he said.
"Galloway does speak for Canadians, especially about the Afghanistan war."
The feedback they've received so far from students have been positive, said Riaz Sayani-Mulji, co-president of the SRWO. He hopes the event will get people more interested in politics, the third-year health sciences student said.
"The purpose of bringing speakers like George Galloway is to inspire people to get involved … and get rid of this apathy."
Political tensions at McMaster over the Middle East peaked two years ago during Israeli Apartheid Week, when the university banned the display of a controversial pro-Palestine banner, resulting in a protest that led to a police investigation.
A university-brokered agreement called the McMaster Peace Initiative was created as a result. Signatories of the accord committed to keeping debate free, open and in a respectful, academic tone.
Schwartz, who was a signatory of the accord, said the Galloway event conflicts with that agreement.
Saif, who was not a student when the initiative was signed, said student groups' ideologies can change from year to year and suggested a review and renewal of the pact. The SPHR was also not a student group at the time the Peace Initiative was created, he said.
"(The agreement) almost loses its credibility if it's not renewed on a yearly basis," Saif said.
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Andre now admits separate amphetamine use
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Join Date: Jul 2009
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Originally Posted by
good grief!
no wonder a current player said Federer is the cleanest world #1 around and that if the ATP were to release the names of superstars that have been caught and tested positive;this would be huge
If Federer is the cleanest nr.1,what does that say about the ATP? If he is the cleanest,the logical assumption would have to be that most other nr.1 had some "dirt" on them.
I for one don't believe in "dirtyness" in a player unless we can find some proof(but real proof not circumstantial evidence). People don't think of Fed as a doper because of his beautiful,efficient game but I have watched Fed since 2002 and I have rarely seen him sweat when he gets to a 4th or 5h set(except in AO where it's really hot and he had mono at the time). McEnroe,a guy who some to this day consider the epitome of classical,beautiful tennis,took steroids. So God only knows what "machines" like Borg took. If guys were doing this sort of stuff in the 80's what doping agents do you think they are doing today and how are they hiding it since the tech has got better.
People point to Nadal because of his muscles and endurance but feats equaling or surpassing Nadal have been done before in the 80's or 90's by other players. Today most players don't have a tennis players body even if everybody points the finger at Nadal. Most guys today are bigger,faster and have more endurance than their past counterparts. Some say it is due to better conditioning than in the past,some say it's because of doping,some think it's a combination of both.
I for one have no idea if Nadal is guilty or not. I hope he isn't but I also hope another thing: if the ATP do dish out the dirt,let us know all the dirty champions,not just recent ones,although this has a one in a million chance of happening.
And another closing thought about that certain player,who I assume is Santoro. How can he and other tennis players know/suspect things like this and not say a word? They are as guilty in my opinion as the guys covering it up. I saw a TV interview with Nastase who,responding to the recent doping discoveries,said that in his day there were certain high profile players who were suspected of doping by their peers but nothing came out. These are words coming from the first official nr.1 in the Open era,back in the 70's. So if this is true,tennis hasn't been a clean sport for quite some time,even though we all like to think that this is a modern problem.
Last edited by namelessone; 11-01-2009 at
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2014-2015 Season Brochure
View Season Brochure
Gallery Exhibits
Open Proposal Period: Aug-Nov
View PDF Guidelines and Application
Call to Artists
Schaefer Portrait Challenge
Gallery Guides
View the PDF booklet
Welcome: Welcome to Our World-Class Performing/Visual Arts Center
Center Stage: Calendar of World-Class Entertainment and Events
Schaefer International Gallery: Visual Arts from Hawai`i and Around the World
Cultural Programs: Na Mo`olelo O Hawai`i as told through Hawaiian Eyes
Arts in Education: Preparing Students for the Future
Facilities: Flexible Venues, Meeting Spaces and Special Event Places
About Us: Discover The MACC, Get the Mission
Membership: Join the `Ohana, Donate to the Community, Learn about Benefits
Tues-Sun 10 am - 5 pm
Also open before Castle Theater shows & during intermission.
FREE Admission!
View Season Brochure
View PDF Guidelines and Application
View the PDF booklet
Hawaiian kapa piece (detail)
by ┬ĀRoen Hufford, 2013
This invitational exhibition will feature a select group of 20+ kapa practitioners from HawaiŌĆśi and California, whose work involves both traditional and non-traditional use of materials and techniques in kapa-making. Learn about the history, tools and botanical resources of this ancient Hawaiian art form, and the dedicated work of those who have revitalized the almost-lost knowledge and cultural value of the craft. We are pleased to share resources and expertise in collaboration with the HawaiŌĆśi State Foundation on Culture and the Arts, and the Maui Historical Society/Bailey House Museum.
February 8 and March 1, 10:00 am- 12:00 pm
Parents and children are invited to Schaefer International Gallery to see the exhibit, watch kapa demonstrations, and make a small piece of art to take home. FREE!
C├®leste Boursier-Mougenot, Untitled (series #3), 2001
Collection Museum of Contemporary Art San Diego
Museum purchase, International and Contemporary Collectors Funds
A unique live performance in the gallery featuring a musical trio under the direction of
composer Takuma Itoh. His composition will accompany the visual and sonic aspects of
Boursier-MougenotŌĆÖs installation, based on reaction and experimental communication.
A conversation with the musicians will follow the performance.
Tickets: $20. Seating is limited. Call The MACC Box Office: (808) 242-7469
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SinusWars LLC revamps the ultimate homeopathic Hayfever and Allergies Remedy
With over 8 years of experience, SinusWars are proud to announce their new SinusWars1 remedy which the company claims to treat all types of allergies in a single bottle.
New York, NY (PRWEB) June 22, 2011
Spring is a time of rejuvenation, re-growth and new beginnings. Flowers blossom, birds sing and the sun peaks over the horizon a little earlier every morning. This is the time to slough off the dregs of winter and re-emerge with a new perspective. But for many this is not a joyous occasion. With the plants and flowers re-awakening come particles such as pollen in the air. These particles can cause havoc with your system when allergies and hayfever are rife.
When foreign bodies enter a person's system, the body's "Ëœreactive' cells are stimulated. These cells such as mast cells and basophills are triggered to release histamine. Histamine is what causes all your allergic symptoms. This is why doctors prescribe "Ëœanti-histamines'.
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Some of the homeopathic ingredients include Ailanthus Glandulosa (Tree of heaven) which detoxifies the body and prevents swelling at the back of the throat. Sabadilla Officinarum (Cevadilla) is indicated for sneezing, runny nose and itchy palate among other things. Basically all the ingredients are carefully selected to deal with various symptoms of this condition.
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For the original version on PRWeb visit: http://www.prweb.com/releases/prweb2011/6/prweb8592764.htm


text: I struggled with the concept of not checking things repeatedly. In fact, you could say I checked things so frequent that I was wasting my life away doing it! The people that mentored me always told me, "Stop checking! It doesn't do you any good." And its true! It doesn't do you any good. Why isn't it good? 1. You're wasting time. You'll be astonished at how much time you can waste just checking ANYTHING repeatedly. Lets take for example, your blog! I find myself amazed … [Read more...]


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4. Companhia Energetica Minas Gerais (CEMIG) (CIG), a Brazil-based electric utility company, engages in the generation, transmission and distribution of electricity, natural gas distribution, telecommunications and implementation and management of systems for electric utilities. The stock accumulated 1.7% at close last week.
Of the five analysts covering the stock, 80% recommend a buy and the rest rate a hold. There are no sell ratings on the stock. A Bloomberg poll expects the stock to gain an average 33.5% to $27.39 in the upcoming 12 months.
The stock has gained on its acquisition spree. The company recently acquired an additional 13.03% interest in Light for $331.8 million, increasing its stake in the latter to 52%. Cemig has indirectly acquired an additional 26.58 million shares of Light's stock by buying investment holding company Luce from Enlighted Partners Venture Capital, as per a regulatory filing.In the long term, the company targets to achieve 20% market share in the various segments of the electricity market. Investments in fiscal 2011 and 2012 are expected at approximately $1.45 billion and $690 million, respectively.