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Our Mission
Our mission is to have millions of people in the Uk sharing the alerts for every missing child and vulnerable adult reported. The aim is to have them found safe and well as quickly as possible x
Missing child alerts system
Providing a professional service and hope for families of missing loved ones. Using Social media, Website & apps,.
The reason I founded Child Alerts Uk in 2011 is because I had no idea of how many children were going missing every day in the UK alone. The worst part of it was the fact that no one knew, we could walk passed a reported missing child and not even know, but now with the help of Social networking sites and our caring natures, we are now getting the faces of the missing children seen, and out of danger. Every child out here in the big world alone is in danger, help us get them back to safety
Now everytime a child is reported missing we get an alert out as soon as possible we know that the first 48 ours are crucial to finding that child alive HELP US TO SAVE LIVES
Copyright 2013. Child Alerts Uk. All Rights Reserved.


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Captain's Place - SAKT 2014
Registration Is Full!
Thank you for being a leader and organizing a team for SAKT 2014. Through your efforts you make a difference in the lives of infants and their families in St. Alexius' Neonatal Intensive Care Unit (NICU) [3].
The links below will help you get your team ready!
- Captain's To-Do List [4] (Download this list if you registered your team online.)
- Captain's To-Do List – Platinum, Gold or Silver Sponsored Team [5] (Download this list if your team is entered through a corporate SAKT 2014 Platinum, Gold or Silver sponsorship.)
- SAKT 2014 Team Roster [6]
- SAKT 2014 Rules [7]
- SAKT 2014 Waiver [8]
SAKT 2014 Team/Individual Fundraising Challenge
The tournament's top fundraising team and top individual fundraiser receives special prizes at SAKT 2014's award ceremony and are recognized in SAKT 2014's thank you advertisement and on the post-event webpage. Here are links to get your team started on its fundraising journey!
- SAKT 2014 Donation Form and Fundraising Challenge To-Do List [9]
- SAKT 2014 How Your Donation Helps [10]
- Fundraise.com instructions [11] (how to set up your fundraising webpage)
- Set up your fundraise.com webpage by clicking here [2]
SAKT 2014 Best Uniform Challenge – Sponsored by Townsquare Media
That's right! We want teams to get creative and come up with the best uniform! There are several uniform categories. The winning uniforms are announced at SAKT 2014's mid-day award ceremony, and those teams win great prizes from Townsquare Media. Click here for more information [12]!
Tournament Check-In and Brackets
Tournament Check-In is Friday, September 26 from 8 a.m. – 6 p.m. at St. Alexius Foundation's office located inside St. Alexius Technology & Education Center at 1310 E Main Ave, Bismarck (between Great Plains Rehabilitation and Burger Time). The tournament brackets are emailed to captains the week of September 22-26.
SAKT Home [1]

subset: commoncrawl


text:
Latest Samsung Instinct Stories
By Jason Gertzen, The Kansas City Star, Mo. Jun. 20--Sprint Nextel on Thursday dodged a potentially crippling blow as federal officials granted more time for a massive project to eliminate interference with public safety radios.
By Jason Gertzen, The Kansas City Star, Mo. Jun. 19--Sprint Nextel is moving to upstage the masterful marketers at Apple with a cheaper touch screen phone it touts as a rival to the iPhone.
Customers of Sprint (NYSE:S) can soon get mobile access to their corporate email accounts on select non-PDA Sprint phones such as the new Instinct by Samsung.
Sprint Nextel Corp. will be taking on the iPhone with a lower price for its own touch-screen smart phone, the Samsung Instinct. The carrier said Wednesday that the Instinct will cost $129.99 when released on Friday.
By PETER SVENSSON AP Technology Writer NEW YORK - This is a review of the 3G iPhone. No, not the one Apple announced on Monday. The other one.
Sprint (NYSE: S) today announced pricing for Instinct, a new wireless device that offers consumers an industry-leading user experience by combining full touch-screen functionality with the fast speeds available on the largest national mobile broadband network.
- A young chicken: also used as a pet name for children.


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Shabby Chic Birthday Cake
This is the ruffle technique that I love doing. It's vanilla cake with buttercream icing. Pink fantasy flower with a Brooch I molded and added pearls to. Hope you enjoy.
Tags: birthday engagement first communion easter wedding mothers day graduation white pink cake vanilla
Lisa McNeil


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Is Institutional Racism Happening In Our Hospitals?
Personal view: Allowing patients to choose the ethnicity of attending doctors is institutional racism
Dr Nadeem Moghal, from George Eliot Hospital in Warwickshire, draws on the Macpherson report (the police investigation which took place following Stephen Laurence's murder) defining institutional racism as "the collective failure of an organization to provide an appropriate and professional service to people because of their color, culture, or ethnic origin".
He says this report is "relevant to every organization, private and public" yet this was not enough in a case which happened in a former workplace where parents of a child patient "refused to have care delivered by black or other minority ethnic doctors". The clinical director at the hospital concluded that the parents' choice "would be enabled". The arrangement continued for more than a year.
However, following a difficult process the parents were told that "care would be provided by staff regardless of their ethnicity" and the family complied.
Dr Moghal asks what we can conclude from this case. He says that there are limits to patient choice and that "when racists are confronted they may ultimately relent".
He says that any organization may find it "hard to accept" that it had behaved in an institutionally racist way but that Macpherson's definition allows understanding and the strengthening of institutions' policies.
Dr Moghal concludes that although it was a difficult journey, the "right outcome was eventually reached" and that the key lesson is "immediately confronting and standing up to racists".
On the Net:


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20 Feb 2014 09:00:49 AM
Gambling Addiction Enabler: 'UFC 170: Rousey vs. McMann' Edition
(Damn, Vin Diesel's acting lessons have clearly taken Rousey's mean-mug to a WHOLE. NOTHA. LEVEL..)
By Dan George
Let us all gather round, hold hands, and pray. Pray that this weekend's UFC 170 manages to rise above the level of the decision-filled snoozefests that were UFC 169 and Fight Night 36. Of course, with a main event featuring Ronda Rousey, whose "kill ratio" is 100% (as Don Frye would put it if he gave two shits about this fight), and a co-main event featuring the biggest squash match of the year (so far), it looks like UFC 170 will rise to the level of those 10 decision events at the very minimum. I'm guessing that sound I just heard was all of you reaching into your wallets for $50.
Regardless of whether or not UFC 170 is able to deliver from an action standpoint, it has plenty of opportunities to deliver from a gambler's standpoint, so join us after the jump for some sexy gambling lines (courtesy of BestFightOdds) and even sexier advice. You know, because women.
The Props:
Josh Sampo (+145) vs. Zach Makovsky (-165)
Makovsky is a perfect 3-0 since dropping down to flyweight and looked outstanding in his upset victory of Scott Jorgensen in his UFC debut at UFC on Fox 9. Sampo is looking to extend his 5 fight winning streak after an equally impressive debut RNC submission win over Ryan Benoit at the TUF 18 finale. The +105 prop that he wins via decision is a nice plus money option, as "Fun Size" should be able to use his NCAA division 1 wrestling to nullify Sampo's submission threat on the ground while getting the better of the exchanges in the stand up department. Makovsky makes the parlay at a bargain -165 to win outright.Read More DIGG THIS


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The present invention relates to an N-input, N-output "Knockout" packet switch (11) which uses decentralized control and distributed routing for routing high-speed, time-multiplexed, variable-length packets of information from the N inputs to the N outputs. More particularly, within the switch, the N input signals are separately synchronized such that the start of each arbitrarily arriving variable-length packet is synchronized to the start of a next mini time period of a sequence of mini time periods common to all inputs. The synchronized N input signals then propagate along separate broadcast buses (14) to each of N bus interface units (15) which include N packet filters (20), a concentrator (21) and a shared buffer (22) capable of processing variable-length packets. Each bus interface unit is associated with a separate one of the N outputs (12) of the switch, and the N packet filters therein are each associated with a separate one of the N broadcast buses for detecting if a packet on the associated bus is destined for the associated switch output. The concentrator is used to (a) reduce the number of separate buffers needed to receive packets which may arrive simultaneously and are destined for the associated output, and (b) only directs a maximum of L concurrently arriving packets to the shared buffer while discarding, or "knocking" out, the remainder. Contending packets at the output of the concentrator are stored in the shared buffer before placement on the output line on a first-in, first-out basis. The discarded packet rate of the "knockout" switch can be made as small as desired and latency of packets in the switch is the smallest achievable by any comparable switch.
1. A switching arrangement employing decentralized control and distributed routing of variable-length packets of information, the switching arrangement comprising:
a plurality of N output terminals (12);
a plurality of N input terminals (10) for receiving N separate input signals, each input signal comprising variable-length packets of information in a time division sequence; and
switching means (11) disposed to receive up to N overlapping variable-length packets of information from the N input terminals during a predetermined time period and for routing each of the packets of information to the destined one of the N output terminals, the switching means being responsive to the reception of a plurality of up to N overlapping variable-length packets of information destined for a particular output terminal for storing up to L of such packets of information for subsequent transmission to the destined output terminal on a first-in, first-out basis from packets of information stored in any subsequent predetermined time period while discarding any overlapping variable-length packets of onformation above the number L, where L<N.
2. A switching arrangement according to claim 1 wherein the switching means comprises:
a plurality of N buses (14), each bus being connected to a separate one of the N input terminals for propagating an associated received input signal therealong; and
a plurality of N bus interface units (15), each bus interface unit comprising
an output connected to a separate one of the N output terminals of the switching arrangement,
means (20) for detecting whether any of the N concurrent variable-length packets of information propagating on the plurality of N buses are destined for the associated output terminal of the switching arrangement, and for passing such packets of information to separate outputs of the detecting and passing means;
means (21) for concentrating the N concurrent output signals from the detecting and passing means into L concurrent output signals which appear at separate ones of L output terminals of the concentrating means, where N>L and the L output signals include all of the concurrent variable-length packets of information destined for the associated output up to a maximum of L of such packets of information; and
buffering means (22) responsive to the L output signals from the concentrating means for temporarily storing each of the variable-length packets of information destined for the associated output and then transmitting such stored packets of information in a first-in, first-out sequence.
3. A switching arrangement according to claim 2 wherein the buffering means comprises:
a plurality of L packet buffers (61) for temporarily storing the variable-length packets of information received from the concentrating means and destined for the associated output of the switching arrangement; and
control means (60, 62-64) for directing each of the concurrently received variable-length packets of information from the concentrator means into a separate one of the plurality of L packet buffers and for routing each of the packets of information stored in the plurality of L packet buffers onto the associated output terminal of the switching arrangement in a first-in, first-out sequence.
4. A switching arrangement according to claim 2 wherein the control means of the buffering means comprises:
a switch (60) including (a) L input terminals for receiving separate ones of the L concurrent output signals from the concentrating means during any instant of time, (b) L output terminals, and (c) means (62-64) for routing any packets of information received from the concentrating means at each of the L inputs, and destined for the associated output terminal of the switching arrangement, to separate ones of the L output terminals;
an input controller (62) for causing the routing means to interconnect each of its L input terminals to the appropriate one of its L output terminals for the duration of the transmission therethrough of each of the variable-length packets of information to be stored in the associated plurality of L packet buffers; and
an output controller (63, 64) for routing the variable-length packets of information stored in the plurality of L packet buffers onto the associated output terminal of the switching arrangement in the first-in, first-out sequence.
5. A switching arrangement according to claim 2, 3 or 4 wherein the concentrating means comprises:
means (30) for determining, at any instant of time, which of the N inputs comprise valid variable-length packets of information destined for associated output terminal of the switching arrangement; and
means for directing each of up to L concurrently received valid variable-length packets of information from the determining means to a separate free one of the L output terminals of the concentrating means while discarding any concurrent packets of information above the value L.
6. A switching arrangement according to claim 5 wherein the directing means of the concentrating means comprises:
contention means (31), responsive to the determining means of the concentrating means detecting that any one or more of the N input terminals includes a separate packet of information destined for the associated output terminal of the switching arrangement, for generating control signals indicative of which of any concurrently received packets of information are to be directed to certain ones of the L output terminals of the concentrator means.
7. A switching arrangement according to claim 6 wherein:
the determining means transmits both (a) a control signal indicative of the reception of a valid packet of information destined for the associated output terminal of the switching arrangement and (b) the received packet signal delayed by a predetermined time period to the contention means; and
the contention means comprises:
a contention circuit for determining which of the L output terminals of the concentrating means are already transmitting a variable-length packet of information, and responsive to the control signals from the determining means, for generating second control signals indicative of which one of the free output terminals of the concentrating means a newly arrived valid packet of information should be directed to, and
N:L switching means including N input terminals and L output terminals, the N:L switching means being responsive to second control signals from the contention circuit for routing up to L concurrent variable-length packets of information to the L outputs of the concentrating means.
8. A switching arrangement according to claim 1 or 2 wherein the switching arrangement further comprises:
input interfacing means connected to the plurality of N input terminals comprising;
means for detecting the start of each variable-length packet of information, and
means for synchronizing the start of each received variable-length packet of information with the start of a predetermined submultiple time period which is common to, and less than, the overall time period for the reception of any possible variable-length packet of information.
9. A switching arrangement according to claim 8 wherein the submultiple time period corresponds to one or more bytes of information forming a part of any possible variable-length packet of information to be received.
10. A switching arrangement according to claim 8 wherein the input interfacing means further comprises:
means for (a) determining both the output terminal of the switching arrangement to which each received variable-length packet of information is destined and the end of each packet of information, and (b) adding a first control word within a first submultiple time period of each packet of information including the address of the output terminal to which that packet of information is destined, and a second control word at the end of each packet of information including an end-of-transmission code for that packet of information.
11. A switching arrangement according to claim 10 wherein the switching arrangement further comprises:
output interfacing means connected to the plurality of N output terminals comprising
means for removing any control words added by the input interfacing means and for formatting each variable-length packet of information from the switching means according to a predetermined protocol required by an external device which is to receive the packet of information.
The present invention relates to a switching arrangement for routing high-speed, time-multiplexed variable-length packets of information from N inputs to N outputs in a high-performance packet switching system. More particularly, the present switch uses distributed control and a fully interconnectable configuration to route arbitrarily arriving variable-length packets from the N switch inputs to their appropriate outputs using a single stage of switching which includes a minimum amount of buffering and provides the lowest packet latency in any switching arrangement.
Every type of communication network interconnecting more than two users depends on some form of switching to efficiently route information among the various users. In such switches, the traffic presented at two or more inputs may be destined for a common output. There are basically only two ways that such a situation can be managed.
First, the switch may require a controller that schedules the arrivals of packets to avoid conflict. The classic Time-Space-Time switch shown in FIG. 3.6 at page 95 of the book by H. Inose entitled "An Introduction To Digital Integrated Communications Systems", University of Tokyo Press, Tokyo, Japan, 1979, falls into this category. There, each input to the switch is preceded by a Time Slot Interchange to rearrange the time sequence of the time-multiplexed traffic so that, when presented to the switch, the data appearing at the N inputs are, at all times, destined for distinct separate outputs. However, scheduling is a difficult task, as shown by T. Inukai in IEEE Transactions on Communications, Vol. COM-27. No. 10, October 1979 at pages 1449-1455 and, although feasible and adequate for circuit switching, requires too much time to determine permissible input/output combinations to be applicable for packet switching.
The second way, and perhaps the more attractive approach for managing contention, employs decentralized control and distributed routing wherein each packet or burst of traffic contains a header bearing the destination port of the switch for that packet, where the header is used in routing the packet through the switch. Without the coordination afforded by the central scheduler, the switch must now recognize conflict among its inputs and internally store, or buffer, all but at most one of several simultaneous arriving packets destined for a common output, thereby leading to statistical delay, or latency, within the switch. Such self-scheduling switches, as shown in the article by D. M. Dias et al. in GLOBECOM '84, Vol. 1, Atlanta, Ga., Nov. 26-29, 1984, pages 5.2.1-5.2.7, typically employ binary switching elements appropriately interconnected and arranged to form a multistage switch. These switches have tended to emphasize a reduction in the number of switch elements needed to a value below that of a fully connected arrangement, one wherein each input has a dedicated path to each output and thereby requiring N2 elements. In addition to congestion at the outputs, these element-efficient switches can also congest at each of the binary switch points, thereby requiring that additional measures be taken, such as buffering within each element. Because these autonomous buffers cannot be shared among elements, the complexity of the buffering is typically much greater than that of the binary switching elements themselves. Moreover, the delay encountered within the network is greater than the unavoidable component caused by destination congestion alone.
The problem remaining in the prior art is to provide a switch which (a) can be used to switch packets which arrive arbitrarily at the N inputs of the switch and include variable lengths and (b) avoids (1) the scheduling problems encountered with switches requiring controllers, and (2) the buffering complexity and delays encountered by the decentralized control and distributed routing switches.
The foregoing problem in the prior art has been solved in accordance with the present invention which relates to a switching arrangement for routing high-speed, time-multiplexed variable-length packets of information from N inputs to N outputs in a high-performance packet switching system. The present switch uses distributed control and a fully interconnectable configuration to passively route arriving variable-length packets to their appropriate outputs using a single stage of switching.
It is an aspect of the present invention to provide a switching arrangement for routing multiple variable-length high-speed, time-multiplexed packets of information from the N inputs to the N outputs using decentralized control and distributed routing. The switching arrangement comprises two basic characteristics: (1) each input has a separate broadcast bus, and (2) each output has access to the packets of information arriving on all inputs. More particularly, each output passively interfaces to the complete set of N input buses and provides several important features. First, no switch blocking occurs where packets destined for one output interfere with packets going to other outputs. Second, the broadcast buses can reside on an equipment backplane with the circuitry for each of the N input/output pairs placed on a single plug-in circuit card. Third, with each bus being driven by only one input it allows for a higher transmission rate on the buses than found with a shared parallel bus accessed by all inputs. Lastly, since every input is available at the interface to every output, arriving packets can be addressed to, and received by, multiple outputs and thereby lends itself to broadcast and multicast features.
It is a further aspect of the present invention to provide a "Knockout" switching arrangement for routing variable-length, high-speed, time-multiplexed packets of information from N inputs to N outputs using decentralized control and distributed routing. Structurally, each of the N input signals has the start of each of its arbitrarily arriving variable-length packet synchronized to the start of a next mini time period of sequential mini time periods common to all inputs, where each mini time period is less that the length of any packet of information. The N input signals propagate along separate buses to each of N bus interface units which include N packet filters, a concentrator and a shared buffer. Each bus interface unit is associated with a separate one of the N outputs, and the N packet filters therein are each associated with a separate one of the N buses for detecting if a packet on the associated bus is destined for the associated output using an address disposed in the packet during a first mini-time period. The concentrator is used at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets. The contending packets are stored in the shared buffer before placement on the output line on a first-in, first-out basis.
Other and further aspects of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings.
Referring, now to the drawings in which like numerals represent like parts in the several views:
FIG. 1 illustrates a block diagram of an N-input, N-output time slotted packet switching arrangement in accordance with the present invention including typical different length packets arriving in a time-slotted sequence at the N inputs and routed to the appropriate N outputs;
FIG. 2 is a block diagram of one of the N bus interface units of the switching arrangement of FIG. 1;
FIG. 3 illustrates an exemplary packet format received by an input interface module of FIG. 1;
FIG. 4 illustrates an exemplary packet format at the output of an input interface module in FIG. 1;
FIG. 5 is a block diagram of an exemplary arrangement of the concentrator of FIG. 2:
FIG. 6 shows an exemplary arrangement of a contention interface in the concentrator arrangement of FIG. 5;
FIG. 7 illustrates a exemplary arrangement of the N:L data switch in the exemplary concentrator arrangement of FIG. 5;
FIG. 8 is a block diagram of an exemplary block diagram of the contention circuitry in the exemplary concentrator arrangement of FIG. 5;
FIG. 9 shows an exemplary block diagram of a shared buffer arrangement in the bus interface unit of FIG. 2; and
FIG. 10 is an block diagram of an exemplary alternative arrangement for the shared buffer in the bus interface unit of FIG. 2.
The switching arrangement in accordance with the present invention includes an N-input, N-output packet switch using decentralized control and distributed routing with all inputs and outputs operating at the same bit rate. Variable-length packets arrive at the N inputs 101 to 10N of the present N-by-N switch 11 in a manner in which each input includes sequential packets having destinations as determined by the individual remote N transmitters sending the packets, as shown in the exemplary sequences of FIG. 1. Each packet in such arrangement contains, somewhere therein, the address of its destination output as shown in the exemplary packet format of FIG. 3.
Aside from having control over the average number of packet arrivals destined for a given output, no control over the specific arrival times of packets on the inputs and their associated output addresses is assumed. In other words, there is no sequential specific scheduling that prevents two or more packets from arriving at different inputs in the same or overlapping time period and destined for the same output, as shown in FIG. 1 for the arriving inputs 101, 102 and 10N which include overlapping packets that are destined for output 121. The addressing information included in each packet is used by N-by-N packet switch 11 to route the incoming packets to their appropriate outputs 121 to 12N. Hence, to avoid lost packets, or at least provide a sufficiently small probability thereof, at a minimum, packet buffering must be provided in switch 11 to smooth fluctuations in packet arrivals destined for the same output.
The interconnection arrangement for N-by-N packet switch 11 has two basic characteristics: (1) each input 101 to 10N is associated with a separate broadcast bus 141 to 14N, respectively, and (2) each output 121 to 12N has access to all packets arriving on all inputs. As shown in FIG. 1, packets arriving at each of the N inputs 10i are processed by a separate input interface module 16i and placed directly on a separate broadcast bus 14i, and each output 121 to 12N of switch 11 passively interfaces to the complete set of N buses 14 via a separate bus interface unit 151 to 15N, respectively and then respective output interface modules 171 to 17N. This simple structure provides several important features within switch 11. First, with each input having a direct path to every output, no switch blocking occurs where packets destined for one output interfere with (i.e., delay or block) packets going to other outputs. The only congestion in the switch takes place at the bus interface unit 15i to each output 12i, where packets can arrive concurrently on different input lines 10 destined for the same output 12i. Without a priori scheduling of packet arrivals, this type of congestion is unavoidable, and dealing with it typically represents the greatest source of complexity within a packet switch. This complexity is minimized by the present N-by-N packet switching arrangement 11.
The input and output modules 16i and 17i are usually necessary in practical applications because of the large variety of line signals and packet protocols available, where the present "Knockout" switch is proposed to be compatible with most of them. The input interface modules 16i are each designed to accept a digital stream at a high-speed rate of R Mb/s, where, for example, R=45 Mb/s hereinafter. Each of these exemplary 45 Mb/s lines may carry incoming packets of different lengths, and different lines may carry packets of different protocols. An important function of the input interface module 16i is to recognize the beginning and the end of each arriving packet from the associated line. For example, as shown in FIG. 3, a typical packet format may include a flag 26 in the beginning, followed by a control field 27 comprising address information plus some other control bits, then a number of information bits, some error control bits and finally terminated by a flag 28 at the end. In order to make the flags 26 and 28 unique in the digital sequence, it is customary to add "stuffing bits" to the original data. As an exemplary standard procedure, the input interface module 16i should first strip off the framing flags 26 and 28 and then remove the stuffing bits. After doing so, the unframed and de-stuffed packet length is assumed to be an integer multiple of bytes. To the beginning of each of these bytes from the original packet, it is preferred that input interface module 16i insert, for example, a single bit "0" to form exemplary successive 9-bit words. Furthermore, each input interface module 16i attaches two exemplary 9-bit control words preceding this entire data sequence and appends an exemplary single 9-bit control word at its end as shown in FIG. 4. Because of the additional bit added to each byte in this process, the bit rate at the output of each input interface module 16i is increased from the exemplary 45 Mb/s rate to the exemplary Ro =9R/8 Mb/s, or 9(45)/8=50.6 Mb/s. This is done to facilitate the features of supporting self-routing and variable-length packets as will be described hereinafter.
In the newly formatted packet shown in FIG. 4, the three control words are seen to frame the original data bytes which have been expanded into exemplary 9-bit words with prefixed zeros. The first two control words span an 18-bit field which is called the control header and is marked uniquely by, for example, two leading 1's. The rest of the field preferably contains two pieces of special data comprising a 10-bit sequence called a local address and 6-bit sequence called a modular packet length. The local address denotes the specific output of "Knockout" switch 11 for which the packet is destined. With 10 bits available, up to 1024 outputs may be specified which is assumed to be the maximum switch dimensions. This local address is derived simply by looking at the address information in the original packet and then performing an address translation with a virtual circuit table. The modular packet length, on the other hand, is generally something that is not available in prior art packet protocols. Although this information is not absolutely required for present "Knockout" switch 11, it is suggested that the information be included.
A number of possibilities for including the modular packet length information exists. For example, the original packet protocol can usually be modified to carry one more control word at the packet originating source; or some packet length information can be added during its passing through an intermediate store-and-forward node. In any event, if the packet length information is available to input interface module 16i, it will be translated into an exemplary 6-bit digital word called the Modular Packet Length for insertion after the local address as shown in FIG. 4. This translation amounts to deciding which of the exemplary 64 predetermined packet sizes the current packet belongs to, and its actual implementation could be very simple. For example, if the maximum packet length is assumed to be 512 bytes, every packet length can be represented as a 9-bit digital word, and the Modular Packet Length can be defined as the most significant 6 bits of this 9-bit word. If the packet length is not available to the Input Interface Module, the default value becomes the maximum allowable packet size in the system. During high congestion periods, the smaller packets will have a higher probability of getting through switch 11 while the maximal length packets will stand the first chance to be dropped upon a buffer overflow.
After adding the two leading 9-bit control words to a newly arrived packet, the input interface module 16i is ready to send data (in exemplary 9-bit words) to "Knockout" switch 11. But module 16i has to do so in a synchronous manner governed by a clock (not shown) associated with switch 11. For example, bit synchronization is provided by a clock associated with switch 11 at the Ro (exemplary 50.6 Mb/s) rate with word framing done at the exemplary Ro /9 rate. Moreover, the leading control words for each packet must be synchronized with the start of message clock which may be a clock pulse mark every 27 bits (or three 9-bit words), i.e., at the Ro /27 rate. More particularly, the start of each packet is synchronized with the next clock pulse mark after its arrival. Therefore, the transmissions from all input interface modules 16i are done synchronously while the incoming packets arrive at the different input interface modules asynchronously. This implies that an elastic buffer has to built into each input interface module 16i. At the end of each packet transmission, the input interface module 16i is also shown to append a single 9-bit control word in which the first bit is set to "1" to denote control; the second bit is set to "0" to denote end-of-transmission; and the remaining 7-bit field carries the Next-Packet address which is added inside switch 11 as will be explained hereinafter.
The output interface module 17i is quite simple. It merely removes both the three control words framing each packet and the additional control bit added to each data byte. The net result is a packet as originally received minus the stuffing bits and flags. The packet can then be easily stuffed and flagged according to the specific protocol required for the output device or communication link. The physical transmissions from output interface module 17i can then be matched to some external clock.
The broadcast bus structure of switch 11 in FIG. 1 has the desirable characteristic that each bus 14i is driven by only one input 10i from an associated Input Interface Module 16i. This allows for a higher transmission rate on the buses and a design more tolerant of faults compared with a shared parallel bus accessed by all inputs. In addition, the packet buffering and bus access control circuitry of the known shared parallel bus architecture is replaced in the present switch 11 by, at most, an elastic buffer at each input which is used to synchronize the time slots from the individual input lines.
FIG. 2 is a block diagram of an exemplary bus interface unit 15i associated with each output 12i of N-by-N packet switch 11. The bus interface unit 15i shown has three major components. First there is a row of N packet filters 201 to 20N, with each packet filter receiving the packets propagating on a separate one of broadcast buses 141 to 14N. In each packet filter 20i, the Local Address of each packet coming to its input is examined and a distinction between valid and invalid packets for the associated output is declared. In so doing, packet filter 20i reduces the control header for all packets from the exemplary 18 bits to 9 bits. If the Local Address agrees with the associated output line number, the packet is valid and its control header will contain two leading 1's, with the rest of the space filled by the exemplary 6-bit Modular Packet length information plus a spare bit. For a mismatched or invalid packet, its new 9-bit control header will contain two leading 0's instead of 1's. The rest of the packet, however, will be completely unaltered. Although invalid packets are not physically blocked, they are in fact marked to be discarded in later stages by virtue of having two leading 0's in their control headers. Because all packets must synchronize their beginnings to the start-of-message clock, the checking of addresses can be done conveniently with, for example, only one shift register storing the relevant output line number.
The minimum delay from input to output through a packet filter 20i is, for example, 12 bits, where 9 bit are from the first word of the original control header plus the leading 3 bits of the control header's second word. In practice, however, it might be advantageous to deliberately lengthen the delay to be exactly the exemplary 18 bits of the control header, or two 9-bit words, for easy maintenance of the synchronous clocks in the entire system. In any case, the N outputs carrying the packets with the short control headers are delivered to a concentrator 21 forming the second component of each bus interface unit.
Concentrator 21 receives the outputs of all associated packet filters 201 to 20N at separate inputs and achieves an N-to-L (L<<N) concentration of the input lines, where up to L concurrently received packets destined for an output making it through the packet filters emerge at the L outputs of concentrator 21. Therefore, concentrator 21 only has to deal with valid packets destined for an associated output, the number of which may conceivable vary from 0 to N. Concentrator 21, however, must be able to account for variable length packets. More particularly, once a connection is granted for a packet within concentrator 21, then it must be guaranteed for the entire duration of the packet, and contention for that path, or output, in concentrator 21 cannot be resumed until the completion of that packet's transmission.
To minimized hardware complexity, the constraint is added that all packets, although of different lengths, must start at the beginning of some narrow time slot, and thus the necessity of the start-of-message clock mentioned earlier. For circuit speed at the exemplary 50 Mb/s, N=128 and L=8, the minimum contention time required would be about 23 bit periods or approximately 460 nsec. By setting the start-of-message message clock to be Ro /27, i.e., each cycle contains three 9-bit words, it should be more than adequate to account for the contention required. A block diagram for an exemplary 128:8 concentrator 21 is shown in FIG. 5.
As shown in FIG. 5, the packets entering concentrator 21 are first passed through contention interfaces 301 to 30N. Each contention interface performs two simple tasks: (1) it continuously looks for the pattern of two consecutive 1's in the beginning of each start-of-message cycle which signifies the arrival of a valid packet and reports the result to contention circuitry 31; and (2) it provides a fixed delay or, for example, D bits to the entire incoming bit stream. This delay D represents the combined total of the detection time for each valid packet arrival, the contention time required by contention circuitry 31 and the control set-up time needed by an exemplary 128:8 Data switch 32 before a reconfiguration. The contention and set-up times are, in turn, determined by the specific designs adopted. In the present arrangement, D is chosen to be, for example, 32 bits and it should be noted that the bit streams propagating through the contention interfaces are totally unchanged.
A contention interface 30i can be implemented in a straight-forward manner as shown in FIG. 6. In FIG. 6, the input from the associated packet filter 20i is received at a delay means 34 which provides the necessary delay D as explained above. Concurrent therewith, the input signal is received in a 1-bit delay circuit 35 and an AND gate 36. This combination looks for the two leading 1s indicating a valid packet and generates an enable signal, C', to a second AND gate 37. Such enable signal permits an 8-bit code word, C, comprising a leading activity bit "1" and a 7-bit input line number (the one of the exemplary 128) to be transmitted from circuit 38 to contention circuit 31, where the input line number is its own input 10i from which the valid packet was received. Therefore, output P is merely the delayed version of the input bit stream, and output C serves to signal contention circuitry 31 for the arrival of a valid packet that needs to enter immediate contention for subsequent transmission through the 128:8 data switch 32. The exact signal format for signal C again depends on the specific design of contention circuitry 31. The detection time for signal C to become active after a packet has entered contention interface 30i should be no more than, for example, 2 bits because only the pattern of two consecutive 1's has to be matched for the present exemplary header bits. All C outputs are connected to contention circuitry 31 and the P outputs are connected to data switch 32. Contention circuitry 31 has the responsibility of resolving conflicts between multiple packet arrivals by deciding which of the inputs are to be connected to the 8 outputs through the exemplary 128:8 data switch 32.
The exemplary 128:8 data switch 32 is essentially a space-division switch which connects specific inputs to the 8 outputs upon command by the contention circuitry 31. New updates on its configuration are allowed at instants marked by the start-of-message clock, i.e, every 27 bits. Once a valid packet is granted a path through data switch 32 the same path is guaranteed for the entire duration of the packet. Various implementations are possible for data switch 32 as, for example, using a cross-bar type N:L switch, or using a separate 1:L for each input to access any output. Each of such implementations may provide a disadvantage of excessive signal delay or a cumbersome switch. The design shown in FIG. 7 overcomes some of these disadvantages and uses eight 128:1 multiplexers 401 to 40L, responsive to control signals from contention circuitry 31, which permits any one of the N inputs to access the appropriate associated output as is well known in the art.
An exemplary design for contention circuitry 31 is shown in FIG. 8. When the arrival of a valid packet is detected in an associated contention interface 30i, its C output generates a digital word denoting its own input line number preceded by an activity bit of "1" as described hereinbefore. This is carried out at the onset of each start-of-message cycle which occurs every 27 bits in accordance with the exemplary arrangement proposed before. The activity bit in the C word is set to "0" for all cases other than the fresh arrival of a valid packet as can be seen from FIG. 6. These 8-bit words generated at the C outputs of contention interfaces 30 are supplied to contention circuitry 31 where they are regarded as individual packets for contention. These C words from the N contention interfaces 301 to 30N enter an N:L "knockout" concentrator 50 from which 8 winners are derived out of the 128 possible contenders.
An arrangement for an exemplary "Knockout" concentrator which can be used for concentrator 50 is described in the copending patent application filed for A. Acampora et al. concurrent with the present application. In a first section of such arrangement, the N inputs from the associated contention interfaces 30 are paired and enter a row of N/2 switching elements. This may be viewed as a first round of a tournament with N players, where the winner of each match emerges from a predetermined side of 2�2 switching elements and the loser from the other side. The N/2 winners from the first round advance to the second round where they compete in pairs as before using a row of N/4 2�2 switching elements. The winners in the second round advance to the third round and this continues until two compete for the championship; that is the right to exit the first output of concentrator 50. The losers from the first section of concentrator 50 can begin competing in a subsequent section before competition is finished in the next previous section. Delay elements can also be included to compensate for an odd number of players in any section. In such manner, L outputs can be derived from the N inputs. A packet losing L times, however, is "knocked out" of the competition and is discarded by concentrator 50 in its last section. In all cases, packets are only lost if more than L packets arrive concurrently at any time, which can be designed to be a low probability occurrence.
The winning line numbers from "Knockout" concentrator 50 are first stored in a set of registers 511 to 51L designated Winning Registers (WR). Winning Registers 511 to 51L are connected in parallel to another duplicate set of Control Registers (CR) 521 to 52L, respectively, through a set of respective transfer control switches 531 to 53L under the control of End-of-Packet Transmission detectors 541 -54L respectively. As shown in FIG. 8, control register 521 is only connected to winning register 511, but control register 522 may be connected to winning registers 511 or 512 via control switch 532, and control register 52L may be connected to any of the L winning registers 511 to 51L via control switch 53L. Control registers 521 to 52L receive the data from the winning registers 51, and the data are precisely the line numbers needed to set proper connections for Data switch 32. The data transfers between these registers can only occur at intervals synchronous to the start-of-message clock, or when Data Switch 32 can be updated because of the variable length packets passing therethrough.
For purposes of discussion, assume that at some moment of time all eight paths in the exemplary 128:8 Data switch 32 are active with valid packet data coming through. This implies that the activity bits in all eight control registers 52 are 1's. For each control register 52, as long as its activity bit is a "1", it would not accept any transfer from winning registers 51. The activity bit can only be reversed to a "0" upon detection of the end of a packet by each of the End-Of-Packet Transmission detectors 541 to 54L, which detectors 54 are responsive to such signal formed by the 9-bit appended control word of FIG. 4 received from the N:L data switch 32. In such case, the particular control register 52i involved has to decide from which of the winning registers 51 it should receive its next connection line number. Such transfer arrangement reflects the intentional priority technique that control register 521 is entitled to the first winning line number, and register 521 can take winning register 511 only if control register 521 does not ask for a transfer at the same time, otherwise register 522 takes the line number from winning register 512. With such logic, for i=2 to 8, each control register 52i has to look at its predecessors, namely control registers 521 to 52i-1 and count low many of them are asking for a transfer. Then control register 52i will receive a transfer from the next one.
In a data transfer, the activity bit in a control register 52 is automatically carried over from the winning register 51, which could actually be a "0" in the event that no valid packet was available. The implementation required for such control is straightforward and involves only simple logic gates, flip-flops and adders. The control set-up time and the data transfer time between registers should be designed to be no more than, for example, 5 bits. Various delay requirements may be, for example: (1) the checking time for a valid packet arrival is 2 bits; (2) the contention time through "Knockout" concentrator 50 is 23 bits; and (3) the data switch 32 set-up time is 5 bits. Thus the exemplary delay totals 30 bits and a delay D of 32 bits in delay 34 of contention interface 30i should, therefore, provide a reasonable margin to satisfy the timing requirements. It should also be noted that when the end of a valid packet under transmission through the exemplary 128:8 data switch 32 is detected, i.e., after the leading "10" of the last 9-bit control word of FIG. 4 has exited data switch 32, the next two bits in this past word are already in transit inside data switch 32, and only 5 bits remain before the next configuration for this particular output might have to take effect. For this reason, it is important to design the switch control set-up time and data transfer between the winning registers 511 to 51L and control registers 521 to 52L to be within 5 bits as suggested above.
The L concentrator outputs then enter a shared buffer 22 which can comprise the exemplary arrangement shown in FIG. 9. In FIG. 9, shared buffer 22 is shown as comprising an LXL switch 60, a plurality of L First-In, First-Out (FIFO) buffers 611 to 61L, and a control section including an input control 62, a log2 L bit wide FIFO 63, and an output control 64. More particularly, shared buffer 22 receives the L data lines from concentrator 21 and feeds one output data line to the output interface module 17i. All of the shared buffer's input and output lines operate at the same data rate, e.g., the exemplary 50 Mb/s. If each switch output is modeled as an M/M/l/K queue as indicated in the book by L. Kleinrock entitled Queueing Systems, Vol. 1: Theory, John Wiley & Sons, N.Y., N.Y., 1975, at page 130, the buffer must be sized, for example, to hold approximately 60 packets to keep the overflow probability below 10-5 with an 85-percent load on the switch 11. The most demanding characteristic of shared buffer 22 is that it must preserve the first-in, first-out discipline as the variable-length packets come through. The arrangement of FIG. 9 accomplishes such task.
In the arrangement of FIG. 9, the L input line of switch 60 can be connected to any one of L FIFO buffers 611 to 61L. When a new packet arrives from one of the input lines, an input controller 62 has to decide which of the L FIFOs this packet should go based on the Modular Packet Length of the new packet, as found in the second control word shown in FIG. 4, as well as the buffer occupancy status of the system. After making this connection, the input control 62 stores the FIFO number assigned for this packet in a separate FIFO 63 which has to be, for example, 3 bits wide if L=8. This latter FIFO 63 can be called the Packet Order FIFO as it contains the specific ordering of successive packets as they come into the system. The unloading of packets from the data buffers 61 is done according to the 3-bit word from packet order FIFO 63 via output control 64 so that the first-in, first-out discipline can be maintained. In other words, the output controller 64 fetches an exemplary 3-bit word from Packet Order FIFO 63 to direct the output to read a packet from a particular data buffer 61i. Then upon detection of the end of packet via the end control word of FIG. 4, output control 64 fetches another exemplary 3-bit address from FIFO 63 for pinpointing the next packet location in buffers 611 to 61L. The main advantage of this technique is the ease of implementation with FIFO buffers. The disadvantage is that the FIFO buffers are usually slower in speed than random access memories (RAMs).
It is to be understood that various approaches can be used for implementing shared buffer 22, and that the present invention is not limited to the arrangement of FIG. 9. For example, an alternative arrangement for shared buffer 22 can comprise the arrangement shown in FIG. 10. FIG. 10 is a block diagram with parallel random access memories to realize the equivalent of a circular buffer. The L input lines, each running at the same data rate, are individually connected to a separate corresponding one of serial-to-parallel (S/P) converters 701 to 70L. For ease of illustration, 9 bits will be selected as an example for the S/P converter length and hereinafter L' will be considered as equal to 9. The serial 9-bit words as received are converted to 9 bits in parallel. The first bits of all the input lines are collected through the multiplexers 711 to 71L, to go into the first connected RAM in a serial manner at the input data rate. Similarly the other bits from the various inputs are also grouped correspondingly for writing onto separate RAMs as shown.
As a result, if one looks at the parallel RAMs 721 to 72L, at a given instant in time during the write cycle, the RAMs are accepting a 9-bit word from the same input line. In other words, the simultaneous 9-bit parallel words from the L input lines are stacked across the L' (9) parallel RAMs (or equivalently one 9-bit wide RAM) one after another in time. Their write addresses are not contiguous as they must follow the assigned positions for their packet locations. It should be noted that it takes only L write cycles at the input data rate to finish the recording of the L input words. Where L=8 and L'=9, this leave one cycle vacant in the 9-cycle period for the nine parallel RAMs, and it can conveniently be used for reading. The read addresses for consecutive read cycles are contiguous, except at the end of each packet where a jump might be required. The output from RAMs 721 to 72L, is parallel-to-serially (P/S) converted in P/S converter 73 to provide serial data to the output interface module 17i. A key characteristic of this implementation is that the RAM speed required is precisely that of the input data rate.
By using the Modular Packet Length control word, as shown in FIG. 4, in the control header, the memory space can be allocated as sensibly as the up-to-date status permits. In fact if an incoming packet fails to declare its approximate length, there is no choice but to assume the maximum in its storage allocation. It is easy to see that under high congestion conditions, a packet declared to be small will have a much better chance to enter into the buffer than an undeclared or, therefore, a maximum-sized one. When the huge disparity between large and small packets are taken into account, e.g., 10 bytes versus 512 bytes, it make sense to drop a large packet under high congestion first so that a considerable number of the small ones can get through.
It is to be understood that the abovedescribed embodiments are simply illustrative of the principles of the invention. Various other modifications and changes may be made by those skilled in the art which will embody the principles of the invention and fall within the spirit and scope thereof. For example, it should also be noted that the interconnection architecture of the present "Knockout" switch 11 lends itself to broadcast and multicast features. Since every input 10 is available at the bus interface units 15 to every output 12, arriving packets can be addressed to, and received by, multiple outputs. Additionally, the present switch can also grow modularly in the manner described for the fixed-length packet "Knockout" switch in the copending patent application filed for A. Acampora et al. on the same day as the present application.
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Description Since the tragedy of 9/11, security in the United States has taken on a new dimension. The demand for effective solutions to ensure the safety of the public and protect civilian and government installations has accelerated, bringing with it the demand and the opportunity for innovations in perimeter security.
Guardium's perimeter security system addresses the critical period between the initial warning of perimeter intrusion and response. Operating in the perimeter fence area, Guardium deploys its unmanned ground security vehicle (UGV) to continuously patrol, survey, and report on the status of the perimeter area and react immediately to isolate, contain, communicate with, and control intruders until backup support arrives. Each high-speed UGV can be equipped with sensors to navigate varied terrain, cameras that relay field data, voice communication capabilities, and other operational means.
The brain of the Guardium system is the C4I (command, control, communication, computer, and intelligence) center, which monitors and controls UGV activity and continuously processes data. As appropriate, the C4I commander can override automatic vehicle operation and assume direct control. This security solution significantly improves incident response times, minimizes the manpower required for continuous monitoring, and reduces security personnel exposure to physical danger.
Applications The Guardium system is a first responder for perimeter intrusion that is appropriate for a broad range of civilian and military applications including:
- Transportation facilities: airports, ports
- Key government installations and assets
- Military bases and installations
- Land borders
- Nuclear and electric power plants
- Oil and gas refineries and storage areas
- Oil and gas pipelines
- Railroad lines/tracks
- Sensitive industrial areas
- Private property - farms and ranches
- Wildlife reserves and safaris
- Prisons and detention centers
Further developments will include mines and roadside bomb detection, and the use of customized scenarios for simulation training.
For more information please visit G-NIUS Unmanned Ground Systems site
IAI and its products are not affiliated with Guardium Inc.
IAI and its products are not affiliated with Guardium Inc.


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Microsoft's week: Latest Windows 10 build and Office for Android phones
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Apple has sent out invitations for an event on 22 October – next Tuesday – where it is widely expected to unveil a host of new products. The event invite reads: "We still have a lot to cover."
This is likely to include a Retina display iPad Mini, a new full-size iPad, a brand new MacPro computer tower, a series of new MacBook laptops and further updates about its new Mac OS X, called Mavericks, as well as its release date.
The Apple event had been widely expected, and it comes around six weeks after the firm unveiled its new iPhone 5S and 5C smartphones.
The event is also a chance for the firm to address problems and criticisms of iOS 7, of which there have been many, such as iMessages not being sent and problems with battery life. Many users have been left hugely frustrated by these issues.
However, Apple chief executive Tim Cook and his cohorts may just focus on the unveiling, which is likely to lead to more clamour for products from the firm.
The event date is bad news for Nokia and Microsoft, both of which have major events planned for 22 October. Nokia is hosting its Nokia World event in Dubai, where it is expected to unveil a series of new devices.
Meanwhile, Microsoft's new Surface 2 and Surface Pro 2 tablets will be going on sale. However, with Apple showing off new iPad models – which will also mean older iPads fall in price again – it could find interest mooted as consumers continue to favour Apple.
Dan Worth is the news editor for V3 having first joined the site as a reporter in November 2009. He specialises in a raft of areas including fixed and mobile telecoms, data protection, social media and government IT. Before joining V3 Dan covered communications technology, data handling and resilience in the emergency services sector on the BAPCO Journal.
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Over 54% polling, almost 15% more than the previous election, was registered in seven Lok Sabha seats in Bihar today in the second phase in the state.
Elections held for Munger, Nalanda, Patna Sahib, Patliputra, Arrah, Buxar and Jehanabad seats registered 54.04% at the end of polling at 6:00 pm, EC sources said.
It was 39.33% in the seats in 2009.
All the seven seats recorded above 50% voting with Buxar topping the list at 57%, while Patna Sahib and Patliputra registered 52%, the sources said.
Voting picked up late at Nalanda the home constituency of Chief Minister Nitish Kumar and reached 55%.
RJD chief Lalu Prasad's eldest daughter Misa Bharti, actor-politician Shatrughan Sinha, former union home secretary R K Singh were among 117 candidates whose electoral fates were sealed in EVMs.
Arrah from where former union home secretary RK Singh was in the race from BJP saw 53% voting against 35.77% last time.
The chief minister cast his vote at a booth in Bakhtiyarpur under the Patna Sahib parliamentary constituency.
Lalu Prasad and his wife Rabri Devi voted at a booth in Patna as also Shatrughan Sinha.
Governor DY Patil and his wife voted at a school near Raj Bhawan.
In Jehanabad, RJD and CPI-ML workers clashed outside at booth in the Ghosi Assembly segment forcing police to fire four rounds in the air to disperse them.
A report from Lakhisarai quoting Sub-Divisional Police Officer Manoj Kumar Tiwari said workers of the BJP and JD(U) clashed in a bazaar under Suryagraha assembly segment in the Munger parliamentary seat, but none was injured.
Polling was postponed at four Maoist-hit booths in Dharhara jungle in Munger district.


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To forgive that person who has hurt and betrayed us is a difficult decision to make and even more difficult is to follow through with that decision. Not being able to forgive may result in negative emotional experiences such as anger, frustration, resentment, and depression. How Can I Forgive You? introduces a fresh and original approach to take on this challenge. The book begins with an introduction to the forgiveness concept and presents it as a choice, not a requirement. The readers are then taken through the different types of forgiveness and acceptance. This book is a practical guide and companion for your journey to forgiveness.
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How to Develop Self-Confidence and a Positive Self-Image Permanently and Foreveris an interactive audio program that provides individuals with a way to develop self-confidence by identifying and challenging self-defeating beliefs and attitudes. Dr. Michael Broder explains how negative beliefs and attitudes contribute to low self-confidence and challenges listeners to aim toward total self-acceptance as a way to develop a positive self-image.
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Meaning and name origin
Zinaida \z(i)-nai-da\ as a girl's name is of Russian and Greek origin, and the meaning of Zinaida is "belonging to Zeus".
Zinaida has 4 variant forms: Zena, Zenaida, Zenaide and Zinaide.
Zinaida is not a popular first name for females and an equally uncommon surname or last name for all people (2000 U.S. Census).
Displayed below is a comparison of the popularity of the girl name Zinaida and its variant forms. The only variation form ranked in the Top 1000/100 is Zena. (2015 statistics).
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Zinaida is also pronounced similarly to Zenayda. Like Zinaida, this name is not commonly used.
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Friday, October 24, 2003
© Copyright 2015 Clayton News Daily
By Jeffery ArmstrongFor the second straight week, the Lovejoy Wildcats football team will face another tough challenge to their undefeated season and their hold on first place in Region 4-AAAAA. The 7-0 (4-0) Wildcats, ranked No. 6 in the latest Associated Press high school football poll, will face the poll's No. 10 team, the Newnan Cougars (8-0, 5-0), tonight at 7:30 p.m. at Twelve Oaks Stadium. Last week, the Wildcats dispatched their first major challenger, defeating East Coweta on the road 28-17. As usual, Lovejoy got outstanding performances last week from its offensive line, quarterback Kisan Flakes, running back Aaron Williams and wide receiver Santini Washington. But it was the defense that kept Lovejoy in the game long enough to finally wear East Coweta down. And those guys on defense are ready to face Newnan and its high-octane offense, which is led by senior quarterback Tyler Horne. "Man, these are the type of games I live for," said Wildcats senior defensive end Jeremy Lomax. "Both teams are undefeated and Newnan is a passing team. It's great." The Lovejoy defensive players really look forward to playing a team like Newnan n a team which is so similar to Lovejoy on offense. "Basically, we need a break from the Wing-T," said senior middle linebacker Keith Boykins. "Every team we've faced throws the Wing-T at us." "We've faced the Wing-T so much, I feel that even I can run it," said Lomax. Senior defensive end Richard Carter said the key to stopping a potent offense like Newnan's is to get pressure up front in order to help the secondary. "Newnan has three good receivers and our defensive backs don't need to be put under a lot of pressure," said Carter. "The d-line has to work on their escapes and get to the quarterback, forcing him to throw a tough pass." Against East Coweta last week, Lovejoy spotted them a 14-0 lead in the first quarter before buckling down and holding them to only three more points. The defense, the No. 1 defense in the region, will try not to let Newnan get off to a quick start. "What's funny is that the teams we've faced this year come up with something we have never seen before," said Boykins. "They dust off the old playbook and catch us completely off guard." "Yeah, it's the Lovejoy special," said Carter. "But our coaching staff does a great job of making adjustments to their schemes." Lomax agreed. "Once the coaches talk to us, we figure everything out and that's when we shut people down," Lomax said. Lovejoy head coach Al Hughes said the key to facing a team so similar to themselves is to employ multiple coverages. "We need to mix man coverage and zone coverage," he said. "We may blitz some, but not a whole lot." Hughes said he is proud of his team's play this year, especially on the defensive side. He said the defense gets the most reps in practice and they work extremely hard. "We emphasize winning a championship with a strong defense. It doesn't always look that way, but that's how we feel," Hughes said. "In this era of offensive football, it's hard to shut people down. So far, we're doing well."
More like this story
- Wildcats stay unbeaten ( October 25, 2003 )
- Wildcats picked to finish second in 2004 ( July 13, 2004 )
- Wildcats remain unbeaten ( October 19, 2003 )
- Big challenge for Lovejoy ( October 17, 2003 )
- Wildcats already thinking about next year ( December 1, 2003 )


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In Search of Santa (2004)
Starring: Hilary Duff Haylie Duff
Learn more about In Search of Santa:
Format: DVD
Manufacturer: Echo Bridge
Sku: 222327195
Category Keywords: Children Christmas Family (General)
Rating: NR
See more in Christmas & Holiday
Editor's NoteTwo royal penguins travel to the North Pole to prove the existence of Santa Claus in IN SEARCH OF SANTA. When a sleigh bell falls out of the clear blue sky, a penguin princess named Crystal (the voice of Hilary Duff) thinks it has descended from Santa's sled. She and her little sister Lucinda (Hilary Duff's real life sister, Haylie Duff) embark on a journey to the North Pole. As it turns out, their journey takes puts them onto path of wild animals, pirates, and rebellious penguins who hope to usurp their family's throne.
Cast & Crew
|Hilary Duff
|Haylie Duff


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text: No recent wiki edits to this page. OriginIron Mask was a villain of the American Old West who wore an iron helmet and body armor, making him impervious to bullets. He was a blacksmith and created his own armor. He also was handy with a handgun. He was a criminal mastermind of his time and led gangs including Bennington Brown, Dr. Danger, Fat Man, Hurricane, Living Totem, Rattler and Red Raven. He faced Kid Colt, Phantom Rider, Rawhide Kid, Two-Gun Kid and the time-traveling West Coast Avengers (Hawkeye, Iron Man, Mockingbird, Tigra, Wonder Man)Alternate VersionMarvel ZombieOn Earth 438 Iron Mask was somehow gunned down and was buried in Boot Hill Cemetery. When the zombie virus arrived from Earth 616 Iron Mask rose as an undead zombie. When Swift Cloud gained her father's power she was able to shoot all the zombies in the head except for Iron Mask who was buried wearing his trademark mask. Iron Mask was about to bite Swift Cloud when Machine Man, sent from Earth 616, used his chainsaw to cut threw the mask and destroy Iron Mask's brain, killing him, again.PowersIron Mask has no super human powers but the fact that he was able to make a iron suit in the time period he lived in was truely a feat.


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by James Slater - 26-year-old Alfredo Angulo is an unbeaten and very exciting Mexican warrior who comes to fight each and every time out. Some fans may well have seen/read about his most recent fight, the 10th-round TKO of Andrey Tsurkan. Much was made of the amount of punches Tsurkan was to take from Angulo before the ref finally stopped the one-sided beating. Speaking to me through his wife/translator, Jessica, from his home in Los Angeles, Alfredo began by speaking about the Tsurkan bout. Was it stopped too late, I asked him.
"Everybody has said that about that fight," the 5'10" light-middleweight said." A lot of people got on the ref's case also, but he [Tsurkan] never once stopped throwing punches, so it was hard to stop the fight."
Angulo was very aggressive in the fight, is this how he fights all the time?
"Yes, I am always very aggressive and I throw lots of punches. But I must add, I do so with my ring intelligence. I fight like my nickname of El Perro, which means dog. I am a terrier in the ring. I'd say my best punch is my right hand."
And how exactly did "El Perro" first get into boxing, and how old was he when he did so?
"I was 17 when I first started boxing. It was after I watched the big Chavez-De La Hoya (rematch) fight in 1998 that I knew I wanted to be a fighter. Without any doubt, Julio Cesar Chavez is my number-one boxing hero."
This comes as no surprise, considering Alfredo is a Mexican. He also has a fondness for another Mexican great though, this one now operating at his very peak.
"I look up to Antonio Margarito, we are pretty good friends today. I have sparred with him a lot. He calls me when he needs good work. I've worked with him for all his recent fights except the Paul Williams fight - which is why he lost (laughs). He's never hurt me apart from the first time we sparred, when he cut my lip. He has great experience, which is the most important thing needed to be a great champ. For instance, I picked Hopkins over Pavlik recently. My wife picked Pavlik (laughs). But he never knew how to work, I said he's no better than me. I am getting my experience so I'll be ready for anyone!"
Alfredo, who moved to L.A in 2005, already has quite a lot of experience. Not only has he sparred with the fearsome Margarito, he also worked with Ricky Hatton ahead of Ricky's Vegas fight with Jose Luis Catillo, and he has sparred with Roy Jones, Carlos Baldomir and Fernando Vargas among others. Angulo also represented his country of Mexico at the 1994 Olympics, unfortunately losing his first bout, to Andy Lee. Alfredo still enjoyed his time at the games.
"It was a very big experience for me, of course. Every athlete's dream is to go to the Olympics. It is the best versus the best. I lost to Andy Lee, but I don't think my fighting style, or the style of any Mexican or Colombian, is suited to the amateurs. I think European boxers are much better suited to the amateur game. I'm better off as a pro, with my style."
Since his January 2005 debut, Alfredo has compiled a record of 14-0(11). Angulo has looked excellent and he has been in no way softly matched, either. Who has given him his toughest fight so far?
"The hardest hitter was Richard Gutierrez. But I beat him in 5 rounds. To me, nothing is tough about fighting. It's my work. If you don't like your work, whether you be a mechanic or whatever, then what are you doing it for? I train and every day I train I smile. Then, when the fight is a week away, I like to play jokes on people. I'm very happy being a boxer."
Alfredo may be happy in his work, but his wife, though she forces herself to ringside whenever her husband fights, suffers from the expected nerves one would expect from a wife or a mother of a pro boxer.
"I go to all of Alfredo's fights," Jessica tells me. "But I get very nervous. I have to be there and I know he will win, but I can't help getting anxious. I like boxing, we watch it at home on TV together, but it is different when I have to watch my husband fight."
Alfredo laughs gently as his wife explains her ringside anxieties. Fear and apprehension are simply not emotions this tough Mexican feels himself when doing what he does best. And Alfredo is sure he will be a world champion. He also assures me he is a natural light-middleweight, and it is at 154-pounds where he will become a world champion.
"154-pounds, that's my natural weight now. I am going to be here [at 154] for a long time, too. I have no problems at all making weight. Whoever gives me the opportunity to become a world champion, that's who I will fight. I hope to be given a chance against a world champion by next year. I WILL be the champion if I'm given the opportunity. Actually, I would say I want to win the IBF title more than any other. The reason is, that title will be for a very dear friend, who it will mean a lot to and will be a special present for. My trainer Clemente Medina, he has trained fighters in the past but never has one of his fighters won the IBF belt. I want to win that title for him."
There are plans for Angulo to box, possibly against Scotland's Craig McEwan, on the Hatton-Malignaggi November 22nd card. But Alfredo finished off by telling me that though he likes to fight every two months or so, November 22nd would perhaps be too soon.
"I like to fight often, and I like being active. I'm always in the gym. But November 22nd may be too soon. I just fought on October 4th. But I will see what my promoter and manager says."
Sincere thanks go to both Alfredo and Jessica for affording me their time.
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Why aren't the United States and other western countries more involved in Zimbabwe?Asked by Paidamoyo Chikate, from College of Saint Benedict & Saint John's University
U.S. and Western influence in Zimbabwe is limited compared to the region's powerhouse, South Africa. South Africa is Zimbabwe's largest trading partner, and South Africa's ruling party, the African National Congress, has wide-ranging contacts in Zimbabwean political circles.
See more in Zimbabwe


text:
KENDRIYA VIDYALAYA NO 1 is located at JIPMER CAMPUS PONDICHERRY 605 006. Contact information of the school is 0413 Office 372457 , 372346 Residence 372346 FAX No. School code or examination code is PO7702. Website and email address of the school is
KENDRIYA VIDYALAYA NO 1 Examination code or School code is PO7702


text:
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Knowledge Base
Installing ESX 2.5.3 on Sun Fire x4100 and x4200 Servers (2085)
My installation of ESX Server 2.5.3 on a Sun Fire x4100 or x4200 server fails to identify the storage device. The server has a LSI 1064 controller. How do I install ESX Server 2.5.3?
Solution Availability
This is an interim workaround solution for installing ESX Server 2.5.3 on Sun Fire x4100 and x4200 servers. This driver disk allows local boot support on Sun Fire x4100 and x4200 servers.
Note: This driver will be integrated into the next version of ESX Server. When that version is released, VMware will no longer support this workaround, and you will need to migrate to the newer version of ESX Server.
Hardware Requirements
- Laptop or PC with serial connection to the Sun Fire x4100 or x4200 server's Service Processor (SP) management port (which is an RJ45 adapter, not the typical 9 pin D connector) using a NULL modem cable
- A serial connection configured on the Laptop/PC as 9600 baud with 8N1 and flow control off/none
- Monitor, USB keyboard, and USB mouse connected to rear USB ports of the Sun Fire x4100 or x4200 server
- External USB floppy drive connected to Sun Fire x4100 or x4200 server
Note: VMware does not support the hardware RAID configuration of the LSI 1064 device with the LSI driver disk in ESX Server 2.5.3.
Enabling the USB Floppy Drive for ESX Server 2.5.3 Installation
Disable the service processor from initializing all the USB devices during the boot process:
- Connect the NULL modem cable of the laptop or PC to the SP port on the rear of Sun Fire x4100 or x4200 server marked SER MGT.
- Connect the server to the power supply.
- The SP serial connection should be alive immediately.
- Enter the default username (root) and password (changeme) once a login prompt appears.
- At the SP prompt (->) issue the following
-> reset /SYS
This command reboots the Sun Fire x4100 or x4200 server.
- You should see BIOS messages on the console of the
Note: You may have to wait 1-2 minutes before you see any activity on the monitor. This is normal.
Installing ESX Server 2.5.3 Using the Driver Disk
- Insert the VMware ESX Server 2.5.3 CD into the drive when BIOS startup messages are displayed.
- The machine detects and boots from the CD, which presents a
menu with the following prompt:
boot :
- Enter esx driverdisk at the boot prompt. Do not press Enter.
- Go back to the SP serial terminal window and enter the
following command at the SP prompt:
"load -source tftp://123.456.789.012/nofile"
Note: Enter the above command exactly as it is. Before submitting the command, ping 123.456.789.012 to make sure there is no host in the local network with this address.
- The SP connection presents a confirmation question. Type y and press Enter.
- SP unloads all USB-related drivers and enters "no usb mode." You can safely ignore all other questions and prompts on the SP terminal.
- Do not enter anything on SP connection at this point.
- Go back to the ESX service console. Press the Enter key to start the installation process.
- You may get an error message stating that the mouse could not be configured. Choose no mouse option (none) and proceed.
- Choose text mode for installation when prompted.
- Insert the driver disk into the floppy drive when prompted for the driver disk. Choose Driver Disk on the first dialog box and continue for the second time (indicating you have only one driver disk).
- From this point, follow the procedure for a standard installation of ESX Server 2.5.3.
ESX Server 2.5.3 Post-Installation Procedure
After the ESX Server installation procedure completes, the server reboots and displays a menu with three entries (esx, linux, linux-up):
- Type esx nousb and press Enter.
- After the system boots, a screen displays showing the IP address and name of the system with instructions for accessing the system from a browser.
- Press Alt-F2 and log on as root.
- Edit /etc/lilo.conf with a text editor.
- Search the file to find the entry with label=esx.
Change the following line from:
append="mem=XXX xxx=XX:XX:XX:XX...."
append="nousb mem=XXX xxx=XX:XX:XX:XX...."
- Search lilo.conf to find the entry with
label=linux. Add the following lines just after the line
containing label=linux:
- Search the file to find the entry with label=linux-up.
Add the following lines just after the line containing
- Once the edits above are completed, execute the following
command as root:
/sbin/lilo -v
- Reboot the Sun Fire x4100 or x4200 server:
- Once the server has rebooted, choose ESX from the LILO menu to start ESX Server 2.5.3.
- Go back to the SP connection. Type n and press Enter to reboot SP.
Known Issues
- The kernel parameter "nousb" is expected to limit USB functionality. However, a USB keyboard or mouse connected to the Sun Fire x4100 and x4200 will continue to work.
- RKVM (remote keyboard, video, and mouse) capabilities are limited. Redirecting the CD-ROM, floppy, floppy image, or CD-ROM image will not function, because the VMware console operating system does not automatically mount these devices.
Request a Product Feature
- Updated:
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text:
Groupcal 2.0 offers MS Exchange option for Mac users
updated 03:15 pm EDT, Thu October 21, 2004
Groupcal 2.0 for Exchange
Snerdware has released , which allows you to access and manage your Microsoft Exchange calendar seamlessly from Apple's iCal calendaring software. It can synchronize events and tasks, book people or resources for meetings, respond to meeting requests, view Free/Busy time and more. It now offers 2-way event synchronization, 2-way task synchronization, improved Free/Busy time adjustments, the ability to send/receive meeting invites, sharing of Exchange calendars, manage Exchange calendars with iSync devices and iCal, and other improvements. It requires Mac OS X 10.2. A single-user license is $65, while a 5-user license is $260.


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Coal Power Plants to Feed Algae Biofuel ReactorsMay 11, 2010 6:39 am | Comments
Three of Australia's largest coal-fired power generators have committed to building test facilities adjacent to their power stations, where smoke-stack CO2 emissions are captured and used to grow oil-rich algae in solar bioreactors.
Hitachi Sees Return To ProfitMay 11, 2010 6:29 am | by Manufacturing.net | Comments
Japanese manufacturer narrowed its annual loss from record red ink the previous year and forecast it would return to profit for the first time in five years.
Workers Strike At Boeing?s C-17 PlantMay 11, 2010 6:29 am | by Manufacturing.net | Comments
Boeing workers who assemble the giant C-17 cargo jets in Long Beach are on picket lines in a dispute over pension and medical benefits.
Ex-Auto Czar: U.S. Could Get $40B Back From GMMay 11, 2010 6:29 am | by Manufacturing.net | Comments
Government could get back $40 billion of its $50 billion investment in General Motors, and difference would be well spent because it prevented mass job losses, Steven Rattner said.
Nokia Shakes Up Management To Tackle RivalsMay 11, 2010 6:28 am | by Manufacturing.net | Comments
Cell phone maker is reorganizing its leadership to tackle growing competition from rivals in smart phones and high-end mobile computers.
Underage Slaughterhouse Workers TestifyMay 11, 2010 6:23 am | by MICHAEL J. CRUMB, Associated Press Writer | Comments
Two former underage workers testified against their former manager, who faces 83 child labor violation charges stemming from a May 2008 raid at the plant in which 389 illegal immigrants, including 31 children, were detained.
Oil Spill Blame Game BeginsMay 11, 2010 6:02 am | Comments
Executives from BP, Halliburton and Transocean are trying to shift responsibility to each other.
BP Resumes Subsea Dispersant Spraying, LA ConcernedMay 11, 2010 5:45 am | Comments
The EPA administrator is meeting with LSU scientists to discuss the state's concerns about the potential longterm effects.
Toyota Quarterly Profit Recovers To $1.2BMay 11, 2010 5:26 am | by Manufacturing.net | Comments
World?s top carmaker cruised back to profit in latest quarter as the company cut costs and hitched a ride on the global auto sales recovery while fighting to salvage its reputation.
U.K. Manufacturing Production Up In MarchMay 11, 2010 5:26 am | by Manufacturing.net | Comments
Manufacturing output in March was 3.3 percent higher than a year ago and 2.3 percent better than the previous month, U.K. government statisticians said.
Samsung Unveils $20.6 Billion Investment PlanMay 11, 2010 5:26 am | by Manufacturing.net | Comments
South Korean conglomerate to invest $20.6 billion in technologies including solar cells and medical devices, aiming to boost sales and increase its work force by tens of thousands.
Glaxo Extends Asia Push With Stake In Dong-A PharmaMay 11, 2010 5:26 am | by Manufacturing.net | Comments
GlaxoSmithKline says it has signed a strategic alliance with South Korea's Dong-A Pharmaceuticals, acquiring a 9.9 percent stake for $109.5 million.
Abbott Forms Unit, Signs Licensing Deal With ZydusMay 11, 2010 5:26 am | by Manufacturing.net | Comments
Drug and medical device maker Abbott Laboratories is licensing the products from Zydus Cadila, based in India, and will sell them in 15 emerging markets through a new unit.
NI reveals graphical system design event scheduleMay 11, 2010 5:23 am | by Processingtalk | Comments
National Instruments (NI) has announced plans for NIWeek, a graphical system design conference and exhibition targeted at engineers, scientists and members of the academic community.
Singapore sand demand seen damaging Cambodia environmentMay 11, 2010 3:30 am | by Reuters | Comments
SINGAPORE (Reuters) - Singapore's thirst for sand to increase land reclamation and construction is driving an ecologically damaging sand-dredging industry in Cambodia, according to a report by a non-governmental organization. London-based Global Witness said on Tuesday that Cambodia's...


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Hi all, I'm Jack, 32, Cardiff. Currently overweight (22st), 6ft3 and about to change my life around for the sake of longevity and for my soon-to-be here daughter, Tali. I work fulltime in Cardiff, in an office where I get very little time to excersise. I have had multiple failed attempts with gym memberships (too corporate, too full of themselves and generally clinical places but that's just my opinion) so I have decided this weekend that I want to start running. I have begun the couch25k plan from the NHS and I completed my initial run at 6.30am this morning. It was very hard going but I aim to persevere. I have quit smoking as of 2 weeks ago and I feel a lot better for it. My life change will be hard going but I am confident that I can stick to it. I've began eating a lot heathier (not dieting - just exchanging bad foods for good and in smaller portions). I look forward to making friends with people on here through my journey and I look forward for your support and advice :)
over 3 years ago
Posted over 3 years ago
Good luck!
Hay, to new boys on a mission we do fine, stick at it mate.
Posted over 3 years ago in reply to daveabel
Cheers guys :)
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