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US 5325490 A Abstract A method and apparatus that provides for the replacement of a first microprocessor with a second microprocessor in a microcomputer system. The method and apparatus allow the second microprocessor to utilize a Numeric Processor Extension (NPX) installed in the microcomputer system. This is accomplished by monitoring control signals, detecting unique error conditions, queuing NPX opcodes and operands when overlap conditions exist, transmitting queued NPX opcodes and operands and translating bus cycles between the microprocessor and the microcomputer system motherboard.
Claims(20) 1. An interface device for the replacement of an original microprocessor with a replacement microprocessor in a microcomputer system, said original microprocessor and said replacement microprocessor having different operating characteristics, said original microprocessor coupled to said microcomputer via a socket, said microcomputer system having means for coupling said original microprocessor with a Numerical Processor Extension (NPX), said interface device comprising:
said replacement microprocessor; a bus cycle conversion means coupled to said replacement microprocessor, said bus cycle conversion means for converting a first bus cycle type associated with said replacement microprocessor to a second bus cycle type associated with said microcomputer system; NPX instruction detection means coupled to said replacement microprocessor, said NPX instruction detection means for detecting an NPX instruction provided by said replacement microprocessor; queuing means coupled to said replacement microprocessor, said queuing means for storing NPX instruction and operands provided by said replacement microprocessor prior to transfer to said NPX; address translation means coupled to said replacement microprocessor for converting an address associated with said replacement microprocessor to an address associated with said original microprocessor and said NPX; and coupling means for coupling said interface device with said socket vacated by said original microprocessor. 2. The interface device as recited in claim 1 wherein said original microprocessor is an Intel 80286 or compatible device and said replacement microprocessor is an Intel 80386SX or compatible device.
3. The interface device as recited in claim 2 wherein said coupling means is comprised of electrically conductive pins defined by said interface device.
4. The interface device as recited in claim 3 wherein said instruction detection means is further comprised of an instruction decode means for decoding the instruction and means for determining that the instruction is an overlap instruction.
5. The interface device as recited in claim 4 wherein said microcomputer system is an IBM PC/AT or compatible system.
6. The interface device as recited in claim 4 wherein said microcomputer system is an IBM PS/2 or compatible system.
7. In a microcomputer system said microcomputer system including an original microprocessor coupled with a Numerical Processor Extension (NPX) said original microprocessor coupled to said microcomputer system through a socket on a motherboard, a module for replacing said original microprocessor comprising:
coupling means for coupling said module to said socket vacated by said original microprocessor on said motherboard; a replacement microprocessor, said replacement microprocessor having different operating characteristics than said original microprocessor; a bus cycle conversion means coupled to said replacement microprocessor and said coupling means, said bus cycle conversion means for converting a first bus cycle type cycle associated with said replacement microprocessor to a second bus cycle type cycle associated with said original microprocessor; and NPX interface means coupled to said replacement microprocessor and said coupling means, said NPX interface means for controlling the communication between said replacement microprocessor and said NPX. 8. The module as recited in claim 7 wherein said replacement microprocessor will transfer any one of a predetermined set of instruction to said NPX, prior to said NPX completing execution of a currently executing instruction.
9. The module as recited in claim 8 wherein said NPX interface means is comprised of:
instruction detection means for detecting means for detecting an NPX instruction has been issued by said replacement microprocessor; and instruction queuing means for queuing NPX instructions and operands that have been transferred by said replacement microprocessor. 10. The module as recited in claim 9 wherein said instruction queuing means is comprised of:
a first memory means for storing NPX instructions and operands; a queuing control means coupled to said first memory means; said queuing control means for controlling the writing to said first memory means and the reading from said first memory means; a first transfer enabling means for enabling transfer of information from said replacement microprocessor to said motherboard; a first disabling means for disabling transfer of information from said replacement microprocessor to said motherboard; a second disabling means for preventing the transfer of information sent by said replacement microprocessor from reaching said motherboard; a second transfer enabling means for enabling the transfer of information from said first memory means to said motherboard; and operating exception handling means. 11. The module as recited in claim 10 wherein said original microprocessor is an Intel 80286 or compatible device, said replacement microprocessor is an Intel 80386SX or compatible device and said NPX is an Intel 80286 or compatible device.
12. In a microcomputer system, said microcomputer system comprising a microprocessor, a Numerical Processor Extension (NPX), and a first memory means, said microprocessor being coupled to said NPX and said first memory means, said microprocessor issuing a plurality of NPX instructions, an overlapping subset of said plurality of NPX instructions being NPX instructions that may be issued while a first NPX instruction is being executed by said NPX, a method for sequential delivery to said NPX of overlapping instructions sent by said microprocessor comprising the steps of:
determining that a second NPX instruction has been issued by said microprocessor; determining that said second NPX instruction is in said overlapping subset; determining that said NPX is busy executing said first NPX instruction; blocking transfer of information from said microprocessor to said NPX; writing said blocked transferred information to said first memory means; determining that the NPX is not busy; and transferring said blocked transferred information from said first memory means to said NPX. 13. The method as recited in claim 12 wherein said first memory means is a First In First Out queue.
14. The method as recited in claim 13 wherein said microprocessor is an Intel 80386SX or compatible device and said NPX is an Intel 80287 or compatible device
15. The method as recited in claim 13 wherein said microprocessor is an Intel 80286SX or compatible device and said NPX is an Intel 80287XL or compatible device.
16. A computer system comprising:
a motherboard having a socket, the socket configured to accept an original processor, the original processor operating according to a first set of operating characteristics; a Numerical Processor Extension (NPX) coupled to the motherboard, the NPX being capable of executing only one NPX instruction at a time; a processor module coupled to the motherboard via the socket, the processor module further including: a replacement processor operating according to a second set of operating characteristics different from the first set of operating characteristics; bus cycle conversion circuitry coupled to the replacement processor, the bus cycle conversion circuitry converting a signal of a first bus cycle type associated with said replacement processor to a signal of a second bus cycle type associated with the original processor; and NPX interface circuitry coupled to the replacement processor, the NPX interface circuitry controlling communication between the replacement processor and the NPX, the NPX interface circuitry delivering NPX instructions to the NPX sequentially. 17. The computer system according to claim 16, wherein the replacement processor is capable of issuing a second NPX instruction to the NPX while the NPX is currently executing a first NPX instruction, the second NPX instruction being issued by the replacement processor if the second NPX instruction is one of an overlapping subset of NPX instructions that may be transferred while the NPX is executing another NPX instruction.
18. The computer system according to claim 17, wherein the NPX interface circuitry further comprises:
instruction detection circuitry, the instruction detection circuitry detecting issuance of the second NPX instruction that has been issued by the replacement processor; and instruction queuing circuitry, the instruction queuing circuitry queuing the second NPX instruction. 19. The computer system according to claim 18, wherein the instruction queuing circuitry further includes:
a first memory for storing the second NPX instruction; queue control circuitry coupled to the first memory, the queue control circuitry controlling write and read accesses to the first memory; first enabling means for enabling transfer of information from the replacement processor to the motherboard; first disabling means for disabling transfer of information from the replacement processor to the motherboard; second disabling means for preventing transfer of information sent by the replacement processor from reaching the motherboard; second enabling means for enabling transfer of information from the first memory to the motherboard; and operation exception handling means. 20. The computer system according to claim 19 wherein the original processor as in Intel 80286 or compatible device, the replacement processor is an Intel 80386SC, and the NPX is an Intel 80287 or compatible device.
Description 1. Field of the Invention The present invention relates to the field of microcomputer systems, in particular, this invention relates to the replacement of a microprocessor in a microcomputer system having a processor extension. 2. Description of the Related Art In microcomputer systems, it is often desirable to increase system performance in order to increase the speed in which tasks are completed. A first known technique for increasing the performance of a microcomputer system is by replacing a microprocessor contained in the microcomputer system with a different microprocessor that provides such increased performance. Replacement of microprocessors is desirable because it is a cost effective in that other components in the microcomputer system are typically retained (e.g. the RAM memory, external disks, etc.). A second known technique for increasing the performance of a microcomputer system is through the use of processor extensions. Processor extensions are special purpose processing components, e.g. a math co-processor, that perform a predefined set of operations at processing speeds significantly greater than that of general purpose microprocessors. Processor extensions receive operation codes and operands from a general purpose microprocessor, perform the desired operation and return the results to the general purpose microprocessor. All of this may occur while the general purpose microprocessor is performing some other task. Mathematical operations are a common predefined set of operations implemented on a processor extension, and are referred to as a Numeric Processor Extension (NPX). Such NPX devices include the Intel� 80287 and 80287XL Numeric co-processors available from the Intel Corporation of Santa Clara, Calif. The 80287 and 80287XL are designed for use with the Intel 80286 line of general purpose microprocessors. The 80287 and 80287XL differ in that the 80287XL has a greater number of numeric operations it may perform. Otherwise, a computer system design utilizing either device would be identical. Typically, an NPX is designed to operate closely with a particular microprocessor. Operate closely refers to design aspects of both the microprocessor and the NPX which would facilitate fast communication and coordination between the two components. This would include dedicated I/O ports as well as dedicated handshaking lines on the respective components. In the case of the aforementioned 80287 and 80287XL, the microprocessor that they operate closely with is the Intel 80286. It is common for different microprocessors to have different methods and techniques for coordinating operations and communicating with an NPX. This occurs because a standard interface does not exist between a microprocessor and NPX. This creates additional requirements for replacing a first microprocessor with a second microprocessor. Typically, in such a replacement, the NPX would also have to be replaced. Known microprocessor devices are members of "families" of such devices. A microprocessor family, for example the 80286 "family" of microprocessors, contains function and performance characteristics that are substantially similar. Differences lie in chip packaging and/or operational specifications. Other differences include CPU clock rates or the size of the address path. The 80286 family of microprocessors are described as 16-bit microprocessors because they have 16-bit internal architectures and are designed for microcomputer systems with 16-bit wide data paths. The Intel� 80386 family of microprocessors have 32- bit internal architectures, but individual members may be used with microcomputer systems that have varying sized data paths. A member of the 80386 family that is designed for use in microcomputer systems with 32-bit wide data paths is the 80386DX�. Alternatively, the 80386SX� has a 32-bit internal architecture but is designed to be used with microcomputer systems that have a 16-bit data path. The 80386 family of microprocessors is distinguishable from the 80286 in that the 80386 family has: a greatly increased addressing range; the ability to accommodate operands with a greater number of bits and may perform operations at a greater speed. The Intel 80286 and 80386 family of microprocessors are described in detail in the publication Microprocessors, order No. 230843-007 available from the Intel Corporation of Santa Clara, Calif. Known microcomputer systems that utilize an 80286 or compatible microprocessor and have 16-bit data paths are the IBM PC/AT and PS/2�; models 25-286, 50, 50-Z, 60, and 30-286 (hereinafter qualifying PS/2 systems); all available from the IBM Corporation of Armonk, N.Y., or PC/AT or PS/2 compatible systems. Technical specifications concerning the PC/AT and PS/2 system design are available from the IBM Corporation. In the aforementioned microcomputer systems, the use of the 80287 or 80287XL as a numerics processor extension is optional. The user of the microcomputer system would optionally install the 80287 or 80287XL if the application software that they used required or would benefit from it. In such systems, a chip socket is provided for electrical coupling of the processor extension. Coupling an 80386DXTM� a PC/AT or compatible microcomputer system is known in the art. The Intel Corporation offers a product under the name InBoard�, which provides for the replacement of the 80286 with 80386DX. With the InBoard, an 80386DX is coupled to a Printed Circuit Board (PCB). The PCB contains it's own RAM memory, processor extension socket for an 80387 Numeric Co-processor, and other support circuitry. The InBoard is coupled to the PC/AT microcomputer system through one of a plurality of I/O slots on the PC/AT microcomputer system motherboard. A ribbon cable with an 80286 socket compatible plug, is used to electrically couple the PCB with the 80286 socket. Detailed technical information about the InBoard product is available from the Intel Corporation. The InBoard design does not make use of processor extensions or all of the RAM memory that currently exist on the PC/AT motherboard. As a result, these components are unneeded. This results in increased costs and wasted assets. The increased costs are in requiring the purchase of new RAM memory and an 80387 NPX. The wasted assets are the unneeded RAM memory and processor extension (i.e. on 80287 or 80287XL). Coupling an 80386DX to a PC/AT or compatible microcomputer system using the InBoard design requires much support circuitry because of the inherent architectural differences between the 80386DX and the 80286 families. Such difference include the additional addressing and data lines in the 80386DX. Additionally, since the InBoard design requires an I/O slot on the PC/AT system, it's use is limited to systems with an available I/O slot. The InBoard design is further limited in that it cannot be used-in non-PC/AT compatible systems. Utilizing an 80386DX Microprocessor with an 80287 Numeric co-processor is described in general in the above referenced publication Microprocessors. However, it is important to note that the description in the reference is directed to the 80386DX microprocessor and not the 80386SX microprocessor. An important distinction between an 80386DX and and 80386SX is that the 80386DX microprocessor has the ability to recognize the 80287 as an NPX and thus communicate with 80287 in a compatible manner. Further, the interface described in the publication assumes that the microcomputer system is being designed specifically for the 80386DX, i.e. it is not intended to be a design for an interface module to an existing microcomputer system. The reference fails to contemplate utilizing a 80386SX replacing a 80286 in a Microcomputer system with an 80287 installed. As described above, the 80386SX is designed to operate in microcomputer systems with 16-bit data paths. Thus, in order to gain the benefits of the 80386 family of microprocessors in a currently existing microcomputer system, it would be desirable to replace the 80286 microprocessor in an IBM PC/AT, PS/2 qualifying or compatible microcomputer systems, with an 80386SX. Although the 80286 and the 80386SX can both be utilized on a microcomputer system with 16-bit wide data paths, the two differ in many other respects. These differences include pin configurations, internal cycle times, exception handing, and operation with NPX devices. It is an object of the present invention to provide for replacement of an 80286 with an 80386SX in a PC/AT, PS/2 qualifying or compatible system when an 80287 or 80287XL has been optionally installed. Further, it is an object of this invention to provide such a method that does not require an I/O slot on the PC/AT or compatible system. The objects of the invention are desirable because it would reduce the consumer cost of obtaining functionality and performance increases of the 80386 line of microprocessors as well as extend the useful life of PC/AT or PS/2 and compatible microcomputer systems. A method and apparatus that provides for the replacement of a first microprocessor with a second microprocessor in a microcomputer system, is disclosed. The present invention allows the second microprocessor to utilize a Numeric Processor Extension (NPX) installed in the microcomputer system. The present invention is embodied in an apparatus that plugs into a microprocessor socket located on the motherboard of a microcomputer system. The apparatus is generally comprised of a Printed Circuit Board that contains gate array logic circuitry, a means for coupling the second microprocessor onto the Printed Circuit Board and means for coupling the module into the microprocessor socket. The method of the present invention provides for the handling of operational differences between the first microprocessor and the second microprocessor and includes the steps of detecting an NPX instruction, translating NPX I/O port addresses, converting bus cycles, storing NPX opcodes and operands when overlap conditions exist and transferring the NPX opcodes and operands when the NPX is available. FIG. 1 is a block diagram of a computer system as embodied by the present invention. FIG. 2 is an exploded side view of an interface apparatus coupled to a microcomputer system as utilized by the present invention. FIG. 3 illustrates in detail the interface apparatus of the present invention. FIG. 4 is a block diagram of the processor extension interface as may be utilized by the present invention. FIG. 5 is a state diagram of a FIFO machine as may be utilized by the present invention. FIGS. 6A and 6B are flowchart outlining the process and method of the FIFO state machine as may be utilized by the present invention. A method and apparatus for interfacing a general purpose microprocessor to a processor extension, namely a Numeric Processor Extension (or NPX), is described. Such an interface is necessary, for example, when replacing a microprocessor in a microcomputer system. In the following description, numerous specific details are set forth such as pin configurations and signal connections, etc., in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known functions, e.g. queuing schemes, detecting signal conditions, or translation logic have not been described in detail in order not to unnecessarily obscure the present invention. The microcomputer system of the preferred embodiment is described with reference to FIG. 1. The present invention may be implemented on a microcomputer system that is designed for use with an Intel� 80286 Microprocessor (hereinafter the '286) or compatible microprocessor coupled with an Intel 80287, 80287XL or compatible numeric co-processor (hereinafter the '287 NPX). Such microcomputer systems include IBM PC/AT� personal computer, selected members of the IBM PS/2� computer family, available from the IBM corporation of Armonk, N.Y., or alternatively, any IBM PC/AT or '286 based PS/2 compatible systems. Referring to FIG. 1, a microcomputer system as may be utilized by the preferred embodiment generally comprises a bus or other communication means 101 for communicating information between the components of the microcomputer system, a microprocessor 102 coupled with said bus 101 for processing information, a processor extension 103 e.g. a Numeric Co-processor coupled with said microprocessor 102 through control lines 112 and said system bus 101, a random access memory (RAM) or other dynamic storage device 104 coupled with said bus 101 for storing information and instructions for said microprocessor 102, a read only memory (ROM) or other static storage device 106 coupled with said bus 101 for storing static information and instructions for said microprocessor 102. Further coupled to the bus 101 are a data storage device 107, such as a magnetic disk and disk drive for storing information and instructions, a display device 108, such as a cathode ray tube, liquid crystal display, etc., for displaying information to the computer user, an alphanumeric input device 109 including alphanumeric and other keys for communicating information and command selections to said microprocessor 102, and a cursor control device 110, such as a mouse, track ball, cursor control keys, etc, coupled to said I/O bus 106 for communicating information and command selections to said microprocessor 102 and for controlling cursor movement. Finally, it is useful, although optional in the preferred embodiment, if the system includes a hardcopy device 111, such as a printer, for providing permanent copies of information. The hard copy device 111 is also coupled to the system through bus 101. The Intel 80286 (hereinafter the '286) family of microprocessors are designed to operate in microcomputer systems with 16-bit wide data paths. Generally, the Intel 80386 (hereinafter the '386) family of microprocessors operates in microcomputer systems with 32-bit wide data paths. The exception is the 80386SX (hereinafter the '386SX), which is designed to operate in microcomputer systems with 16-bit wide data paths. The '386SX was designed to provide the benefits of the architecture of the '386 family of microprocessors on microcomputer systems with 16-bit data paths. Specific detailed information about the '286, '287 NPX and the '386SX can be found in the publication Microprocessors, order No. 230483-007 available from the Intel Corporation of Santa Clara, Calif. The preferred embodiment of the present invention is coupled to the microprocessor socket located on a motherboard of the microcomputer system, and is sometimes termed a daughterboard. Motherboard is a term commonly used to refer to a printed circuit board that is the primary system board that includes the microprocessor, processor extension, memory chips, other system support chips and bus structure. As utilized by the preferred embodiment, the present invention enables an Intel '386SX or compatible microprocessor to replace a '286 or compatible and not require replacement of an Intel '287 or compatible NPX. In certain aspects, the present invention and the '386SX will emulate a '286 microprocessor. In other aspects, the present invention and the '287 will appear to the '386SX as an Intel 80387SX NPX. It should be noted that in the preferred embodiment, the terms NPX and processor extension refer to the same device, i.e. the '287 or '287XL. However, it is apparent from the description that a processor extension may be something other than on NPX, e.g. a graphics accelerator or a high speed memory device. The preferred embodiment described herein may be used as '386SX upgrade modules for existing PC/AT or compatible systems. Alternative embodiments would provide for the manufacture of new '386SX based systems utilizing PC/AT compatible motherboards. Thus, the present invention is beneficial to both existing owners of PC/AT or compatible systems and to manufacturers of PC/AT compatible systems. The present invention reduces the cost of upgrading a microcomputer system from '286 to '386 technology and allows for extending the useful life of existing IBM PC/AT and compatible systems. The present invention avoids costs when upgrading a PC/AT or compatible system, since the '287 Numeric Co-processor need not be replaced. FIG. 2 is an exploded side view of the interface module of the preferred embodiment as coupled to a '286 Pin Grid Array (PGA) socket. It should first be noted that it is typical for a microprocessor to be coupled to a motherboard through a pin and socket assembly. In a pin and socket assembly, a microprocessor socket is electrically coupled to the motherboard, often through a soldering process. The microprocessor socket is comprised of a plurality of pin sockets. Electrical traces on the motherboard are coupled to each of the pin sockets. Pins coupled to the microprocessor chip and leading to the electrical circuits in the microprocessor are inserted into corresponding pin sockets of the microprocessor socket, thus creating an electrical coupling with the motherboard. A pin and socket assembly provides for easy replacement of the microprocessor in a microcomputer system. Referring to FIG. 2 a '286 socket 202 is coupled to a motherboard 201. In the preferred embodiment the '286 socket 202 will accommodate a PGA packaged '286 microprocessor. Alternative chip packaging technologies may be utilized, e.g. Plastic Leaded Chip Carrier (PLCC) or Leadless Chip Carrier (LCC) packaging without departing from the spirit and scope of the present invention. An interface module printed circuit board (PCB) 203 coupled with pins 204 is inserted into pin slots 206 defined by the '286 socket 202. It should be noted that if alternative packaging technologies are utilized, the '286 socket would take an alternative form corresponding to that technology. In any event, the pins 204 coupled to the module 203 are aligned in a one to one correspondence with the pin sockets 206 of the '286 socket 202. A pin support 207 is positioned between the pins 204 and the socket 202. The pin support 207 is used to hold the pins 207 in alignment with the socket 202 and is constructed of plastic, although other non-conductive material e.g. fiberglass, may be utilized. The '286 chip in a PGA packaging is square in shape and defines 68 pins (e.g. the pins 204) resulting in the '286 socket having 68 pin sockets (11 of which are illustrated). The pins are arranged in a first row of 9 and a second row of 11 face each side. The total number of 68 pins results because some pins face 2 sides. The pins 204 of the PCB 203 provide signal paths that are identical to the signals represented by the pins of a '286 chip. In other instances, the pins 204 are directly routed from corresponding pins on the '386SX. In some instances, the pins are routed from functional elements embodied by an ASIC Logic Chip (illustrated in FIG. 3). The ASIC Logic Chip win be described in more detail below. Finally, in some instances, the pins 204 are held in a steady first (on) or second (off) state. This occurs when the pin represents a signal not utilized by the 386SX but is utilized by a '286. The devices that are coupled to a top side of PCB 203 are illustrated in FIG. 3. FIG. 3 is a top view of the interface module of the preferred embodiment. In the preferred embodiment, surface mount technology is utilized for the integrated circuit components. Surface mount technology mounting technologies where the integrated circuits are not coupled to the PCB through sockets, but rather they are directly coupled, usually by soldering, to the PCB. This has the advantages of reducing the number of components required on a PCB, reducing the physical height of a printed circuit board (by eliminating the socket) and reducing the potential for errors due to poor electrical connections. In any event, when the microcomputer system is a PC/AT or compatible system, the PCB 203 generally has the shape of two squares that overlap in one corner. This shape is utilized to avoid existing obstructions, e.g. a hard disk assembly, that arise due to the location of the '286 socket on the PC/AT motherboard when installed in the computer system. In the preferred embodiment, the dimensions of a first square 301 are 17/8�17/8 inches and the dimensions of a second square 302 are 15/8�15/8 inches. The overlapping sides of the square 301 are of length 11/4 inches and 11/8 inches. The overlapping sides of the square 302 is for length of 7/8 inches. It would be apparent to one skilled in the art to utilize a PCB of different shapes or dimensions, e.g. to avoid other obstructions, without departing from the spirit and scope of the present invention. On the square 301, a '386SX chip 303, memory chips 304, 305, and 307 and an oscillator 308 are mounted. On the underside of square 301, the pins 204 (illustrated in FIG. 2) are fastened and electrically coupled to components on the PCB 203. On the square 302, a logic chip 306 is mounted. The logic chip 306 is an Application Specific (also known as ASIC) chip. An ASIC chip is a component that is designed and manufactured to perform specific functions. ASIC chip technology is well-known in the art. In the preferred embodiment, a gate array chip is utilized for logic chip 306 and Static Random Access Memories (SRAM's) are used as memory chips 304,305, and 307. It would not depart form the spirit and scope of the present invention to use other logic chips, e.g. PLA's (Programmable Logic Arrays) or Standard Cells. The Logic Chip 306 contains circuit logic which perform many of the translation and decoding functions of the preferred embodiment. In some instances, output from the Logic Chip 306 is to the pins 204. In other instances, output is to the '386SX chip 303. The same is true for inputs to the Logic Chip 306. Generally, the object code that contains NPX instructions that executes on a '286 based system is compatible with a '386 based system, i.e. it will execute without changes on the '386 based system. However, the manner in which a '386SX operates and communicates with an NPX (i.e. the '387SX) is different than the manner in which a '286 operates and communicates with an NPX (i.e. a '287 or '287XL). Thus, despite the fact that the '286 based object code contains NPX instructions that will run unmodified on a microcomputer system designed specifically for the '386SX/'387SX, it may not operate correctly on a microcomputer system where the '386SX has replaced the '286 as the microprocessor or a '286/287 based computer system. The dependency is on which '287 instructions are being used, since the '386SX based system and the '286 based system will handle some NPX instructions differently. The present invention addresses the aforementioned differences and provides for the execution of unmodified '286/'287 object code on a microcomputer system when the '286 is replaced with the '386SX. Existing application software need not be rewritten or re-compiled. This is beneficial in that it allows a user to retain their software investment in '286/'287 software. It should be noted that the '387SX instruction set contains instructions that are not defined on the '287. These instructions are documented in the aforementioned Microprocessors reference. Thus, such instructions would not operate on the '287 despite the interface of the preferred embodiment. The interface module of the preferred embodiment operates asynchronously from the motherboard of the microcomputer system. Thus, the interface module operates at a different CPU clock speed than the PC/AT or PS/2 motherboard. Since a '386SX is able to operate at higher clock speeds, this provides for the microcomputer system to run at increased processing speeds, in relation to when the '286 processor was installed. The interface module of the preferred embodiment provides for the handling of operational differences between the '286 and the '386SX. First, the internal Clocking Cycles between the '386SX and the PC/AT or PS/2 motherboard and the bus cycles of the 386SX and the 286, are different. Second, Processor Extension I/O Port addresses differ between the '386 and the '286. Third, the '386SX assumes that the NPX is operating with is a '387SX. The '387SX NPX allows certain instructions to be received prior to completion of a currently executing instruction. This feature is called instruction overlap. The '287 does not provide for instruction overlap. Finally, during the execution of certain instructions and upon the occurrence of an operation exception, the '386SX may enter a hang state where no instructions can be executed. Each of these operational differences will be discussed with reference to FIG. 4. FIG. 4 is a block diagram of the interface module with respect to the aforementioned operational differences. It is known that microprocessors operate at particular clock cycles (often measured in MegaHertz). Clock cycle refers to the frequency (or speed) at which an oscillator, within a microcomputer system completes a phase change cycle. Clock cycles are used to synchronize operation of the computer system. The underlying microcomputer system and peripheral components are designed in accordance with that clock cycle time. Also associated with a microcomputer system is a bus cycle. A bus cycle refers to the number of clock cycles required to perform a particular task. The '286 and the '386SX operate at different dock and bus cycle times. As shown in FIG. 4, a 40 MHz clock source 416b, is used as input to a CLK input 416a of the '386SX chip 430. Since the interface module of the preferred embodiment operates asyncronously to the PC/AT motherboard, the clock cycles of the interface module and the PC/AT motherboard need not be synchronized. It should be noted that the '386SX will internally convert the 40 MHz clock source to a 20 MHz internal clock cycle. However, the bus cycles between '286 based PC/AT or PS/2 microcomputer system differs from that of a '386SX based microcomputer system. Thus, all signals between the '386SX chip and the PC/AT motherboard must undergo Bus Cycle Conversion. A Bus Cycle Conversion Means (BCCM) converts '386SX bus cycles to appear as '286 cycles on the motherboard. Depending on the model, the PC/AT motherboard is clocked at 6-12 MHz while the '386SX is clocked at 20 MHz. Conversion of bus cycles is accomplished through logic embodied in the logic chip 306. Techniques for converting bus cycles is known to those skilled in the art. Thus, no further discussion of how bus cycles are converted is deemed necessary. The logic chip 306 provides the appropriate signals to the PC/AT motherboard and the '386SX microprocessor during the performance of a microcomputer system task. Such appropriate signals are dependent on the task being performed. In this respect, the '386SX is being made to emulate a '286 from the PC /AT or PS/2 motherboard point of view. The appropriate signals that must be presented to the PC/AT or PS/2 motherboard sockets and the '386SX are documented in the Intel Microprocessors Data Books Volumes 1 and 2 available from the Intel Corporation. The '386SX sends opcodes and operands to the NPX through I/O ports located on the NPX. Since the '386SX assumes it is coupled to a '387SX, when communicating to an NPX, the '386SX automatically generates '387SX I/O bus port addresses. I/O bus port addresses differ between the '287 and the '387SX. Thus, address translation is required to correct for these differences. Table 1 shows the address translation needed for converting the '387SX address to the appropriate '287 address. TABLE 1______________________________________I/O PORT ADDRESS TRANSLATION 80387SX 80287REGISTER I/O CYCLE Address Address______________________________________Command Port write 80000F8 00F8Status Port read 80000F8 00F8Operand Port wr/rd 80000FC 00FAOperand Port on wr/rd 80000FE N/Aodd word 32-bit______________________________________ Referring back to FIG. 4, address lines 409 enter an NPX Address Translation Means 410. As is apparent from Table 1, only the right most significant bits need be translated to create proper addressing. This is accomplished in the logic chip 306. In any event, after the address translation has been performed, the translated address is coupled to the Bus Cycle Conversion Means (BCCM) 411 where the '386SX address cycles are translated into PC/AT or PS/2 Motherboard address cycles and transferred to the PC.AT or PS/2 motherboard via the '286 socket. The '386SX and '387SX have been designed so that certain NPX instructions can begin opcode (i.e. instruction) transfer to the '387SX before the '387SX has completed processing a currently executing instruction. This is referred to as instruction overlap. Instruction overlap allows the '386SX to transfer an NPX opcode, while the NPX continues processing a previously transmitted instruction. This creates improved microcomputer system performance since the task of transferring the instructions need not be deferred to the time the NPX has completed executing the prior instructions. The '287 NPX does not have the capability to support instruction overlap. In the instance an opcode is received by the '287 prior to completion of a currently executing instruction, the microcomputer system will "hang" (i.e. abnormally terminate processing). The NPX instructions which can overlap are FLD instructions with 4 or 8 byte operand sizes. FLD instructions are described in greater detail in the 80286 Programmer's Reference Manual, available from the Intel Corporation. Since the '386SX does not distinguish between a '287 and a '387SX, upon encountering an NPX instruction which may overlap a currently executing NPX instruction, the '386SX will attempt to transfer the opcode to the '287 as though it were a '387SX. To prevent an overlap instruction from reaching the '287 while an instruction is being executed, a First In First Out (FIFO) queuing mechanism is utilized. FIFO queuing is a control mechanism by which elements (in this case instructions and operands) that are first placed in an array are the first ones taken out. FIFO queueing is well known in the art. FIG. 5 illustrates a state diagram of a FIFO state machine of the preferred embodiment that is used to control the queuing of overlap instructions. Such a FIFO state machine as utilized in the the preferred embodiment, is illustrated in FIG. 4 as FIFO STATE MACHINE 419. When the '386SX is executing non-overlap NPX instructions or no NPX instructions are being executed, the FIFO machine is in an idle state 501. Upon detection of an overlap NPX instruction while the '287 is currently executing an NPX instruction, a FIFO state 502, is entered. Note that both of these conditions must be met. If either one of the conditions is not met, the FIFO state 502 will not be entered. In any event, while in the FIFO state, a FIFO array is loaded with the overlap NPX opcode and the instruction operands over '386SX data lines D0-D15. When the final NPX operand has been loaded into the FIFO and the '287 has completed processing the prior instruction, the FIFO machine will enter a transfer state 503, where the contents of the FIFO are transferred to the AT motherboard for delivery to the '287. While in the transfer state 503, the READY signal to the '386SX is blocked, which effectively suspends operation of the '386SX. Upon completion of the transfer of the FIFO contents, the FIFO machine returns to the idle state 501 and the READY signal is allowed to pass to the '386SX in order to resume operation. The FIFO state machine also provides for '386SX operation in a paged mode. Paged mode operation refers to the ability to address and manipulate data that is not contained within the RAM memory on the microcomputer system, but can be dynamically swapped into RAM memory by operating system software. Operating systems using paging are well-known in the art. In any event, an invalid condition may arise due to the '386SX handling of page faults. A page fault occurs when the '386SX requires data that is not found in the microcomputer system's RAM memory. In these instances, the data must be retrieved from an external memory source, e.g. a hard disk. When a page fault occurs on a page where an NPX opcode or operand is being read from, the '386SX will re-write the NPX opcode to the NPX. In these situations, the FIFO State Machine will detect the page fault restart by detecting an NPX opcode I/O write while the FIFO state machine is in the FIFO state 502. In order to avoid corrupting the contents of the FIFO, the controls of the FIFO will be reset, essentially flushing the FIFO, and the FIFO state machine will return to the idle state 501. At this point, the FIFO state machine may again enter the FIFO state 502 based on the re-written instruction. Referring back to FIG. 4, FIFO state machine 419 enters a FIFO state when an NPX overlap instruction is detected by an NPX instruction decode means 418. The NPX instruction decode means of the preferred embodiment is provided by logic imbedded in logic chip 306. Such logic recognizes predetermined bit patterns as NPX instructions. The NPX instruction decode means 418 receives as input data lines 412, control lines 415 and address lines 409. The data lines 412 contain opcodes and operands. The control lines provide synchronization signals and status information. Also illustrated in FIG. 4 are '386SX and NPX "handshaking" signals 413 and 417. The "handshaking" signals are dedicated lines of communication between the '386SX and the NPX. The "handshaking" signals utilized in the preferred embodiment include the PEREQ line 413 and the BUSY line 417. The PEREQ line 413 is used by the NPX to tell the '386SX that it is ready for another operand. The BUSY line 417 is used by the NPX to tell the '386SX that it is executing an NPX instruction, and cannot receive another instruction until the previous instruction is completed. In normal usage the NPX opcode is transferred from the '386SX to the NPX by an I/O write to address OFA (hex) when the BUSY line is inactive (i.e. in a high state). If there are any operands associated with the opcode, the 386SX will transfer these one at a time by I/O cycles (at address OFC hex) to or from the NPX when the PEREQ signal is active (in the high state). The '386SX will then provide the operands to the NPX via the data lines 412. In providing the operands to the NPX, the microprocessor may be required to perform other tasks to obtain the data, e.g. reads from registers, memory or auxiliary storage means. When the NPX has received the operands, it will begin execution and place the Busy line 417 in the active (Busy) state. A third "handshake" signal provided by the '386SX is the ERROR line. The ERROR line is used to signal an unmasked error encountered by the NPX. The ERROR line is not utilized in PC/AT or PS/2 designs so it is pulled inactive up to logic 1 (i.e. 5 Volts) by a pull up resistor at the '386SX. It should also be noted that the '286 socket defines a slot for a PEACK signal. However, the '386SX to '387SX interface does not utilize a PEACK signal, so this line at the '286 socket is also pulled up to logic 1 by a resistor on the module. As described above, 4 or 8 byte FLD instructions may overlap a currently executing instruction. Thus, these instructions when in an overlap condition, do not follow the general handshaking rules as described above, i.e. the Busy line 417 is not needed for transfer of the next opcode. FIFO control means 420 is used to control the FIFO Array 422 and thus, enable the processing of overlap instructions. The FIFO control means generates write WR 423 (enabling data to be written to the FIFO Array 422 from the data lines 412), read RD 424 (allowing the contents of the FIFO Array 422 to be transferred to the AT motherboard through a line 428) and reset RS 425 (resetting counters and FIFO array pointers to zero) signals to the FIFO array 422. In the preferred embodiment, the FIFO array must be capable of storing at least five 16-bit data words. The size corresponds to the fact that overlap instructions always contain 2 or 4 word operands. Further control mechanisms in the FIFO Array 422 are called terminal counts, here Count In 426a and Count Out 427a. The terminal counts 426a and 427a maintain counts of the number of words written into and read from the FIFO Array 422. The contents of the terminal counts 426a and 427a are provided as input to FIFO state machine 419 through lines 426b, and 427b, respectively. Data read out of the FIFO array 422 is on line 428. The data transferred on line 428 is to the PC/AT or PS/2 Motherboard database. In the preferred embodiment the line 428 is a 16 bit wide bus. The Operand count means 421 receives the operation code for the overlap NPX instruction and determines the number of operands associated with the particular instruction, This is then used by the Count in 426a to know how may words to transfer out. In the preferred embodiment, the Operand count means is used to determine the number of operands by examining the data bits comprising the overlap operation code through logic contained within logic chip 306. Alternative schemes, e.g. table look-ups could be utilized without departing from the spirit and scope of the present invention. In the preferred embodiment the NPX instruction decode means 418, the FIFO state machine 419, the FIFO control 420, the operand count machine 421, the FIFO Array 422, the count-in 426a and the count-out 427a are embodied within the logic chip 306. Use of other logic chips would not depart from the spirt and scope of the present invention. As described above, the ready line 405, is used to signal completion of '386SX bus cycles. When the Ready line 405 is in an active (Ready) state, the '386SX may execute the next bus cycle. When the ready line 405 is in an inactive (Non-ready) state, the '386SX continues with its current bus cycle. In the preferred embodiment, the ready line 405, is put in an active state by either a signal from the FIFO state machine 429 or by an AT READY 408a allowing a signal 408 originating from the PC/AT motherboard to reach the '386SX. The NPX Ready 429 drives the READY line 405 into the active state when the FIFO state machine 419 is in a FIFO state, except when the last operand is being transferred to the FIFO at which time the READY line 405 is kept in an inactive state. Then when the FIFO state machine 419 moves into the transfer state, the PC/AT Ready Block 407 blocks the PC/AT motherboard from generating a Ready signal 408 to the '386SX until all NPX operands from the FIFO Array 412 are transferred to the PC/AT motherboard, at which time the PC/AT motherboard READY may drive READY line 405, to the active state. Viewed in conjunction with the states of the present invention, referring to FIG. 5 when the FIFO machine is in the FIFO state 502 logic will provide READY 406 to the 386SX for the NPX opcode and each NPX operand stored in the FIFO except the last operand. When the FIFO machine then moves into the TRANSFER state 503, AT Ready block 407 will prevent AT motherboard READY 408 from reaching the '386SX. This prevents the '386SX from executing further instructions or responding to Interrupts or Hold requests until the opcode and operands are all transferred to the AT motherboard. This also keeps the 386SX address bus at the operand address 80000FX (hex). When the FIFO state machine moves from the TRANSFER state 503 back to the IDLE state 501 the FIFO STATE MACHINE 419 will remove AT Ready block 407 and the AT motherboard READY will generate the '386SX READY signal 429 so the '386SX can then continue normal operation. The address translation as described above denotes which I/O port on the NPX that the instruction or operands must be sent. The address translation during a FIFO transfer occurs as follows. As the transfer state is entered and 386SX READY is blocked, the operand address (800000FA) is maintained by the 386SX. This in turn is translated to the address 80000FC. But since the first element out of the FIFO is the NPX opcode, the address translation converts the operand port address 80000FC into the command port address 80000F8 (which is simply a matter of converting the second least significant bit from a 1 to a 0 value). Subsequent FIFO elements are NPX operands so the normal '387 to '287 operand address conversion is restored changing the 80000FA still at the '386SX to 80000FC on the PC /AT address bus (this is simply a matter of converting the three least significant bits to the binary value 010). The processing of NPX instructions in an overlap condition is illustrated in FIGS. 6A and 6B. Assuming that the FIFO state machine is in the idle state, it must first be determined whether an NPX instruction has been issued, step 601. NPX instructions are detected by decoding the '386SX address and control lines. It is then determined if the NPX instruction is an FLD 4 or 8 byte instruction, step 602. If not, it is then immediately translated to a '287 address, step 603. The '386 and '286 cycle conversion occurs, step 604 and the instruction is written to the AT motherboard, step 604. Assuming that the NPX instruction is a 4 or 8 byte FLD, an instruction FIFOing process is invoked. At this point, the FIFO state machine enters the FIFO state. First, the instruction FIFO and accompanying control logic are reset and initialized to a predetermined start state, step 607. This is accomplished by the invocation of a FIFO Reset signal that is coupled to FIFO control counters. The NPX instruction is then decoded by the operand count machine 421 where the number of operands for the instructions is determined. The number of operands is loaded into a maxcount operand counter, step 608. Next, the NPX opcode ('386SX data D0-D15) will be loaded into the FIFO array, step 609 and the count-in 426 of the FIFO array 422 is incremented by 1, step 610. The instruction is written into the FIFO Array 412 by a FIFO write signal 423 being activated whereby the contents of the data lines 412 are written into the FIFO Array 422 and blocked from the AT motherboard. After the opcode has been loaded into the FIFO, a fake PEREQ signal is sent from activate PEREQ means 414 to the '386SX in order for the operands of the opcodes to be transferred onto the data lines, step 611. When each subsequent operand write occurs, the write enable signal is activated and the operand is written into the FIFO, step 612. The count-in is then incremented by 1, step 613, to reflect an operand being inserted into the FIFO. The operand count is then compared to the maxcount operand counter, step 614. If the operand count does not equal the maxcount the PEREQ is still activated by activate PEREQ means 414 and more operands are FIFOed to the FIFO array 422. When the FIFO state machine 419 moves to the transfer state, then 1) the operand count does equal the maxcount operand and 2) PC/AT Ready is blocked, step 616a. READY to the 386SX is blocked during the transfer state in order to prevent bus operations by the processor that could create undesired results. The PC/AT Ready Block 407 blocks the PC/AT Ready signal by gate logic contained within logic chip 306. Next, the address on the address lines is set to 0000F8 step 616b. The NPX opcode is then written immediately to the PC/AT motherboard, step 617. The NPX element that will be sent first is the opcode of the instruction to be executed. Further, the count-out of FIFO Array 422 is incremented by 1, step 618. Next, the NPX operands will be transferred to the PC/AT motherboard for transfer to the NPX. First, the PC/AT I/O port address is changed to 0000FA, step 619. The transfer of operands will only occur when the PEREQ signal from the motherboard is active. Thus, a wait state is entered until PEREQ signal is received from the '287, step 620. When PEREQ is active, a Read signal 424 is generated by the FIFO control 420 to the FIFO Array 422 and an operand is written to the PC/AT motherboard, step 621. Further the count-out 427 is incremented by 1 step 622. Next, the count-out 427 is compared to the count-in 426, step 623. If the count-out 427 is less than the count-in 426 then the process is repeated at step 620, i.e. wait for PEREQ to generate a ready signal. If the count-out 427 is greater than or equal to the count-in 426, then reads from the FIFO Array 422 are completed and the PC/AT motherboard Ready signal can be let through to the the '386SX, step 624, thus completing the NPX overlap instruction processing. As noted above, during the processing of an overlap instruction, the '386SX may suffer a page fault when in a paged mode operation. Page faults are detected in the preferred embodiment by the detection of a new NPX opcode write while the FIFO state machine is in the FIFO state. The detection of a new NPX opcode write is detected by the NPX instruction decode means 418. The preferred embodiment detects page faults and then processes them by resetting the FIFO state machine controls and putting the FIFO machine in the idle state. This is accomplished by logic embodied by logic chip 306. Effectively, this will require a re-execution of the NPX instruction that was executing when the page fault occurred. When the NPX instruction is re-executed, the FIFO state machine may be again invoked if the '287 is still processing the prior instruction. If the '287 has completed processing the prior instruction, then no the FIFOing process need not be invoked. In the event of an error during the execution of an instruction, the '287 activates the ERROR signal for exception reporting. However, some system implementations, e.g. ones utilizing IBM PC/AT and compatible motherboard circuitry, do not utilize this ERROR signal. Because of this, it is known that NPX FSTR instructions that generate an exception in the middle of NPX operand transfers can cause the '386SX to enter a "hang" condition. A "hang" condition refers to a state where the processor is unable to continue processing without some manual intervention, e.g. a restarting of the '386SX processor. The hang condition is created because the '386SX expects activation of the PEREQ line when the exception occurs. A '387SX NPX would thus, activate the PEREQ line. The '287 does not activate the PEREQ line in these situations because the '286 does not need to complete transfer of the operands in order to service the exception, but the '386SX does. Referring back to FIG. 4, the PEREQ signal is interfaced with an activate PEREQ Means 414. The activate PEREQ Means 414 detects a '386SX hang condition resulting in an operation exception occurring while the '386SX is transferring operands to the FIFO Array 422. A hang condition is detected by determining a lack of processor activity over a predetermined period of time. In the preferred embodiment, a recurring signal, in this case a HOLD signal generated from a device such as a Direct Memory Access (DMA) device, is used as a counting source. Processor activity is detected by monitoring data bus activity. Thus, a hang condition is detected if no data bus activity is detected over a predetermined number of HOLD signals. In the preferred embodiment, the predetermined number of HOLD signals approximates one millisecond. When a hang condition is detected the Activate PEREQ Means 414 activates the PEREQ signal 414. The activation of PEREQ signal 413 allows the 386SX to continue transferring operands and then to service the operation exception. Thus, a method and apparatus that provides for the replacement of a microprocessor in a microcomputer system is disclosed. Patent Citations
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Reviewed By Leonard D (Fall River, MA) Reviewed for a 2008 Jeep Liberty —10/31/2014 6:51 AM
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Tom Robertson Feature Archive
Rural septic systems imperiled by mild winter
The Minnesota Pollution Control Agency is warning rural homeowners to protect their septic systems to prevent freeze-ups.
Brown winter puts squeeze on winter tourism
The lack of snow is hurting Minnesota businesses that cater to winter recreation, especially in the snowmobile and ski sectors, meaning a potential loss in millions of dollars in revenue in communities across the state.
Lack of snow is affecting tourism
Reporter Tom Robertson talks to Cathy Wurzer about what's going in northern Minnesota. Tourism is down this winter because of the lack of snow around the state, but the lakes are making cool sounds as they freeze.
Minnesota scrutinizes 40-year-old 'Miracle'
A 40-year-old idea that shifted the way Minnesota pays for many local government services -- the "Minnesota Miracle" -- is getting new scrutiny as budgets tighten.
Under pressure, Ely scales back proposed property tax hike
Ely city leaders have responded to pressure by presenting a revised budget that trims a proposed levy increase down to 14 percent from 27 percent.
Struggling Ely taxpayers confront city leaders
When Ely set its preliminary budget back in September, town leaders decided to raise the tax levy by 26 percent. As part of our Forced to Choose series, we report on the town's Truth in Taxation hearing Tuesday night, where the mayor and others felt the blowback for their plans.
Fallout from Delta's decision to cut services in rural areas
On Wednesday, we check in with one of our reporters who is based outside the Twin Cities. MPR's Cathy Wurzer spoke with Minnesota Public Radio news' Tom Robertson who covers northern Minnesota from our Bemidji bureau.
Tax notices generate relief, anger
In Minnesota, every year there are lots of reasons property taxes can go up or down. This year there are even more, as homeowners and business people are learning when they open their proposed property tax statements.
Small towns 'just one disaster away'
Tough economic times are forcing cities of all stripes to re-examine how they spend tax dollars. But in small towns like Floodwood, many worry their actual existence is endangered.
Duluth voters reject school referendum, approve parks fund
Duluth voters rejected three different school referendum options on Tuesday that would have raised property taxes to provide more money for schools.
Duluth ballot asks for higher taxes to restore services
Many Minnesota cities have whittled away at their library and park budgets the past few years, and Duluth is no exception. The city is, however, taking the step of asking residents to vote on whether they want to raise their taxes to restore some services.
For Grand Rapids, cash crunch spurs innovative ways to save
State aid cuts have compelled Grand Rapids to trim more than $1 million from its budget, but it's also dropped the local property tax rate by 18 percent and avoided big layoffs and major cuts in services.
Border crossing building picks up support
On Wednesdays, Morning Edition checks in with an MPR reporter who is based outside the Twin Cities. Today, Tom Robertson, who covers northern Minnesota out of our Bemidji bureau, talked about a story he's tracking. It's happening in International Falls where local officials are throwing support behind a proposed new border crossing facility on the Rainy River.
Tax hike saddles business, property owners
Business owners are just beginning to learn how changes lawmakers and the governor made last summer are going to affect them. Many property owners are just learning of the tax hike enacted last summer.
Rare WWII fighter plane under restoration in Bemidji
The new owner of the Sierra Sue II, a World War II fighter plane that's been featured in midwestern air shows for years, wants it to look the way it did when it rolled out of the factory nearly 70 years ago.
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Amsterdam09 highlights (12 images)
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Yup, it's Amsterdam
Holocaust memorial
Centraal Station
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In Amsterdam harbor
Illuminated history of the Netherlands
Binnenhof (?), The Hague
All images © Sharon Goldwater.
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It's all about energy, from renewable sources to energy-efficient usage.
By Megan Phelps
Tags: wind, electricity
Which countries have installed the most wind power? It used to be Germany, followed by Spain. But the United States is now in the lead, according to estimates from the American Wind Energy Association. You can read more about it here in the Financial Times, or here, on Live Science.
Looking for more statistics on wind energy around the world? A good source for this kind of information is the Global Wind Energy Council. Here's their 2007 Global Wind Report (pdf).
Is it possible that the sheer extra number of calories produced by our food system could be partly r...
Vertical axis wind turbines don't always produce as much power as expected. Here's what we were able...
Make your home more energy efficient with Indow Windows Shade Grade.
When shopping for new windows, take advantage of these helpful resources.
Dot Earth
Earth Policy Institute
DOE's Renewable Energy Page
Inhabitat Energy
Into the Wind
Low-Tech Magazine
Renewable Energy World
Rocky Mountain Institute
The Sietch
Solar Power Rocks
MOTHER EARTH NEWS is the guide to living — as one reader stated — "with little money and abundant happiness." Every issue is an invaluable guide to leading a more sustainable life, covering ideas from fighting rising energy costs and protecting the environment to avoiding unnecessary spending on processed food. You'll find tips for slashing heating bills; growing fresh, natural produce at home; and more. MOTHER EARTH NEWS helps you cut costs without sacrificing modern luxuries.
At MOTHER EARTH NEWS, we are dedicated to conserving our planet's natural resources while helping you conserve your financial resources. That's why we want you to save money and trees by subscribing through our earth-friendly automatic renewal savings plan. By paying with a credit card, you save an additional $5 and get 6 issues of MOTHER EARTH NEWS for only $12.00 (USA only).
You may also use the Bill Me option and pay $17.00 for 6 issues.


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The Xbox 360 version of Burnout Revenge has finally emerged. In their efforts to gain 360 market share and show greater HD graphic prowess, Electronic Arts and Criterion have taken the current gen version of Revenge and remodeled, re-formed, and re-energized it for Microsoft's hot little system. The playable version we handled showed off a remarkably slick and fast racing game, plus that same instant and addictive quality that made the series so damn popular.
The differences between the Xbox 360 version and the current gen systems are both big and small. First, this is a reworked version of Burnout Revenge, not an entirely new version. It's not the sequel to Burnout Revenge, it's reworked, HD-ified port. The game you played on Xbox and PS2 last fall will of course look and sound better on Xbox 360, and you'll get to grips with 10 new cars and 10 new crash junctions. The main difference is the online functionality, and the game, just like Battlefield 2: Modern Combat, is slated to ship March 14.
Visually, you'll see a lot of great new imagery. The non-licensed cars are built from scratch. They feature new shader technology, more polygons, textures, and more dynamic crashes and particles. The cars start off smooth and shiny, but continuously take on scrapes and scratches as you thrash and burn through a course. The first screenshots demonstrated this very well, and in action it's just like you expected: Gorgeous, fast, and frenetic. The game blazes away at 60 FPS and though we witnessed some frame drops, we expect these to get hammered out in the final version.
Scrape it!
Otherwise, the game is relatively the same, just far prettier. It will feature all the same offline and online modes as Burnout Revenge on the current generation systems. Additionally, Criterion considered toying with Traffic Attack, but the mode was a less-than-an-enjoyable online experience so the team pulled it. As many as six players can play online simultaneously, just like the other iterations.
Count on IGN having a bundle of new media, details and more on Burnout Revenge soon.


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South Cinema
Tigmanshu Dhulia's decoit drama 'Sultana Daku' will be like 'Indiana Jones'
December 27, 2014
New Delhi: Filmmaker Tigmanshu Dhulia is attempting another dacoit drama 'Sultana Daku' after the success of 'Paan Singh Tomar' and he says it would be on the lines of 'Indiana Jones'. Tigmanshu, 47, said the film is for kids and it will be India's answer to American popular entertainment franchise based...
Bullett Raja: 15 'Tamanche pe disco' dialogues
November 29, 2013
New Delhi: Tigmanshu Dhulia gained a lot of prominence in the Hindi film industry with his critically and commercially acclaimed films such as 'Saheb Biwi Aur Gangster' and 'Paan Singh Tomar'. The filmmaker is known to have a good grip on UP's crime underbelly. From his first film 'Haasil' to...
BiharUP: Why doesn't Bollywood look beyond crime stories?
November 27, 2013
New Delhi: UP and Bihar became the beneficiaries of paradigm shift in Bollywood during the 2000s. These apparently less sophisticated states were taken to the prominence by the filmmakers who hailed from the other side of North India. First, Delhi became the new Mumbai and then the story travelled towards...
Tigmanshu Dhulia feels a strong connect with Chambal
November 9, 2013
Mumbai: Filmmaker Tigmanshu Dhulia captured various aspects of the Chambal ravines for 'Paan Singh Tomar' and now for 'Bullett Raja'. He says he feels love for the location because of which he tries to fit it in every film. "I feel a strong connect with Chambal," Dhulia said in a statement. "Bahut...
Kannada film 'Bharath Stores' to be screened at IFFI 2013
October 16, 2013
New Delhi: While films like 'Ship Of Theseus', 'OMG Oh My God!', 'Paan Singh Tomar' and 'Bhaag Milkha Bhaag' are among the 26 feature films which will be shown in the Panorama section of IFFI, a Kannada film has also be chosen. IFFI (International Film Festival of India), which...
Biopics 'Bhaag Milkha Bhaag', 'Paan Singh' in IFFI Panorama
October 15, 2013
New Delhi: Bollywood biopics 'Bhaag Milkha Bhaag' and 'Paan Singh Tomar' are among the 26 feature films and 16 nonfeature films selected for IFFI's Indian Panorama section. Tigmanshu Dhulia's nationalawardwinning film, starring Irrfan, made it to the list by the virtue of a direct entry while a jury, headed by...
Idol Chat: Tigmanshu Dhulia talks about 'Butch Cassidy and the Sundance Kid'
October 3, 2013
In an interview to CNNIBN's Entertainment Editor Rajeev Masand, filmmaker Tigmanshu Dhulia said that 'Butch Cassidy and the Sundance Kid' changed his life. ...
Ship Of Theseus: Can it be India's Oscar entry this year?
July 23, 2013
New Delhi: The rave reviews that 'Ship Of Theseus' is getting, are not wrong or misdirected, neither they have originated from wrong interpretation of the subject. The critics are expected to be a lot who have at least basic exposure to the world cinema, but even the film doesn't contain...
Actor should be vulnerable before the camera: Irrfan
July 7, 2013
Mumbai: While his acting skills have brought him appreciation from all quarters and also a national award, Irrfan Khan feels an actor should never be too sure of his work as it helps him better his craft. "Being an actor is also about being unsure of things that bring freshness...
Don't want to be highest paid actor, says Irrfan
June 29, 2013
Mumbai: Irrfan loves his craft and aims to nurture his relationship with his fans by giving them "memorable films". As far as money is concerned, the Padma Shri winner's motto is to earn enough to enjoy life and not to be the highest paid actor. "I don't look at my...
Wish I had more turning points like 'Paan Singh Tomar': Irrfan
June 24, 2013
Mumbai: Acclaimed actor Irrfan, who won a National Award for his performance in 'Paan Singh Tomar', says he hopes many more such "unique" projects come his way. "There have been few turning points (in my life) and 'Paan Singh Tomar' was one of them. It was made in a unique way,...
Anurag Basu's 'Barfi!' wins top honours at TOIFA
April 7, 2013
Vancouver: The story of a deaf and mute boy, 'Barfi!' turned out to be the top winner at the maiden edition of the Times of India Film Awards (TOIFA) cornering the best film, best director, best actor and best actress trophies. At a glittering awards function Saturday, Anurag Basu picked up...
I should have won the National Award for 'Haasil': Irrfan
March 29, 2013
Mumbai: Irrfan is elated by the National Award for best actor for his performance in 'Paan Singh Tomar' (PST), but says the prestigious award has come his way after several disappointments. Directed by Tigmanshu Dhulia, the film saw Irrfan playing Paan Singh Tomar, a former national steeplechase championturnedbandit. "I thought I should...
60th National Film Awards: The winners
March 19, 2013
The 60th National Film Awards were announced in the capital on Monday. ...
Winning National Award feels fantastic: Irrfan Khan
March 19, 2013
Actor Irrfan Khan received the Best Actor honour for 'Paan Singh Tomar' at the 60th National Film Awards. ...
Have the National Film Awards lost their sheen?
March 18, 2013
An interesting mix of films were chosen as winners for the 60th National Film Awards. Talented actor Irrfan Khan won the Best Actor award for his role in Tigmanshu Dhulia's 'Paan Singh Tomar'. The award was shared with veteran actor Vikram Gokhale who won it for his role in Marathi...
National Film Awards: Victory for Bollywood's new wave filmmakers
March 18, 2013
New Delhi: Tigmanshu Dhulia's 'Paan Singh Tomar', that narrates the gritty story of a national athlete forced to live the life of an out-law, was announced the best picture at the 60th National Film awards as its lead protagonist Irrfan Khan shared the best actor trophy with Vikram Gokhale for...
'Barfi' was unfairly overlooked at the National Awards: Rajeev Masand
March 18, 2013
CNN-IBN's Entertainment Editor Rajeev Masand joined IBNLive readers for an interaction on the National Film Awards. Q. Have the National Film Awards lost their relevance? Asked by: Ayush A. On the contrary, I think this year they've proved they're just as relevant and on-the-ball...
60th National Film Awards: The winners playlist
March 18, 2013
An interesting mix of films were chosen as winners for the 60th National Film Awards. Talented actor Irrfan Khan won the Best Actor award for his role in Tigmanshu Dhulia's 'Paan Singh Tomar'. The award was shared with veteran actor Vikram Gokhale who won it for his role in Marathi...
I would like to do all kinds of films but I am here to redefine things for myself: Irrfan Khan
March 8, 2013
Actor Irrfan Khan joined IBNLive readers for an interaction on his new movie 'Saheb Biwi aur Gangster Returns'. Q. Do you ever see yourself playing an angry young man,a dreaded cop in khakhi or say a strong negative character? I would like you to take on our commercial "hero" brigade with...
Irrfan Khan, Tigmanshu Dhulia get candid about 'Sahib, Biwi aur Gangster Returns'
March 2, 2013
Tigmanshu Dhulia, director of the well received 'Sahib Biwi Aur Gangster' had a 'germ' of an idea of its sequel even before the release of the first installment, says the producer. ...
B'wood award shows have reduced to TV shows: John Abraham
February 28, 2013
Mumbai: Actor-turned-producer John Abraham, who has been in the industry for a decade now, says Bollywood award shows have been reduced to prime-time television shows and believes they can never reach the level of a fair award. "All our award shows are television shows. Actors have to dance on those shows...
Michelle Obama looked great at the Oscars but she should not have been there: Anna MM Vetticad
February 25, 2013
Film critic and author Anna MM Vetticad joined IBNLive readers for an interaction on the Oscar Awards 2013. Q. Are you satisfied with this Oscar Awards 2013? If no then what are your reasons for the same? Asked by: Anant Jain A. No. Not satisfied. Though it's...
Mahie Gill: I am not an intelligent actress
February 14, 2013
Mumbai: After winning critical acclaim for her roles in 'Dev D', 'Saheb Biwi Aur Gangster', 'Paan Singh Tomar', actress Mahie Gill says she is confused about her standing in Bollywood as new roles are not coming her way. "I don't know if I have cemented my position in the industry....
Still too few Vicky Donors and Kahaanis: Tigmanshu Dhulia
February 7, 2013
Mumbai: It is a good time for Indian cinema with films like 'Vicky Donor' and 'Kahaani' striking a chord but such successes are still few and not enough to transform the economics of filmmaking, says writerdirector Tigmanshu Dhulia. And change is still some way away. "It's a good time, but how...
Irrfan has great sex appeal: Tigmanshu Dhulia
February 5, 2013
New Delhi: Filmmaker Tigmanshu Dhulia, who has roped in Irrfan for 'Saheb Biwi Aur Gangster Returns', feels the actor has a distinct sex appeal. "Irrfan's got a great sex appeal and he triggers the sensitive side of women in an intellectual way. He's not for frivolous women, but for those...
Director Tigmanshu Dhulia to act in Ketan Mehta's next
February 4, 2013
Mumbai: After his highlyacclaimed acting debut in Anurag Kashyap's 'Gangs Of Wasseypur', filmmaker Tigmanshu Dhulia, currently swamped with two backtoback directorial undertakings, has been persuaded to face the camera again. He will act in Ketan Mehta's 'Mountain Man', a biopic on the unsung Bihari hero Dashrath Manjhi, who dug a...
Irrfan Khan: Acting is an insecure business
December 14, 2012
New Delhi: Uniqueness and variety are two rules Irrfan has stuck to throughout his film career. The acclaimed actor, known for movies like 'The Namesake', 'Life In A... Metro', and 'Paan Singh Tomar', says he wants to continue breaking his own image in the industry with new and fresh projects. "I...
FTN: 'Barfi' not the best Indian entry for the Oscars
September 26, 2012
Sagarika Ghose: Hi there. Yes, the film 'Barfi!' is India's entry for the Oscars for the year 2013. There's been a great deal of adverse comment on this choice made by the jury of the Film Federation of India with many, saying 'Barfi!' was simply not the best in...
Indie films can help tackle issues: Tigmanshu
August 22, 2012
New Delhi: Filmmaker Tigmanshu Dhulia, who is riding high on the success of 'Paan Singh Tomar', feels independent filmmaking can help tackle socially relevant issues in a big way. "I think independent filmmaking is the only way out in this country. There are so many issues that can be tackled through...
Next »


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BCPR Anthony Brown
( Illustration by Alex Fine / July 1, 2014 ) Anthony BrownThe lieutenant governor easily won the Democratic nomination for governor, making him the overwhelming favorite to win the general election and become only the third elected African-American governor in U.S. history. We wish he had some more innovative plans for Maryland, but if he makes as much progress as O'Malley--who signed bills to legalize gay marriage, abolish the death penalty, and decriminalize marijuana--he'll do just fine. |


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Register with us or sign in
in Home : Projects: Herbs
A sharp knife
A pot
Soil-based potting compost
As the weather turns colder in autumn, it's sensible to be prepared and insure your precious herbs against damage. Tender herbs such as tropical herb, lemon grass, need some extra TLC if they're to survive our cold winters.
These steps shown below can also be used for cardamom and ginger.
Remove the plant from the pot; trim the leaves to just above the stems. Slice a thin section off the base of the rootball, then use a sharp knife to remove sections of grass, each with a chunk of root.
Lemon grass likes being pot-bound, so choose a container a fraction larger than the rootball. Pot up using soil-based potting compost. Label, water in and place in a warm, frost-free environment.


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New subscription
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Hi! My name is Midnight
I am an American Shorthair from lockport, IL
Nicknames: Mater
Age: 7 years old
Gender: M
Coat: short haired
Education: He helped my other cat get through hard times.
My favorite tricks and treats are: He jumps bords and does flips. and Mice,bunnys.
Where I hang out: Under horse trailer and in the horse barn on the hay.
My favorite grubs: Cat food
My pet peeves: Eat mice
What I love about my owners: She cares for me and loves me.
My cat hobbies: Play pounce on other cat.
Pet motto: Eat mice,Live good.
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I found him in my yard. with a broken leg. When I started healing him I got attacted to him.
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22 friends have voted for me since I joined Club Cat!
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Continue to Business Insider »
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Chairman of the Federal Reserve Ben Bernanke spoke to members of the Senate today on the reality of our economy.
He denied being "out of bullets," but the reality is that he is facing up to an extraordinary combination of deflation, unemployment, and sovereign debt woe.
To fully understand that horror, check out the Fed's charts describing our reality.
It's very dark in here.
How investing in your company's benefits can help you save for a vacation — or retirement
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Publisher's Description
+Python is a high-level programming language that is suitable for simple scripting tasks as well as writing large applications. MacPython offers alot of Mac-specific extensions, including access to all major MacOS Toolbox modules (QuickDraw, QuickTime, AppleScript and many more), an Integrated Development Environment (in Python!), frameworks for windowing applications, unix-compatible cgi-scripting, image-manipulation libraries, numerical libraries, tk-based machine independent windowing and lots more. It also uniquely among Pythons allows you to create fully selfcontained (and, hence, distributable) applications without needing a C compiler or anything.
What's new in this version:
- Types and classes are unified, so you can subclass builtin types.
- Iterators and generators allow objects to be "looped over" and producer/consumer-style programming.
- Accept both unix- and mac-style newlines
- Automatic garbage collection
- Better Carbon support and better integration with OS X command line Python


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In the week before Labor Day's traditional fall campaign kickoff, Ohio governor's race has been anything but static. Continue reading
Gunmen dressed in Iraqi police uniforms kidnapped at least 50 people Monday at bus stations in Baghdad a day after 21 Shiite students were killed. The New York Times' Baghdad bureau chief discusses the kidnappings and the deadlock over ministerial nominations. Continue reading
Zalmay Khalilzad, the U.S. ambassador to Iraq, calls on the new Iraqi unity government to take decisive action against local militias and outlines the U.S. role in security and reconstruction. Continue reading
Iraq's new prime minister, Nouri al-Maliki, who was sworn in with 36 of his ministry appointments Saturday, said Iraqi forces could assume control of much of the country by year's end. Three Iraq analysts access the new government and the challenges ahead. Continue reading


text:
Damaged Sign Request at Columbia St, Brookline
Closed over 3 years ago via iPhone
request #: 1112
status: Closed. Thank you for your recent request using the BrookOnline Notify Application. The damaged sign has been repaired.has pole: yes
submitted: Wed Nov 23, 2011 12:53PM
opened: Wed Nov 23, 2011 12:53PM
closed: Tue Nov 29, 2011 07:28AM


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51 U.S. Code § 50917 - Enforcement and penalty
A person may not violate this chapter, a regulation prescribed under this chapter, or any term of a license issued or transferred under this chapter.
General Authority.—
In carrying out this chapter, the Secretary of Transportation may—
under lawful process—
enter at a reasonable time a launch site, reentry site, production facility, assembly site of a launch vehicle or reentry vehicle, crew or space flight participant training site, or site at which a payload is integrated with a launch vehicle or reentry vehicle to inspect an object to which this chapter applies or a record or report the Secretary requires be made or kept under this chapter; and
Civil Penalty.—
After notice and an opportunity for a hearing on the record, a person the Secretary finds to have violated subsection (a) of this section is liable to the United States Government for a civil penalty of not more than $100,000. A separate violation occurs for each day the violation continues.
(Pub. L. 103–272, § 1(e),July 5, 1994, 108 Stat. 1341, § 70115 of title
49; Pub. L. 105–303, title I, § 102(a)(14),Oct. 28, 1998, 112 Stat. 2850; Pub. L. 108–492, § 2(c)(24),Dec. 23, 2004, 118 Stat. 3981; renumbered § 70115 then § 50917 of title
51, Pub. L. 111–314, § 4(d)(2), (3)(Q),Dec. 18, 2010, 124 Stat. 3440, 3441.)
Revised Section | Source (U.S. Code) | Source (Statutes at Large) |
70115(a) | ||
49 App.:2617. | ||
Oct. 30, 1984, Pub. L. 98–575, §§ 17–19, 98 Stat. 3061. | ||
70115(b)(1) | ||
49 App.:2616(b). | ||
70115(b)(2) | ||
49 App.:2616(a). | ||
70115(c)(1) | ||
49 App.:2618(a) (1st, 2d sentences). | ||
70115(c)(2) | ||
49 App.:2618(c). | ||
70115(c)(3) | ||
49 App.:2618(a) (3d, last sentences). | ||
70115(c)(4) | ||
49 App.:2618(b). |
In subsection (a), the words "a requirement of" are omitted as surplus. The word "prescribed" is substituted for "issued" for consistency in the revised title and with other titles of the United States Code. The words "condition, or restriction" are omitted as surplus.
In subsection (b)(1)(A)–(C), the words "concerning any matter relating to enforcement of this chapter" are omitted as surplus.
In subsection (b)(1)(B) and (C), the words "from any person" are omitted as surplus.
In subsection (b)(1)(B), the word "affirmation" is omitted because of 1:1.
In subsection (b)(2), the text of 49 App.:2616(a) (1st sentence) is omitted as surplus because the Secretary of Transportation enforces programs the Secretary carries out unless otherwise provided. The words "the exercise of" are omitted as surplus. The words "duty or power" are substituted for "authority" for consistency in the revised title and with other titles of the Code. The words "to any officer or employee of the Department of Transportation" are omitted as surplus because of 49:322(b).
In subsection (c)(1), the words "in accordance with section
554 of title
5" are omitted for consistency in the revised title and because 5:554 applies to a hearing on the record unless otherwise stated. The words "for each violation" are omitted as surplus.
In subsection (c)(2), the words "relevant papers, books, documents, and other" are omitted as surplus. The words "(3) administer oaths and affirmatives" are omitted as surplus because of subsection (b)(1)(B) of this section.
In subsection (c)(3), the word "impose" is substituted for "assessed" for consistency in the revised title and with other titles of the Code. The words "amount of such" and "modify . . . with or without conditions" are omitted as surplus.
Subsection (c)(4) is substituted for 49 App.:2618(b) to eliminate unnecessary words.
2010—Pub. L. 111–314successively renumbered section
70115 of title
49 and section
70115 of this title as this section.
2004—Subsec. (b)(1)(D)(i). Pub. L. 108–492inserted "crew or space flight participant training site," after "site of a launch vehicle or reentry vehicle,".
1998—Subsec. (b)(1)(D)(i). Pub. L. 105–303inserted "reentry site," after "launch site," and inserted "or reentry vehicle" after "launch vehicle" in two places.
LII has no control over and does not endorse any external Internet site that contains links to or references LII.


text:
Hello, Sometimes I use modsecurity rules in my virtual domains. It's a very powerful mod. I would like to add a geoip rule to my ispconfig.vhost but I found the next directive: Code: <IfModule mod_security2.c> SecRuleEngine Off </IfModule> Oops! Why ispconfig set to off the RuleEngine? Cheers!
Mod_security is disabled as some mod_security rules block ispconfig functions. ISPConfig is s server control panel, so it has to work with paths in system directories like /etc, but mod_security falsely detects this as attack and blocks ispconfig.


text:
Marear DeSilva PALMER Home Page Site Home Page & Index Contact Details - if you think you have any information that will help me with my research and these webpages.
Walter William born baptised Louis Charles born baptised Herbert born baptised Harold DeSilva born baptised Charles born baptised And please, don't forget to sign my Guest Book before you leave! This page created 7 August 2002 & amended/updated 19:20 30/01/2005


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TABLE OF CONTENTS FOREWORD by Richard Kaufman PREFACE by Cassidy J. Alexander INTRODUCTION CHILDHOOD MEMORIES: 1922 - 1936 PRE-WORLD WAR II: 1936 - 1942 WAR YEARS: 1942 - 1947 BROOKLYN COLLEGE: 1947 - 1957 PRIVATE PRACTICE: 1957 - PRESENT THEORIES CARD ROUTINES Hold My Hand The Power of ESP What it Takes to Make it to the Top Another Man's Game SS Cards to Pocket BASIC COIN SLEIGHTS: THE SOL STONE WAY Fingertip Pinch Grip Finger Palm and Ramsay Subtlety The Basic Pivot Vanish Pivot Transformation "No Table" Pivot Vanish Pivot Click Pass The Simplified Spider Vanish The Townsend Acquitment Sequence One-Hand Thumb Palm Turnover Switch Hot Potato Shuttle Pass Sol's Spellbound Sequence The Brush Change (a.k.a. Tumble Switch/Change) AMAZING PENETRATIONS The Jarred Coin Baby Jarred Coin Sweet and Low Cointemplate STRANGE TRANSPOSITIONS Two-Timing Transpo The Direct Transposition (Three Handlings) "I'd Rather Be Rich." FIFTY-ONE CENTS AND COUNTING Fifty-One Cent Routine: Original Handling Another Fifty-One Cent Routine PSYCHOLOGICAL SPLITS Coin Fusion Pulling Silver SOFT SLEEVING Basic Soft Sleeve Technique Soft Sleeve Cover Soft Sleeve Turnover vanish/Change One-Hand Spectator Sleeve Change Soft Sleeve Short Routine BACK FINGER CLIP: STEP-BY-STEP The Sol Stone Back Finger Clip Second and Third Finger Back Clip Back Clip Recoveries Back Clip Change Number One Back Clip Change Number Two The One-Two-Three Cover BACK CLIP ROUTINES The Shrinking Coin "Right There" Revisited The Invisible Coin The Hung Coin Simple Triple One-Hand Spellbound Quadruple One-Hand Spellbound: The Patriotic Poker Chip Advanced Triple One-Hand Spellbound TENKAI PENNIES & VARIATIONS Classic Two-Coin Handling with Back Clip Tenkai Preliminary: The Malini Routine One Coin Tenkai ON THE MISER�S DREAM Sol's Miser's Dream Sequence Tenkai's Miser's Dream Move Back Clip vanish and Production IMPOSSIBLE LINKS Linking Links Ring on Pen ("On Again Off Again") ODDS AND ENDS The Ultimate Imp Bottle Finger through Jacket The New York Jumping Knot The Bornstein Floating Bill TWO CLASSICS The Chaperone $1,000 Dice Routine |
At long last, legendary New York magician Sol Stone's best effects have been amassed into a single, hard-bound volume. Here are over 50 of Sol's favorite effects -- including some of his most closely-guarded secrets -- all completely updated and rewritten, with the full routines and Sol's newest improvements.
The book details all of the sleights and subtleties in Sol's arsenal, clearly and in isolation, thereby streamlining and simplifying the learning process. Magicians of all skill levels can learn from this master of intimate illusion. Written by Stephen Hobbs, Edited by Richard Kaufman, with over 350 crystal-clear illustrations by portrait artist Cassidy J. Alexander, this is a book that will delight performers and collectors alike.
"Sol Stone is one of magic's greatest treasures."
-Richard Kaufman
"Sol Stone has "the touch." He manages to find the most subtle, deceptive, and direct way to create the impression of real magic. Lovers of pure magic will be delighted that his work is now available in this beautifully written and illustrated book."
-John Carney
"If it is from Sol Stone's mind it will be great for your hands!" -Harry Lorayne
"Sol Stone creates intimate miracles that are casual yet devastating. I wish I was more like Sol. After mastering the magic in this book maybe I will be. Highly recommended!" - Meir Yedid
Hardcover with dust jacket
$55.00 plus shipping + handling
S/H $4.50 for U.S. media mail. Please email for
U.S. Priority mail rates.
International customers, please contact me
directly for shipping + handling charges for
your country.
We accept Visa, Mastercard, Discover or American
Express by phone, or Paypal online.
No checks or money orders, please. To order,
contact Cassidy Alexander at:
or call 630-859-3551. Please include your name and address.


text:
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http://www.w3.org/Bugs/Public/show_bug.cgi?id=13124 Summary: The allowtransparency attribute on the iframe element is obsolete. Use CSS instead. Product: HTML WG Version: unspecified Platform: Other URL: http://www.whatwg.org/specs/web-apps/current-work/#aut hors-using-xhtml OS/Version: other Status: NEW Severity: normal Priority: P3 Component: HTML5 spec (editor: Ian Hickson) AssignedTo: firstname.lastname@example.com ReportedBy: email@example.com QAContact: email@example.com CC: firstname.lastname@example.com, firstname.lastname@example.com, firstname.lastname@example.com Specification: http://www.whatwg.org/specs/web-apps/current-work/ Multipage: http://www.whatwg.org/C#authors-using-xhtml Complete: http://www.whatwg.org/c#authors-using-xhtml Comment: The allowtransparency attribute on the iframe element is obsolete. Use CSS instead. Posted from: 184.108.40.206 User agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0 -- Configure bugmail: http://www.w3.org/Bugs/Public/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.Received on Saturday, 2 July 2011 11:23:28 UTC
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