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About David Spade
David Wayne Spade (born July 22, 1964) is an American stand-up comedian, actor, writer, musician, and television personality. He rose to fame in the 1990s as a cast member on Saturday Night Live, then began a successful acting career in both film and television. He has starred or co-starred in the films Tommy Boy, Black Sheep, Joe Dirt, Grown Ups and Grown Ups 2, among others. He has also been part of an ensemble cast of two long-running sitcoms: Just Shoot Me! (1997-2003) and Rules of Engagement (2007-2013). He also starred as C. J. Barnes in the sitcom 8 Simple Rules from 2004-2005. Spade also notably provided the voice of Kuzco in the 2000 animated film The Emperor's New Groove and its direct-to-video sequel, Kronk's New Groove. Spade is known for a comedic style, in both his stand-up material and acting roles, that involves a combination of sarcasm and self-deprecation. Early life, high school and college: Spade was born on July 22, 1964 in Birmingham, Michigan, and is the son of Judith J. (née Meek), a writer and magazine editor, and Wayne M. Spade, a sales representative. His brothers are Bryan and Andy Spade; Andy is the husband of designer Kate Spade. Spade and his family moved to Scottsdale, Arizona, when he was four years old. His parents divorced soon thereafter, and he and his brothers were raised for the most part by their mother, in relative poverty. Spade attended Saguaro High School and later Scottsdale Community College, before transferring to Arizona State University, where he earned his bachelor's degree in business in 1986. He also was a member of the Sigma Alpha Epsilon fraternity. Spade performed standup at the university's long-running sketch comedy show, Farce Side Comedy Hour, on numerous occasions. In the mid-80s he also did "stand up" in the Monday night comedy show at Greasy Tony's Pizza in Tempe, Arizona. Career: With the help of friend and fellow comedian Dennis Miller, he joined Saturday Night Live in 1990 as a regular cast member and writer. While there, he became known for his brand of sarcasm, and his smart aleck characters in a number of sketches were hits. Some of them include a flight attendant for "Total Bastard Airlines" who bids a perceived-as-unpleasant "Buh-Bye" to each passenger upon disembarking; a receptionist for Dick Clark who, as a matter of policy, asks people indiscriminately "And you are?"; and the sarcastic "Hollywood Minute" reporter who communicates with celebrities by means of one-liners. Other characters include Christy Henderson from the Gap Girls, and Karl from the Karl's Video sketches. He also did impressions of various celebrities, including Brad Pitt and Michael J. Fox. According to interviews with Spade, most of the material that he wrote early in his time at SNL was given to Dana Carvey to perform on the show. Due to his relatively low work rate, he was in danger of being fired as a performer, until the "Hollywood Minute" segment secured his position. The most infamous moment of "Hollywood Minute" occurred in 1996, when a picture appeared on-screen of Eddie Murphy, himself a former Saturday Night Live cast member, and Spade exclaimed, "Look children, it's a falling star. Make a wish!", referring to Murphy's lack of box office success at the time, most recently with the film Vampire in Brooklyn. The crack led to audience boos, and made Murphy upset at both Spade and SNL for years afterwards. Though most of the cast left in 1995, Spade stayed the following year to help in the transition with the new cast. He then quit in 1996 citing "burnout" as the reason. Said Spade, "When I leave, it will be to ease the pressure, not to be a movie star. You can't stay there forever - it kills you inside. It ages you in dog years. It's a tough place." He returned to host an episode in 1998 and another in 2005. Spade's attempt at a film career met with success. He appeared with fellow Saturday Night Live cast member and friend Chris Farley in two buddy comedy films, Tommy Boy (1995) and Black Sheep (1996). The two were planning a third film together when Farley died of a drug overdose in 1997 at the age of 33. Although he received several offers to star in his own TV shows, he turned them down and joined the ensemble cast of Steven Levitan's office sitcom Just Shoot Me!, opposite Laura San Giacomo and George Segal, which ran for seven seasons from 1997 to 2003. He played a sarcastic receptionist, Dennis Finch. While appearing on Just Shoot Me, Spade had his first solo starring role as the title character in the 2001 film Joe Dirt, which was a modest box office success. The film was co-written by Spade and Fred Wolf. Spade starred again in the 2003 film Dickie Roberts: Former Child Star, again co-written by Spade and Wolf. It was the first of many films in which Spade has appeared that were produced by another Saturday Night Live castmate, Adam Sandler. Most notable among these are the films Grown Ups (2010) and Grown Ups 2 (2013), both of which included Spade and Sandler among the lead roles, and both of which were major box office hits. Spade hosted both the Teen Choice Awards and SpikeTV's Video Game Awards in 2003. He voiced characters on several episodes of Beavis and Butt-head, and produced his own TV series Sammy in 2000. From 2002 to 2006 Spade regularly appeared in commercials for Capital One (with Nate Torrence) where he played the employee of a fictional rival company whose policy toward honoring credit card rewards (and just about everything else) is "always no." In 2004, he joined the cast of 8 Simple Rules, following the death of the sitcom's star, John Ritter, for the show's third and final season. He hosted the Comedy Central TV show The Showbiz Show with David Spade for three seasons, from September 2005 to October 2007. On the show Spade made fun of Hollywood and celebrities in a manner similar to his old "Hollywood Minute" segment on SNL. Spade was one of the voice talents for the 2006 video game The Legend of Spyro: A New Beginning. He provided the voice of Spyro's dragonfly companion, Sparx. From 2007 to 2013, Spade starred as Russell Dunbar in the ensemble CBS sitcom Rules of Engagement. In 2010 he worked with TBS on a pilot for an animated series based on Joe Dirt, but it was eventually dropped. Awards and honors: Spade received an Emmy nomination and two Golden Globe nominations for his role as Dennis Finch on Just Shoot Me!. On September 5, 2003, Spade received a star on the Hollywood Walk of Fame. Personal life: Spade has one daughter named Harper with Playboy Playmate Jillian Grace. Spade has become very sensitive to light. The combination of bright lights on-set and working under sunlight while filming Black Sheep caused permanent damage to his eyes, and requires Spade to wear a hat, even indoors, and to dim the lights in the make-up trailers. In December 2005, Spade donated $100,000 to the police department in his hometown of Phoenix, which provided 50 AR-15 semi-automatic rifles for the officers. Spade also donated $200,000 for the Oklahoma tornado relief program on May 20, 2013 and $100,000 towards the ALS ice bucket challenge in 2014. Filmography: Year Title Role Notes 1987 Police Academy 4: Citizens on Patrol Kyle 1992 Light Sleeper Theological Cokehead 1993 Coneheads Eli Turnbull 1994 Reality Bites The "Wienerschnitzel" Manager 1994 PCU Rand McPherson 1995 Tommy Boy Richard Hayden MTV Movie Award for Best On-Screen Duo 1996 Black Sheep Steven "Steve" Dodds 1996 Very Brady Sequel, AA Very Brady Sequel Sergio 1996 Beavis and Butt-head Do America uncredited voice role 1997 8 Heads in a Duffel Bag Ernest "Ernie" Lipscomb 1998 Senseless Scott Thorpe 1998 Rugrats Movie, TheThe Rugrats Movie Ranger Frank "Franklin" voice role 1999 Lost & Found Dylan Ramsey writer 2000 Loser The Video Store Clerk 2000 Emperor's New Groove, TheThe Emperor's New Groove Emperor Kuzco / Llama Kuzco voice role, Nominated - Kid's Choice Award 2001 Joe Dirt Joseph "Joe" Dirt writer 2003 Dickie Roberts: Former Child Star Dickie Roberts writer 2005 Racing Stripes Scuzz voice role 2005 Lil' Pimp Principal Nixon voice role, Direct-to-video 2005 Kronk's New Groove Emperor Kuzco voice role, Direct-to-video 2006 Grandma's Boy Shilo 2006 Benchwarmers, TheThe Benchwarmers Richie Goodman Nominated - Teen Choice Award for Best Choice Chemistry 2007 I Now Pronounce You Chuck and Larry Transvestite Groupie 2010 Grown Ups Marcus Higgins 2011 Jack & Jill Monica Razzie Award for Worst Supporting Actress 2011 Snowflake, the White Gorilla Jenga voice role 2012 Hotel Transylvania Griffin the Invisible Man voice role 2013 Jungle Master Boss Cain voice role 2013 Grown Ups 2 Marcus Higgins 2015 Space Breakout Xanor voice role 2015 Hotel Transylvania 2 Griffin the Invisible Man Post-production, voice role 2015 Joe Dirt 2: Beautiful Loser Joseph "Joe" Dirt Post-production 2016 The Ridiculous Six General Custer Filming Television: Year Title Role Notes 1988 Facts of Life, TheThe Facts of Life Scott Season 9, Episode 22: "Big Apple Blues" 1989 Baywatch B. J. Season 1, Episode 3: "Second Wave" 1990 ALF Larry Slotkin Season 4, Episode 14: "Make 'em Laugh" 1990 Monsters Teddy Season 3, Episode 7: "Small Blessings" 1990 Born to Be Mild Stage Assistant uncredited; cameo 1990-1996 Saturday Night Live Various writer and cast member from 1990-1996, Emmy Award for Outstanding Writing in a Variety or Music Program (1990-1993), Hosted episodes in 1998 and 2005. 1992 Larry Sanders Show, TheThe Larry Sanders Show Himself Season 1, Episode 2: "The Promise" 1994 Beavis and Butt-Head Mr. Manners, Mr. Candy, Ticket Attendant voice role; uncredited; cast member from 1994-1997 1997-2003 Just Shoot Me! Dennis Finch Nominated - Emmy Award for Outstanding Supporting Actor in a Comedy Series, Nominated - Golden Globe Award for Best Performance by an Actor in a Supporting Role in a Series, Mini-Series or Motion Picture, Nominated - Golden Globe Award for Best Performance by an Actor in a Supporting Role in a Series, Mini-Series or Motion Picture Made for TV, Nominated - TV Land Award for Co-Worker You're Least Likely to Invite Out for Happy Hour, Nominated - American Comedy Award 1998 David Spade: Take the Hit Himself Stand up comedy special 2000 Sammy Sammy Blake, James Blake voice role; canceled after 2 episodes 2002 Greg The Bunny Himself cameo 2003 2003 Spike Video Game Awards Host TV special 2004 Father of the Pride Tommy the Coyote voice role 2004-2005 8 Simple Rules C. J. Barnes main cast member from 2004-2005 2005-2007 Showbiz Show with David Spade, TheThe Showbiz Show with David Spade Himself 2007-2013 Rules of Engagement Russell Dunbar main cast; nominated - Teen Choice Award for Choice TV Actor: Comedy 2011 Entourage Himself Season 8 Episode 6 "The Big Bang" 2012 Hot in Cleveland Christopher Season 3 episode 24: "Blow Outs" 2014 The Spoils of Babylon Talc Munson Episode 4: "The Foundling" 2014 David Spade: My Fake Problems Himself Stand up comedy special 2014 The Goldbergs Foto Shop owner Season 2 episode 1 "Love is a Mixtape" 2014 Ridiculousness Himself Season 5 Episode 3 "David Spade" Music videos: Year Title Performer Notes 1993 "Buddy" Adam Sandler Video games: Year Title Character Notes 2000 The Emperor's New Groove (video game) Kuzco/Llama Kuzco 2006 The Legend of Spyro: A New Beginning Sparx
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Chronicle: Living Like Lou - Pittsburgh Cured Polio
UPDATED 12:04 PM EDT Mar 26, 2014ALS researchers hope that history with repeat itself when it comes to developing a preventative measure for ALS just like what happened with Polio. Dr Jonas Salk discovered a Polio vaccine in Pittsburgh only decades ago; his son Dr. Peter Salk reflects back on his father.
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subset: commoncrawl


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The Great Escape
The Prolific Writer in Schnottz's Landing wants you to collect 6 Fresh Uniforms from Schnottz Sea Sailors.Fresh Sailor Uniform (6) |
Please, <class>! We need your help!We're being kept in this building against our will. And with the commander on such a tirade, there's no telling what he might do to us!
Perhaps if you were to secure some uniforms for us, we could sneak away.
We never should have come here. I see that now.
If you help us escape, I will write the TRUTH of what has happened here.
The men on those ships are all dressed in the garb we need.
You will be able to choose one of these rewards:Mirror-Polished Boots | Gauntlets of the Obelisk | ||
False-Face Mask | Officer's Formal Baton |
The Great Escape Initialize |
Upon completion of this quest you will gain:- 12,600 experience


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US 5835949 A Abstract A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.
Claims(16) 1. A pipelined microprocessor that supports self-modify code comprising:
(a) at least one execution pipeline having a plurality of stages; (b) a primary instruction cache coupled to said at least one execution pipeline and supplying instructions thereto; (c) an index tag module, disposed adjacent to said at least one execution pipeline, having a plurality of index tags, one for each of said plurality of stages in said at least one execution pipeline, each index tag identifying at least one cache line from where an instruction originated; (d) cache replacement logic, responsive to said plurality of index tags, to replace lines in said primary instruction cache which are not in said at least one execution pipeline; and (e) flush means, responsive to an instruction writing to an address within said primary instruction cache, for flushing said at least one execution pipeline. 2. A pipelined microprocessor as recited in claim 1 wherein said plurality of index tags further includes logical OR circuitry to identify more than one cache line from where said instruction originated.
3. A pipelined microprocessor as recited in claim 1 further comprising a secondary instruction cache disposed between said primary instruction cache and main memory.
4. A pipelined microprocessor as recited in claim 3 wherein said secondary instruction cache is a unified cache.
5. A pipelined microprocessor as recited in claim 1 wherein said primary instruction cache has a first and a second valid bit associated with each cache line, and further comprising:
(f) means for clearing both first and second valid bits for a particular line in said primary instruction cache in response to said instruction write in (e); and, (g) means for clearing said second valid bit only in response to an external snoop or replacement hit in said instruction cache. 6. A pipelined microprocessor as recited in claim 5 further comprising:
(h) means for setting said first valid bit and clearing said second valid bit in response to non-cacheable instruction data being executed in said execution pipeline. 7. A pipelined microprocessor as recited in claim 1 wherein said flush means flushes only those stages in said at least one execution pipeline preceding a stage that contains a target address of said instruction write.
8. A pipelined microprocessor that supports self-modify code comprising:
(a) pipelined execution means for executing instructions in multiple stages; (b) cache means, having cache lines, for supplying instructions to said pipelined execution means; (c) index tag means for supplying an index tag that identifies a cache line origin of an instruction being executed in said pipelined execution means; (d) cache replacement logic means, responsive to said index tag means, for replacing lines in said cache means which hold instructions that are not in said pipelined execution means; and (e) flush means, responsive to a write to a target address within said cache means, for flushing said pipelined execution means. 9. A pipelined microprocessor as recited in claim 8 wherein said index tags means further includes logical OR means for identifying more than one cache line from where said instruction originated.
10. A pipelined microprocessor as recited in claim 8 wherein said cache means includes a primary cache and a secondary instruction cache wherein said primary cache is relatively small with respect to said secondary cache.
11. A pipelined microprocessor as recited in claim 10 wherein said secondary instruction cache is a unified cache.
12. A method of identifying and handling self-modifying instructions in a processor having at least one multiple-stage execution pipeline and an instruction cache, comprising steps of:
(a) fetching instructions into said at least one multiple-stage execution pipeline from at least one line in said instruction cache; (b) tagging each instruction with an index tag to identify where each instruction originated in said instruction cache; (c) propagating in parallel, each instruction and its index tag through said at least one execution pipeline; (d) monitoring each index tag with cache line replacement logic; (e) inhibiting replacement of instruction cache lines indicated by any index tag as originating from any instruction in said at least one execution pipeline; and, (f) flushing said at least one execution pipeline if an instruction write is made to said instruction cache. 13. A method as recited in claim 12 wherein step (b) further includes said step of logically ORing multiple index tags to identify where each instruction originated in said instruction cache.
14. A method as recited in claim 12 wherein said instruction cache has a first and a second valid bit associated with each cache line, and further comprising said steps of:
(g) clearing both first and second valid bits for a particular line in said instruction cache in response to said instruction write in step (f); and, (h) clearing said second valid bit only in response to an external snoop or replacement hit in said instruction cache. 15. A method as recited in claim 12 wherein step (f) flushes only those stages in said at least one execution pipeline preceding a stage that contains a target address of said instruction write.
16. A method as recited in claim 12 wherein step (a) further comprises said step of fetching instructions into said at least one execution pipeline from a higher order cache or main memory in parallel with filling said instruction cache in response to a miss in said instruction cache.
Description The present application is a file wrapper continuation of application Ser. No. 08/364,354, filed Dec. 27, 1994, now abandoned. 1. Field of the Invention The invention relates generally to computer systems, more particularly to microprocessor architectures which employ caches and pipelined instruction stages, and even more particularly, to a system and method of tagging instructions in an execution pipeline with an index tag to identify self-modifying code. 2. Description of Related Art Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application. Many computer architectures permit program instructions to write to address space which is allocated for program instructions. This is commonly referred to as "self-modifying code". A classic example of self-modifying code in the x86 microprocessor architecture is a technique for handling floating point instructions. Floating point units (FPUs) a.k.a. numeric coprocessors, were at one time, cost prohibitive for general usage. Accordingly, a typical program written for the x86 microprocessor architecture assumed that the FPU was not present in a system and handled floating point instructions through software emulation by calls to subroutines. If however, the program detected a FPU through means well known in the art, the program code "self-modified" itself to increase speed so that opcodes were executed directly by the FPU rather than through emulation by the CPU. Another exemplary, but not exclusive, illustration of self-modifying code in the x86 architecture is programming which employs software interrupts with modifiable immediate operands. For example, the immediate operand "5" in the software interrupt instruction (INT #5) could be modified to "3" based on some program condition so that an interrupt routine 3 rather than 5 is executed. By way of further background, caching and pipelining techniques are complicated by self-modifying code since the self modifications must be propagated through the caches and the execution pipeline in the event that the code to be modified resides therein. More specifically, all levels of cache must be checked to see if any hold the instruction which is to be modified and accordingly, must be modified. Similarly, the execution pipeline must be checked for an "instruction to be modified" match which is queued deeper in the pipeline than the modifying code, and if a match occurs, must be modified accordingly. The complications of self-modifying code are even further exacerbated by variable length instruction set microprocessors since instruction opcodes can cross cache line and page boundaries. Yet another obstacle with self-modifying code is virtual memory addressing. The physical address rather than the virtual or "linear" address of the instruction which is to be modified, must be compared to the physical addresses of all instructions queued deeper in the execution pipeline as well as to ones in the instruction cache. An even further complication of self-modifying code is sharing memory resources such as in a multiprocessor environment. Specifically, external processors or DMA controllers perform "snoops" on local caches to identify overlapping physical addresses. Accordingly, these physical addresses must be tagged and compared for each entry in the caches and potentially for each entry in the execution pipeline. Heretofore, techniques which have addressed self-modifying code in pipelined/cached processor designs have employed a content addressable memory (CAM) to store and compare the linear and physical address tags of each instruction queued in the execution pipeline or stored in the instruction cache. Each cell in the CAM therefore, requires a lengthy comparator, a lengthy linear address tag, and a lengthy physical address tag, requiring more die area and taking up valuable space on an integrated circuit, forcing the designer to make tradeoffs between the depth of the execution pipeline and the number of CAMs. Moreover, the CAMs in the execution pipeline are some what duplicative with CAMs already in the instruction cache, consuming more power and compounding power dissipation problems within the integrated circuit. It can be seen from the foregoing that there is a need for a technique of identifying and handling self-modifying code in the execution pipeline(s) without the need to compare the full linear and physical address of each instruction in every pipe stage. To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a system and method of tagging instructions with an index tag as each instruction enters the execution pipeline(s) of a pipelined processor so that each instruction can be readily identified in the event of self-modifying code. The index tag reflects the line number origin(s) in an instruction cache for the instruction traveling through the execution pipeline. The index tag signals replacement logic in the instruction cache not to replace any cache line that holds instruction data which is currently active in the execution pipeline. If an instruction write is identified to a location in the instruction cache, pipeline control logic flushes the execution pipeline(s) from that location and back, and instruction data is refetched from a higher order cache or main memory and re-executed. On external and higher order cache replacement snoop hits, the pipeline control logic preferably does not flush the execution pipeline(s) but rather, the cache line which hit is marked as read invalid. A feature of the present invention is utilization of a small index tag rather than the full physical and linear addresses to indicate the instruction cache origin(s) for each instruction in a multiple-stage execution pipeline processor. Another feature of the present invention is the use of separate Valid and Read Valid bits to accommodate non-cacheable instruction data, and external and higher order cache replacement snoops without flushing the execution pipeline(s). Another feature of the present invention is accommodation of variable length instruction sets with the use of logical OR circuitry to OR multiple (cache line origin) index tags which describe a single instruction. These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described specific examples of systems and methods in accordance with the present invention. Referring now to the drawings in which like reference numerals and letters indicate corresponding elements throughout the several views: FIG. 1a illustrates a block diagram of an exemplary microprocessor practiced in accordance with the principles of the present invention; FIG. 1b illustrates in more detail, a block diagram of the instruction pipelines for the microprocessor in FIG. 1a, employing index tags practiced in accordance with the principles of the present invention; FIG. 2 illustrates a block diagram of an exemplary computer system utilizing the microprocessor depicted in FIG. 1a; FIG. 3 illustrates the flow of eight instructions through a dual pipeline processor practiced in accordance with the principles of the present invention; FIG. 4 illustrates a block diagram of the instruction fetch flow for the exemplary microprocessor depicted in FIG. 1a; FIG. 5 illustrates the instruction cache for the exemplary microprocessor depicted in FIG. 1a in more detail; and, FIG. 6 illustrates virtual address mapping to the instruction cache along with instruction cache indexing for the exemplary microprocessor depicted in FIG. 1a. In the following description of the preferred embodiment(s), reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiment(s) in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Throughout the following detailed description, the terms "execution pipeline" and "instruction pipeline" are used interchangeably to describe a pipelined processor having multiple stages for processing instructions. The terms "instruction cache", "instruction line cache", "instruction line buffer", and "ILB" are also used interchangeably throughout the following detailed description. The detailed description of an exemplary embodiment of the microprocessor which employs systems and methods for detecting self-modifying code is organized as follows: 1. Exemplary Processor System 1.1 Microprocessor 1.2 System 2. Generalized Pipeline Flow 3. Instruction Fetch Flow 4. ILB Tag Module 5. Instruction (L0) Cache 5.1. Non-cacheable Instructions/Linear Address Directory 6. Virtual Memory/Instruction Cache Map 7. Conclusion This organizational outline, and the corresponding headings, are used in this Detailed Description for convenience of reference only. Detailed descriptions of conventional or known aspects of microprocessor systems are omitted so as to not obscure the description of the invention with unnecessary detail. In particular, certain terminology related to the x86 computer architecture (such as register names, signal nomenclature, etc.) is known to practitioners in the field of microprocessor design. 1. Exemplary Processor System The exemplary processor system is shown in FIGS. 1a and 1b, and FIG. 2. FIGS. 1a and 1b respectively illustrate the basic functional blocks of an exemplary super-scalar, super-pipelined microprocessor along with the pipe stages of two execution pipelines (X and Y), practiced in accordance with the principles of the present invention. FIG. 2 illustrates an exemplary processor system (motherboard) design using the microprocessor. 1.1. Microprocessor Referring to FIG. 1a, the major sub-blocks of a microprocessor 10 include: a CPU core 20, prefetch buffer 30, prefetcher 35, branch processing unit (BPU) 40, address translation unit (ATU) 50, and a sixteen Kilobyte code/data unified cache 60, including TAG RAM 62. A two hundred fifty six byte instruction cache 65 provides a primary instruction cache to reduce instruction fetches to the unified cache 60, which operates as a secondary instruction cache. An onboard floating point unit (FPU) 70 executes floating point instructions issued to it by the CPU core 20. The microprocessor 10 uses internal thirty-two bit address and sixty-four bit data buses ADS and DATA, respectively. A two hundred fifty six bit (thirty-two byte) prefetch bus PFB, corresponding to the thirty-two, thirty-two byte line size of the unified cache 60 and the instruction cache 65, allows a full line of thirty-two instruction bytes to be transferred to the instruction cache 65 in a single clock. External interface to the ADS and DATA buses is through a bus interface unit (BIU) 90. The unified cache 60 is four-way set associative (with a four Kilobyte set size), using a pseudo-LRU replacement algorithm, with write-through and write-back modes. It is dual ported (through banking) to permit two memory accesses (data read, instruction fetch, or data write) per clock. The instruction cache 65 is a fully associative, lookaside implementation (relative to the unified cache 60), using an LRU replacement algorithm. The FPU 70 includes a load/store stage with four-deep load and store queues, a conversion stage (thirty-two bit to eighty bit extended format), and an execution stage. Loads are controlled by the CPU core 20, and cacheable stores are directed through the write buffers 29 (i.e., a write buffer is allocated for each floating point store operation). The CPU core 20 is a super-scalar design with two execution pipelines X and Y. It includes an instruction decoder 21, address calculation units 22X and 22Y, execution units 23X and 23Y, and a register file 24 with thirty-two, thirty-two bit registers. An AC control unit 25 includes a register translation unit 25a with a register scoreboard and register renaming hardware. A microcontrol unit 26, including a microsequencer and microROM, provides execution control. Writes from CPU core 20 are queued into twelve, thirty-two bit write buffers 29--write buffer allocation is performed by the AC control unit 25. These write buffers provide an interface for writes to the unified cache 60--non-cacheable writes go directly from the write buffers 29 to external memory. The write buffer logic supports optional read sourcing and write gathering. A pipe control unit 28 controls instruction flow through the execution X and Y pipes, including keeping the instructions in order until it is determined that an instruction will not cause an exception, squashing bubbles in the instruction stream, and flushing the execution pipelines behind branches that are mispredicted and instructions that cause an exception. For each stage, the pipe control unit 28 keeps track of which execution pipeline contains the earliest instruction, and provides a stall output and receives a delay input. Referring to FIG. 1b, the microprocessor 10 has seven-stage X and Y execution pipelines namely: instruction fetch (IF), two instruction decode stages (ID1, ID2), two address calculation stages (AC1 and AC2), execution (EX), and write-back (WB). Note that the complex instruction decode ID and address calculation AC pipe stages are super-pipelined. The IF stage provides a continuous code stream into the CPU core 20. The prefetcher 35 fetches sixteen bytes of instruction data into the prefetch buffer 30 from either the (primary) instruction cache 65 or the (secondary) unified cache 60. BPU 40 is accessed with the prefetch address, and supplies target addresses to the prefetcher 35 for predicted changes of flow, allowing the prefetcher 35 to shift to a new code stream in one clock. The ID1 and ID2 decode stages decode the variable length x86 instruction set. The instruction decoder 21 retrieves sixteen bytes of instruction data from the prefetch buffer 30 each clock. In ID1, the length of two instructions is decoded (one each for the X and Y execution pipelines) to obtain the X and Y instruction pointers--a corresponding X and Y bytes-used signal is sent back to the prefetch buffer 30 (which then increments for the next sixteen byte transfer). Also in ID1, certain instruction types are determined, such as changes of flow, and immediate and/or displacement operands are separated. The ID2 stage completes decoding the X and Y instructions, generating entry points for the microROM and decoding addressing modes and register fields. During the ID stages, the optimum pipe for executing an instruction is determined, and the instruction is issued into that pipe. Pipe switching allows instructions to be switched from ID2x to AC1y, and from ID2y to AC1x. In the exemplary embodiment, certain instructions are issued only into the X pipeline, namely: change of flow instructions, floating point instructions, and exclusive instructions. Exclusive instructions include: any instruction that may fault in the EX pipe stage and certain types of instructions such as protected mode segment loads, string instructions, special register access (control, debug, test), Multiply/Divide, Input/Output, PUSHA/POPA, and task switch. Exclusive instructions are able to use the resources of both pipes because they are issued alone from the ID stage (i.e., they are not paired with any other instruction). Except for these issue constraints, any instructions can be paired and issued into either the X or Y pipe. The AC1 and AC2 address calculation stages calculate addresses for memory references and supply memory operands. The AC1 stage calculates two thirty-two bit linear (three operand) addresses per clock (four operand addresses, which are relatively infrequent, take two clocks). During this pipe stage, data dependencies are also checked and resolved using the register translation unit 25a (register scoreboard and register renaming hardware)--the thirty-two physical registers in the register file 24 are used to map the eight general purpose programmer visible logical registers defined in the x86 architecture (EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP). During the AC2 stage, the register file 24 and the unified cache 60 are accessed with the physical address (for cache hits, cache access time for the dual ported unified cache is the same as that of a register, effectively extending the register set)--the physical address is either the linear address, or if address translation is enabled, a translated address generated by an ATU 50. Translated addresses are generated by the ATU 50 from the linear address using information from page tables in memory and workspace control registers on chip. The unified cache 60 is virtually indexed and physically tagged to permit, when address translation is enabled, set selection with the untranslated address (available at the end of AC1) and, for each set, tag comparison with the translated address from the ATU 50 (available early in AC2). Checks for any segmentation and/or address translation violations are also performed in AC2. Instructions are kept in program order until it is determined that they will not cause an exception. For most instructions, this determination is made during or before AC2--floating point instructions and certain exclusive instructions may cause exceptions during execution. Instructions are passed in order from AC2 to EX (or in the case of floating point instructions, to the FPU)--because integer instructions that may still cause an exception in EX are designated exclusive, and therefore are issued alone into both execution pipelines, handling exceptions in order is ensured. The execution stages EXx and EXy perform the operations defined by the instruction. Instructions spend a variable number of clocks in EX, i.e., they are allowed to execute out of order (out of order completion). Both EX stages include adder, logical, and shifter functional units, and in addition, the EXx stage contains multiply/divide hardware. The WB write back stage updates the register file 24, condition codes, and other parts of the machine state with the results of the previously executed instruction. The microprocessor 10 supports speculative execution in the case of both branch and floating point instructions. That is, instructions following either a floating point instruction, or a branch for which the BPU 40 has predicted the direction (taken or not taken), are speculatively allowed to proceed in the execution pipelines and complete execution. If a floating point instruction faults (which may be tens or even hundreds of clocks after being issued to the FPU 70) or if a branch is mispredicted (which will not be known until the EX or WB stage for the branch), then the execution pipeline must be repaired to the point of the faulting or mispredicted instruction (i.e., the execution pipeline is flushed behind that instruction), and instruction fetch restarted. Pipeline repair is accomplished by creating checkpoints of the machine state at each pipe stage as a floating point or predicted branch instruction enters that stage. For these checkpointed instructions, all resources (programmer visible registers, instruction pointer, condition code register) that can be modified by succeeding speculatively issued instructions are checkpointed. If a checkpointed floating point instruction faults or a checkpointed branch is mispredicted, the execution pipeline is flushed behind the checkpointed instruction--for floating point instructions, this will typically mean flushing the entire execution pipeline, while for a mispredicted branch there may be a paired instruction in EX and two instructions in WB that would be allowed to complete. For the exemplary microprocessor 10, the principle constraints on the degree of speculation are: (a) speculative execution is allowed for only up to four floating point or branch instructions at a time (i.e., the speculation level is maximum four), and (b) a write or floating point store will not complete to the cache or external memory until the associated branch or floating point instruction has been resolved (i.e., the prediction is correct, or floating point instruction does not fault). 1.2. System Referring to FIG. 2 for the exemplary embodiment, microprocessor 10 is used in a processor system that includes a single chip memory and bus controller 82. The memory/bus controller 82 provides the interface between the microprocessor 10 and the external memory subsystem--level two cache 84 and main memory 86--controlling data movement over the sixty-four bit processor data bus PD (the data path is external to the controller which reduces its pin count and cost). Controller 82 interfaces directly to the thirty-two bit address bus PADDR, and includes a one bit wide data port (not shown) for reading and writing registers within the controller. A bidirectional isolation buffer 88 provides an address interface between microprocessor 10 and VL and ISA buses. Controller 82 provides control for the VL and ISA bus interface. A VL/ISA interface chip 91 (such as an HT321) provides standard interfaces to a thirty-two bit VL bus and a sixteen bit ISA bus. The ISA bus interfaces to BIOS 92, keyboard controller 93, and I/O chip 94, as well as standard ISA slots 95. The interface chip 91 interfaces to the thirty-two bit VL bus through a bi-directional thirty-two/sixteen multiplexer 96 formed by dual high/low word 31:16!/ 15:0! isolation buffers. The VL bus interfaces to standard VL slots 97, and through a bi-directional isolation buffer 98 to the low double word 31:0! of the sixty-four bit processor data bus. 2. Generalized Pipeline Flow FIG. 3 illustrates the flow of eight instructions through the pipeline, showing the overlapping execution of the instructions, for a two pipeline architecture. Additional pipelines and additional stages for each pipeline could also be provided without departing from the scope of the present invention. In the preferred embodiment, the microprocessor 10 uses an internal clock 122 which is a multiple of the system clock 124. In FIG. 3, the internal clock is shown as operating at two times the frequency of the system clock. During the first internal clock cycle 126, the ID1 stage operates on respective instructions X0 and Y0. During internal clock cycle 128, instructions X0 and Y0 are in the ID2 stage (X0 being in ID2x and Y0 being in ID2y) and instructions X1 and Y1 are in the ID1 stage. During internal clock cycle 130, instructions X2 and Y2 are in the ID1 stage, instructions X1 and Y1 are in the ID2 stage (X1 being in ID2x and Y1 being in ID2y) and instructions X0 and Y0 are in the AC1 stage (X0 being in AC1x and Y0 being in AC1y). During internal clock cycle 132, instructions X3 and Y3 are in the ID1 stage, instructions X2 and Y2 are in the ID2 stage, instructions X1 and Y1 are in the AC1 stage and instructions X0 and Y0 are in the AC2 stage. The instructions continue to flow sequentially through the stages of the X and Y pipelines. As shown in clocks 134-140, the execution portion of each instruction is performed on sequential clock cycles. This is a major advantage of a pipelined architecture--the number of instructions completed per clock is increased, without reducing the execution time of an individual instruction. Consequently a greater instruction throughput is achieved without requiring greater demands on the speed of the hardware. The instruction flow shown in FIG. 3 is the optimum case. As shown, no stage requires more than one clock cycle. In an actual machine, however, one or more stages may require additional clock cycles to complete thereby changing the flow of instructions through the other pipe stages. Furthermore, the flow of instructions through one pipeline may be dependent upon the flow of instructions through the other pipeline. A number of factors may cause delays in various stages of one or all of the pipelines. For example, an access to memory may miss in the memory cache, thereby preventing access of the data in the time required to process the instruction in one clock. This would require that either, or both, sides of the EX stage to delay until the data was retrieved from main memory. For a particular stage, other stages of the pipeline may be using a needed resource, such as a multiplier, which is only in one of the execution stages in the illustrated embodiment In this case, the stage must delay until the resource is available. Data dependencies can also cause delays. If an instruction needs the result from a previous instruction, such as an ADD, it must wait until that instruction is processed by the execution unit. Other delays are caused by "multi-box" instructions; i.e., instructions which are implemented using multiple microinstructions, and therefore require more than one clock cycle in the EX pipe stage to complete. These instructions stop the flow of subsequent instructions through the pipeline at the output of the ID2 stage. The flow of instructions through the pipeline is controlled by the pipe control unit 28. In the preferred embodiment, a single pipe control unit 28 is used to control the flow of instructions through both (or all) of the pipes. To control the flow of instructions through the pipes, the pipe control unit 28 receives "delay" signals from the various units comprising the X and Y pipes, and issues "stall" signals to the various units. Although a single pipe control 28 unit is used for both X and Y pipelines, the pipelines themselves are controlled independent of one another. In other words, a stall in the X pipeline does not necessarily cause a stall in the Y pipeline. 3. Instruction Fetch Flow Reference is now made to FIG. 4 which depicts a more detailed diagram of the instruction fetch flow in the present invention. The prefetch buffer 30 receives a lower quad-word (bits <63:0>) from multiplexer 220 and an upper quad-word (bits <127:64>) from multiplexer 222. Multiplexers 220 and 222 have inputs coupled to either the instruction cache 65 (a.k.a. L0), the unified cache 60 (a.k.a. L1), or to external memory through the bus interface unit (BIU) 90. Since the instruction cache 65 is organized thirty two bytes (256 bits) wide, multiplexer 224a-224b reduces the cache line down to sixty-four-bit chunks for multiplexers 220 and 222, one-hundred-twenty-eight bits at a time. Similarly, multiplexer 226a-226b reduces the cache line down from the unified cache 60 to sixty-four-bit chunks for multiplexers 220 and 222. The third set of inputs to multiplexers 220 and 222 originate from the BIU 90 which supplies instruction data from external memory. The instruction cache 65 receives two physical addresses from multiplexer 230. Multiplexer 230 has physical address inputs from the ATU 50 (program writes), the BIU 90 (external snoops), and from the unified cache 60 (L1 Replacements). The instruction cache 65 receives linear or "virtual" addresses from the prefetcher 35 (FIG. 1a). The BIU 90 supplies via concentrator 228, two-hundred-fifty-six bit wide instruction data to the instruction cache 65. Likewise, the unified cache 60 supplies two-hundred-fifty-six bit wide instruction data directly to the instruction cache 65 over the PFB bus. An ILB tag module 200 supplies eight (ILB0 -ILB7) hit signals to the instruction cache 65. It should be understood that the eight hit signals (ILB0 -ILB7) correspond to the number of lines in the instruction cache 65 and it is contemplated that the number of hit signals can be expanded or contracted to accommodate other size instruction caches. It should also be understood that while the ILB tag module 200 is depicted as a single functioning module, it does not necessarily represent the structural arrangement of the exemplary system. Rather, it is primarily intended to illustrate the major components in a convenient functional grouping wherein the present invention may be more readily understood. 4. ILB Tag Module The ILB tag module 200 is best described with reference again to the block diagram in FIG. 1b. The seven-stage X and Y execution pipelines are shadowed by index tag registers TAG1-TAG13 in the ILB tag module 200 which hold the line number origin(s) in the instruction cache 65 of instruction data traveling down the instruction pipeline. Index tag registers TAG1-TAG13 include a 3-to-8 decoder (not shown) to expand the line number of instruction cache 65 to one-of-eight hit signals. Tags TAG9-TAG13 further include logical OR circuitry (not shown) to logically OR together multiple one-of-eight hits signals to identify that more than one line in the instruction cache 65 is associated with a particular instruction in a pipe stage, described in more detail hereinbelow. Each time the prefetcher 35 fetches instruction data into the prefetch buffer 30 (FIG. 1a), two index tags from the instruction cache 65 indicating the line hit (described in more detail hereinbelow) are loaded into the IF stage to identify the origin of the instruction data in the instruction cache 65. If the instruction data originates from the unified cache 60 (L1) or from main memory via BIU 90, it is also concurrently stored in the instruction cache 65 and assigned an index tag corresponding to its instruction cache line number. In the preferred embodiment, the instruction cache 65 is eight lines deep by thirty-two bytes (256 bits) wide. Accordingly, a three bit index tag can uniquely identify each of the eight lines in the instruction cache 65. The instruction fetch (IF) stage preferably has eight tags (TAG1-TAG8) associated with it since it can hold eight instruction fetches. The ID1 and ID2 instruction decode stages, the AC1 and AC2 address calculation stages, and the EX execution stage, each have two index tags, one for each X and Y pipeline, although each tag may represent more than one cache line as described in more detail hereinbelow. It is to be understood that the index tags can be extended or contracted (in length and in quantity) to fit other pipeline stage sizes and other instruction cache sizes without departing from the scope of the present invention. Each of the eight bits in each index tag are logically OR'ed together by logical OR array 202. The logical OR array 202 has eight sets of eighteen inputs and provides eight hit outputs (ILB0 -ILB7) to indicate that a particular line in the instruction cache 65 is present somewhere in the execution pipeline. ILB0 -ILB7 are routed to replacement logic 232 in the instruction cache 65, depicted in FIG. 5 and described in more detail hereinbelow. 5. Instruction (L0) Cache Reference is now made to FIG. 5 which depicts the instruction cache 65 in more detail. Each cache line in the instruction cache 65 preferably includes two copies of the same physical address (tags I and II), two copies of the same linear address (tag I--Prefetch) and (tag II--Prefetch+8), a Valid bit, a Read Valid bit, thirty-two bytes of instruction data, three-bit--index tag Hit I and index tag Hit II signals, and Snoop Hit I and Snoop Hit II signals. It should be understood that index tag Hit I and index tag Hit II signals could be eight bits wide instead of being encoded as three bits, as described in more detail hereinbelow. Replacement logic 232 has inputs coupled to the ILB0 -ILB7 outputs from the ILB tag module 200 as well as to LRU circuitry 234. The replacement logic 232 generally follows some form of least recently used scheme designated by LRU 234 to evict and replace entries in the instruction cache 65 unless the ILB0 -ILB7 signals indicate that a selected cache line is in either the X or Y execution pipeline or in the prefetch buffer 30. Accordingly, any cache line identified by ILB0 -ILB7 as being in either execution pipeline is not replaced. The physical address tags are compared whenever there is a program write to an instruction address, an external memory request to the microprocessor (e.g. DMA controller or an external processor in a multiple processor environment with shared memory), or a cache line replacement from the unified cache 60. The physical address is "snooped" (compared) to determine whether or not it is contained in the instruction cache 65. If a physical address of a program write is found in a line in the instruction cache 65, the Valid and Read Valid flags are both invalidated (cleared), the appropriate Hit signal is asserted, and if the cache line is propagated into the execution pipeline, the respective execution pipeline is flushed. If however, a snoop hit results from an external snoop or a replacement snoop from the unified cache 60, only the Read Valid flag is invalidated (cleared) and the execution pipelines are not flushed. The pipeline flushes are preferably invoked through an exception handler rendered through microcode. Moreover in the preferred embodiment, the X and Y pipelines are only flushed from the stages preceding the stage that contain the hit. After the execution pipelines are flushed and the line in the instruction cache 65 is invalidated, the prefetcher 35 refetches the modified cache line(s) which will be supplied from the unified cache 60, or if necessary, from main memory. Self-modifying code thus "modifies" (writes) to the unified cache 60 or higher level cache rather than to the instruction cache 65. The linear address tags which identify the lines in the instruction cache 65, are compared with the linear address supplied by the prefetcher (prefetch) and an address indexed by eight (prefetch+8), to determine if any instruction hits are in the instruction cache 65. Index Hit I and Hit II tags identify the line number in the instruction cache 65 that hit, if any, and are asserted if the Valid and the Read Valid bits are set (valid). 5.1. Non-cacheable Instructions/Linear Address Directory In the event instruction data is deemed non-cacheable, prefetcher 35 does not load instruction data into/from the unified cache 60. However, a cache line in the instruction cache 65 is still allocated for the non-cacheable instruction data, the Valid bit is set, and the Read Valid bit is cleared. In this manner, subsequent requests for the non-cacheable instruction data results in a cache miss but the cache line origin (i.e. ILB tag) is still in the ILB tag module 200 and is used for comparison to identify self-modifying code. Moreover, while the preferred embodiment has been described with respect to the instruction cache 65 functioning as an L0 (primary) cache, the present invention also has application with a large (L1) type instruction cache. In this case, the primary origin for instructions is from the L1 cache 60. Although cache 60 is depicted as being unified, it may also be a separate instruction and data cache. In the alternative embodiment, the L0 cache 65 functions as a linear address directory (i.e. similar to the function for non-cacheable instruction data) rather than an instruction cache for storing all the elements depicted in FIG. 5 with the exception of instruction data. That is, the instructions originate from a relatively large instruction cache 60 and the L0 cache 65 functions as an indirect index to cache line hits (i.e. a linear address directory 65) for providing tags to the ILB index tag module 200. 6. Virtual Memory/Cache Map Reference is now made to Table 1 below and FIG. 6, which best exemplify how virtual memory address space is mapped into the instruction (or linear directory) cache 65 and how the ILB tags identify stages in the execution pipelines. It should be understood however, that arbitrary values for the linear address tags are used for purposes of explanation. The virtual or linear memory address space is depicted vertically along the right side in FIG. 6. In this example, program flow occurs top to bottom with arbitrary change of flow (COF) instructions occurring in address space 7e00f-7e010 and in address space 7e040-7e047. To simplify explanation, the address space along the cache line in instruction cache 65 is broken down into eight-byte wide "quadrants" designated A, B, C, and D. Access to the instruction cache 65 is described with respect to the internal clock 122 depicted in FIG. 3. Referring specifically to Table 1, during clock cycle zero, program execution begins with a prefetch linear address of 7e000 resulting in a hit in the instruction cache 65 on line five, quadrants A and B. The three bit Hit I and Hit II index tags "tag" the instruction data located at these addresses with the instruction cache line number (binary 101). The three bit tag is decoded in the ILB tag module 200 into an eight bit tag. As the instruction travels through the X and Y pipelines, the decoded eight-bit tag propagates through the ILB tag module 200 as discussed hereinabove, identifying the instruction as originating from line five (00010000) in the instruction cache 65. During clock cycle one, program execution continues with prefetch and prefetch+8 linear addresses 7e010 and 7e018 respectively, resulting in hits in the instruction cache 65 on line five, quadrants C and D respectively. Accordingly, Hit I and Hit II index tags "tag" the instruction data located at these addresses with the instruction cache line number. The execution of a change of flow instruction (e.g. Jump) somewhere in address space 7e010-7e01f forces the prefetcher 35 to fetch prefetch and prefetch+8 linear addresses 7e038 and 7e040 respectively during clock cycle two. As a result, a "split line" hit occurs in the instruction cache 65 on line zero, quadrant D and line six, quadrant A. Accordingly, Hit I index tag indicates "000" and Hit II index tag indicates "110". At this point, it should be noted that it is possible for a single (multiple-byte) instruction to cross cache line boundaries such that two ILB index tags actually describe one instruction. Typically however, the subsequent instruction will reflect the same ILB index tag as the second tag for the multiple-byte instruction unless the multiple-byte instruction is a COF type instruction. If for example, a "split line" single instruction fetch from cache lines 1 and 6 travels down the X-pipe, TAG9X-TAG 13X would reflect both cache lines by ORing both ILB tags (00000001 and 00100000) together to produce a unitary hit tag of (00100001). Thus both ILB1 and ILB6 would be asserted. Continuing the discussion with respect to FIG. 6, the execution of a change of flow instruction (e.g. Jump) somewhere in address space 7e040-7e047 forces the prefetcher 35 to fetch prefetch 7e060 address during clock cycle 3. As a result, a miss occurs in the instruction cache 65 and instructions for this section are dispatched directly from the unified cache 60 or main memory via BIU 90. The instruction cache 65 is updated with the instruction data and the index tag identifying the instruction cache 65 line where it will be stored is propagated through the ILB Tag module 200. As discussed above, the cache line replacement is preferably performed with a LRU technique along with consideration of the ILB0 -ILB7 hit tags. TABLE 1______________________________________Address Quadrant Cache Line Index Tag HitClockPrefetch Prefetch + 8 I II I II I II______________________________________0 7e000 7e008 A B 5 5 101 1011 7e010 7e018 C D 5 5 101 1012 7e038 7e040 D A 0 6 000 1103 7e060 Instruction Cache Miss xxx xxx______________________________________ 7. Conclusion Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. For example, specific register structures, mappings, bit assignments, cache associations and sizes, and other implementation details are set forth solely for purposes of providing a detailed description of the invention. However, the invention has general applicability to any computer system architecture which permits self-modifying code. Various modifications based on trade-offs between hardware and software logic will be apparent to those skilled in the art. Also, the specific address nomenclature (linear address, effective address, segment base, relative base, etc.) is conventional for the x86 architecture, and is used for the purpose of describing the exemplary embodiment only. The invention encompasses any modifications or alternative embodiments that fall within the scope of the Claims. Patent Citations
Referenced by
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The Manchester United striker will miss Tuesday's crucial World Cup qualification clash against Ukraine after picking up a yellow card to go with his two goals at Wembley
Roy Hodgson admits that England's 4-0 victory over Moldova was "overshadowed" by the booking for Danny Welbeck that rules the striker out of Tuesday's crucial World Cup qualifying clash against Ukraine.The Manchester United forward scored twice at Wembley on Friday night but received his second yellow card of qualifying in the first half for kicking the ball away, leaving the Three Lions desperately short of strikers, with Wayne Rooney injured and Daniel Sturridge struggling with a thigh problem.
5/1 | Rickie Lambert is 5/1 with BetVictor to score the first goal in Ukraine v England |
"The win was overshadowed, especially coming at a time when we're short of front players anyway," Hodgson told the press. "It doesn't get much more unfortunate than that but we're getting used to dealing with it.
"We were shaken, if not stirred, by Welbeck's booking. I don't think there are too many people in the game who would say that's a yellow card - it was a 40-yard sprint and a first-time shot just after the whistle.
"He's got a yellow card, he's out of the game and we'll live with it. Did I think it's a correct decision? No I didn't."
Sturridge will join up with the rest of the England squad on Saturday night but Hodgson fears that the Liverpool forward has only a slim chance of being fit to face Ukraine.
"There's no reason why we should give up hope," he added. "It's not impossible but it's definitely no more than 50-50 - and I fear it's worse than that."


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AllocateRegistrySpace Action
The AllocateRegistrySpace action ensures that the amount of free registry space specified by the AVAILABLEFREEREG property exists in the registry.
Sequence Restrictions
The AllocateRegistrySpace action must be called after InstallInitialize. It is advisable to schedule the AllocateRegistrySpace before all other actions to ensure there is enough registry space available to continue.
ActionData Messages
Field | Description of action data |
[1] | Registry space required in KB. |
Community Additions


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College of Liberal Arts and Sciences
Unit Head Mailing 11-11-08
Provost to host town hall meetings
What are Noroviruses?
Geography Awareness Week
CHAKA-Music of an African Icon
Additional Rationale Required for Prerequisites in Curriculum Proposals-message from Mary Schutten, Chair of CCC
Co-curricular Activities: Second Year Students
CLAS Important Dates
1. Provost to host town hall meetings
Provost Gayle R. Davis will host two Academic Affairs town hall meetings on the Allendale and Pew Grand Rapids campuses.
Discussion will center on the state of academic affairs at Grand Valley, higher education in Michigan, Davis said.
Meetings are set for Wednesday, November 19, beginning at 3:30 p.m. in the Eberhard Center; and November 24, 4 p.m., in the Kirkhof Center, room 2204.
2. What are Noroviruses? (attachment)
With the recent breakout at Hope College many questions have come up regarding this virus. Tony Nieuwkoop, Biomedical Health Sciences Chair, has put together a FAQ file to share with faculty, staff, and students.
3. Geography Awareness Week – message from Jeroen Wagendorp
There will be a lecture on Nov. 18 in celebration of Geography Awareness Week. Please share the attachment with your faculty and students.
4. CHAKA – Music of an African Icon-Message from Professor Alvarez
Next Monday, November 17th at 4:30 p.m., South African scholar Johann S. Buis will deliver a lecture on the legendary figure of Chaka, the founder of South Africa's Zulu nation. Please share the attachment with your faculty and students.
5. Additional Rationale Required for Prerequisites in Curriculum Proposals-message from Mary Schutten, Chair of CCC
This message was sent to all CCC Chairs from UCC Chair, Robert Adams.
Please note the change in documentation required by the University Curriculum Committee in the "Prerequisites Section" of New Course Proposals and Course Change Proposals.
Given UCC's recent (and ongoing) pre-requisite removal fast-track process, UCC is requesting that proposers justify each and every pre-requisite course included in a new course proposal or a course change. This will ensure that proposers think about and provide a rationale for why the pre-requisites are needed. In short, this means UCC would like to see something more than "The pre-requisites provide foundation knowledge upon which this course will build." UCC would like to see why EACH pre-requisite course is needed.
Thank you for your cooperation.
6. Co-curricular Activities: Second Year Students
In follow-up to last week's Unit Head discussion about co-curricular activities that enhance first year student success, we've been requested by the Provost's Office to expand our discussion to include second year students. Would each of you please send me a list and brief description of unit co-curricular activities that target promoting the academic success of second year students? Please send your information via e-mail to Donna Larson before Monday, December 1. Thank you.
Important Dates |
Event |
Location |
Nov. 14 |
Staffing Plans for W09 due |
Nov. 19 |
Unit Head Meeting |
3:00-5:00, 2270 KC-note location change |
Nov. 19 * |
Draft W09 Contract letters to Unit Head |
Nov. 21 |
Nov. 21* |
Draft W09 Contract letters back from Unit Head |
Nov. 26-28 |
Thanksgiving Recess |
Dec. 1 |
Out of the Box Lunch |
Dec. 3 |
Unit Head Meeting |
Dec. 4 |
GVSU Holiday Party |
3:00-5:00, Grand River Room |
Dec. 5 |
CLAS Holiday Luncheon |
11:30-1:15, Pere Marquette Room, KC |
Dec. 8-12 |
Final Exam Week |
Dec. 16 |
Final Grades Due from faculty |
*New Dates
Page last modified May 18, 2012


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The MG T series included the TA, TB, TC, TD, and TF Midget models, a range of body-on-frame convertible sports cars produced in a... More
1949 MG TC, This MG TC has recently had a complete ground up restoration. Not a bolt was left unturned. There is not enough... More
1948 MGTC 1250 ROADSTER. EX-TORREY PINES RACECAR FROM 1953 AND 1954. FORMER TOD MORCOTT CAR. BLACK WITH GREEN WINGS, GREEN LEATHER TRIM, BLACK CANVAS... More
MG TC 1946 body off restored in absolute showcondition 1946 MG TC body off restored. Perfect restored in Holland in 2013. Everything is brandnew restored... More
1949 MG-YT 4-PASSENGER TOURER. 4-passenger. White with tan leather interior and canvas top. Rare left-hand drive, very correct, restored example. $42,500 1949 MG-YT TOURER #19798284. (Stock... More


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Woman With Autistic Son Reflects on the Struggles, Joys of Raising Him
SPRINGFIELD, Mass. (WGGB) – Lydia Alicea never realized that something might be amiss with her son Nathan until he went to day care, when she realized that something may not be right.
"He wasn't making eye contact, wasn't interacting with other kids and that's when we had concerns," she said.
She had never heard of Autism and she described feeling lost after his diagnosis, but she did everything she could for her son.
"There were many years of therapy, trips to Children's Hospital Boston and I had to just educate myself and my family on how to deal with him," said Alicea.
Now, Nathan is 20-years-old. He has a job and a black belt.
"I like to work at Big Y, like to play some video games and have some fun, and watch the Springfield Falcons," he said.
And of course, his favorite part of the hockey games are the fights.
"Fighting! Fighting, yea!" he said.
Looking back, Lydia said all the struggles she went through after Nathan's diagnosis were worth it to see all of his accomplishments today. And she has some advice for all the parents who have children with Autism as well.
"I think lots of patience, understanding and a lot of love. Those are the three keys that got me where I am today. Because every child is different," she said.


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Bailey Gray Cloud's Most Excellent Adventures
OMC!!April 1st 2012 6:31 am[ Leave A Comment ]
OMC! I can't believe that I'll be 7 years old tomorrow! I'm still a lively mancat and don't feel that old! Also, I demonstrated this morning to Mommy that I can still jump through the railing 4-5 feet down instead of walking all the way down the stairs. I still get a kick out of doing this. There's no arthritis in me at all!! Leave a Comment |
BAILEY GRAY CLOUD Family Pets
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· About $50,000 worth of tools and vehicle diagnostic equipment was stolen from a resident's locked garage in the 8700 block of South 27th Street at 9:20 p.m. May 31. The suspect(s) kicked in the garage door to gain entry.
· A catalytic converter was stolen off a work truck in the Valenti Classics lot at 9848 S. 57th St. sometime between May 1 and May 28.
· A 21-year-old woman, two 20-year-old women and an 18-year-old woman, all of Milwaukee, were arrested for shoplifting after they were seen filling duffel bags with clothing at Walmart, 6701 S. 27th St., and then fled the store at about 10:55 a.m. May 28.
· The driver of a red Dodge Caravan left without paying for $70 worth of gas at Kwik Trip, 10750 W. Speedway Drive, at about 3 p.m. May 31.
· An 18-year-old man and a 16-year-old boy were arrested for disorderly conduct and battery after they injured a 23-year-old man during a physical altercation in the 6300 block of South 35th Street at about 4:30 p.m. May 27. Police later cited a third suspect, a 15-year-old boy, for disorderly conduct and battery for his role in the incident.
· A 39-year-old Franklin woman was arrested for battery after she injured a 16-year-old girl during a physical altercation at Walmart, 6701 S. 27th St., at about 9:10 p.m. May 30. The fight allegedly started when one person cut in front of the other in the checkout line. The victim sustained scratches and a few abrasions.
· A 42-year-old male resident reported he was attacked by five unidentified males in the backyard of his home in the 9100 block of South 41st Street at 2:55 a.m. May 31. The suspects, described as white males in their late teens or early 20s, were not located. The victim was transported by the Franklin Fire Department to Wheaton Franciscan Hospital where he was treated for multiple contusions and cuts to his face that required six stitches on his left brow and a nasal bone fracture.
Drug possession
· A 33-year-old man was arrested for obstructing/resisting an officer and possession of drug paraphernalia in the 2000 block of South 15th Place (in Milwaukee) at about 10 a.m. June 1. The man, who was a suspect in several retail thefts, was arrested after he fled from police and led them on a short foot pursuit when they approached him.
· A 24-year-old woman was arrested for drugged driving in the 12100 block of West Bel Mar Drive after an off-duty Milwaukee police officer reported seeing her putting on a tourniquet and injecting a needle into her arm before driving off in a black Saturn Vue with two passengers at about 11:55 a.m. June 1. One passenger in her car, a 30-year-old man, was also taken into custody for having two warrants for possession of drug paraphernalia and obstructing with the Rock County Sheriff's Department and for having an extraditable felony warrant with the Lake County Sheriff's Department in Illinois. The second passenger, a young child, was turned over to a relative.
Drunken driving
· A 22-year-old Milwaukee woman was arrested for drunken driving and was cited for deviating from a designated lane in the 4600 block of West Drexel Avenue at about 1:55 a.m. June 1. A chemical breath test indicated a blood alcohol content of 0.10.
· A 60-year-old man was transported to St. Luke's Hospital after he apparently suffered a heart attack while driving his 2005 black SUV out of the parking lot at Target, 7800 S. Lovers Lane Road, at about 11:43 a.m. May 30. The man drove directly into a wooded area across the street and was found breathing but unresponsive.
· A 16-year-old girl was arrested for battery after she was involved in a physical altercation with her grandmother at a residence in the 7200 block of South 51st Street at about 7:40 p.m. May 27. At about 9:20 p.m. May 29, the girl jumped out of a car while she was being transported to the juvenile detention center. She was last seen in the area of South 84th Street and Greenfield Avenue, where she fled from her parents, and is now listed as missing.
· An apartment window was broken in the 3600 block of West College Avenue sometime between 7 a.m. and 5 p.m. May 29. It was unknown if entry was made to the apartment or if anything was stolen at the time of the report.
· A man was cited for vandalism and disorderly conduct after he damaged a screen on a home in the 3900 block of West Heatheridge Drive during a verbal argument with the residents at 10:45 p.m. June 1. The man was apparently arguing with a woman over another boyfriend she had, and when he was told to leave, he punched out a screen and threatened to break the woman's phone.
· Firefighters and police responded to a house fire in the 6500 block of South 120th Street at about 7:03 p.m. June 1. When police arrived, the home and attached garage were fully engulfed in flames, and a 65-year-old man had to be rescued from the home. He was transported to the hospital where he was treated for smoke inhalation. The cause of the fire is unknown, and damage is estimated at $60,000.
· A deer head was found lying on the bike path that leads to Forest Park School near the 8000 block of West Lake Pointe Drive at about 9:40 a.m. May 27. Police called the Franklin Department of Public Works, who picked up the deer head soon afterward.
· A 24-year-old man was arrested for eluding (causing injury), resisting arrest, operating after suspension and suspended registration after he fled a traffic stop on South 27th and West College Avenue and led them on a pursuit at about 2 p.m. May 27. The man struck another vehicle on South 27th and Layton Avenue, causing minor injuries to the driver, and was finally stopped on South 27th Street and Goldcrest in Greenfield and taken into custody. Police also discovered the suspect had a warrant through the Milwaukee County Sheriff's Department for resisting/obstructing an officer and possession of a controlled substance.
· A resident in the 5300 block of West Ryan Road reported their small pet turkey went missing sometime between 7 a.m. and 5:55 p.m. May 27. The resident stated the turkey is caged but sometimes manages to get out.
· A 37-year-old man was arrested at the American Motel, 9335 S. 27th St., at about 1:15 p.m. May 29, after police discovered he had a valid warrant for multiple theft convictions through Wisconsin Community Corrections. The man was also wanted by Milwaukee police for a robbery where he allegedly impersonated an officer, pushed the victim against the old squad car he was driving and stole the victim's wallet. He was taken into custody and turned over to the Milwaukee Police Department.
· A 24-year-old man was cited for possessing open intoxicants in a vehicle (passenger) after an employee reported seeing an open container of alcohol in a vehicle going through the drive-thru at Wendy's, 6715 S. 27th St., at about 7:25 p.m. May 29.
· A resident in the 9800 block of South 76th Street reported at about 8 p.m. May 29 that an unidentified person(s) used his personal identifying information to take out a fraudulent loan from a financial institution in Illinois in order to purchase $7,970 worth of tires and rims. The incident occurred April 17, and the victim discovered the theft after being contacted by the financial company at 4 p.m. May 29.
· Franklin police responded to one domestic violence call and one fire call between May 26 and June 1.
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- Franklin police report: Feb. 26, 2015, issue
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- Franklin police report: Jan. 29, 2015, issue
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I would like to use colormapeditor inside a GUI, and I want a pause in the program that waits for me to finish with the colormap settings and then to continue in the code. I don't know how to make this pause, and to test if the user pressed OK, apply or other button inside colormapeditor. In other words I want to get the button that was pressed and then to continue in the code. Any suggestions?
No products are associated with this question.
Quick way to fix the problem is:
colormapeditor; pause; %conntinue your code
With this, after the colormap editor appears, you can do whatever you need, then close it by clicking OK and after press any key to resume the program.
Thanks. I knew this was an option. Is there another way to continue the code, exactly when you press some button in the |colormapeditor| window, without needing to press another button after that? And how can I test if the user pressed Yes, Apply, or Cancel in the |colormapeditor| window?


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207 posts found | |
Well i always see alot of post of peeps asking what game's to play or if they should play rift or WoW wtf why dnt people see aion? I mean ive been playing the game for only like 3 weeks and am level 31 and am having a blast of a time best game in my opnion i love the gear the wings the skills the people even the mobs lmfao i jsut love the game i go to bed sometimes still thinking am playing in the game still lol so why dnt people give aion a try? Is it because how NCSOFT screwed it up at launch? Or is it because some people find it boring i just want the opnions of why u dnt like aion or what gives u the turn off for this game? Just curious to now other people's opnion's. |
I played the game in beta and into launch and i just didnt like the one sided PVP and the grind was pretty grueling. Is it better now? I dont know but i really dont fill like re-installing the game and forking up the 15 bucks to play a game that may or may not be worth it again. They just havnt shown enough improvement from the launch for me to justify it. |
ya aion to me was always a must must try at the very least. The atmoshpere your thrown into when you first step foot in Atreia is amazing. |
Advanced Member
Joined: 5/01/10 No Gods, no Masters. Knowledge is Power, Power is Freedom. |
When game come out in spetember i hit lvl 35 and i quit it was pain...grind grind grind.. And i afraid to come back . Good game dont make only graphics and good music.. Currently playing: HC Diablo 3, DDO |
I played the game from launch, and thought it was a good game for what it was, but it just wasn't for me, PVP was very one sided and getting steamrolled over and over loses appeal fast, though i'll add that i'm not a Huge PVP fan and once i hit level cap there wasn't anything for me to do. My two cents. The Deep Web is sca-ry. |
The enchanting and manastoning system depresses me and makes me not want to play for extended periods of time. Those are my main reasons why I have quit several times and why I don't stay subbed for longer periods. This is also probably the reason why many dub it a grind and do not recommend the game to others. I know I haven't. Also I've grown a bit tired of the click-to-attack & stand-there-and-trade-blows-combat (I can't remember the word for this) but I wouldn't unsub from a fun game for that. |
It's awesome.....right up until you meet up with a cleric in the Abyss only 2 levels higher then you and your friends and he rapes all 5 of you in a few minutes. They may have changed that, but that ruined it for me. At the time I last played, there was no real guarunteed stuns or interupts...you could use a skill that had a CHANCE to do those things, but to be honest, they hardly ever did, leading to clerics healing themselves to full every couple of seconds, all while dropping their little lightning thingy that kills you. That alone was enough for me to say screw it and leave for another game. ALL games have problems with balance as far as PvP goes, don't get me wrong, but when the guy that keeps everyone alive is almost unkillable unless you gang up on him, it kind of takes away from anyone NOT being a cleric, and there were a TON of them back then. |
Originally posted by nblitz Its called Tab-targeting Combat. Nothing Wrong with it but i can see why people are getting tired of it. |
Loved the game up until 30 then started getting into the PVP side of things, then it was a grind fest lack of quests, kept getting ganked into the open world part of it by maxed out players... and the bots really took the cake for me... up side graphics and music r amazing, havnt played it for a good year or so now, might be better but yeh dont wanna start another sub on a game until TOR and then GW2 =) |
I really wanted to play Aion but the P2P + CS is really a huge turn off for me. Most of the CS items look way more cooler than ingame items. Wtf I pay monthly for? So that the dev can more cool CS items and entice you to buy it? Pardon my English as it is not my 1st language :) |
I played it in beta and was very disappointed about the lack of PvP and the annoying HAAAI-YAH my character did everytime it did an attack. I really dislike games that force you to level up in PvE just to be able to PvP. If they had more PvP earlier in the game I probably would have stuck with it longer. I'd just have to play with the volume off until they fix my character to not sound Asian. www.agonysend.org |
I was playing aion from release until a couple months ago. My problem was that the game is way to gear dependant and not just in the tiered sense like most gear dependant mmo's. The best PvE gear in the game does not compare to the best PvP gear. PvP gear doesnt just give you some of an advantage in PvP, It gives you a major advantage. That and the manastone/enchantment stoning that you have to do to become competetive is a painful experience that is based mostly on luck. I dont mind grinding for a month to get enough currency to improve my toon incrementally, But it is possible (likely even) that you will grind for a solid month or 2 and actually come out less powerful from failing your manastone/enchantment stones (which each can cost millions). Oh and the class balance is non-existent. i had 1 of each toon. Some of them pissed me off when i saw how easy mode a couple of them were. FYI: dont play a chanter. Just play a cleric if you want to go priest. My gf played a cleric and my main was a chanter. Not only does she heal better (no contest), clerics also hit harder(about 50%) and at range. |
easy answer to OP. They dont. |
Originally posted by Toxia |
well seems most of u guys not all but most havnt played it recently aion has changed alot the graphics got improved more then before theres actaully not alot of botters theres very few left and the grind has been reduced by like 75-85% seriously NCSOFT took the grind off alot and its easier to get drops from DP now then before and more content with the 2.6 patch that came out in my opnion if u liked the game a bit or so when it came out if u played it now u would love the GAME...another thing to the guy that said he doesnt like the CS bro's the CS is more of a luxury like fashion and stuff like that nothing really game changing at all its more of a show off type stuff theres actaully nothing in the CS that makes a player like a super player or anything...and to the person talkinga bout reinstalling just go to bed while downloading try the free trail or if u want to buy the game amazon is selling aion at 10 bucks with shipping and 30 free ingame days thats an epic deal in my opnion....but yes i would love to see more people play the game although most of the starting zones u see at least 2-4 new people or more every day but either way it be better for more new people the community is nice the PVE is actaully gotten way better than before x10 better and the PVP got even better than before also they fixed up the balances issue's a bit and the grinding for GEAR has improved alot also seems like NCSOFT decided to finally hear the opnions of the players and fix the game up. So i think if u ever thought of trying aion why not give it a try dnt listen to anyone talking crap about it just find out for urself. |
Originally posted by Qtar oh sweet lord... there isnt any 'grind' in Aion before 35, there really isnt. If you was claiming this higher up I would probably agree with you, though saying that it has gotten alot better now, but 'grind' at 35 in this game? No, that never has been true in the Western version. You honestly just sound like someone who is repeating what the cool kids say on the internet in an effort to be 'pro' and have a 'pro' opinion. |
I just return to Aion about 3 weeks ago, left 1 month after launch, and i agree that the community is very helpful. So im slowly ( lvl 23 now ) leveling and see what this game have to offer. However regarding the CS, reading from Aion source http://www.aionsource.com/topic/128583-aion-cashshop-finally-revealed/ some form of play to win is creeping in, sad eh? RIP Orc Choppa |
Cause there is nothing about the game that interest me the slightest.... just to answer you question. |
Originally posted by manny702 Boring grind. |
i think the last time i tried this game was assault on balaura.. can't say it improved the game all that much, i think i played for 7 days out of a 1 month sub.. you have wings you can hardly use, and the grind.. .. the game just isnt interesting enough to play because of it.. i don't really have that kind of willpower.. |


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Rocky Martinez will be defending his WBO super featherweight title against Mikey Garcia, while Vic Darchinyan and Nonito Donaire will finally have their rematch, which is long overdue.
Martinez vs Garcia (WBO Super Featherweight Title - 12 Rounds)
The defending champion's last defeat dates back in 2010, when he faced British Ricky Burns, wherein the former was brought to school by the latter.
"I don't think Martinez has looked the same fighter since losing to Ricky Burns three years ago, which is still the only defeat on his thirty fight ledger. He's still a good fighter, and a pugnacious one, but recently his offensive game has become more predictable and his defence, which was never the best, is virtually non-existent," opined badlefthook.com's Dave Oakes.
While Garcia is not of the same level as Burns, he has the advantage in the speed department and is an overall better boxer. Martinez, on the other hand, compensates his deficiencies with toughness.
"Martinez is tough enough that I see him going the distance, though a later stoppage from Garcia wouldn't surprise me one bit either," said bloodyelbow.com's Fraser Coffeen.
Garcia will be the likely winner of this bout, given his edge, but expect a tough fight as both boxers are a no let-up.
Donaire vs Darchinyan (Rematch, 10 Rounds)
"The Filipino Flash" had his career blossomed after defeating "The Raging Bull" in 2007.
Donaire lost his recent bout to Guillermo Rigondeaux and will be looking to get back on track. Lack of motivation on the part of Nonito was to blame as he felt that he had nothing more left to prove, winning all of his fixtures since June 2001 before falling in April 2013.
Donaire is the favourite to win this fight as he is still in his prime, experiencing a seemingly slight bump.
Meanwhile, Darchinyan is making his last push, being at the twilight of his career, against the person who he handed "the" big-break.


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Tag Archives: NYC
Long Time No Blog…
I haven't posted in awhile. A lot has been going on. I lost my beloved cat Hammy to cancer, and in the middle of that taking a new sublet while trying to change careers. Once I find a job we … Continue reading
Music In Brooklyn.
Went to a little gathering in Brooklyn yesterday. Lots of music being played by some very talented people. I brought the cupcakes… It was a fun Saturday afternoon!
Just in time.
Just got back from being in the city for the last four days. Just in time to see the quince blooming!
Springtime In The City.
Random shots from yesterday. It was a beautiful day! I love this time of year!
Snow Brooklyn Style…
Someday soon I hope to post about something other than snow… At 7:30 this morning it was beautiful.
Tess & Chris in the glass. Lunch.
Angela's apartment in Brooklyn.
This is my friends Angela's beautiful apartment in Brooklyn Heights. It reminds me of Paris.
Random photo's…
On my way into the "big city". Thought I would post some random photos taken with an iphone. This photo was taken by Chris Kelly.


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Every WikiGroup can have GroupHeader and GroupFooter pages that contain markup that should be included at the beginning or end of each page within the group. This feature is useful for:
To create a group header, just create a new page called The default GroupHeader or GroupFooter can be suppressed on an individual page (such as a group's HomePage) by using the If a generic GroupHeader is used in one wikigroup (say, the Site wikigroup), then the code can be easily duplicated in the GroupHeader of any other group by using
If you want a header or footer to appear when you print a page (action print), simply create a page called You can also set the variable See also How do I set the same header or footer for all pages/groups? The header and footer for each page are controlled by the variables ### If you use Site.SiteHeader and Group.GroupHeader $GroupHeaderFmt = '(:include {$SiteGroup}.SiteHeader' . ' basepage={*$FullName}:)(:nl:)' . $GroupHeaderFmt; ### If you use Site.SiteHeader instead of Group.GroupHeader $GroupHeaderFmt = '(:include {$SiteGroup}.SiteHeader' . ' basepage={*$FullName}:)(:nl:)'; ### If you use Site.SiteFooter and Group.GroupFooter $GroupFooterFmt .= '(:nl:)(:include {$SiteGroup}.SiteFooter' . ' basepage={*$FullName}:)'; ### If you use Site.SiteFooter instead of Group.GroupFooter $GroupFooterFmt = '(:nl:)(:include {$SiteGroup}.SiteFooter' . ' basepage={*$FullName}:)'; Note that single quotes must be used in the lines above. See also the Cookbook:AllGroupHeader recipe. Instead of using an additional page, you could set any wiki text in $GroupHeaderFmt .= "Global message here.";
This page may have a more recent version on pmwiki.org: PmWiki:GroupHeaders, and a talk page: PmWiki:GroupHeaders-Talk. |
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