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An interface device for synchronizing an internally clocked modem and data terminal equipment (DTE) provided with their own clock circuits, each of said own terminal clock circuit providing an external clock signal (RC Ext). The interface includes a PLO generating a recovered clock signal (XCO). At a moment defined by a request to send signal the phases of XCO and RC Ext are compared with each other and a switched clock signal SWC oscillating at a fast rate for a time interval corresponding to the phase delay between RC Ext and XCO and subsequently oscillating at a slow rate, is generated. The signal SWC is used for shifting RC Ext and terminal provided data RD Ext into shift registers respectively. The shifted RC Ext is used for controlling the adjustment of the interface PLO.
1. An interface device for synchronizing together an internally clocked modem and at least one data terminal equipment (DTE) each of said DTE being provided with a clock circuit for generating an external clock signal RC Ext, said interface including:
a phase locked oscillator (PLO) provided with a control input and generating a recovered clock signal (XCO) to be used for adjusting said modem clock;
a switched clock generating circuit connected to said PLO and provided with one of said RC Ext signals for deriving a switched clock signal representative of the phase delay between said recovered clock signal and said one RC Ext signal;
a first shift register provided with said one RC Ext signal and controlled by said switched clock signal for providing a shifted reference signal, said reference signal being applied to said PLO control input;
a second shift register connected to said at least one DTE for receiving data therefrom, and controlled by said switched clock signal for shifting said data; and
a gate connected to said second shift register and controlled by said recovered clock signal for providing in phase data to said modem.
2. An interface device according to claim 1 wherein said switched clock generator includes:
first generating means for generating a fast clock signal;
second generating means for generating a slow clock signal;
comparing the phases of said recovered clock signal and said external clock signal to derive phase delay information therefrom;
first gating means connected to said first generating means and to said comparing means for gating said fast clock signal at the output of said switched clock generator during said phase delay and following the occurrence of a modem request to send;
second gating means connected to said second generating means and to said first gating means for gating said slow clock signal at the output of said switched clock generator subsequently to said gating of said fast clock signal.
3. An interface citcuit according to claim 1 or 2 wherein said first shift register is provided with an inhibit output connected to said gate.
4. An interface circuit according to claim 1 or 2 wherein said PLO includes:
a crystal oscillator;
a frequency divider circuit the input of which is connected to said crystal oscillator and the output of which is made to provide said recovered clock signal, said divider being initially set to divide by a given factor;
a phase comparing circuit for comparing said recovered clock signal with said reference signal, and for deriving therefrom information for adding or subtracting one unit to N.
5. An interface circuit according to claim 3 wherein said PLO includes:
a crystal oscillator;
a frequency divider circuit the input of which is connected to said crystal oscillator and the output of which is made to provide said recovered clock signal, said divider being initially set to divide by a given factor;
a phase comparing circuit for comparing said recovered clock signal with said reference signal, and for deriving therefrom information for adding or subtracting one unit to N.
This invention relates to digital data transmission systems and more particularly, to a device for synchronizing a modem with external clocks.
In digital data transmission systems, sequences of bits are exchanged between terminals through a transmission channel after having usually been submitted to a so-called "modulation" operation at the input terminal, and to a so-called "demodulation" operation at the output terminal. In fact, the bits or groups of bits converted into symbols, are transmitted or "emitted" one by one, at so-called "signalling instants" which are evenly separated and defined by a transmit clock. Consequently, the transmitted wave represents data only on said signalling instants which must be accurately defined. The transmit clock is often comprised of an oscillator of the so-called "digital phase locked" type (PLO). The PLO includes a crystal oscillator which is, therefore, accurate and stable, and operates at a frequency substantially exceeding the desired clock frequency. The crystal oscillator wave goes through frequency divider stages the output of which provides a signal having the adequate clock frequency. The clock signal phase is adjusted by controlling the dividing factors of the divider stages.
Thus, the emitter or transmitter can, to a certain extent, synchronize the internal operations performed to fetch out and process the bits to be emitted which are provided by a terminal at the operating rate of said terminal. In certain cases, the actuation of the PLO does not allow the synchronization problems to be properly solved. More particularly, this is the case when the phase of the clock signal defining the data bit rate, varies too briskly. Then, other means are used like those described in the IBM Technical Disclosure Bulletin, Vol. 22, No. 10, March 1980, pages 4597-4599. The rate at which the data are provided by a terminal and the rate at which the emitter fetches them out, are matched by using so-called "elastic" buffers. In addition to the fact that additional equipment is required to ensure the above indicated buffer function, the elasticity of the registers is limited by their size and by the differences between their loading and unloading rates. It is easy to understand that under certain operating conditions, some bits can be lost, which therefore, leads to transmission errors.
Also, in up-to-date transmission systems, a single transmitter or "emitter" is connected to service data from several terminals. Although the terminals individually connected to the system are exclusively actuated one by one, the transmitter clock must be able to quickly adjust itself to any one of the terminal clock phases and frequencies to enable proper operation of the system. In certain instances, the clock of the terminal to be connected may be in opposite phase and/or at a frequency different from the one of the presently connected terminal. The emitter clock should be able to be switched from one frequency to another and, more particularly, from one phase to another. This switching should be quickly carried out to avoid losing any data.
An object of this invention is to provide an improved interface circuit ensuring a quick compensation of the phase delay between an emitter clock (internal clock) and a terminal clock (external clock) provided by a terminal to be served by said emitter while preventing data (bits) from being lost.
To meet the foregoing object and others not specifically enumerated, the data emitting system is provided with an interface having clock and data buffering circuits. Said buffering circuits comprise a phase locked clock provided for generating a recovered clock signal with which the emitter clock is to be synchronized. Said phase locked clock is controlled by a reference signal provided by a clock shift register which is loaded with said external clock signal. The content of said clock shift register is shifted at the rate of a so-called switched clock signal. The switched clock signal is generated by comparing the phase of the recovered clock signal with the phase of the external clock and by generating, starting at an initial time reference, a first signal oscillating at a given fast frequency for a fraction of the first external clock cycle following said initial time. This fraction corresponds to the phase delay between the recovered clock and external clock signals. Subsequently, a second signal oscillating at a low frequency is generated. The switched clock signal is also used to control a data shift register loaded with the data signal to be transmitted. The initial time reference is defined based on a request to send signal switching from one binary level to the other.
FIG. 1 illustrates a transmission network.
FIG. 2 is a detailed illustration of a portion of the network shown in FIG. 1.
FIGS. 3A and 3B are detailed illustrations of portions of the interfaces of circuits 34 and 36 shown in FIG. 2.
FIG. 4 shows circuit 50 of FIG. 4B.
FIG. 5 is a block diagram of the buffering device 52 of FIG. 3B.
FIG. 6 is a time diagram of the operation of the device of the invention.
FIGS. 7 and 8 represent a block diagram of the phase locked clock device of FIG. 5.
FIG. 9 is a block diagram of device 98 of FIG. 5.
FIG. 10 is a block diagram of clocks 100 and 102 of FIG. 5.
Represented in FIG. 1 is an example of a digital transmission system. A local network 10 is provided at one end of the system. Network 10 comprises a terminal 14 (DTE) connected to a modem (Modulator/Demodulator) M1. The modem M1 is made for emitting or transmitting data provided by terminal 14 and for receiving data from the line 22 and providing said received data to the terminal 14. The data exchanges between terminal 24 and modem M1 are carried out through channels 16, 18, 20. A remote network 12 is provided at the other end of the system. The network 12 comprises a modem M2 connected to modem M1 through the bidirectional transmission channel 22. In addition, modem M2 is connected through interfaces I1 and I2 to tributary modems M3 and M4 which serve other modems M5, M6, M7 connected to other terminals (not shown). Modems M1 to M7 can be any of most commonly available modems such as the IBM modems of the 3863 or 3864 or 3865 type. In addition, modem M2 serves a terminal (DTE1) through interface circuit I3.
As shown in FIG. 1, modem M2 serves several terminals (or modems). Therefore, the above indicated problem which is due to the presence of multiple inputs to a modem appears most severely at the level of modem M2. Although the figure shows a network in which the number of the elements which are directly served by modem M2 is limited to 3, namely terminal DTE1 and modems M3 and M4, it should be noted that this number (3) and the composition of said elements are not restrictive. In addition, for the invention, the difference between modems M3, M4 and terminals DTE1 has no importance. They can all be considered as terminals connected to modem M2.
FIG. 2 is a more detailed view of modem M2 and provides a better description of the invention. First of all, it should be noted that the modem is divided into two portions, namely the upper portion representing the receive devices and the lower portion representing the emit devices. Functionally, the receiver comprises three blocks 30, 32 and 34. Block 30 (SP1) performs a signal processing function on the signal received through line 22. Block 32 derives receive clock (RCO) and receive data (RDO) signals from the signal processed by SP1. Then, block 34 dispatches the data RDO towards their respective destination, namely modems M3, M4 or terminal DTE1, through fan-out device MPS and interface circuits I1, I2 or I3. MPS and interface circuits I1, I2, I3 are parts of a multiplexing/demultiplexing device MPX.
Detailed information relating to the means provided for processing the received signal and, to the means provided for deriving the receive clock signal (RCO) therefrom could be more particularly found in copending U.S. patent application Ser. No. 156,140, filed on June 3, 1980. Briefly stated, the receive clock signal (RCO) is produced in the receiver by using a PLO controlled by information derived from the received signal and processed in SP1. The same clock also controls the fetching of the data (RDO) out of the received signal. The appropriate orientation of the received information (data bits) towards to appropriate interface, is ensured by the use of an address information within the received data. On the receive end, the synchronization of the various operations to be carried out, is under the control of the received clock signal (RCO). Therefore, as far as this synchronization is concerned, there is no particular problem to be solved in order to avoid clock mismatches. Such is not the case on the emission side.
The lower portion of FIG. 2 has been shown to emphasize the distribution of the major emit functions and to enable locating the invention within its context. Modems M3 and M4 and terminal DTE1 are respectively connected to interfaces I1, I2 and I3 of a device 36 orientating the data to be transmitted towards emitter 38. Emitter 38 may be of the type used in the IBM 3863 to 3865 modems and operates in the so-called "double side band-quadrature carrier" technique (DSB-QC).
The data bits provided by terminal DTE1 and modems M3 and M4 are grouped according to predetermined rules. For instance, emitter 38 forms groups of four bits (quadbits). Each quadbit defines a data symbol ai, which is, in turn, converted into information relating to the phases and/or amplitudes of the carriers to be transmitted. Obviously, all these operations must be synchronized one with respect to the others. To ensure this synchronization, the emitter is provided with an oscillator 40 or clock of the PLO type. But terminal DTE1 and modems M3 and M4 provide data bits at their own rate, to interfaces I1, I2 and I3. In this case, modem M2 is said to operate with respect to external clocks. In order to allow the emission to be correctly performed, the bits are to be fetched out of interfaces I1 through I3 at the right times. Therefore, a phase and frequency synchronization must be ensured between PLO 40 and the external clocks while preventing data from being lost. The phase synchronization problem will more particularly be addressed here.
In the present case, this synchronization is ensured by an input interface multiplexer or Fan-In device (MPE) 42. This device acts as a buffer between the clocks of the external sources of data to be transmitted and PLO 40 so as to neutralize any effect due to the phase delays between said external clocks and PLO 40. The fan-in device 42 will provide the PLO 40 with a recovered clock signal XCO whichever the terminal in function may be. It is to be noted that only one external source provides data bits at a time. In other words, when a source provides a bit, the other sources are on stand-by. To improve this exclusive provision of bits by only one source at a time, interfaces I1, I2, I3 are connected to an excluding circuit to be described later.
FIGS. 3A and 3B are detailed illustrations of interface circuits I1, I2, I3 as well as of their corresponding circuits I'1, I'2 and I'3 which are respectively located in modems M3, M4 and terminal DTE1. All these interfaces are designed in accordance with the CCITT requirements and more particularly, with its recommendation V24. This recommendation defines connecting circuits numbered in the "100" series from 102 to 192. More particularly:
Circuit 103 V24: Transmit Data (XD): The data signal received by modem M2 and to be transmitted by said modem M2 go through this circuit.
Circuit 104 V24: Receive Data (RD): The data signals provided by modem M2 go through this circuit.
Circuit 105 V24: Request to Send (RTS): The signals on this circuit control modem M2 to set into transmit condition. Depending upon the logic level of this circuit, the modem is set to transmit condition on the data channel, or on the contrary, no transmit condition.
Circuit 106 V24: Ready for Sending (RFS): The signals on this circuit indicate whether modem M2 is ready to operate or not. One of the logic conditions of this circuit indicates that the modem is connected to the transmission line and that it is ready to exchange other control signals with the device (M2, M3 or DTE1) in order in initiate the data exchange.
Circuit 108/2 V24: Data Terminal Ready (DTR): The signals on this circuit control switching of modem M2 in order to connect it to the line or to disconnect it. The terminal (or tributary modem) can present a given logic level onto circuit 108/2 each time it is ready to emit or receive data.
Circuit 109 V24: Data Channel Received Line Signal Detector: Also called "carrier detection" (CD).
Circuit 113 V24: Transmitter Signal Element Timing (XC): The signals on this circuit provide to the modem, the time base (external clock) for the signal elements.
NOTE: It is the external clock whose synchronization is to be ensured as accurately as possible with clock (PLO) 40 (or conversely).
Circuit 115 V24: Receiver Signal Element Timing (RC).
The abbreviations for the above-described circuits are shown on FIGS. 3A and 3B and are provided with an index defined in accordance with their location. Index "0" is used for modem M2. Index "1" for interfaces I1 and I'1, index "2" for interfaces I2 and I'2, index "3" for interfaces I3 and I'3. The circuits themselves are well known from the CCITT reference.
FIG. 3A illustrates the connections at the receive end of modem M2, (the upper portion of FIG. 2). It appears that the fan-out device MPS is reduced to its simplest expression. Its purpose is to connect circuits RDO (104), RCO (115), CDO (109), RFSO (106) and DSRO (107) directly to interfaces (I1, I'1) (I2, I'2) and (I3, I'3). Therefore, MPS applies the time base signal RCO (clock) extracted from the data by device 32, to the interfaces and from there, to modems M3, M4 and to terminal DTE1. The device MPS also dispatches the received data RDO to the group of interfaces. The identification of the specific terminal to be really provided with the data, will be performed by said terminal identifying itself from an address information within the received data.
FIG. 3B illustrates the circuits interconnecting the interfaces with the transmit portion of modem M2. It should be remembered that for the sake of the invention, modems M3 and M4 can be considered as terminals. As indicated above, the interconnections are more difficult to be established in this case. The input interface multiplexer (fan-in) device MPE is more sophisticated than the device MPS since it is necessary to synchronize the extractions of the data to be emitted, i.e., to ensure more particularly the reciprocal synchronizations of the clock signals in use, namely the so-called "external" clocks of modems M3, M4 and terminal DTE1 and to provide a single signal as stable as possible to clock 40 for an easy synchronization thereof.
As soon as one of the interfaces I1, I2 or I3 is functioning, it is necessary to exclude the two other ones. This is ensured by an excluding circuit 50. This excluding circuit provides external clock (RC Ext) and data (RD Ext) information which are in fact, the clock and data signals provided by the interface I1, I2 or I3 to be served by emitter 38 after the exclusion of the two other interfaces. A data and clock buffering device 52 connecting the excluding circuit 50 to emitter 38, ensures the appropriate phasing of the data (DXO) provided to emitter 38 and provides a recovered clock information (XCO). Information XCO is provided to ensure an appropriate time synchronization of the data to be emitted. The clock of emitter 40 must be synchronized with XCO. Therefore, XCO should be as stable in phase and frequency as possible, whatever RC Ext may be.
FIG. 4 shows an embodiment of excluding circuit 50. Signal CD1, CD2 and RTS3 (the bar above the signal reference indicates that the referenced signal is an inverse logic signal) of interface I1, I2 and I3 and applied to the input of a NAND logic circuit 52. The output of circuit 54 is used to trigger three latches 56, 58 and 60 respectively delivering signals α, β, γ and their complements (inverses) α, β, γ. The set inputs of latches 56, 58 and 60 are respectively connected to the outputs of NAND logic circuits 62, 64 and 66. The inputs of circuits 62 receive signals β, γ, CD1, CD2 and RTS3. Circuit 64 receives α, γ, CD2, CD1 and RTS3. And circuit 66 receives α, β, RTS3, CD1 and CD2. OR logic circuit 68 receives signals α, β and γ and provides information RTSO=α+β+γ which informs the emitter 38 of the request to send expressed by one of modems M3 or M4 or by terminal DTE1, to modem M2. External clock signals RC1, RC2, RC3 provided by interfaces I'1, I'2 and I'3 (through circuits XC1, XC2 and XC3 of interfaces I1, I2 and I3) are respectively applied to one of the inputs of a NAND circuit 70, 72 or 74. Another input of circuits 70, 72 and 74 also respectively receive signals α, β and γ. OR circuit 76 the input of which are connected to the outputs of circuits 70, 72 and 74, outputs so-called "external clock" information RC Ext issued from the one of terminals M3, M4 or DTE1 which has been chosen to be served by emitter 38 of modem M2. In fact, this chosen terminal is, at a given instant, the first terminal which provided a request to send and thus, has excluded all the other terminals. Data RD1, RD2 and RD3 provided by interface I'1, I'2 and I'3 (through circuits XD1, XD2 and XD3 of interfaces I1, I2 and I3) are respectively applied to the inputs of NAND circuits 78, 80 and 82. Another input of these NAND circuits respectively receives signals α, β and γ. The outputs of circuits 78, 80 and 82 are connected to the inputs of NAND circuit 84. The output of circuit 84 provides signals RD Ext representing the data to be emitted and provided by one of terminals M3, M4 or DTE1.
Clock signals RC Ext are the signals to be processed in order to apply a signal relatively stable and consistent in phase and frequency to oscillator PLO 40, this operation being to be carried out without any disturbance of the transmission of data RD Ext to be sent to emitter 38. The frequency adjustments are relatively simple. Signal RC Ext must be at the same frequency as clock 40 of emitter 38 of modem M2. Adequate crystal controlled clocks are conventionally used within the transmission network.
The phase adjustments which are the most critical, are carried out by using the device schematically shown in FIG. 5. This device is part of the clock and data buffering circuit 52. The circuit 52 comprises a conventional PLO clock, i.e., mainly including a crystal oscillator 90 connected to a frequency divider circuit 92. The output of divider 92 from which the recovered clock signal XCO is to be picked up, is connected to one of the inputs of a phase comparing circuit 94. Compare circuit 94 is provided with two outputs connected to the (+) and (-) inputs of divider 92. The purpose of circuit 90, 92, 94 is to track signal XCO.
The external clock signal RC Ext is applied to one of the inputs of switched clock generating circuit 98. Another input of circuit 98 is connected to receive the recovered clock information XCO. Three other signals, namely a fast clock signal (FC), a slow clock signal (SC) and a time reference signal (RTSO) provided through the excluding circuit 50, are also applied to the input of circuit 98. Circuit 98 provides a switched clock signal (SWC) which is used to control the shifting of shift registers 100 and 102. The first one of these shift registers which is labelled SCR, acts as a clock shift register. Its input is connected to receive the signal RC Ext and its output (X) is connected to the second input (also called "control" or "reference" input) of phase comparator 94. Therefore, signal X represents a shifted clock signal reference. The data input of the second shift register which is labelled SRD, is connected to receive data RD Ext provided by the terminal and to be transmitted by the modem M2. Said second register acts as a data shift register. The output of shift register SRD 102 drives a latch or gate 104 also controlled by the recovered clock signal XCO (and by a so-called "INH" inhibit signal provided by the next to last stage of register SRC). The PLO (90, 92, 94) includes a crystal oscillator 90 adjusted to a frequency equal to 96 Fb with Fb being the frequency of the emitter clock 40. The clock signal 96 Fb is divided in divide circuit 92 by a factor of N�1, with N=3. When comparator 94 applies a signal to the (+) input of divider 92, said divider 92 divides the frequency of the signal oscillating at 96 Fb, by a factor equal to 97. When the signal of comparator 94 is applied to the (-) input of divider 92, the frequency of the signal at 96 Fb is divided by 95. When neither of the comparator 94 outputs is energized, circuit 92 divided the frequency of the signal provided by crystal oscillator 90, by a factor equal to 96.
FIG. 6 is a time diagram of the operations performed by the device of FIG. 5. The first three lines represent the signals at frequencies 8Fb, 4Fb, 2Fb and Fb=XCO. These signals are derived from the signal at 96FB provided by crystal oscillator 90. The fifth line of the diagram represents external clock signal RC Ext. The sixth line represents a signal Δ indicating the phase delay between the first leading edge of RC Ext and the first leading edge of signal XCO shown on line 4 of the diagram. In the present case, the "first leading edge" means the first leading edge following the occurrence of a request to send, i.e., passage of RSTO from the low logic level to the high logic level (see the next line of the diagram).
Signal Δ is generated only when a leading edge of signal RSTO appears. When the signal Δ is high and starting with a leading edge of fast frequency clock signal FC=8Fb, the signal SWC (represented on the eighth line of the diagram) varies at same frequency FC. For the remaining time, i.e., when Δ is low, signal SWC varies at slow frequency SC. It should be noted that on the diagram of FIG. 6, FC=8Fb and SC=2Fb. These limits have been chosen only to simplify the time diagrams. In practice FC has been equal to 16Fb, said signal at 16Fb being itself obtained from a signal FC' at 32Fb.
The next three lines of the diagram are respectively referenced SRC1, SRC2 and SRC3. The signals illustrated on these lines show the evolution of the contents of shift register SRC for three successive shifts. This register is loaded with signal RC Ext and its contents is shifted under the control of the trailing edges of switched clock signal SWC.
Line 12 shows data bits A, B, C, etc., which are applied to the input of register SRD. These data bits are applied to the input of register SRD in phase with external clock signal RC Ext. The phase of the same data bits is originally independent of the phase of recovered clock signal XCO. But, as shown by the signals on the diagram lines referenced SRD1, SRD2 and SRD3, the data, i.e., the level values, at the input of register SRD at switched clock instants SWC, are shifted by this switched clock signal. The shifts are performed on the leading edges of signal SWC. In practice, registers SRC and SRD have been chosen with sixteen stages and not three. As shown by the signal of diagram line SRD3, bit A the phase of which is to be adjusted, is extended with respect to bits B, C, D, etc. Then, the so-called "gate inhibit" signal referenced INH, is used for appropriately truncating bit A to the same length as the others to cause it to appear in phase with the recovered clock signal. This is shown by diagram line XDO representing the in-phase data to be submitted to emitter 38. Therefore, SDO represents the data bit train to be submitted to emitter 38.
A more particular embodiment of the various elements comprising the clock and data buffering device shown on FIG. 5 will be described in the following.
FIG. 7 illustrates the control elements of the feedback loop of the PLO provided in the buffer device shown on FIG. 5. More particularly, it is a description of the circuits belonging to devices 92 and 94 in which the frequency of the signal at 96Fb provided by crystal oscillator 90 is divided by N'=3, N'-1=2 or N'+1=4. The adjustment to the frequency (96�1) Fb is ensured through the use of a second divider (not shown) included in circuit 92 and mounted in series with the circuit of FIG. 7. The recovered clock signal XCO provided by divider 92 is applied to input J of a latch 106 of the J-K type. The reference signal X appearing at the output of shift register SRC is applied to the input of a first invert circuit 107 followed by a second invert circuit 108. The output of invert circuit 108 is applied to input C of J-K latch 106. It should be noted that the wire leading to input C of J-K latch 106 is referenced N. This means that said J-K latch reads the level of the signal applied to input J when the signal applied to input C is on a negative going edge (negative slope). The substitution of P for N would thus mean that the positive slope of the signal applied to input C, is taken into consideration. The normal output of latch 106 is applied to input J of another J-K latch 110. The normal output of latch 110 is fed back to input K of the same latch. The normal output signal of latch 110 is referenced δ. Input C of latch 110 receives signal T1 which will be described later. Latch 106 is latched by the application of inverse output (Q) of latch 110 thereto until a new negative going edge of signal XCO appears. Same output Q of latch 110 is applied to one of the inputs of a NAND logic circuit 112 provided with two other inputs receiving signals T1 and T2 (to be described later).
The signal at 96Fb provided by crystal oscillator 90, is applied to the inputs of two flip-flop 114 and 116 mounted in cascade. The normal output of flip-flop 114 provides signal T1. The outputs of latch 114 are connected to the inputs of latch 116 which provides signal T1, the inverse of which (T2) is applied to frequency dividing circuit 94. The outputs of latch 116 are applied to the input of latch 114. The output of NAND circuit 112 controls flip flop 114.
Signals T1 and T2 are applied to the inputs of NAND circuit 118 a third input of which receives signal ε. The output of NAND circuit 118 controls latch 114.
Signal A taken from the output of invert circuit 107, is applied to input C of J-K latch 120 in FIG. 7. Input J of latch 120 receives the recovered clock signal XCO. The normal output of latch 120 is connected to the input of J-K latch 122. The normal output of latch 122 provides signal ε which is applied to its own input K. The inverted output of latch 122 controls the latching of J-K latch 120.
A signal at 96Fb provided by crystal oscillator 90 is applied to one of the inputs of NAND circuit 124 which is provided with a second input receiving signal T1. The output of NAND circuit 124 is inverted in 126 and the applied to input C of J-K latch 122.
Signal RTSO is used to latch J-K latches 110 and 122.
The circuit comprising elements 106, 107, 108 and 110 can be considered as used to define and indicate the lagging delay separating recovered clock signal XCO and reference signal X. The circuit comprising 120, 124 and 226 defines and indicates the leading delay between clock XCO and reference signal X.
Circuits 112, 114, 116 and 118 divided the signal at 96Fb provided by crystal oscillator 90, by 2, 3 or 4. Three states are defined, namely: a stationary state, a delayed state and an advanced state. In the stationary state obtained when δ=1 and ε=0 or δ=0 and ε=1, the dividing factor obtained is 3. The delay state corresponding to δ=ε=0 involves a division by 4. And the advance state corresponding to δ=ε=1 involves a division by 2.
FIG. 8 shows an illustration of the device carrying out the frequency divisions as well as the diagrams of the signals T1 and T2. The operation consisting in switching from a dividing factor of 3 to a factor of 2 or 4 is performed only once per period 1/Fb. The dividing factor is brought back to "3" as soon as output Q of latch 110 goes to logic level one.
Output T2 of latch 116 drives a dividing circuit (not shown) dividing frequencies by a factor of 32. Therefore, the set of operations performed by circuits 92 and 94 consist in adding or subtracting "1" to or from factor N once per period 1/Fb until the shifted clock signal X becomes in phase with XCO.
FIG. 9 illustrates a particular embodiment of the switched clock generating circuit 98 providing the switched clock signal SWC. This figure also shows a diagram of the signals involved during the operation of circuit 98.
The external clock signal is applied to the input of a latch 128 whose inverted output (Q) is applied to the input of a NOR circuit 130. The output of circuit 130 is applied to the input of a latch 132. The recovered clock signal XCO is also applied to circuit 132. The inverted output of latch 132 is fed back to the input of circuit 130 and to one of the inputs of a NAND circuit 134. A second input of circuit 134 receives signal RTSO from excluding circuit 50. Signal RTSO is also applied to latch 132. The output of circuit 134 receives signal RTSO from excluding circuit 50. Signal RTSO is also applied to latch 132. The output of circuit 134 is inverted through 136 and applied to latch 128. Assembly 128 to 136 acts as a circuit comparing the phases of XCO and RC Ext.
The normal output of latch 128 is supplied to the input of a NAND circuit 138. The output of circuit 138 is applied to the input of a latch 140 controlled by signal FC' at 32Fb. The normal output of latch 140 is applied to the input of NAND circuit 138. Inverted output (Q) of latch 140 delivers a signal at 16Fb which is applied to one of the inputs of a NAND circuit 142 a second input of which is connected to the output of a NAND circuit 144. The inputs of NAND circuit 144 receive SC at 2Fb and the signal issued from normal output (Q) of latch 132. Switched clock signal SWC is obtained at the output of circuit 142. Therefore, assembly 142-144 acts as a gate.
The lower portion of FIG. 9 illustrates the diagram of the signals obtained through the use of the circuits shown in the upper portion of said FIG. 9. The first line represents signal RC Ext. The second line represents FF1, XCO, FF2 and FF3. Signals FF1, FF2 and FF3 are respectively delivered by latches 128, 132 and 140.
The appearance of a leading edge on RC Ext causes latch FF1 to be triggered and normal output (Q) thereof goes to the high level. When signal XCO goes high, RTSO being high, latch FF2 goes high. The level of the output of inverter 136 goes low and causes FF1 to go back to the low level. Therefore, the signal obtained at normal output (Q) of latch 128 comprises a pulse the duration of which corresponds to the phase delay between external clock signal RC Ext and recovered clock signal XCO. (Therefore, latch 128 measures the phase delay referenced Δ on FIG. 6. When Δ is high, gate 138 is open. On each positive going edge of signal FC', latch 220 reads the logic level applied to its input D and reproduces this level at normal output (Q). The gate 138 and latch 140 assembly consists, therefore, in a frequency divider by two, operating only during interval Δ=1. Then, signal FF3=FC is obtained at 16Fb on inverted output (Q) of latch 140.
Normal output (Q) of latch 132 controls the opening of a gate 144 the input of which receives signal SC at 2Fb. Inverted signal SC is transmitted as an output from gate 144. A circuit 142 ensuring a NAND function on the signals issued from circuits 140 and 144, outputs signal SWC, i.e., a signal oscillating either at FC=16Fb (fast clock) or at SC=2Fb (slow clock).
Signal RTSO controls the locking of latch 132. To cause circuit 128, 130, 132 to restart an operating cycle, RTSO must go through a positive going edge. This means that the excluding circuit must stop serving the currently served terminal and then, be switched to the first terminal raising RTS.
FIG. 10 shows an embodiment of the portion of the data and clock buffering circuit shown in FIG. 5, which mainly includes the two shift registers SRC and SRD and latch 104 acting as a gate. On FIG. 10, each shift register SRC and SRD is represented by two registers mounted in series. This is only due to the fact that 8-bit modules (Texas Instrument and referenced 74LS164), have been used. As also indicated about FIG. 5, the inputs of registers SRC and SRD respectively receive signals RC Ext and RD Ext. These signals are sampled at the rate of appearance of the positive going edge of signal SWC.
Output Qn of register SRC delivers the shifted clock reference signal X provided for phase comparator 94. The output of register SRD goes through gate 104 the opening of which is controlled by the positive-going edges of signal XCO. In addition, the output of penultimate stage Qn-1 of shift register SRC goes through inverter 146, then through latch 148 and provides the "inhibit" information INH which inhibits the opening of gate 104 so as to truncate to the appropriate length, the first data bit introduced into register SRD after the passage of RTSO from the "0" level to the "1" level. In other words, the first bit introduced into register SRD during the adjustment period of clock XCO is truncated, as required, to the same length as the bits which are normally received.
In addition, signal XCO goes through a circuit applying a delay of 16 bit-times to signal RTSO. This circuit includes a NAND circuit 150 in series with an inverter 152 and a binary counter 154. The output of binary counter 154 (referenced RTSO') is used to unload registers SRC and SRD after the return of signal RTSO to the low level.
As it could be noted from the above description in the system of the invention, it does not make any difference what the exact origin of external clock signal XCO may be. Whether said signal is issued from a modem (M3, M4) or from a terminal (DTE1), has no importance for the invention. Therefore, in all cases the element providing the external clock signal can be considered as a terminal.
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Ruth Elaine Schram Mixed Choir Music: 2 items found
Advent Peace Canon
Composed by Johann Pachelbel (Canon in D). Arranged by Ruth Elaine Schram. Choir Sacred. For Opt. Flute or Other C-Instrument (SATB choir). Choral (Sacred); Choral Octavo; Masterworks; Worship Resources. Alfred Archive Edition. Advent; Baroque; Christmas; Masterwork Arrangement; Sacred; Winter. Grade 3. Choral Octavo. 12 pages. Published by Alfred Music (AP.BSCM04009)
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Be Born in Us
Composed by David S. Gaines. Arranged by Ruth Elaine Schram. For SATB choir. Sacred Anthem, Advent. Octavo. Published by Exaltation Publications (LO.10-3015L)
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You are currently browsing comments. If you would like to return to the full story, you can read the full entry here: "Why Own Guns?".
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0 thoughts on "Why Own Guns?"
Why Own Guns?
1. A cop is too heavy to carry around for protection, and really difficult to conceal.
2. A cop eats, sleeps, rests, takes a day off — Guns don't
3. When seconds count, the police are ONLY minutes away.
4. Because it is MY RIGHT to do so!
I'll give up my gun when they pry my cold, dead fingers from around it!


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Environmental Issues: Health
Health Main Page
All Documents in Health Tagged environmental threats
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Trooper rescues flood-stranded farmer in Lac qui Parle County
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Posted 16 February 2013 - 22:36
Posted 16 February 2013 - 22:44
So I guess its open Go install, the closed was a load of fun, only complaint was the length of the tracks, bit too short, but the driving was good fun
Posted 16 February 2013 - 22:58
I was actually thinking about trying it when it popped up on steam. But after reading the blerb it suggested that it came with the bare bones of a game with the option to buy in game cars and tracks. So I didn't bother and went back to playing Dirt Showdown lol.
Let us know how it plays and what you actually get for free.
Posted 16 February 2013 - 23:27
Hmm, not sure about trying this now, after all its a 10gig download...


text:
Teleportation — Fact and Fiction 348
from the there-and-back-again dept.
We've improved Slashdot's video section; now you can view our video interviews, product close-ups and site visits with all the usual Slashdot options to comment, share, etc. No more walled garden! It's a work in progress -- we hope you'll check it out (Learn more about the recent updates).
I'm just assuming that everyone here knows this already, but for the one or two of you who don't know, the Heisenberg Compensator is the part of the ST transporter that deals with the pesky quantum issue of not being able to pin down the exact location of the subatomic particles whizzing around in Picard's body.
Of course it's physically impossible to make such a compensation, and when one of the technical guys on the show's staff (Okuda?) was asked how the Heisenberg Compensator worked, he replied, "Very well, thank you."
Hayden is Star Wars, not Star Trek. That's why he doesn't know it.
To err is human -- to blame it on a computer is even more so.


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Search the Delaware Valley College site:
Follow this link to E-Sign Online to proceed.
Delaware Valley College is rated one of the best colleges in the Northeast.
Get Directions
Helping students prepare for the Spring Job and Internship FairPosted on March 25, 2015 by Maggie Villari '13 (B.A.), '15 (M.A.).
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The ramblings & obsessions of a fisherman's wife! ~ a potpourri of history, genealogy and books. Also some general ramblings if they take my fancy!
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Wednesday, 13 July 2011
Wordless Wednesday - Identity Crisis!
About 20 years ago I was given this photograph, complete with frame by the Uncle of my Cousin. The gentleman in question, Fred Boxall of Compton Surrey England is now deceased. Over time the identity of the lady in the photograph has been lost. It is likely to be either Fred's wife, whose maiden name was SPICER or Fred's sister.
Do you recognise this lady?
Posted by Julie Goucher at 10:09 am
Labels: Boxall, Spicer, Wordless Wednesday
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New Bike & Gear Previews
Road Bike Wheels Preview
Easton Unveils 2014 Road Bike Wheels
Easton Echo and V5 Hubs
3 / 9
The Echo hubs found on every wheel with "90" in the model name, use double butted, straight pull spokes. Straight pull spokes, advocates say, are more durable because they don't have a bent elbow, which can be a fatigue failure point. Stainless steel reinforces the spoke flanges, allowing for a lighter configuration, the company claims.
70-series wheels get Easton's new V5 hub. It's a rather ordinary hub for traditional J-bend spokes, though Easton claims they were able to push the load bearings out further than they are on most other hubs, although not as far as the Echo's.
All 2014 Easton wheels will be sold with a Shimano/SRAM 9/10/11-speed compatible driver body. The tifosi will need to purchase a Campy driver body separately. Easton also redesigned their quick releases, which now feature an internal cam and chrome-plated steel rod.


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Water levels at Lake Mead are expected to drop up to 25 feet over the next year after federal officials announced Friday a record-low annual release of water from an upstream reservoir.
More water being choked off from drought-stricken Lake Mead
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THE Netflix of #BLACKBUSINESS #URBANEVENTS PROMOTIONS. Create a Profile at WWW.BLACKFOLKHOTSPOTS.COM for us to start promoting your business.
50 Cent is one of the richest hip hop performers, having an estimated net worth of over $440 million, Rags to Riches In 2007, Jackson was the second wealthiest performer in the rap industry, behind Jay-Z.[105] He resides in Farmington, Connecticut, in the former mansion of ex-boxer Mike Tyson.[106] He is consistently ranked among the richest figures in the American hip hop scene. In 2011, Jackson was ranked the fifth richest figure in American hip hop with a net worth estimated at $100 million.[107]
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Why The Russos Are The Best Thing to Happen to the MCU Since Joss Whedon
TV, Comic Books
Comic Books
Shelf Life
The Buy Pile
In Your Face Jam
The Mission
Spinoff Online
Robot 6
Spinoff Online
Spinoff Online
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Milltown, NJ
No, it' s not an INXS tribute.
It's a "guns blazing, white-knuckled, preternatural joy ride to hell and back," according to its creators Dennis Calero (Solar Man of the Atom, X-Men: Noir) and actor Todd Staswick (Heroes, The Riches). Devil Inside is a new online strip that follows an arcane drifter named Jack Springheel (Springheel Jack, get it??) who's on the run with a bounty on his head. Sara Lima at ComicVine did an interview with them about the series in July.
Devil Inside is 28 pages into its run, and Calero and Staswick post up a new installment each week on Staswick's website.
Home | News | Columns | Reviews | Video | Blogs | Forums | Find A Comic Shop
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Wando Woods is a populated place LOCATED WITHIN the City of North Charleston. In turn, the City of North Charleston is located within Charleston County.
Wando Woods is located at latitude 32.852 and longitude -80.036. The elevation of Wando Woods is 26 feet above mean sea level.
Since Wando Woods is located within the City of North Charleston, all of the census and demographic data for residents of Wando Woods are included as part of the information reported for City of North Charleston in the "Data" tab above.
In similar fashion, ALL OF THE NAVIGATION TABS ABOVE ARE FOR THE City of North Charleston Community Profile.
Charleston County: Cities & Towns | ZIP Codes | Schools | Features (airports, churches, hospitals, etc.)
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Data Source - USGS GNIS FID: 1231892
BOUNDARY MAPS: City of North Charleston | North Charleston Division | Charleston County


text:
Google: Teach Girls Coding, Get $2,500; Teach Boys, Get $0 673
from the got-enough-of-the-other-kind-already dept.
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So lets have some discrimination of boys to fix it!
Makes perfect sense.
A geeky guy suddenly find himself out of a jahb - victim of downsizing, outsourcing, H1B1-jeebies etc etc - and thinks up a plan to take advantage of this new program by dressing up as a woman and teaching inner-city girls all about the ins-and-outs of programming, and in the process learns a little bit about something called life.
"He taught them how to code, but they taught him how to live."
From the producers of Mrs Doubtfire and I Spit on Your Grave, this summer Paramount Pictures brings you a feel-good, down-on-your-luck, rags-to-riches, local-boy-make-good, shaggy-dog, fish-out-of-water, girl-meets-boy, boy-turns-into-girl story.
Michael Cera in Class Act.
So if you are a white straight male, or in some cases a male period, you are not a "protected class"
Think of the male periods!
Unless you visit your local shaman for healthcare, there is probably quite a bit of technology involved.
*Rivenaleem puts on his flame-resistant clothing*
I just saw it as compensation for having to teach girls anything.
If I chose to go to a strip club, I would feel appropriate tipping the (female) dancers but not the (male) bouncers with my privately owned dollars.
No, man, you have to get a random dance from either a dude or a lady. And they have to be a random age and weight. No discrimination allowed
Computers can figure out all kinds of problems, except the things in the world that just don't add up.


text:
Launcher Update
Get the Desktop App for Battle.net Now
- All your games in 1 place
- Log in once
- Automatic game updates
Community Manager
Posts: 1,247
I just want to remind everyone that we continue to closely monitor the change we implemented to league boundaries on the ladder with Patch 2.1. We've seen continued progress toward our intended league sizes, although the system is still subject to further adjustment if necessary.
We've followed your feedback on this issue very closely throughout this process, and we greatly appreciate your understanding as we get closer to our goal for the shape of the leagues. Please don't hesitate to let us know how it's going for you on the ladder.
You have our thanks!
PatchGoGoGo #944
Posts: 5,192
Thanks for the promotion, Love the work your doing blizzard ! ♥
Manipulation #777
Posts: 429
I feel the leagues are either easier now or im just better then i thought lol. i felt i was plat level not diamond tho haha
Inter-league automated tournaments to give large bonus' to MMR, sort of like bonus xp weekends or w/e but with skill being the deciding factor, rather than playing more/less on ladder.
"I'm high plat"
"I'm low plat but have a top 5 plat tournament finish"
Creates more equality between players and a more definitive view of a player's relative skill and improvement. Promotions are a good milestone of achievement, but is far too static to be motivating more than when it is imminent.
punchingbag #651
Posts: 1
Thanks David Kim!
KimDaeKyung #672
Posts: 65
I'd like to just say something...
I started Starcraft, learning about leagues.
My most anticipated goal was reaching "Top 2% Masters".
Although before all the problems, it was easy to reach that, as I assume it was more than 2%,
I think being "Top 2% " should be more special. It was hard to actually find masters with the problem, which seemed like God to all the others.
However, I hope the fix fixed :)
Well It's nice to see I'm not in Gold anymore, but It took a dozen games while hanging around top 8 Gold to promote me to Platinum finally x.x and it's good to see I'm fighting Plat/Diamond opponents. Will update you further on the next update but I do agree the system needs a tweak and I think Demotions need to come back in.
heyilikethis #590
Posts: 19
Thank u guys for real this issue was really bumming me out sc2 is easily top 2 or 3 favorite games and i havnt felt any kind of fun or competition rather in some time do to league issues and mostly stopped playing altogether thank u for communicating and taking steps to ensure a better play experience for all =D see u all on the ladder
28-8 in random 2s. FOREVER DIAMOND auuuuuuuuuuuuuuughh!=
I just hope there's no more of this bull nonsense decay. I literally spent the previous ladder season just repromoting all my leagues to masters. And that took somewhere around 300 games total. It was extremely exhausting.
I don't understand why the ladder needs to be adjusted. Don't you only need so many points to be in a certain ranking? Is there some sort of anomaly where players keep losing to others and falling into a certain league with no espcape?
HardBounce #429
Posts: 13
Great work on the leagues! Nothing is perfect but happy to see you guys are open to change and feedback (even though most the feedback is rude and unhelpful)
Things are definitely better then what they were, and thanks for the updates and posts.
Threats of violence. We take these seriously and will alert the proper authorities.
Posts containing personal information about other players. This includes physical addresses, e-mail addresses, phone numbers, and inappropriate photos and/or videos.
Harassing or discriminatory language. This will not be tolerated.


text:
Dr. Laurie Marker
2012 Year-end Report
2012 detailed annual progress report
Goodbye to Chewbaaka
Photo courtesy of Frans Lanting. (c) Frans Lanting. My dear friends, With the deepest sorrow, we said … Read more »
Update from Dr. Laurie Marker
Hello! We are having intermittent email reception due to satellite issues, but thought I'd send a quick … Read more »
The Cheetah: A Race for Survival
Dr. Laurie Marker lectures at the Library of Congress
2011 Year-end Report
2011 detailed annual progress report
2010 Tyler Prize Laureate Lecture Pt. 1
Dr. Laurie Marker, Tyler Prize winner, lectures at USC Davidson
2010 Tyler Prize Laureate Laurie Marker Pt. 2
Dr. Laurie Marker, Tyler Prize winner, lectures at USC Davidson
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"Missing Link" is vintage Frank Herbert. It tells the story of Lewis Orne, junior I-A field man, on the planet Gienah III. He is there to investigate a ...read more »
"Old Rambling House" is a short story by science fiction author Frank Herbert which first appeared in Galaxy magazine in 1958 and later in Herbert's 198...read more »
It's hard to ferret out a gang of fanatics; it would, obviously, be even harder to spot a genetic line of dedicated men. But the problem Orne had was on...read more »


text:
Nice song,
Verified Purchase(What is this?)
This review is from: Let Her Down Easy (Album Version) (MP3 Download)
I'd never heard of this song until I heard that George Michael was doing a cover version of it, from his 'Symphonica' album, due for release soon. A good song with good lyrics, not as well known as his bigger hits, ie. 'Sign Your Name' etc but a likeable track. Trent D'Arby was quite big for a time but then went out of the spotlight. This track disappeared with him it seems.
Review Details
(2 customer reviews)
Top Reviewer Ranking: 282,434


text: 500 pts Astonishing Facts About Famous Companies <JAMZ MVP According to this article, Ben & Jerry's almost sold what food? Click here for the answer. Sign in to Play With Us! Category: Trivia Visit our sponsor: Click here for the answer. Share on Facebook Share on Twitter More Leave a comment Send to a friend! Print this page Pin it! Reddit This! Share on Tumblr! More Ways To Get and Use Points Win a Trip to Moody GardensWin $2,500 Cash!Win a ChromebookWin a $100 Visa Gift CardWin a $500 Apple Gift CardWin a ZVOX SoundBase 670 Home Theater Sound System


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Why would anyone still use ISP email for anything these days considering there are better alternatives (free or very cheap)?
. . . and Fastmail now has been bought by Opera....
Generally that's true. But FWIW I've not experienced it in FM's case.
When a small upstart is bought by a larger and more established company (which Opera is by now) things usually suffer.


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I've boarded many safari vehicles to venture off into places filled with the sights and sounds of Africa. But this ride was different. The further we drove, the less there was to see, the more there was to feel… The enormity of silence, solitude and serenity was captivating. To stand at the edge of the earth where in every direction the world laid the hope of infinite possibility gently at your feet…
That is the magic of the sun setting on Namibia's Skeleton Coast.
Shot handheld using:
Canon EOS 40D
Canon EF28-135 f/3.5-5.6L IS USM lens
Featured by the groups
The Woman Photographer April 7 2011
The World As We See It Or as we missed it January 22 2013
The World As We See It Or as we missed it 2nd Runner-up Photo Of The Week January 27 2013
Afrikaans April 18 2013
Top Ten Challenge Winner
The World As We See It Or as we missed it Travel Scenes January 2013
The World As We See It Or as we missed it Vehicles December 2013
Oh my… such a wonderful honor! THANK YOU so very much! ;-)
– Owed to Nature
Love the angle you shot this at
This was a moment, a place, an experience like no other… so personally meaningful. Tried several angles, trying to catch something of the emotion I felt. So, wow, I'm thrilled to hear your comments! Thank you very much John!
– Owed to Nature
A very nice pic. great composition. sometimes we need to try different camera angles to get the best of it haha. its tough sometimes. but this is well taken. :)
Now that is a problem I like to have… needing to go in every direction, trying every vantage point, then having to choose which wonderful sight I like best… If only all problems were that tough! ;-)
Thank you Azmi for your wonderful comments.
– Owed to Nature
Thank you Derek! And for my part, I always enjoy… ;-)
– Owed to Nature
Wonderful info…you should write a book!! Lovely pic!
Oh Elizabeth, aren't you SO very nice! I'm not much for writing but with the right subject… and Africa inspires me to no end… some images write themselves. ;-) Thank you for your wonderful words and this huge smile I know have on my face!!! …Sylvia
– Owed to Nature
Great image !
Thank you very much Trish! …Sylvia
– Owed to Nature
So Many Thanks and Heartfelt Appreciation for your support and Feature!
– Owed to Nature
Thanks so much Tony
– Owed to Nature
Excellent work… Congratulations 2nd Runner-Up!
Editors Weekly Choice Ending January 27th, 2013
The World As We See It , or as we missed it.Group
Oh Evita, your support is so generous, kind and appreciated… Thank you so very much! …Sylvia
– Owed to Nature
MANY Thanks for your support and comments!
– Owed to Nature


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One phone call and life changes: "Lael, this is Mom. They've called in hospice for Dad."
In Nigeria, families await answers about their kidnapped girls. Daughters, sisters, cousins, friends have been kidnapped by terrorist groups and reportedly being sold to men as wives for $12. They were in school, they were kidnapped and have been treated as property. Their families have not seen their faces, touched their hands or heard their laughter in days. (For a link to an AP article, click here.)
It's less than two weeks away—Mother's Day, which, like all holidays, can be difficult for lots of people. Those who have lost or are estranged from parents or children feel pain on the day set aside for honoring mothers. Included in that group of mourners are the infertile. For them the day serves as a reminder of the gift they long to have but that continually evades them.
The subject of infertility is surrounded by many myths. So let's put some of them to rest.
Myth: Infertility and sterility are the same thing.
Recently, my students, future ministers, gave oral reports on ministries they visited and evaluated. For the first time, I heard several of them use the word "organic" as an adjective to describe healthy ministries, and lacking "organic" as a negative. What is organic ministry anyway and why are so many of my students drawn to it?
His dark shadow looms in the distance—heart pounding with trepidation and grief. He saw in the sacred pages that something like this would happen. So he made the proper plans. Now he must step from the shadows, stand, and speak.
His simple but significant act is recorded in all four of the gospels. Yet somehow we often overlook him during Passion Week.
The day after Easter, our beloved Golden Retriever Calvin, only seven years old (that's mid-life in dog years) had to be put to sleep because of cancer that had been sucking the life out of him. When our son and his wife moved from Texas to California, they were forced to leave him behind because their housing does not allow dogs, and Calvin became my husband's dog.
A friend of mine recently told me of the change in her work environment that happened with the addition of one female co-worker. Just one. Female. Assistant. What was once a team-oriented, respect-and-support-each-other work climate went toxic—because of the influence of one woman. Ms. Toxic's continual gossiping about the other women and backbiting created "toxic shock" in a matter of 3-4 weeks! How does that happen?
My earliest memories of Easter include new church dresses with hats and lots of yellow ribbons, intense searches for plastic eggs with the rare $2 bill stuffed inside, marshmallow peeps (which I never liked) and loads of Cadbury chocolate, complete with the resulting stomach-ache. The day came and went with a little bit of anticipation, but nominal impact on my day-to-day life.
As I grew up, the cognitive recognition that Easter celebrated something important, something critical, something that all of reality hinges upon, was not lost on me. However, the disconnect between head and heart can sometimes keep the significance of an event at a distance. I would reflect on its importance for a moment, perhaps at a Sunday service, but its formative impact quickly lost its potential on me as I turned my attention to the week and people and tasks ahead.
Until last year.
One way to keep our fingers on the pulse of the people we teach is to know what they're hearing and watching. Here are some top tens for Christians:
Top Ten Christian Movies (by profit)
10 Jonah: A VeggieTales Movie
9 God's Not Dead
Pray without ceasing--I'm learning what that means this week:
My friend and renowned author Carolyn Custis James's diagnosis of stage 1 lung cancer and her surgery today.
My friend and long-time Bible teacher Shirley Hotchkiss's miserable bout with brain cancer causing such severe nausea that she ended up in the hospital this week.
An unnamed friend who lost a promising ministry opportunity because someone snuck in and sabotaged the hiring process this week.
Oh, Lord, I'm reeling from a bad news tidal wave week and I want it to stop.
One of the first poems I remember memorizing as an elementary student is, "A Dream Deferred" by Langston Hughes.
What happens to a dream deferred?
Does it dry up
like a raisin in the sun?
Or fester like a sore--
And then run?
Does it stink like rotten meat?
Or crust and sugar over--
like a syrupy sweet?
Maybe it just sags
like a heavy load.
Or does it explode?
March madness has ended. The NCAA tournament is over for another year. Today many will feel a little bit of sadness that the momentum of the unpredictable, drama infused and entertaining madness has concluded. Do any folks who sacrifice for the tournament ever say, "Yeah, that was so worth it?"
Cherry and Beth met in a MOPS (Mothers of Preschoolers) group at their church, hitting it off immediately. They loved the mutual connection with another mom, understanding the stresses and joys of having small children about the same age. Their weekly playdates became the highlight of each girl's week. They would chat on the phone every day, comparing notes on what they would be fixing for dinner or what great, repeatable golden nuggets their toddlers spouted. That morphed to texting each other throughout the day, at least once an hour.
Our topic of conversation around the table at lunch yesterday was "faith in the workplace." My husband Ron had recently attended a conference on that very subject so he had some "takeaways" to share with us and discuss. For a Christian, all of life is an extension of our faith, including the time spent at work and the relationships made there. But, how do you live out your faith at work without stealing time from your employer?
Our son (almost) five year old son, Luke, comes to our church's contemporary worship service with us. During the service he often takes his daddy's watch and changes the time, hoping that he can move time along and therefore, the service along by moving the hands on the watch. He believes that if he changes the time then time will pass more quickly. (Note: this is not a commentary on the quality of our worship service – we are talking about a five year old, here!)
In•ter•sec•tion -the place or point where two or more things come together, especially the place where two or more streets meet or cross each other.
I loved John Grisham's book, The Firm. But my husband, Gary, never read it. Consequently, when he and I watched the movie together, I disliked what Hollywood had done to the story. But Gary, unfamiliar with the plot in the original, really liked the movie version. In fact, for some strange reason it annoyed him when I constantly interrupted the film to whisper, "That's not how it happened in the book! The book was way better!" In fact, he finally, kindly, asked me to be quiet so he could just enjoy the show.
Never judge a book by its movie, as the saying goes.
A life well lived. It's something that we all want, isn't it? We want the satisfaction and joy of knowing that we loved fiercely and refused to live in fear. That we lived generously, gave of ourselves without reservation, and chose to see the best in others. That we forgave and forgot, and overall, that we let the love of God rule in our hearts and minds. In essence, we want to know that who we are and what we did mattered. That I, Tiffany, stewarded well the life I was given, and that it brought pleasure to God. Two weeks ago I got to witness that very thing—a life well lived.


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Celebrate Earth Day With These Great Movies
page 1 of 7
Celebrate Earth Day With These Great Movies
In addition to previously recommended Earth Day movies, take a look at these gorgeous documentaries about the creatures with whom we share this great planet.
Nell Minnow blogs for Beliefnet at http://blog.beliefnet.com/moviemom/.
6 Things The 'Killing Jesus' Movie Is NotThe upcoming miniseries on National Geographic is not like any other 'Jesus'...
Unbelievable Facts That Will Completely Throw Off...Brace yourself. These facts will totally warp your perception of time.
7 Life Lessons From The Fresh Prince of Bel-Air"In West-Philadelphia born and raised…" we all know the song and we all loved...


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Gomez back in Germany squad for France friendly
Mario Gomez is back in Germany's squad for Wednesday's friendly against France in Paris.
Germany coach Joachim Loew announced the squad on Friday, recalling Gomez for the first time since the European Championship semifinal loss to Italy in June following the Bayern Munich striker's three months out with an ankle injury.
''Gomez is in good shape again after his long injury,'' Loew said. ''Like Miroslav Klose, he brings our game philosophy to the position of central striker. I'm convinced because of his qualities and experience that he will prevail again at the highest international level.''
Loew also selected Klose, giving the veteran Lazio striker another opportunity to score the goal he needs to equal Gerd Mueller's German record of 68.
There is no place, however, for Bayer Leverkusen striker Stefan Kiessling, whose league-leading 13 goals led to speculation of a first call-up since 2010.
Hamburger SV goalkeeper Rene Adler was recalled in November for the first time after two injury-plagued years, and the 28-year-old Adler has another chance to impress after staying on the bench for the 0-0 draw against the Netherlands in Amsterdam.
''Adler played a very strong opening half to the season in the Bundesliga,'' Loew said. ''Now he's earned the chance to prove himself against France. For the decisive World Cup qualifiers in March we'll trust Manuel Neuer again. He's currently our clear No. 1.''
Germany, which leads Europe Group C in World Cup qualifying, plays Kazakhstan twice in March.
The Germans have not beaten France since 1987, when Rudi Voeller scored both goals in a 2-1 win, with Eric Cantona scoring for the visitors.
''I think we've a very good squad, but one which needs to be. France are on the way back to their old strengths and for me are back among the world's best teams, thanks also to outstanding players like Karim Benzema and Franck Ribery,'' Loew said.
''The team impressed me very much in both the last away games in Spain and Italy. You could sense coach Didier Deschamps' signature. I rate him very highly, especially since he loves the fast attacking game as much as I do. The game will be a real tough test.''
Germany squad:
Goalkeepers: Rene Adler (Hamburger SV), Manuel Neuer (Bayern Munich)
Defenders: Jerome Boateng (Bayern Munich), Benedikt Hoewedes (Schalke), Mats Hummels (Borussia Dortmund), Philipp Lahm (Bayern Munich), Per Mertesacker (Arsenal), Marcel Schmelzer (Borussia Dortmund), Heiko Westermann (Hamburger SV)
Midfielders: Lars Bender (Bayer Leverkusen), Julian Draxler (Schalke), Mario Goetze (Borussia Dortmund), Ilkay Guendogan (Borussia Dortmund), Sami Khedira (Real Madrid), Toni Kroos (Bayern Munich), Thomas Mueller (Bayern Munich), Mesut Oezil (Real Madrid), Lukas Podolski (Arsenal), Marco Reus (Borussia Dortmund), Andre Schuerrle (Bayer Leverkusen), Bastian Schweinsteiger (Bayern Munich)
Forwards: Mario Gomez (Bayern Munich), Miroslav Klose (Lazio)
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