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A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of one of a set of microinstructions stored in a control store. The microinstructions have a data path control field, a condition/size field and a next address control field. A microinstruction logic control is responsive to the microinstructions, and a memory control unit that includes a data cache memory array operates asynchronously with respect to the data path unit, translating virtual memory addresses to access data from the data cache memory array or from the central memory unit.
1. A central processing unit in a data processing system including a system bus and a central memory unit, which comprises:
(a) macroinstruction execution means for issuing a memory control command and a virtual memory address to access a variable length macroinstruction consisting of an operation code and one or more operand specifiers stored in said central memory unit, such access occurring in accordance with a microprogram selected in response to said memory control command, said macroinstruction execution means comprising:
(i) decode means for decoding the operation code of said macroinstruction to issue a microaddress of one of a set of microinstructions, a size code indicating the length in bytes of data upon which said macroinstruction shall operate, and a condition code class code specifying the mapping of microinstruction condition codes to macroinstruction condition codes, and including means for decoding said operand specifies to issue either data upon which said macroinstruction is to operate or a data address and an addressing mode indicator specifying any one of multiple addressing modes;
(ii) control store means having stored therein microinstructions comprised of a data path control field, a condition code/size field, and a next address control field, the control store means being adapted for issuing said memory control command and for supplying a microinstruction in response to said microaddress; and
(iii) microinstruction logic control means responsive to said data path control field, said size code, and said condition code/size field, and receiving data from said decode means and indirectly from said central memory unit for executing said set of microinstructions and for issuing said virtual memory address to access data from said central memory unit; and
(b) memory access means responsive to said memory control command and to said virtual memory address, and including a data cache memory array and a microprogram control means, and operating asynchronously to said macroinstruction execution means under the control of said microprogram, for translating said virtual memory address to access data from said data cache memory array or by way of said system bus from said central memory unit and supplying data so accessed to said macroinstruction execution means.
2. The central processing unit as set forth in claim 1, wherein said decode means includes microsequencer means comprising:
(a) page register means receiving said microaddress from said decode means;
(b) microprogram counter means responsive to said microaddress for supplying the address of a word within said page; and
(c) jump control logic means responsive to said page register means, said microprogram counter means, and said next address control field for issuing said microaddress.
3. The central processing unit as set forth in claim 1, wherein said microinstruction logic control means includes register save means comprising:
(a) plural registers for storing data and said macroinstruction received from said memory access means, and for storing data received from said decode means;
(b) program control means responsive to said microinstruction for operating upon said macroinstruction and data received from said plural registers; and
(c) last-in-first-out (LIFO) logic means responsive to said program control means for temporarily saving the contents and address of each of said plural registers during macroinstruction operations and the execution of said microsubroutine.
4. The central processing unit as set forth in claim 1, wherein said macroinstruction execution means includes microsequencer means for determining the microaddress of the next microinstruction to be executed by the logic control means said microaddress having a high and low portion, the microsequencer means comprising:
(a) page register means for storing the high order portion of the microaddress of the microinstruction currently being executed by the control logic means;
(b) microprogram counter means for storing the low order portion plus one of the microaddress of the microinstruction currently being executed by the control logic means; and
(c) jump control logic means responsive to the contents of said page register means, the contents of said microprogram counter means, and said next address control field for issuing the microaddress of the next microinstruction to be executed by the control logic means.
A number of digital computers have been developed in recent years with virtual memory management systems, 32 bit data paths, data caches, the ability to use a variety of data types and addressing modes, variable length instruction formats, and other advanced features. To date, however, the result of including such features has been a computer of considerable cost and physical size. For example, it would not be unusual for the central processing unit of a computer having the attributes listed above to occupy 500 square inches of circuit board space. As a consequence, it has been impossible or impractical to use such computers in many applications.
The present invention provides a central processing unit for a digital computer that is compact and economical, and yet supports a 32 bit data path, variable length instructions, a variety of addressing modes, and other advanced features. The central processing unit utilizes a pipelined, microprogrammed design and includes a number of hardware features that permit implementation of powerful functions with extremely compact microcode.
In one aspect, the present invention provides a central processing unit for a digital computer having a central memory unit connected to a system bus. The central processing unit comprises a memory control module and a data path module. The memory control module operates asynchronously with respect to the data path module, and provides an interface between the data path module and the system bus. The memory control module also provides address translation, instruction prefetch and data cache functions for the data path module. The data path module executes macroinstructions provided from the central memory unit by the memory control module. Each macroinstruction comprises an operation code (op code) followed by one or more operand specifiers. The operand specifiers specify either the data or the location of the data upon which the macroinstruction is to operate. The execution of macroinstructions is carried out by means of microninstructions that are stored in a control store and executed by a control logic unit. A decode ROM decodes each macroinstruction and provides the microaddress of the next microinstruction to be executed. Subsequent microinstructions corresponding to a macroinstruction are specified by a microsequencer. Each microinstruction includes a data path control field, a condition code/size field, and a next address control field. The data path control field is used to control the execution of the microninstruction by the control logic unit. The condition code/size field specifies either the width of the data path or the handling of condition codes. The next address control field is used by the microsequencer to determine the address of the next microinstruction.
These and other features of the invention will be apparent from the detailed description and claims to follow, taken in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of a computer system incorporating the central processing unit of the present invention.
FIG. 2 is a block diagram of one embodiment of a central processing unit of the present invention.
FIG. 3 is a block diagram of a microsequencer for use with the central processing unit of the present invention.
FIG. 4 is a table illustrating the method for determining the next microaddress by the microsequencer.
FIG. 5 is a table indicating the control signals that may be used to modify the next microaddress.
FIG. 6 is a block diagram detailing the control logic unit of the central processing unit of the present invention.
FIG. 1 illustrates a computer system which includes a preferred embodiment of the central processing unit of the present invention. The computer system includes central processing unit (CPU) 10, system bus 20, memory array 22, and console terminal 24. The computer system can also include various peripheral devices (not shown) connected to system bus 20, for example disk controllers and network interfaces. Console terminal 24 may be omitted if a suitable interface is provided on bus 20, e.g., an interface to a local area network. CPU 10 consists of memory control module 12 and data path module 14. The actual execution of program instructions is controlled by data path module 14, and memory control module 12 acts generally as an interface between the data path module and the system bus. The memory control and data path modules communicate via memory control bus 16 and memory data bus 18.
Memory control module 12 is a microprogrammed device that operates asynchronously with respect to data path module 14. The memory control module provides an interface between the CPU and the system bus and, in addition, provides address translation, instruction prefetch, and data cache functions for data path module 14. Address translation refers to the translation of virtual addresses specified by data path module 14 into actual physical addresses. The term data cache refers to a unit for the storage of recently used data in high speed memory arrays within the CPU.
Referring now to FIG. 2, memory control module 12 includes transceiver 30, buses 32 and 34, translation buffer/cache 40, physical address register 42, system bus interface 44, merge/rotate unit 48, microsequencer/control store 50, bus controller 52, and instruction prefetch unit 56. The function of the memory control units will be described by outlining the sequence of operations that takes place when data path module 14 requests that data be read from a specified virtual address. The data path module places the virtual address in bus latch 64 from which point it is sent to memory control module 12 over memory data bus 18. The address passes through transceiver 30 onto bus 32. The virtual address on bus 32 is presented to translation buffer/cache 40 and if the required translation entry is present (i.e., a cache hit), the corresponding physical address is produced on bus 34. From bus 34, the physical address is loaded into physical address register 42, from which point it is loaded onto bus 32. The physical address on bus 32 is then simultaneously presented to translation buffer/cache 40 and to the system bus interface unit 44. If the required data is in the cache, the translation buffer/cache 40 asserts the requested data onto bus 34 in the next machine cycle. If a cache miss occurs, a system bus cycle is executed to fetch the requested data from memory array 22. When the data is received from memory, it is passed from system bus interface 44 onto bus 34. Once the data from the cache or from memory is received on bus 34, it is loaded through merge/rotate unit 48 back onto bus 32. The requested data is then passed to data path module 14 via transceiver 30 and memory data bus 18, completing the virtual read cycle. The above-described sequence of memory control operations is carried out and coordinated by control signals emanating from microsequencer/control store 50. The particular microprogram executed by microsequencer/control store 50 is selected by memory control command 28 sent by data path module 14 to memory control module 12 over memory control bus 16. This command is asserted at the same time that the virtual address is placed on memory data bus 18. For memory control module microprograms that require the use of system bus 20, the microprograms operate through bus controller unit 52.
An additional function performed by memory control module 12 is the prefetching of instructions for execution by data path module 14. The prefetched instructions are stored in instruction prefetch unit 56, and are passed to data path module 14 as needed, one byte at a time, via memory control bus 16. Memory control bus 16 therefore performs two distinct functions: the transfer of instructions from memory control module 12 to data path module 14, and the transfer of memory control commands from data path module 14 to memory control module 12.
Each macroinstruction executed by data path module 14 generally consists of an operation code (op-code) followed by one or more operand specifiers. The operand specifiers specify either the data or the location of the data upon which the macroinstruction is to operate. In the former case, the data contained within the operand specifier is termed a literal. In the latter case, the operand specifier designates the addressing mode and the number (i.e., address) of a register. Examples of addressing modes are direct, in which the designated register contains the data, and indirect, in which the designated register contains the address of the data. By way of example, in a macroinstruction to add the contents of registers 3 and 4, the op-code would specify addition, and the two operand specifiers would specify register 3 direct and register 4 direct, respectively. In the preferred embodiment describe herein, each op-code and operand specifier consists of one or more bytes, and such macroinstruction bytes are received and processed one byte at a time by data path module 14.
Referring now to data path module 14 in FIG. 2, the execution of macroinstructions is carried out by means of microinstructions executed by control logic unit 60. The control logic unit includes the ALU, the general purpose registers, two pointer registers, the macroprogram counter, and other elements as described below. For each macroinstruction, contorl logic unit 60 executes a series of microinstructions stored in control store 62. The microinstruction sequence commences when the op-code of a new macroinstruction is loaded into instruction register 70 from memory control bus 16. The value of the op-code and a portion of the current microinstruction are used to address a location in decode ROM 74. In response, the decode ROM supplies a number of outputs: a next microaddress, which specifies the address in control store 62 of the first microinstruction coresponding to the macroinstruction op-code; a SIZE signal indicating the length in bytes of the data upon which the macroinstruction is to operate; and a CC CLASS (condition code class) signal whose function is described below. When the instruction register contains a operand specifier, decode ROM 74 in addition supplies a REGISTER signal indicating whether or not the addressing mode is direct.
The next microaddress supplied by decode ROM 74 is passed by microsequencer 76 to control store address register 78. The address in control store address register 78 specifies the microinstruction which is accessed in control store 62. Portions of the accessed microinstruction are routed to a number of destinations. One portion goes to control logic unit 60 for execution. A second portion goes to microsequencer 76 where it can be used to determine the address of the next microinstruction. In certain situations, control store 62 also supplies memory control signal 28 and values to be loaded into size register 88 and CC logic 90. After the first microinstruction has begun executing, microsequencer 76 causes the address of the next microinstruction to be placed into control store address register 78, and the sequence continues until all microinstructions corresponding to the macroninstruction have been executed. Microstack 80 is included to permit the use of microsubroutines and microtraps in the microprograms in control store 62. The operation of the microstack is described in detail below.
Other elements included in data path module 14 are bus latch 64, buses 82 and 84, latch 86, size register 88, condition code logic 90, index register 92, console interface 94, interrupt control logic 96, and instruction register buffer 98. Buses 82 and 84 are used in a variety of contexts to pass data between data path elements. Latch 86 provides isolation between buses 82 and 84. Size register 88 is used to hold a code, usually derived from the SIZE signal from decode ROM 74 or from control store 62, indicating a default data path width for control logic unit 60. Condition code logic 90 is used to control the setting of macrolevel condition codes based on control logic unit 60 outputs. Index register 92 is a four-bit register that may be used by microsequencer 76 to determine the next microaddress. Console interface 94 is a serial port used to interface the data path module with console terminal 24 (FIG. 1). Interrupt control logic 96 compares any interrupt received from system bus 20 with the current state of the CPU, to determine whether the interrupt should be taken. Instruction register buffer 98 provides a means for sending the contents of instruction register 70 to control logic unit 60 via bus 82.
The function of microsequencer 76 is to determine the sequence in which microinstructions are executed by control logic unit 60. It accomplishes this by determining, during the execution of a given microinstruction, the address in control store 62 of the next microinstruction, and placing that address in control store address register 78. The microsequencer determines the next microinstruction address based on information coded into the current microinstruction, and on the signals on various status and control lines.
FIG. 3 illustrates microsequencer 76 in greater detail. The next microaddress is determined by the output of MUX (multiplexer) 200. The inputs to MUX 200 are page register 201, microprogram counter 202, and OR gate 204. The selection between these inputs is determined by the output of JUMP MUX 206 and by certain other control signals to be described. Page register 201 contains the high order bits of the current microinstruction address. Microprogram counter 202 contains the low order bits of the current microinstruction address, plus one. Page register 201 and microprogram counter 202 therefore together point to the next sequential microinstruction address. The selection of these inputs by MUX 200 represents the simple case in which the computer system executes microinstructions in a sequential fashion.
OR gate 204 performs a logical OR operation between the output of OR MUX 208 and the address on bus 210. Bus 210 contains an address determined either by decode ROM 74, jump register 212, or microstack 80. The bus 210 address is derived from decode ROM 74 when a macroinstruction op-code or operand specifier byte is being decoded. In this case, the decode ROM provides either all or part of the address of the first microinstruction requied to carry out the function specified by this macroinstruction byte. In general, jump register 212 is the source of the address on bus 210 when a nonsequential jump or branch is to be taken in the microinstruction sequence. The address to which the branch is to be taken is derived from the contents of the current microinstruction in control store 62 and placed in jump register 212. Finally, microstack 80 is the source of the address on bus 210 when a return from a microsubroutine or microtrap is to be taken. The retrun address is stored in microstack 80 when the original subroutine call or trap is taken. The return address is determined either by the contents of page register 201 and microprogram counter 202 for a subroutine call, or by the contents of the page register and the microprogram counter less one (i.e., the current microaddress) for a trap. In the latter case, conditional decrementer 214 is used to subtract one from the contents of microprogram counter 202.
Each microinstruction stored in control store 62 includes three fields: a data path control field, a condition code/size field, and a next address control field. The data path control field is used to control the execution of the microinstruction by control logic unit 60 (FIG. 2). The condition code/size field is discussed below. The next address control field is used by microsequencer 76 to determine the address of the next microinstruction. The next address control field can conceptually be broken down into four subfields as follows:
Jump Condition
Jump Address
The Type subfield specifies one of the branch types listed in FIG. 4 and explained more fully below. The Jump Condition subfield specifies the condition to be tested to determine whether or not a nonsequential branch is to be taken in the microinstruction sequence. Referring to FIG. 3, the Jump Condition subfield in part determines which of the inputs to JUMP MUX 206 is selected for controlling MUX 200. Typical Jump Conditions which may be selected are the ALU condition codes, whether or not an interrupt or console halt has been received, whether or not the outputs of OR MUX 208 are zero, and whether the signal IR INVALID has been asserted. The IR INVALID signal is generated by instruction prefetch unit 56 whenever instruction register 70 does not contain valid information. In general, if the selected condition is true, then MUX 200 selects the address supplied by OR gate 204 and the branch is taken. If the condition is not true, MUX 200 selects the next sequential address supplied by page register 201 and microprogram counter 202.
The OR operation performed by OR gate 204 only operates on the less significant bits of the address on bus 210. In a preferred embodiment of the present computer system, the output of OR MUX 208 is four bits wide, and, for certain microinstruction branch types, these four bits are ORed with the low order four bits on bus 210. The OR MUX is thus capable of providing multidestination branching (i.e., casing). The output of OR MUX 208 is controlled by the OR subfield of the current microinstruction. FIG. 5 shows one preferred embodiment of the present invention in which the OR subfield is up to three bits wide and capable of selecting from up to eight sets four bit inputs. For each selection, corresponding to OR subfield values zero through seven, FIG. 5 lists the values for each of the OR MUX output bits ORMUX3 through ORMUX0. For a subfield value of zero, all OR MUX outputs are zero. For a value of one, ORMUX0 is set to one if the IR INVALID signal is asserted. For a value of two, ORMUX1 is set to one. This value may conveniently be used to provide multiple returns from microsubroutines. For a value of three, the OR MUX output is determined by the signals on four memory status lines as indicated. MEM ERR refers to a miscellaneous error signal from memory control module 12. PAGE CROSSING indicates an attempt to access data that crosses a 512 byte page boundary. TB MISS indicates that a translation entry for a requested virtual address was not found in translation buffer/cache 40. MODIFY REFUSE indicates that a memory write operation could not be performed because the modify bit in the corresponding translation buffer entry was not set. For a code value of four, the OR MUX output is determined by the IR INVALID signal and by BR FALSE, the latter indicating whether a macrolevel branch will be taken. For a code value of five, the OR MUX output is determined by the indicated status signals. OVERFLOW refers to the PSL V code described below. INTERRUPT and CONSOLE HALT refer to signal from interrupt control logic 96 and console interface 94, respectively. For a code value of six, the OR MUX output is equal to the contents of index register 92 (FIG. 2). For a code value of seven, the OR MUX output is determined by the contents of size register 88.
FIG. 4 summarizes the methods by which microsequencer 76 selects the next microaddress. The Type subfield of the current microinstruction specifies one of the branch types listed in the first column of FIG. 4. The operation of these types is described in the following paragraphs. In FIG. 4, the symbol .sub.μ PC stands for microprogram counter 202.
When the branch type is Jump or Jump to Subroutine, the address contained in the Jump Address subfield of the current microinstruction is loaded into Jump Regiser 212. This address is enabled onto bus 210, from which point it passes without modification through OR gate 204 and MUX 200. The next microaddress is therefore determined entirely by the Jump Address subfield of the curret microinstruction. Jump and Jump to Subroutine branch types are used to cause unconditional branches in microinstruction flow. When a Jump to Subroutine is executed, the contents of page register 201 and microprogram counter 202 are pushed onto microstack 80.
A branch type of Branch is used to perform a conditional Jump to a microaddress within the current page. As indicated in FIG. 4, the high order five bits of the next microaddress are determined by page register 201, and the low order eight bits are determined based on the Jump Condition. If the Jump Condition is true, the low order bits are derived from the low-order Jump Address subfield of the current microinstruction via Jump Register 212. If the Jump Condition is false, no jump is taken, and the low order bits are derived from microprogram counter 202. The Jump Condition is equal to the signal selected by Jump MUX 206 based upon the Jump Condition subfield of the current microinstruction.
The Case branch type is similar to Branch, except that if the Jump Condition is true, the low order bis of the next microaddress are determined by the Jump Register in combination with the OR MUX output. In particular, the four OR MUX output bits (FIG. 5) are ORed with the low order four bits of the Jump Register by OR gate 204.
The Branch to Subroutine and Trap branch types are similar to Case, except that if the Jump Condition is true, the high order bits of the next microaddress are forced to zero, and either the next sequential microaddress (Branch to Subroutine) or the current microaddress (Trap) are pushed onto microstack 80.
The Return branch type is used to return to any microaddress which has been pushed onto microstack 80. The Return branch type is conditional, and will only return if the Jump Condition is true. A false Jump Condition will cause the next sequential microaddress to be selected by microsequencer 76.
FIG. 4 also illustrates the way that the next microaddress is determined when control logic unit 60 executes a microinstruction which calls for the decoding of an op-code or an operand specifier in instruction register 70. For an op-code decode, the next microaddress is determined by the address supplied by decode ROM 74 if the specified Jump Condition is false. In this event, the high order bit of the next microaddress is set to zero. However, if the specified Jump Condition is true, then the next microaddress is determined entirely by the four bit output of OR MUX 208, and the current microaddress is pushed onto microstack 80. In general, the Jump Condition specified in an op-code decode microinstruction will be the IR INVALID signal. As a result, when data path module 14 attempts the decode an op-code which is not yet available in instruction register 70, a trap is taken to a low microaddress where a subroutine waits for instruction prefetch unit 56 to catch up.
When an operand specifier decode microinstruction is executed, the next microaddress is determined by two signals: the IR INVALID signal and the REGISTER signal supplied by decode ROM 74, the latter indicating whether the addressing mode of the operand specifier is direct. If the instruction register is valid and the mode is direct, then the next sequential microaddress is selected. If the instruction register is valid and the mode is indirect, then the microprogram jumps to a subroutine at an address whose high order portion is determined by the high-order bits of Jump Register 212, and whose low order portion is equal to the microaddress supplied by decode ROM 74. The address in Jump Register 212 is derived from Jump Address subfield of the current microinstruction. Finally, if the IR INVALID signal is asserted, then the microprogram traps to a subroutine whose address is specified by the output of OR MUX 208, which in this case is set to a value equal to one.
The last situation illustrated in FIG. 4 is power-up or a parity error. In this case, data path module 14 begins executing microinstructions at address zero.
FIG. 6 illustrates control logic unit 60 in greater detail. The control logic unit includes buses 100 and 102, ALU 104, result register 106 and 107, barrel shifter 108 and associated shift count register 110 and result register 112, pointer registers 120 and 122, register file 124, program counter 126, constant ROM 130, register save stack 132, I/O port 134, and control store register 140.
The execution of a microinstruction by control logic unit 60 commences when the data path control field of the microinstruction is loaded into control store register 140 from control store 62. In general, the data path control field includes a micro op-code and two micro operand specifiers. When the micro op-code specifies an arithmetic or logical operation (e.g., Add, And, Mask, Compare), the operation is carried out by ALU 104. The two required operands are supplied via buses 100 and 102, and the result of the operation is placed in result register 106 or 107, depending on a bit contained within the current microinstruction.
Barrel shifter 108 is used for shift operations. The shift count may be stored in shift count register 110 or supplied as a literal in the microinstruction. The result of the shift operation is stored in result register 112.
Register file 124 contains a number of general registers accessible to the macrolevel program, plus both general and special purpose microlevel registers. The term general register will hereafter be used to refer to both macrolevel and microlevel general purpose registers in registers file 124. Each register may be read from either bus 100 or 102, but may be written only from bus 102. Each register in register file 124 has a unique register address associated with it, the register address being used as described below to specify the register during microinstruction execution.
Size register 88 is used to control the width of the data path utilized by control logic unit 60, and to control microprogram branching as indicated in FIG. 5. In a preferred embodiment of the present computer system, the data path can be up to 32 bits wide, although particular macroinstructions may specify a smaller data path such as byte (eight bits) and word (16 bits). For example, a macroinstruction might specify that a byte is to be retrieved from a particular virtual memory address and loaded into general register 3 (i.e., the general register in register file 124 having a register address of 3). This macroinstruction would affect only the low order eight bits of general register 3, leaving the high order 24 bits unaffected. A full 32-bit block of data is referred to as a longword.
Size register 88 is loaded with a two-bit code directly from decode ROM 74 when a macroinstruction op-code is decoded. In one preferred embodiment, the coding scheme is:
2-not used
Thus the data path width specified by an op-code can be made available to the control logic unit (as signals SIZE0 and SIZE1) during the entire execution sequence for that op-code, without the use of ALU operations for masking, and without any moving, rotating or refreshing of the register.
The contents of the size register can be altered when a microinstruction for performing an operand specifier decode is executed. When such a microinstruction is executed, the condition code/size field of the microinstruction is loaded from control store 62 into size register 88 if the value of the field is zero (byte), 1 (word), or 3 (longword). If the value is 2, then the size register 88 is unaffected, leaving intact the size specified by the preceding op-code.
Aside from decode microinstructions, the size register can be modified only by Move microinstructions that explicitly specify the size register as their destination operands. Microinstructions other than decodes can, however, control the data path width during their execution by means of their condition code/size field. For ALU and shift microinstructions, the condition code/size coding is discussed below. For other microinstructions, (e.g., Move, Memory Request), the condition code/size field coding is as follows:
2-use size register
Thus a given microinstruction can either specify its own data path width, or can specify the size register and therefore use the width specified by a preceding op-code or operand specifier. The result is that the efficiency gained by the use of size register 88 does not cause any corresponding loss of flexibility in the microprogramming of the present computer system.
Pointer registers 120 and 122 are six-bit registes that can each serve two functions: they can contain the address of (i.e., point to) a particular general register in register file 124, or they can contain a literal value derived from an operand specifier. Pointer registers 120 and 122 can be read from buses 100 and 102, and written from bus 102. The use of two pointer registers provides significant advantages in the execution speed of many macroinstructions. For example, a macroinstruction to add the contents of general registers R1 and R2, placing the result in general register R2, might be coded as follows:
Op-code -Add
Operand specifier 1 -R1, direct mode
Operand specifier 2 -R2, direct mode
with each operand specifier including a mode specifying the addresser, mode and either a register field containers the address of a register (as above) or a literal. Without the use of the pointer registers of the present invention, the microinstruction sequence for this macroinstruction would require seven steps as follows:
1. Decode op-code
2. Decode operand specifier 1
3. Move R1 to TEMP1
4. Decode operand specifier 2
5. Move R2 to TEMP2
6. Add TEMP3=TEMP1+TEMP2
7. Move TEMP3 to R2
where TEMP1, TEMP2 and TEMP3 stand for general microlevel registers. The use of two pointer registers reduces the required number of steps to five, as follows:
1. Decode op-code
2. Decode operand specifier 1, place address of R1 in PTR1
3. Decode operand specifier 2, place address of R2 in PTR2
4. Add TEMP1=@PTR1+@PTR2
5. Move TEMP1 to @PTR2
where the symbol @X signifies the location (i.e., register) whose address is in register X, and where PTR1 and PTR2 specify pointer registers 120 and 122. As indicated in steps 2 and 3 above, an operand specifier decode causes one of the pointer registers 120 or 122 to be loaded with the number of the register specified by the operand specifier. This loading of a pointer register takes place regardless of the addressing mode specified by the operand specifier. In the case of an operand specifier containing a literal, the literal is likewise loaded into a pointer register. In all cases, a bit in the microinstruction for performing the operand specifier decode determines which pointer register (120 or 122) is loaded. Referring to FIG. 2, the pointer registers are loaded from instruction register 70 through instruction register buffer 98, bus 82, latch 86, bus 84, I/O port 134 and bus 102.
The Add and Move microinstructions in steps 4 and 5 of the second example above indirectly address registers R1 and R2 through the use of pointer registers 120 and 122. To implement such an addressing method, two register addresses are assigned to each of the pointer registers, a direct address and an indirect address. The direct address of a pointer register is fully analogous to the address of the registers in register file 124, and is used to specify the contents of that register. For example, for a microinstruction such as Move 3, 4 in which the first and second micro operand specifiers specify the registers in register file 124 whose addresses are 3 and 4 respectively, the result would be that the contents of register 3 would be moved to register 4. Pointer registes 120 and 122 provide a different and generally more efficient method of accomplishing the same result. Each pointer register is assigned a unique indirect address different from the direct address of any register. When the indirect address is specified by a micro operand specifier, the register actually accessed is determined by the contents of the indirectly addressed pointer register. For example, if pointer registers 120 and 122 were assigned indirect addresses of 54 and 55, and contained the numbers 3 and 4, then the microinstruction Move 54, 55 would be equivalent to Move 3, 4.
Program counter 126 is a register which stores the address of the next macroinstruction byte to be executed. As with pointer registers 120 and 122 and the registers in register file 124, program counter 126 may be read from either bus 100 or 102, and may be written from bus 102. Program counter 126 is automatically incremented, by 1,2 or 4, when one of the following occurs:
(1) An op-code decode microinstruction is executed.
(2) An operand specifier decode microinstruction is executed.
(3) The current microinstruction specifies instruction register 70 as the location of one of the microinstruction operands.
(4) A microinstruction is executed which specifies retrieval of data from the macroinstruction instruction stream.
Cases (1) and (2) have already been described. Program counter 126 is incremented by one whenever a new macroinstruction byte is clocked out of the instruction register 70, such that the address in program counter 126 corresponds to the virtual address of the new macroinstruction byte. An example of case (3) is a situation in which a byte in the macroinstruction stream contains literal data. For example, one type of operand specifier specifies the address of the operand by specifying a register which contains a base address, and a fixed offset to be added to the base address found in the register. In this situation, the operand specifier would consist of two bytes, the first byte specifying the register address (e.g., register 2) and the addressing mode, and the second byte containing the fixed offset (i.e., a literal). The microinstructions for accessing such an operand would begin by decoding the first operand specifier byte and putting the value 2 (the register address) in pointer register 120. The following microinstruction would then Add the value pointed to by pointer register 120 to the literal contained in instruction register 70. The microinstruction would reference instruction register 70 by specifying a unique register address assigned to the instruction register. The literal would reach ALU 104 from instruction register 70 through instruction register buffer 98, bus 82, latch 86, bus 84, I/O port 134 and bus 102. The execution of the Add microinstruction specifying the address of instruction register 70 as an operand causes porgram counter 126 to be incremented by 1.
Case (4) listed above is termed an instruction stream memory request. When such a microinstruction is executed, control signals are sent from control store 62 to memory control module 12 via memory control bus 16. At the same time, the unincremented contents of program counter 126 are driven onto bus 84 via bus 102 and I/O port 134, and from there sent to memory control module 12 via memory data bus 18. Program counter 126 is then incremented by 1, 2 or 4 depending upon whether the instruction stream memory request microinstruction specified a byte, word or a longword. On memory control module 12 (FIG. 2), instruction prefetch unit 56 maintains a prefetch buffer filled with macroinstruction stream bytes. An instruction stream memory request first clears the prefetch buffer, then reads a byte, word, or longword from translation buffer/cache 40 or memory array 22 and sends the resulting data to data path module 14 via memory data bus 18. Instruction prefetch unit 56 then refills the prefetch buffers beginning with the next byte in the macroinstruction stream following the bytes sent to data path module 14.
Register save stack 132 is a LIFO stack used to temporarily store the contents of specified registers. Each entry on the stack consists of the contents of a register plus the address (number) of that register. An example illustrating the use of the register save stack is the decoding of an operand specifier that specifies an autoincrement addressing mode. In such a mode, the contents of a specified register is first used as an address to access the operand, and the register is then automatically incremented by 1, 2 or 4. When an autoincrement mode operand specifier is decoded, the unincremented contents of the register are automatically pushed onto the register save stack. If the attempted memory access then results in an error condition, the register can be restored to its preexisting condition by popping the stack. The push operation is controlled by the current microinstruction, which contains a bit that determines whether or not a push will occur. If a push is to occur, one of the micro operand specifiers contains the address of the register.
Condition code logic unit 90 is used for storing and controlling two sets of condition codes: microprogram level (ALU) condition codes and macroprogram level (PSL) condition codes. Four conditions are provided at each level:
The ALU condition codes reflect the result of the last microinstruction executed by control logic unit 60, which specified in the condition code/size field that the ALU condition codes were to be loaded, and comprise four of the inputs to JUMP MUX 206 (FIG. 3). The ALU condition codes can therefore be used as jump control signals by microinstructions, as indicated in FIG. 4. The PSL condition codes are the condition codes available to the macroprogram level, and may be used by the macroprogram to determine whether a macrobranch should be taken.
When an op-code is decoded by decode ROM 74, a two-bit Condition Code Class signal is produced and sent directly to a condition code class register (not shown) contained within condition code logic unit 90. The contents of the condition code class register determine how the ALU codes are mapped to the PSL codes as follows:
______________________________________Condition CodeClass Register Class______________________________________0 Logical ALU N to PSL N ALU Z to PSL Z ALU V to PSL V PSL C to PSL C1 Arithmetic ALU N to PSL N ALU Z to PSL Z ALU V to PSL V ALU C to PSL C2 Compare ALU N to PSL N ALU Z to PSL Z Clear PSL V ALU C to PSL C3 Floating ALU N to PSL N Point ALU Z to PSL Z ALU V to PSL V Clear PSL C______________________________________
The actual setting of condition codes by a given microinstruction is determined by the condition code/size field of that microinstruction. As described above, certain types of microinstructions (e.g., Move, Memory Request, Decode) use the condition code/size field to specify data path width, and for these microinstructions, the condition codes are never set. For other microinstructions (e.g., Add, And, Shift) the condition code/size field controls data path width and condition code setting as follows:
______________________________________Condition Code/ Data PathSize Field Value Width______________________________________0 longword condition codes not affected1 longword set ALU condition codes2 longword set ALU & PSL condition codes3 per size set ALU & PSL condition register codes______________________________________
For such microinstructions, the contents of the condition code/size field is sent directly to the CC logic unit 90 from control store 62.
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by Patrick Rall
I drive a great many new trucks for my day job and the biggest difference between these newer trucks and my 2006 Dodge Ram 1500 is generally the fancy infotainment system. My Ram has a pretty run of the mill radio with a plain readout in green digits while pretty much every new truck sold …
by Patrick Rall
The 2015 Dodge Challenger SRT Hellcat will arrive as the most powerful V8 Mopar of all time with output guaranteed to top 600 horsepower and 575lb-ft of torque from the supercharged 6.2L Hemi. In the history of Mopar performance cars, only the mighty Viper has packed more power than the Hellcat Challenger so in terms …
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The 3rd generation Dodge Ram ran from 2002 through 2008 so with those trucks now ranging from 6 to 12 years old, they are among the more common options in the affordable used vehicle market for those folks looking to buy a Ram. The problem that many shoppers may encounter when looking to buy a …
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This week's Truckin Fast Wednesday feature takes a slightly different approach than usual, trading a dry drag strip or a muddy Tuff Truck course for a big, snow covered parking lot where a 2g Dodge Dakota R/T is stretching its legs and having fun doing so. This Dakota starts by drifting from around the building …
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Apparently, Dr. Frankenstein is a real guy. It seems he's moved from cobbling creatures to assembling quick sleeper cars for the drag strip.


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Damaged axons in adult mammalian central nervous system (CNS) are unable to regenerate after injury although axons in the peripheral nervous system (PNS) or embryonic CNS can. The inhibitory molecules associated with myelin are one of the major obstacles to successful axon regeneration in the adult mammalian CNS. To date, three inhibitors of regeneration have been identified in myelin: NogoA, myelin-associated glycoprotein (MAG), and oligodendrocyte-myelin glycoprotein (OMpg) (Filbin, 2003). Interestingly, all these three ligands bind to the same receptor Nogo receptor (NgR) to mediate the inhibitory effect. p75NTR or TROY and Lingo-1( LRR and Ig domain-containing, Nogo Receptor interacting protein) are necessary components of the receptor complex as NgR is glycosyl phosphatidylinositol (GPI)-anchored and lacks a signaling domain (Wang et al., 2002a; Mi et al., 2004; Park et al., 2005; Shao et al., 2005). Activation of the receptor complex by myelin inhibitors activates the small GTPase RhoA resulting in rearrangement of the cytoskeleton and inhibition of axonal outgrowth (Hu and Strittmatter, 2004). It has been shown in our lab that elevating intracellular levels of cyclic AMP (cAMP), either via application of a cAMP analog or by prior exposure to neurotrophins (NTs) can block the inhibition of axonal regeneration by MAG and myelin (Cai et al., 1999; Cai et al., 2001; Qiu et al., 2002). Elevation of cAMP results in up-regulation of arginase I (ArgI) and subsequent synthesis of polyamines. Up-regulation of ArgI or priming with the polyamine putrescine or spermidine blocks the inhibition of axonal growth by MAG/myelin (Cai et al., 2002; Deng et al., 2009). Polyamines are known to have effects in regulating cytoskeleton organization in both the short term and the long term, but their downstream effectors have yet to be identified. Many studies have shown that Cyclin-dependent kinase 5 (Cdk5) is involved in neurite outgrowth and regulates the neuronal cytosekeleton, which prompted us to hypothesize that Cdk5 may play a role in blocking MAG/myelin-mediated inhibition. Cdk5 is a multifunctional serine/threonine kinase and its activator, p35, is expressed only in the nervous system (Tsai et al., 1994). It has been shown that activity of Cdk5 is required for neurite elongation (Nikolic et al., 1996; Paglini et al., 1998; Li et al., 2000; Harada et al., 2001). Cdk5 phosphorylates cytoskeleton proteins and regulates the organization of all three cytoskeleton elements microfilaments, microtubules and intermediate filaments (Dhavan and Tsai, 2001). Here we show that Cdk5 is required for db-cAMP and putrescine to overcome inhibition. The effect of db-cAMP and putrescine in overcoming inhibition by MAG is abolished in the presence of a specific inhibitor of Cdk5, Roscovitine. Neurons infected with dominant negative Cdk5 HSV viruses are not able to overcome inhibition by MAG in the presence of db-cAMP or putrescine. Importantly, neurons infected with HSV viruses overexpressing p35, the neuronal specific activator for Cdk5, overcome MAG's inhibition. Moreover, db-cAMP and putrescine increase the expression of p35. This in turn induces the kinase activity of Cdk5. The up-regulation of p35 by putrescine is also reflected in the increased distribution of p35 in neurites and growth cones. Furthermore, we show that putrescine up-regulates p35 protein by hypusine modification of eukaryotic Initiation Factor 5A (eIF5A), and this hypusination is necessary for putrescine to overcome inhibition by MAG. Our findings reveal a previously unknown mechanism by which polyamines encourage regeneration after CNS injury.
The rapid point-to-point movements of the eyes called saccades are some of the most commonly made by humans, yet differ from nearly every other type of motor output in that they are completed too quickly to be adjusted during their execution by visual feedback. Yet, saccadic accuracy remains quite high over a lifetime despite inevitable changes to the physical structures controlling the eyes, indicating that the oculomotor system actively monitors and adjusts motor commands to achieve this consistent behavioral production. Indeed, it seems that beyond the ability to compensate for slow, age-related bodily changes, saccades can be modified following traumatic injury or pathology that affects their production, or in response to more short-term systematic alterations to post-saccadic visual feedback in a lab setting. It is, in fact, thought that all of these forms of plasticity rely on the visual detection of accuracy errors by a unified set of mechanisms that support the process known as saccade adaptation. A great deal has been learned about saccade adaptation, as it has been extensively studied as a phenomenon in its own right, as well as being used to explore the process of motor learning in general. However, many fundamental questions about saccade adaptation remain unanswered, often related to the way that saccade adaptation might operate in the natural environment with substantially more complex visual stimuli than are generally used in the lab. Here, we addressed these questions with (in some cases original) variants and more conventional examples of the frequently used intrasaccadic target step (ISS) paradigm (in which an experimenter causes saccadic error by shifting a target during the movement). By exploring the responses to whole-field-ISSs, we have inferred that saccade adaptation might be supported by a trans-saccadic integration mechanism, and may be sensitive to intrasaccadic motion signals. Challenging the oculomotor system by confronting it with multiple post-saccadic targets has revealed that saccade adaptation can occur in a target-identity specific manner, so that even if post-saccadic error varies from trial-to-trial, adaptation seems to reflect the average behavior of the target. At a more basic level, we systematically varied ISSs to determine the lower limits of the oculomotor system's sensitivity to intrasaccadic displacement during adaptation. Also at a more basic level, we looked at the effects of rendering post-saccadic feedback more intermittent during adaptation, finding it to have little effect on the magnitude or rate of adaptive dynamics, similar to other forms of motor learning but somewhat dissimilar from operant conditioning. These experiments also furnished a useful setting to develop and test a novel model of saccade adaptation which more explicitly relies on post-saccadic sensory prediction than previous models, but that is nonetheless in keeping with the ethos of modern motor learning theory. Finally, we found that the establishment and maintenance of a context for saccadic performance by adaptation could be achieved by consistently pairing a target's visual-identity with a specific ISS, extending what had been previously recognized as constituting a cue for contextual motor learning. In general, our results suggest that saccade adaptation is a highly flexible mechanism that not only supports the maintenance of accuracy, but also makes use of a wide range of brain functions to deftly tailor saccadic behavior contingent on task demands.
Phylogenetic analyses based on morphological and DNA sequence data were generated to test the monophyly of Eschweilera and Lecythis and to investigate the relationships of these two genera and their close relatives (Bertholletia and Corythophora). The final results were applied to questions of taxonomic rearrangements and character evolution in traits related to pollination. A cladistic analysis based on morphology indicates that Bertholletia, Corythophora, Eschweilera, and Lecythis form a clade (the Bertholletia clade), but the resolution within the clade is too poor to elucidate the phylogenetic relationships among the genera. Nonetheless, the data support the monophyly of Corythophora. Eschweilera is divided into two clades: Eschweilera section Tetrapetala and Eschweilera s.s. Whether or not the two clades form a clade remains as unresolved. Lecythis is not resolved as monophyletic, but each of the Sections Corrugata, Pisonis, and Poiteaui is monophyletic. A combined analysis based on morphology and nuclear ITS and plastid ndhF, trnL-F, and trnH-psbA sequence data was conducted to improve the resolution of the phylogenetic tree. The results support the generic circumscriptions of Bertholletia and Corythophora based on morphology, but suggest the revision of Eschweilera and Lecythis. Eschweilera is paraphyletic and divided into three clades: the Eschweilera section Tetrapetala clade, the Eschweilera andina clade, and the core Eschweilera clade. Lecythis is polyphyletic and consists of five clades: the Lecythis s.s. clade, the Pachylecythis clade, the Lecythis chartacea clade, the Holopyxidium clade, and the Section Corrugata clade. Based on the results of these analyses, Section Tetrapetala clade merits recognition as an independent genus and should be segregated from Eschweilera. On the other hand, the five clades of Lecythis are distinct from each other and should be recognized as five separate genera. Androecial evolution inferred from the resulting phylogeny demonstrates that features such as floral zygomorphy, closed androecia, coiled ligules, and the production of nectar are homoplasious. Evolution of these characters most likely is because of the adaptation in response to pollinator shift and does not simply represent a process of morphological transformation from a simpler to a more complicated structure as previously suggested.
Valued internationally for the aromatic oil found within its heartwood, Sandalwood (Santalum, Santalaceae) is one of the most heavily exploited groups of plants across its range. While historically, most oil has been harvested from Santalum album in Southeast Asia and India, the decrease of S. album sources has caused a widening gap between supply and demand, which creates profitable market opportunities and increasing harvest pressure for alternative sandalwood oil sources. Santalum yasi, a quality alternative, has been harvested extensively in Fiji and Tonga, yet is vastly under-studied. The absence of basic data on population dynamics and genetic variation for remnant populations remains a major constraint to the sustainable management of this culturally and economically valued resource. This dissertation focuses on the ecological and genetic data and analyses that can aid in developing sustainable management strategies. Population size-class structure data was collected using transects in the three densest natural populations of Santalum yasi. Population dynamics, current species distribution, and ecological threats were investigated to find that the few remaining wild stands display discontinuous size class structures, are under regenerative stress and that the natural distribution has diminished significantly, even to local extinction in some areas. Using a nuclear microsatellite analysis, genetic variability within and between populations was investigated. Results suggest that there is no significant genetic variation between populations, but that most of the genetic variation lies within populations. This genetic distribution suggests that there is a significant level of gene flow between and among populations, most likely through human induced dispersal, showing a more panmictic trend than previously supposed. This may provide molecular evidence confirming the Western documentation and traditional oral history of extensive interaction between Fiji and Tonga and their trade of plants and culture. Based on these dwindling levels of yasi population size and unstructured genetic variation in Fiji and Tonga, further enumerations and resource surveys are not practical to conduct at this time. Rather, forestry and governmental efforts should be focused on promotion of local involvement in assisted natural regeneration of wild stands and preservation of genetic variation through in situ, community-mediated conservation.
Branching morphogenesis in vivo is a highly ordered process that necessitates spatially and temporally choreographed cues by growth factors and hormones, as well as mechanical and signal feedback from the extracellular matrix. Successful completion of this developmental process results in the architectural, and thereby the functional, basis for the lung, collecting ducts of the kidney, salivary, and mammary glands. The quest to understand the basic biological mechanisms underlying this developmental morphogenesis has lead to many seminal findings in the field of epithelial tube generation, as well as provided valuable insight into the pathogenesis of cancer. The primary focus of this thesis was elucidating the role of the Na+/H+ exchanger type 1 (NHE1) in branching morphogenesis of the mouse mammary gland. To accomplish this goal, we used three-dimensional (3D) primary tissue culture of mammary gland pieces (organoids) in a four day organotypic assay of growth factor induced branching morphogenesis. NHE1 is a ubiquitously expressed master regulator of intracellular pH (pHi). We found that blocking the function of this exchanger in the presence of growth factor stimulation led to altered kinase signaling, inhibition of growth factor induced alkalization, sustained proliferation after four days, ectopic expression of keratin 6 (K6), and a dramatic failure to undergo branching morphogenesis. These findings led us to question the role of NHE1 in the maintenance of branched mammary tissue architecture. We, therefore, inhibited NHE1 function on fully branched structures in our assay and found that NHE1 inhibition led to rapid loss (within 24 hours) of branched architecture by a process of branch fusion, with complete loss of the branched morphology after four days. This was not accompanied by cell death or altered proliferation, however, we did record altered intracellular pH (pHi) in the end buds of branched structures that had NHE1 inhibited. NHE1 localization, F-actin organization, and myoepthelial cell location were altered in structures that had undergone a loss of architecture, indicating a loss of tissue organization. Finally, we found that NHE1 inhibition resulted in a decrease in mammary Ecadherin. Having found that NHE1 function is vital for both branching morphogenesis and the maintenance of branched architecture, we considered the role that NHE1 could be playing in the pathology of breast cancer. Both intracellular and extracellular pH is deregulated in cancer. This could be attributed to over activity of NHE1. Additionally, NHE1 is over expressed in many cancers. We used the ER+ breast cancer cell line MCF7 to investigate the therapeutic potential of chemotherapy augmentation by NHE1 inhibition. We found that Cycylophosphamide, a DNA alkylating chemotherapeutic agent known to be more effective in an acidic environment, was roughly 5 times more effective when used along with NHE1 inhibition. These findings indicate that NHE1 is a critical regulator of branching morphogenesis and tissue stability, as well as suggests a potential therapeutic target for the treatment of breast cancer.
The larval hematopoietic system of Drosophila melanogaster consists of freely circulating cells, the sessile population, and the hematopoietic organ called the lymph gland. Most hemocytes function as macrophages and play a significant role in innate immunity. Hemocytes also remodel tissues, aiding in development of the organism. Constitutive activation of immune signaling pathways, as well as various mutations in genes which are not linked to immune pathways, result in the overabundance of circulating hemocytes and tumor formation. Many aspects of tumor development, such as the identity of the affected hematopoietic population and mechanisms of tumor growth are either not characterized or not well understood. The overall goal of this project was to understand the origin and development of hematopoietic tumor formation in Ubc9 mutants. Ubc9 is an E2 enzyme, which conjugates SUMO (small ubiquitin-like modifier) to a range of target proteins. Sumoylation targets vary in function from structural components to enzymes and transcription factors. Thus, sumoylation affects multiple cellular functions via modification of protein localization, stability or activity. Loss-of-function Ubc9 mutants of Drosophila exhibit severe defects in hematopoietic and immune tissues, including hemocyte overproliferation and tumor formation during larval stages. In this dissertation, we report that the hemolymph of Ubc9 mutants contains hematopoietic cells and structures that range from aggregates (composed of only few cells) to small and large tumors. The largest tumors are less than 1 mm3 in volume. Most cells and aggregates exhibit high ration of mitotic cells, but only a few of the largest tumors in the hemolymph contain actively dividing cells. Based on staining patterns and genetic rescue experiments, we propose that the large tumors are derived specifically from overgrown posterior lobes of the hematopoietic organ. The origin of smaller tumors and aggregates is less clear. Our data suggest that these structures likely derive from circulating hemocytes and fragments of dispersed anterior lobes. Microtumors in Ubc9 mutants arise from the highly-mitotic mutant stem/progenitor cells of the lymph gland. Loss of sumoylation cascade enzymes E1 (Aos1/Uba2), E2 (Ubc9), or E3 (PIAS) leads to loss of proliferative quiescence in hematopoietic precursors localized within the lymph gland. Proliferative quiescence of these precursors is at least in part mediated by the activity of the cyclin-dependent kinase inhibitor Dacapo/p21. Expression of Dacapo homolog, human p21, in the Ubc9 progenitor cells relieves tumor formation. These studies suggest that sumoylation provides a cell-intrinsic mechanism to preserve stem/progenitor cell states for stress response, immunity and development of the fly.
Biological processes are dynamic, requiring both simple and complex mechanisms that enable cells to adapt with the ever-changing environment. Ubiquitination is one of many posttranslational modifications that result in a change in cellular activity. Mono-ubiquitination, the addition of a single ubiquitin moeity leads to endocytosis and membrane trafficking, while the addition of a multiple ubiquitin chains primarily results in protein degradation. Rap/Fzr acts as an activator of the E3 ubiquitin ligase, Anaphase Promoting Complex (APC) which has been studied for its role in the timely degradation of cell cycle regulators. My thesis work focuses on novel roles Rap/Fzr during nervous system development and specifically investigates its role during glia development. My results show that Rap/Fzr regulates glia development through its interaction with Loco, an RGS protein and Nonstop, a ubiquitin specific protease. Bioinformatic analysis revealed that both Loco and Nonstop contain Destruction box (D-box) motifs and KEN box motifs, which are amino acid sequences used by Rap/Fzr for substrate recognition. My thesis work shows that Rap/Fzr targets Loco for ubiquitination, and subsequent degradation and thus, inhibits the formation of glia from dividing neuroblasts. Furthermore, Rap/Fzr together with Nonstop, regulates the migration and the endoreplication of glia cells.
Autism is a behaviorally defined neurodevelopmental disorder characterized by impairments in three main areas of social interaction, communication, and repetitive, restricted interests and behaviors. There has been an increase in the prevalence of autism with recent estimation of 1 in every 50 children diagnosed with autism. Though there is no single identifiable cause for autism, several studies have shown an increase in oxidative stress and decrease in antioxidants in autism. The role of environmental factors has also been implicated in autism. Bisphenol A (BPA) is a widely used chemical in the manufacturing of plastics, and its exposure has raised concerns in a variety of conditions. The present study with lymphoblastoid cells and Drosophila melanogaster identifies BPA as an environmental risk factor for the increased oxidative stress, mitochondrial dysfunction and behavioral impairments in lymphoblasts and Drosophila melanogaster. When lymphoblastoid cells were exposed to BPA, there was an increase in lipid peroxidation and free radicals (reactive oxygen species) and decrease in mitochondrial membrane potential generation suggesting BPA induced oxidative stress and mitochondrial dysfunction. The study also illustrates an increase in the mitochondrial DNA (mtDNA) copy number in the lymphoblasts in response to the BPA exposure. In neurodevelopmental disorders such as autism, behavior is an important component of the condition. We therefore attempted to detect behavioral modifications in Drosophila melanogaster following exposure to BPA. In this study, we used an open field assay to help identify disturbances in locomotion along with repetitive behavior in BPA-exposed flies. We also observed an abnormal social interaction between the BPA-exposed flies in a social setting. Along with the behavioral modifications, there was also an increase in the lipid peroxidation in the brains of the BPA-exposed flies. Furthermore there was also a delay in the development of the Drosophila embryos, although we did not detect any gross morphological changes in the peripheral nervous system of the embryos following BPA exposure. We have therefore demonstrated that Drosophila may be used as an animal model for complex neurodevelopmetal disorders, which have a poorly understood etiology.
Humulus lupulus L. (hops) is an agricultural crop valued for its inflorescences, commonly known as hop cones, which produce a diverse collection of secondary metabolites. Hop cones are most valued for their terpenophenolic contents, which are essential to beer production, and the subject of biomedical research. We studied two hop cultivars, Willamette and Zeus, over five stages of development, which were characterized by detailed flower morphology, gross cone measurements, and phytochemical quantitation. By combining morphological observations with phytochemical quantitation we produced an index to inform our developmentally dependent experiments. In order to understand these developmental processes and in an attempt to induce agronomically positive effects, we perturbed hop morphological and phytochemical development using enzyme inhibition. Prohexadione-calcium (Pro-Ca) is a known inhibitor of 2-oxoglutaric acid dependent dioxygenases present in the flavonoid, gibberellic acid, and ethylene biosynthetic pathways. We treated hops with Pro-Ca at each of the five time-points over two seasons; these time-points were later characterized as five developmental stages. Pro-Ca treatment induced significant increases in terpenophenolic content by 9.1-87.3%; however some treatments also induced significant decreases. Increases in cone biomass production by 1.5-19.6% were also measured in response to treatment in both seasons. Induced changes in cone biomass production and terpenophenolic accumulation were most dependent on cultivar and the developmental stage at which plants were treated. In a second series of experiments we conducted a targeted analysis of phenolic acids, flavonoids, and terpenophenolics over 22 days following a single Pro-Ca treatment conducted during early flowering. Terpenophenolics significantly increased following treatment, and coincided with changes in the flavonoid biosynthetic pathway including accumulation of metabolic precursors upstream from flavanone-3-hydroxylase, and decreases in flavonoid products downstream from flavanone-3-hydroxylase. In addition to changes in known compounds, marker analysis revealed the presence of two markers in treated samples not previously reported from hops. One of these markers has been tentatively identified as the antimicrobial compound luteoliflavan. This research provides insight into the relationship between secondary metabolic pathways in hops and indicates targets for future research into perturbation of metabolic pathways to increase medicinal and flavor compounds in hops.


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Warner Bros. Offers Details For Dark Knight Rises Blu-ray & DVD
Warner Bros. Home Entertainment Group has at last revealed the details for the Dec. 4 Blu-ray and DVD release of director Christopher Nolan's The Dark Knight Rises.
Warner Bros. Home Entertainment Group has at last revealed the details for the Dec. 4 Blu-ray and DVD release of director Christopher Nolan's The Dark Knight Rises.
Warner Bros. has announced that director Christopher Nolan's The Dark Knight Rises will be available on Blu-ray and DVD and for digital download on Dec. 3. Expect more details soon.
Contrary to earlier rumors it appears as if fans of director Christopher Nolan's Batman series won't get an extended edition of The Dark Knight Rises on Blu-ray. Instead, they'll have to be satisfied with the version they saw in theaters.
Rumors suggest The Dark Knight Rises director's cut and Blu-ray will include Bane origin scene and more footage of Liam Neeson as Ra's al Ghul.
The holiday weekend gave Marvel's The Avengers and Warner Bros.' The Dark Knight Rises the chance to surpass $1.5 billion and $1 billion worldwide, respectively.
After one week at the top, The Bourne Legacy falls to the second spot as Lionsgate's The Expendables 2 wins the North American box office with a $28.75 million opening weekend.
The Dark Knight Rises co-star Joseph Gordon-Levitt discusses the possibility of returning for another Batman movie. "I always choose scripts the same way," he says. "If it's a great script and a great filmmaker, then I'm interested."
A resurgent weekend at the box office finally unseated The Dark Knight, rocketing The Bourne Legacy and The Campaign to the top two spots.
Industry analysts expect Universal Pictures' The Bourne Legacy to topple The Dark Knight Rises from atop its box-office perch with a $25 million opening weekend.
With a global haul of $732 million, The Dark Knight Rises slipped past Ice Age: Continental Drift on Sunday to become the second-highest grossing film of the year, behind Marvel's The Avengers.
The Dark Knight Rises grossed another $36.4 million in its third weekend, easily beating new release Total Recall, which opened in North American theaters to just $26 million.
This weekend's Total Recall marks the last blockbuster release of the summer season, closing us out with a remake of a much-beloved movie from two decades earlier. Remakes, comic book movies and a misconceived toy movie: What's been your favorite of this summer's big blockbuster movies?


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Analyst Research
|Report Title
Flux Power Holdings Inc: Business description, financial summary, 3yr and interim financials, key statistics/ratios and historical ratio analysis.
Provider: Reuters Investment Profile
Provider: Wright Reports
Provider: Thomson Reuters StreetEvents
NYSE and AMEX quotes delayed by at least 20 minutes. NASDAQ delayed by at least 15 minutes. For a complete list of exchanges and delays, please click here.
Flux Power Holdings Inc Announces Executive Officer Changes
Flux Power Holdings Inc announced that Chris Anthony has tendered his resignation as Chief Executive Officer(CEO) and President, effective immediately, in order to return full time to his position as CEO of Epic Boats, LLC, a company he founded in 2005. Mr. Anthony, a founder of Flux Power, will remain on the Company's Board of Directors as an outside director and continue to provide on-going advisory services in this capacity. Flux Power's CFO, Ron Dutt, has been named interim Chief Executive Officer. Upon the closing of the proposed acquisition of KleenSpeed, its current CEO, Timothy Collins, will join the Board of Flux Power and assume Mr. Anthony's role of Executive Chairman.
Latest Developments forFlux Power Holdings Inc
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Seven performance categories of the Living Building Challenge have made their mark in green building and set future trends for bringing net-zero building to the next level.
Here are six simple steps you can take during your homebuying search to ensure the house you buy won't break the bank with high energy bills later.
The three-dimensional signs and billboards of science fiction movies are not just for the 2D screen anymore.
Power House, a strategic web game designed to reduce your energy consumption, has paired up with California utility provider PG&E to train you to use less energy in your household.
Is the curtain obsolete?
Heightened U-factor and SHGC requirements in a region encompassing nearly half the country had the window industry worried that Energy Star products would become too expensive to build with. Important discussions helped address those concerns.
Power House, a new Facebook game, effectively promotes lowering utility use so effectively that users demonstrate increased energy-efficient behavior immediately after playing the game.
In this video segment from the 2014 Remodeling Show | Deck Expo | JLC Live (R|D|J), Jeremy O'Brien breaks down building science principles that provide homeowners knowledge to decipher what goes on in the home, and allow professionals to guide customers in achieving the comfort they seek.
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If you like this, Harlequin recommends
- Blown Away
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At five months pregnant, Mona Grainger was facing danger on all fronts. With cattle rustlers driving her ranch to ruin, she needed a man ready for long hours and hard work. Enter Reed Bryson, who could ride, rope, kiss...and certainly handle a gun.
His new boss may have depended on him more than she'd liked, but Reed wasn't hired to do her dirty work. She could do that herself. He was there to defend her land and cool down the hot-headed sheriff, whose advances threatened everything Mona held dear. Now the lone cowboy had more than his honor to uphold--he had a petite, pregnant powerhouse running his senses wild.


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Floor Plans and Pricing
1 Bedroom
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Nice large apts with central air, balcony/patio, dishwasher, off street parking, bbq/picnic areas, play area, heated pool, basketball court, wifi in common areas.
2 Bedrooms
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Large roomy apts lots of amenities including wifi on premises, heated pool, bbq/picnic areas, basketball court. Dishwashers, patio/balcony, central air.
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Very large roomy clean apts with lots of amenities including WIFI on premises, central air, dishwashers, patio/balcony, bbq/picnic areas. Come by and view our lovely apts.
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Centennial Place Apartments in Greeley, CO
Thank you for your inquiry. We have Spacious 1 (one), 2 (two), and 3 (three) bedroom units. They Include: Central Air, Refrigerator, Stove, Dishwasher, Garbage Disposal. Patios with balconies and storage. We offer FREE WiFi, Heated Pool, Cubroom/Fitness Center, Basketball Court, Playground, Perqola, BBQ Grills, Laundry Facility, and On-Site Management. Our leases are 12 months.
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We believe school data to be accurate, but do not guarantee that. Please be sure to verify where your children will attend school before making your housing decision.
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Winnipeg Free Press - PRINT EDITION
PBS's Dust Bowl documentary history lesson, cautionary tale
Call it a history lesson, if you like. Or, perhaps, a warning.
Given the increased number of weather- and climate-related catastrophes in recent years, Ken Burns says it would be unwise to consider his latest PBS documentary series, The Dust Bowl, merely an examination of past events with no future implications.
"Conventional wisdom and shorthand history seem to always relegate the story of the Dust Bowl to just a handful of storms and an inevitable connection to John Steinbeck's The Grapes of Wrath," Burns said when he met with the press last summer during PBS's portion of the U.S. networks' semi-annual press tour in Los Angeles. "We quickly discovered, however, a much more complex, tragic, and interesting story that continues to resonate today. This is a cautionary tale... but is still a story of our complex and often fraught relationship with the land.
"This is the story of the greatest man-made ecological disaster in American history, a 10-year apocalypse punctuated by hundreds, hundreds of terrifying black blizzards that killed not only farmers' crops and cattle, but their children, too.
"And all of this was superimposed on the greatest economic catastrophe in the history of the world, the Depression. It was an epic of human pain and suffering, but it is also the story of heroic perseverance."
The Dust Bowl, a two-part, four-hour documentary that airs Sunday and Monday at 8 p.m. on Prairie Public TV, is American-history storytelling in the classic Ken Burns style, employing a seamless mix of still images and grainy motion-picture footage laid over a period soundtrack. In addition to the expert perspectives featured in Burns's earlier projects, such as The Civil War and Jazz, The Dust Bowl also includes the vivid recollections of several people who were eyewitnesses to the fury of the Dirty '30s.
"More than any other film we have made, it is an oral history populated less by historians and experts than those who survived those horrible days," Burns says. What's particularly interesting about this documentary project is that unlike The Civil War or Jazz or Baseball, which were distinctly and limitedly American stories, The Dust Bowl is an examination of an historical event whose impact straddled the Canada-U.S. border.
The same economic, agricultural and ecological conditions that Burns explores from an American perspective were also present on the Canadian Prairies -- first, the stock-market crash of 1929 caused wheat prices to plummet, and then the decade-long drought and dust storms that began in 1930 turned Canada's wheat belt into an unproductive wasteland.
"Our film is about nature, but it's also about human nature," said Dust Bowl co-producer and writer Dayton Duncan. "We believe that we can ignore the limits of the environment, and of nature, if it suits our purposes, and that if things are going on a roll, they will continue to go on a roll.
"We are human beings, and we think ... that either we can control nature or we can just ignore nature. We can do neither, and that's what the cautionary tale is about."
-- -- --
Also new on the historical-documentary front is the new History TV series Mankind: The Story of All of Us, an ambitious 12-hour project that examines the against-the-odds triumph of our unique species on our unique planet.
The series, which premieres Monday at 8 p.m. on History, breaks the story of humankind's existence into chapters defined by the accomplishments that allowed us to survive and advance. Monday's première includes two segments -- Inventors, which starts with early man's creation of rudimentary tools and clothing and follows through to explore agricultural techniques, city building and the ever-advancing machinery of war; and Iron Men, which focuses on the discovery and refinement of the metal that fundamentally altered the course of human history.
It's a lot to take in, but Mankind: The History of All of Us looks to be a thoughtful attempt at addressing a story that many would consider too big to be told on TV.
email@example.com Twitter: @BradOswald
The Dust Bowl
Produced by Ken Burns
Sunday and Monday at 8 p.m.
Mankind: The Story of All of Us
Narrated by Josh Brolin
Monday at 8 p.m.
Republished from the Winnipeg Free Press print edition November 17, 2012 G5
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Retail investors fell out of love with US bank loans this year, but demand from issuers of collateralized loan obligations (CLOs) has remained strong. New regulations may change that. Should investors be concerned? We think so. (more…)
high yield bank loans
Are Bank-Loan Investors Getting What They Bargained For?
Ashish Shah (pictured) and Ivan Rudolph-Shabinsky
Investors who chose high-yield bank loans over high-yield bonds earlier this year, expecting to be insulated against rising rates, might be surprised to find that bonds might have worked out better. (more…)
Looking Under the Hood at High-Yield Bank Loans
Ashish Shah, Gershon Distenfeld and Ivan Rudolph-Shabinsky
When you're shopping for a car, you take a look under the hood to see what makes the thing run. You also check out the car's features: does it have heated seats, a rear-view camera, a GPS? (more…)
High-Yield Bank Loans: Look Before You Leap
Ashish Shah, Gershon Distenfeld and Ivan Rudolph-Shabinsky
High-yield bank loans are a hot topic again in capital markets, with features touted as ideal for today's environment. But we think it makes sense to take a closer look at what bank loans really are—and aren't. In our opinion, there are a few holes in the case for piling into high-yield loans. (more…)


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World presses Europe on debt crisis
Sep 24, 2011, 10:07 a.m.
A senior lawmaker from German Chancellor Angela Merkel's conservatives said the euro zone's permanent rescue mechanism should be introduced sooner than mid-2013 to beef up private creditors' response to the Greek debt crisis.
Geithner and Fed Chairman Ben Bernanke met on Friday with top officials from the ECB and other national central banks from Europe, in part to discuss international financial regulatory reform.
In a reminder of how sensitive some European officials are to the ECB taking a more active role in the crisis, a board member of Germany's central bank, the Bundesbank, suggested the time was coming for the ECB to stop buying government bonds.
"I think the time is coming for this to stop," said Joachim Nagel, adding that the ECB's bond buying was only supposed to be a temporary measure until the euro zone's bailout fund is beefed up with powers to buy bonds and lend to governments.
Another top ECB official sought to quash growing expectations that Greece will eventually default.
ECB Governing Council member Athanasios Orphanides said the idea of a Greek default was "surreal" but warned that it could occur as the result of a "political accident."
Greece is in tense talks with the IMF and European authorities to secure a new 8 billion-euro installment of its rescue package.
In return, Athens has pledged deep austerity measures but negotiators are frustrated at what they say is Greece's slow reform pace. October's loan payment, however, is still widely expected to be made. The next installment is due in December.
Germany, as the strongest economy in Europe, plays a central role in any effort to curb a debt crisis but public opinion there has turned against further big bailouts for fellow euro zone countries.
Finance Minister Wolfgang Schaeuble said on Saturday he will meet his Greek counterpart, Evangelos Venizelos, while in Washington for the IMF meetings.
"We are permanently in contact and talk a lot," Schaeuble said, a day after Merkel sought to dampen speculation about the chances of a Greek default by saying it was not an option for her.
"The damage would be impossible to predict," Merkel warned members of her political party in Germany.
Greece's Venizelos was quoted by two newspapers on Friday as saying an orderly default with a 50 percent haircut for bondholders was one way to resolve the heavily indebted euro zone nation's cash crunch.
Speaking to Reuters on Saturday, Venizelos said Greece would stick to its austerity commitments.
(Additional reporting by IMF reporting team in Washington, Sakari Suoninen in Frankfurt, Writing by Glenn Somerville and William Schomberg; Editing by Andrea Ricci)
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Some parents may avoid traveling with babies because they fear the challenge. The truth is, with the right preparation, travel with an infant can be smooth sailing. Take this 10-question quiz to see if you're ready to hit the road with your little one in tow.
By Danielle Ryan
How will your accommodate your infant's routine while you're on the road?