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From Wikipedia, the free encyclopedia MOSFET MOSFET transistor, and is almost synonymous with MOSFET, though it can refer to FETs with a gate insulator that is not oxide. Some prefer to use "IGFET" when referring to devices with polysilicon gates, but most still call them MOSFETs. Composition Two power MOSFETs in the surface-mount package D2PAK. Each of these components can sustain a blocking voltage of 120 volts and a continuous current of 30 amperes. A matchstick is pictured for scale. The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a device used to amplify or switch electronic signals. The basic principle of the device was first proposed by Julius Edgar Lilienfeld in 1925. The MOSFET includes a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common. Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two gates and three source/drain nodes are labeled. Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, have begun to use a mixture of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good semiconductor-to-insulator interfaces and thus are not suitable for MOSFETs. However there continues to be research on how to create insulators with acceptable electrical characteristics on other semiconductor material. To overcome power consumption increase due to gate current leakage, high-κ dielectric is replacing silicon dioxide as the gate insulator, and metal gates are making a comeback by replacing polysilicon (see Intel announcement[1]). The gate is separated from the channel by a thin insulating layer of what was traditionally silicon dioxide, but more advanced technologies uses silicon oxynitride. Some companies have started to introduce a high-κ Etymology The 'metal' in the name is now often a misnomer because the previously metal gate material is now a layer of polysilicon (polycrystalline silicon; why polysilicon is used will be explained below). Previously aluminium was used as the gate material until the 1980s when polysilicon became dominant, owing to its capability to form self-aligned gates. However the metallic gates are making a comeback. It is difficult to increase the speed of operation of transistors without metal gates. IGFET is a related, more general term meaning insulated-gate field-effect 1 From Wikipedia, the free encyclopedia dielectric + metal gate combination in the 45 nanometer node. When a voltage is applied between the gate and source terminals, the electric field generated penetrates through the oxide and creates a so-called "inversion layer" or channel at the semiconductor-insulator interface. The inversion channel is of the same type – Ptype or N-type – as the source and drain, so it provides a channel through which current can pass. Varying the voltage between the gate and body modulates the conductivity of this layer and makes it possible to control the current flow between drain and source. MOSFET Nchan Circuit symbols A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for enhancement mode and a solid line for depletion mode. Another line is drawn parallel to the channel for the gate. The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (Nchannel in P-well or P-substrate) has the arrow pointing in (from the bulk to the channel). If the bulk is connected to the source (as is generally the case with discrete devices) it is sometimes angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS, alternatively an arrow on the source (not depicted below) may be used in the same way as for bipolar transistors (out for NMOS, in for PMOS). Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols (Note, the 2nd and 4th columns of images should be flipped across y=0, so the higher voltages are above the lower voltages. The JFET symbols should be checked for correctness.): MOSFET dep For the symbols in which the bulk, or body, terminal is shown, it is here shown internally connected to the source. This is a typical configuration, but by no means the only important configuration. In general, the MOSFET is a four-terminal device, and in integrated circuits many of the MOSFETs share a body connection, not necessarily connected to the source terminals of all the transistors. JFET MOSFET enh MOSFET operation Example application of an N-Channel MOSFET. When the switch is pushed the LED lights up.[2] For the operation of MOS devices discussed next, an authoritative reference is Tsividis.[3] Metal–oxide–semiconductor structure Pchannel Metal–oxide–semiconductor structure on Ptype silicon 2 From Wikipedia, the free encyclopedia A traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon dioxide (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline silicon (the latter is commonly used). As the silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor. When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage, VGB, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions (see doping (semiconductor)). If VGB is high enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator (unlike the MOSFET where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region). Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions. MOSFET Cross section of an NMOS without channel formed: OFF state Cross section of an NMOS with channel formed: ON state (MISFET). The MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a '+' sign after the type of doping. If the MOSFET is an n-channel or nMOS FET, then the source and drain are 'n+' regions and the body is a 'p' region. As described above, with sufficient gate voltage, MOSFET structure and channel formation A metal–oxide–semiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to as oxide) are employed the device may be referred to as a metal–insulator–semiconductor FET 3 From Wikipedia, the free encyclopedia above a threshold voltage value, electrons from the source (and possibly also the drain) enter the inversion layer or n-channel at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small subthreshold leakage current can flow between the source and the drain. If the MOSFET is a p-channel or pMOS FET, then the source and drain are 'p+' regions and the body is a 'n' region. When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain. The source is so named because it is the source of the charge carriers (electrons for nchannel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel. The device may comprise a Silicon On Insulator (SOI) device in which a Buried OXide (BOX) is formed below a thin semiconductor layer. If the channel region between the gate dielectric and a Buried OXide (BOX) region is very thin, the very thin channel region is referred to as an Ultra Thin Channel (UTC) region with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. Alternatively, the device may comprise a SEMiconductor On Insulator (SEMOI) device in which other semiconductors than silicon are employed. Many alternative semicondutor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as Raised Source/Drain (RSD) regions. MOSFET voltages at the terminals. In the following discussion, a simplified algebraic model is used that is accurate only for old technology. Modern MOSFET characteristics require computer models that have rather more complex behavior. For example, see Liu [4] and the device modeling list in [1]. For an enhancement-mode, n-channel MOSFET the three operational modes are: Cut-off or Sub-threshold or Weak Inversion Mode When VGS < Vth: where Vth is the threshold voltage of the device. According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. In reality, the Boltzmann distribution of electron energies allows some of the more energetic electrons at the source to enter the channel and flow to the drain, resulting in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turnedoff switch, there is a weak-inversion current, sometimes called subthreshold leakage. In weak inversion the current varies exponentially with gate-to-source bias VGS as given approximately by:[5][6] , where ID0 = current at VGS = Vth and the slope factor n is given by n = 1 + CD / COX, with CD = capacitance of the depletion layer and COX = capacitance of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once VDS > > VT, but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage Vth for this mode is defined as the gate voltage at which a selected value of current ID0 occurs, for Modes of operation The operation of a MOSFET can be separated into three different modes, depending on the 4 From Wikipedia, the free encyclopedia example, ID0 = 1 μA, which may not be the same Vth-value used in the equations for the following modes. Some micropower analog circuits are designed to take advantage of subthreshold conduction.[7][8][9] By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductanceto-current ratio, namely: gm / ID = 1 / (nVT), almost that of a bipolar transistor. Unfortunately, bandwidth is low due to the low drive currents. Also, the subthreshold I-V relation depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization of circuits operating in the subthreshold mode.[10][11] MOSFET Cross section of a MOSFET operating in the linear (Ohmic) region; strong inversion region present even near drain Cross section of a MOSFET operating in the saturation (active) region; channel exhibits pinch-off near drain voltages. The current from drain to source is modeled as: where μn is the charge-carrier effective mobility, W is the gate width, L is the gate length and Cox is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest. MOSFET drain current vs. drain-to-source voltage for several values of VGS − Vth; the boundary between linear (Ohmic) and saturation (active) modes is indicated by the upward curving parabola Triode Mode or Linear Region (also referred to as the Ohmic Mode[12][13]) When VGS > Vth and VDS < ( VGS Vth ) The transistor is turned on, and a channel has been created which allows current to flow between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain Saturation Mode (also referred to as the Active Mode[14][15] ) When VGS > Vth and VDS > ( VGS Vth ) The switch is turned on, and a channel has been created, which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel 5 From Wikipedia, the free encyclopedia region near the drain. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage, and modeled very approximately as: MOSFET The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is: , where the combination Vov = VGS - Vth is called the overdrive voltage.[16] Another key design parameter is the MOSFET output resistance rO given by: . If λ is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits. As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in VGS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In addition, the output current is affected by drain-induced barrier lowering of the threshold voltage. Ohmic contact to body to insure no body bias; top left:subthreshold, top right:Ohmic mode, bottom left:Active mode at onset of pinch-off, bottom right: Active mode well into pinch-off - channel length modulation evident effect parameter, and 2φ is the surface potential parameter. The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect". [17] The primacy of MOSFETs In 1959, Dawon Kahng, Ernesto Labate, and Martin M. (John) Atalla at Bell Labs invented the metal–oxide–semiconductor field-effect transistor (MOSFET).[18] Operationally and structurally different from the bipolar junction transistor,[19] the MOSFET was made by putting an insulating layer on the surface of the semiconductor and then placing a metallic gate electrode on that. It used crystalline silicon for the semiconductor and a thermally oxidized layer of silicon dioxide for the insulator. The silicon MOSFET did not generate localized electron traps at the interface between the silicon and its native oxide layer, and thus was inherently free from the trapping and scattering of carriers that had impeded the performance of earlier field-effect transistors. Following the (expensive) development of clean rooms to reduce contamination to levels never before thought necessary, and of photolithography[20] and the planar process to allow circuits to be made in very few steps, the Si − SiO2 system possessed such technical attractions as low cost of production (on a per circuit basis) and ease of integration. Largely because of these two factors, the MOSFET has become the most widely used type of integrated circuit. A Body effect The body effect describes the changes in the threshold voltage by the change in the source-bulk voltage, approximated by the following equation: , where VTN is the threshold voltage with substrate bias present, and VTO is the zero-VSB value of threshold voltage, γ is the body 6 From Wikipedia, the free encyclopedia historical timeline of semiconductors can be found at computerhistory.org. MOSFET Analog The MOSFET's advantages in most digital circuits do not translate into supremacy in all analog circuits. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time outside the switching region, while analog circuits depend on MOSFET behavior held precisely in the switching region of operation. The bipolar junction transistor (BJT) has traditionally been the analog designer's transistor of choice, due largely to its higher transconductance and its higher output impedance (drain-voltage independence) in the switching region. Nevertheless, MOSFETs are widely used in many types of analog circuits because of certain advantages. The characteristics and performance of many analog circuits can be designed by changing the sizes (length and width) of the MOSFETs used. By comparison, in most bipolar transistors the size of the device does not significantly affect the performance. MOSFETs' ideal characteristics regarding gate current (zero) and drain-source offset voltage (zero) also make them nearly ideal switch elements, and also make switched capacitor analog circuits practical. In their linear region, MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than BJTs. In high power circuits, MOSFETs sometimes have the advantage of not suffering from thermal runaway as BJTs do. Also, they can be formed into capacitors and gyrator circuits which allow op-amps made from them to appear as inductors, thereby allowing all of the normal analog devices, except for diodes (which can be made smaller than a MOSFET anyway), to be built entirely out of MOSFETs. This allows for complete analog circuits to be made on a silicon chip in a much smaller space. Some ICs combine analog and digital MOSFET circuitry on a single mixed-signal integrated circuit, making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and Silicon-On-Insulator (SOI). The main advantage of BJTs versus MOSFETs in the analog design process is the ability of BJTs to handle a larger current in a smaller space. Fabrication processes exist that incorporate BJTs and MOSFETs into a single CMOS circuits The principal reason for the success of the MOSFET was the development of digital CMOS logic,[21] which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in integrated circuits since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no power is consumed, except when the inputs to logic gates are being switched. CMOS accomplishes this current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation. Digital and analog CMOS applications are described below. Digital The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor. A timeline can be found at computerhistory.org.[22] A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single MOSFET output to drive a considerable number of MOSFET inputs. Bipolar transistor-based logic (such as TTL) does not have such a high fanout capacity. This isolation also makes it easier for the designers to ignore to some extent loading effects between logic stages independently. That extent is defined by the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases. 7 From Wikipedia, the free encyclopedia device. Mixed-transistor devices are called Bi-FETs (Bipolar-FETs) if they contain just one BJT-FET and BiCMOS (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density. BJTs have some advantages over MOSFETs for at least two digital applications. Firstly, in high speed switching, they do not have the "larger" capacitance from the gate, which when multiplied by the resistance of the channel gives the intrinsic time constant of the process. The intrinsic time constant places a limit on the speed a MOSFET can operate at because higher frequency signals are filtered out. Widening the channel reduces the resistance of the channel, but increases the capacitance by the exact same amount. Reducing the width of the channel increases the resistance, but reduces the capacitance by the same amount. R*C=Tc1, 0.5R*2C=Tc1, 2R*0.5C=Tc1. There is no way to minimize the intrinsic time constant for a certain process. Different processes using different channel lengths, channel heights, gate thicknesses and materials will have different intrinsic time constants. This problem is mostly avoided with a BJT because it does not have a gate. The second application where BJTs have an advantage over MOSFETs stems from the first. When driving many other gates, called fanout, the resistance of the MOSFET is in series with the gate capacitances of the other FETs, creating a secondary time constant. Delay circuits use this fact to create a fixed signal delay by using a small CMOS device to send a signal to many other, many times larger CMOS devices. The secondary time constant can be minimized by increasing the driving FET's channel width to decrease its resistance and decreasing the channel widths of the FETs being driven, decreasing their capacitance. The drawback is that it increases the capacitance of the driving FET and increases the resistance of the FETs being driven, but usually these drawbacks are a minimal problem when compared to the timing problem. BJTs are better able to drive the other gates because they can output more current than MOSFETs, allowing for the FETs being driven to charge faster. Many chips use MOSFET inputs and BiCMOS outputs (see above). MOSFET MOSFET scaling Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel lengths were once several micrometres, but modern integrated circuits are incorporating MOSFETs with channel lengths of less than a tenth of a micrometre. Indeed Intel began production of a process featuring a 65 nm feature size (with the channel being even shorter) in early 2006. Until the late 1990s, this scaling resulted in great improvement in MOSFET circuit operation. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower output resistance, discussed below). The semiconductor industry maintains a "roadmap", the ITRS [23], describing forecasts and technology barriers to development for device sizes updated approximately annually. The 2006 roadmap[24] refers to devices with a physical gate length of 13 nm in size by the year 2013. Reasons for MOSFET scaling Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example the number of MOSFETs in a microprocessor fabricated in a 45 nm technology is twice as large as in a 65 nm chip. This doubling of the transistor count was first observed by Gordon Moore in 1965 and is commonly referred to as Moore's law.[25] It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET 8 From Wikipedia, the free encyclopedia MOSFET leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.[26][27][28] Increased gate-oxide leakage The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption. Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. Trend of Intel CPU transistor gate length that requires all device dimensions to reduce proportionally. The main device dimensions are the transistor length, width, and the oxide thickness, each (used to) scale with a factor of 0.7 per node. This way, the transistor channel resistance does not change with scaling, while gate capacitance is cut by a factor of 0.7. Hence, the RC delay of the transistor scales with a factor of 0.7. While this has been traditionally the case for the older technologies, for the state-ofthe-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant. Difficulties arising due to MOSFET size reduction Producing MOSFETs with channel lengths much smaller than a micrometre is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometers, has created operational problems. Higher subthreshold conduction Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the "on" case and low current in the "off" case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide Increased junction leakage To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth,[29][30] all to decrease drain-induced barrier lowering (see the section on junction design). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically 9 From Wikipedia, the free encyclopedia active defects must be curtailed[31] increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage. MOSFET velocity saturation of the carriers, limiting the current and the transconductance. Interconnect capacitance Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the wires connecting different parts of the chip) is becoming a large percentage of capacitance.[32] [33] Signals have to travel through the interconnect, which leads to increased delay and lower performance. Heat production MOSFET version of gain-boosted current mirror; M1 and M2 are in active mode, while M3 and M4 are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance The ever-increasing density of MOSFETs on an integrated circuit is creating problems of substantial localized heat generation that can impair circuit operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors. Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the heatsink is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device. Lower output resistance For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the cascode and cascade amplifiers, or by feedback circuitry using operational amplifiers, for example a circuit like that in the adjacent figure. Process variations With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See design for manufacturability, Lower transconductance The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is 10 From Wikipedia, the free encyclopedia reliability engineering, six sigma and statistical process control.[34] MOSFET metal–insulator interfaces contain significant levels of defects which can lead to Fermi-level pinning, charging, or other phenomena that ultimately degrade device performance. 3. In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better performing transistors. Such high temperature steps would melt some metals, limiting the types of metals that could be used in a metalgate based process. While polysilicon gates have been the de facto standard for the last twenty years, they do have some disadvantages, which have led to the announcement of their replacement by metal gates. These disadvantages include: 1. Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. In order to improve conductivity further, sometimes a high temperature metal such as tungsten, titanium, cobalt, and more recently nickel, is alloyed with the top layers of the polysilicon. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide, self-aligned silicide. 2. When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the socalled poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem, a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride are used, usually in conjunction with high-k dielectrics. An alternative is to use fully- Modeling challenges Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult. MOSFET construction Gate material The primary criterion for the gate material is that it is a good conductor. Highly-doped polycrystalline silicon is an acceptable, but certainly not ideal conductor, and it also suffers from some more technical deficiencies in its role as the standard gate material. Nevertheless, there are several reasons favoring use of polysilicon as a gate material: 1. The threshold voltage (and consequently the drain to source on-current) is modified by the work function difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same bandgap as the underlying silicon channel, it is quite straightforward to tune the work function, so as to achieve low threshold voltages for both NMOS and PMOS devices. By contrast the work functions of metals are not easily modulated, so tuning the work function to obtain low threshold voltages becomes a significant challenge. Additionally, obtaining low threshold devices on both PMOS and NMOS devices would likely require the use of different metals for each device type, introducing additional complexity to the fabrication process. 2. The Silicon-SiO2 interface has been well studied and is known to have relatively few defects. By contrast many 11 From Wikipedia, the free encyclopedia silicided polysilicon gates, and the process is referred to as FUSI. MOSFET Insulator As devices are made smaller, insulating layers are made thinner, and at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place. To reduce the resulting leakage current, the insulator can be made thicker by choosing a material with a higher dielectric constant. To see how thickness and dielectric constant are related, note that Gauss' law connects field to charge as: , with Q = charge density, κ = dielectric constant, ε0 = permittivity of empty space and E = electric field. From this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased. The voltage on the gate is given by: MOSFET showing shallow junction extensions, raised source and drain and halo implant. Raised source and drain separated from gate by oxide spacers. using shallow junction extensions. In addition, halo doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions.[35] The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon. [36] These various features of junction design are shown (with artistic license) in the figure. Junction leakage is discussed further in the section increased junction leakage. , with VG = gate voltage, Vch = voltage at channel side of insulator, and tins = insulator thickness. This equation shows the gate voltage will not increase when the insulator thickness increases, provided κ increases to keep tins /κ = constant (see the article on high-κ dielectrics for more detail, and the section in this article on gate-oxide leakage). The insulator in a MOSFET is a dielectric which can in any event be silicon oxide, but many other dielectric materials are employed. The generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the MOSFET. Other MOSFET types Dual gate MOSFET The dual gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small signal devices in radio frequency applications where the second gate is normally used for gain control or mixing and frequency conversion. Junction design The source-to-body and drain-to-body junctions are the object of much attention because of three major factors: their design affects the current-voltage (I-V) characteristics of the device, lowering output resistance, and also the speed of the device through the loading effect of the junction capacitances, and finally, the component of stand-by power dissipation due to junction leakage. The drain induced barrier lowering of the threshold voltage and channel length modulation effects upon I-V curves are reduced by FinFET A double-gate FinFET device. 12 From Wikipedia, the free encyclopedia The Finfet, see figure to right, is a double gate device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. MOSFET Depletion-mode MOSFETs There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. In order to control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch.[2] Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolars in RF front-ends such as in TV sets. Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by Philips (dated 1980s), whose derivatives are still used in AGC and RF mixer front-ends. Cross section of a Power MOSFET, with square cells. A typical transistor is constituted of several thousand cells a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage. It is worth noting that power MOSFETs with lateral structure are mainly used in high-end audio amplifiers. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications. NMOS logic n-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the 1980s to become the preferred process for digital chips. DMOS DMOS stands for double-diffused metal–oxide–semiconductor. Most of the power MOSFETs are made using this technology. MOSFET analog switch MOSFET analog switches use the MOSFET channel as a low–on-resistance switch to pass analog signals when on, and as a high impedance when off. Signals flow in both directions across a MOSFET switch. In this application the drain and source of a MOSFET exchange places depending on the voltages of each electrode compared to that of the gate. For a simple MOSFET without an integrated diode, the source is the more negative side for an NMOS or the more positive side for a P-MOS. All of these switches are limited on what Power MOSFET Power MOSFETs have a different structure than the one presented above.[37] As with all power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In 13 From Wikipedia, the free encyclopedia signals they can pass or stop by their gatesource, gate-drain and source-drain voltages, and source-to-drain currents; exceeding the voltage limits will potentially damage the switch. MOSFET voltage limits for both FETs. Also, the P-MOS is typically three times the width of the NMOS so the switch will be balanced. Tri-state circuitry sometimes incorporates a CMOS MOSFET switch on its output to provide for a low ohmic, full range output when on and a high ohmic, mid level signal when off. Single-type MOSFET switch This analog switch uses a four-terminal simple MOSFET of either P or N type. In the case of an N-type switch, the body is connected to the most negative supply (usually GND) and the gate is used as the switch control. Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An N-MOS switch passes all voltages less than (Vgate–Vtn). When the switch is conducting, it typically operates in the linear (or Ohmic) mode of operation, since the source and drain voltages will typically be nearly equal. In the case of a P-MOS, the body is connected to the most positive voltage, and the gate is brought to a lower potential to turn the switch on. The P-MOS switch passes all voltages higher than (Vgate+Vtp). Threshold voltage (Vtp) is typically negative in the case of P-MOS. A P-MOS switch will have about three times the resistance of an N-MOS device of equal dimensions because electrons have about three times the mobility of holes in silicon. References and notes Dual-type (CMOS) MOSFET switch This "complementary" or CMOS type of switch uses one P-MOS and one N-MOS FET to counteract the limitations of the singletype switch. The FETs have their drains and sources connected in parallel, the body of the P-MOS is connected to the high potential (VDD) and the body of the N-MOS is connected to the low potential (Gnd). To turn the switch on the gate of the P-MOS is driven to the low potential and the gate of the N-MOS is driven to the high potential. For voltages between (VDD–Vtn) and (Gnd+Vtp) both FETs conduct the signal, for voltages less than (Gnd+Vtp) the N-MOS conducts alone and for voltages greater than (VDD–Vtn) the PMOS conducts alone. The only limits for this switch are the gate-source, gate-drain and source-drain [1] "Intel 45nm Hi-k Silicon Technology". http://www.intel.com/technology/ architecture-silicon/45nm-core2/ index.htm. [2] "Using a MOSFET as a Switch". http://brunningsoftware.co.uk/FET.htm. 090507 brunningsoftware.co.uk [3] Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor (Second Edition ed.). New York: McGraw-Hill. ISBN 0-07-065523-5. http://worldcat.org/ isbn/0070655235. [4] William Liu (2001). MOSFET Models for SPICE Simulation. New York: WileyInterscience. ISBN 0-471-39697-4. http://worldcat.org/isbn/0471396974. [5] P R Gray, P J Hurst, S H Lewis, and R G Meyer (2001). Analysis and Design of Analog Integrated Circuits (Fourth Edition ed.). New York: Wiley. p. 66-67. ISBN 0-471-32168-0. http://worldcat.org/ isbn/0471321680. [6] P. R. van der Meer, A. van Staveren, A. H. M. van Roermund (2004). Low-Power Deep Sub-Micron CMOS Logic: Subthreshold Current Reduction. Dordrecht: Springer. p. 78. ISBN 1402028482. http://books.google.com/ books?id=nyken8ivkb8C&pg=PA78&dq=weak+inve tRbG1cSjQBemdM22PgU. [7] Leslie S. Smith, Alister Hamilton (1998). Neuromorphic Systems: Engineering Silicon from Neurobiology. World Scientific. p. 52-56. ISBN 9810233779. http://books.google.com/ books?id=kWSXEHyQL9sC&pg=PA55&dq=subthres [8] Satish Kumar (2004). Neural Networks: A Classroom Approach. Tata McGrawHill. p. 688. ISBN 0070482926. http://books.google.com/ books?id=GJQh-2p6TvgC&pg=PA688&dq=neuromor [9] Manfred Glesner, Peter Zipf, Michel Renovell (2002). Field-programmable Logic and Applications: 12th International Conference. Dordrecht: 14 From Wikipedia, the free encyclopedia MOSFET Springer. p. 425. ISBN 3540441085. [20] Computer History Museum - The Silicon http://books.google.com/ Engine | 1955 - Photolithography books?id=fneXs6IY2-oC&pg=PA425&dq=analog+array+subthreshold&as_brr=0&sig=pZhV3OYe7YS Techniques Are Used to Make Silicon [10] Sandeep K. Shukla, R. Iris Bahar (2004). Devices Nano, Quantum and Molecular [21] Computer History Museum - The Silicon Computing. Springer. p. 10 and Fig. 1.4, Engine | 1963 - Complementary MOS p. 11. ISBN 1402080670. Circuit Configuration is Invented http://books.google.com/ [22] Computer History Museum - Exhibits books?id=lLvo1iMGhJgC&pg=PA10&dq=subthreshold+%22process+variation%22&as_brr=0&sig=Microprocessors oK8URqQwvDqmxjr7V4bhuOBtS4. [23] "International Technology Roadmap for [11] Ashish Srivastava, Dennis Sylvester, Semiconductors". http://www.itrs.net. David Blaauw (2005). Statistical Analysis [24] "Process Integration, Devices, and and Optimization For VLSI: Timing and Structures". International Technology Power. Springer. p. 135. ISBN Roadmap for Semiconductors: 2006 0387257381. http://books.google.com/ Update. http://www.itrs.net/Links/ books?id=WqsQTyOu5jwC&pg=PA9&dq=%22variation+in+leakage+current%22&as_brr=0&sig=6c 2006Update/FinalToPost/ PnNvk0bE7zPYViDSjU#PPA135,M1. 04_PIDS2006Update.pdf. [12] C Galup-Montoro & Schneider MC [25] "1965 – "Moore's Law" Predicts the (2007). MOSFET modeling for circuit Future of Integrated Circuits". Computer analysis and design. London/Singapore: History Museum. World Scientific. pp. 83. ISBN http://www.computerhistory.org/ 981-256-810-7. http://worldcat.org/isbn/ semiconductor/timeline/ 981-256-810-7. 1965-Moore.html. [13] Norbert R Malik (1995). Electronic [26] Kaushik Roy, Kiat Seng Yeo (2004). Low circuits: analysis, simulation, and design. Voltage, Low Power VLSI Subsystems. Englewood Cliffs, NJ: Prentice Hall. McGraw-Hill Professional. Fig. 2.1, p. 44. pp. 315–316. ISBN 0-02-374910-5. ISBN 007143786X. http://worldcat.org/isbn/0-02-374910-5. http://books.google.com/ [14] PR Gray, PJ Hurst, SH Lewis & RG books?id=jXm4pNxCSCYC&printsec=frontcover&dq Meyer. §1.5.2 p. 45. ISBN 0-471-32168-0. IafjcoHio7vmvpQ#PPA44,M1. http://worldcat.org/isbn/0-471-32168-0. [27] Kaushik Roy, Kiat Seng Yeo (2004). Low [15] A. S. Sedra and K.C. Smith (2004). Voltage, Low Power VLSI Subsystems. Microelectronic circuits (Fifth Edition McGraw-Hill Professional. Fig. 1.1, p. 4. ed.). New York: Oxford. pp. 552. ISBN ISBN 007143786X. 0-19-514251-9. http://worldcat.org/isbn/ http://books.google.com/ 0-19-514251-9. books?id=jXm4pNxCSCYC&pg=PA4&dq=Energy+sw [16] A. S. Sedra and K.C. Smith. p. 250, Eq. OzbVgLa_4pC0do1pkaZeo. 4.14. ISBN 0-19-514251-9. [28] Dragica Vasileska, Stephen Goodnick http://worldcat.org/isbn/0-19-514251-9. (2006). Computational Electronics. [17] Body effect Morgan & Claypool. p. 103. ISBN [18] "1960 – Metal Oxide Semiconductor 1598290568. http://books.google.com/ (MOS) Transistor Demonstrated: John books?id=DBPnzqy5Fd8C&pg=PA103&dq=MOSFET Atalla and Dawon Kahng fabricate [29] http://frontiersemi.com/pdf/papers/ working transistors and demonstrate the RsLransist.pdf Frontier Semiconductor first successful MOS field-effect Paper amplifier (U.S. Patent 3,102,230 filed in [30] Wai-Kai Chen (2006). The VLSI 1960, issued in 1963)". Handbook. CRC Press. Fig. 2.28, p. 2-22. http://www.computerhistory.org/ ISBN 084934199X. semiconductor/timeline/1960-MOS.html. http://books.google.com/ [19] Computer History Museum - The Silicon books?id=NDdsjtTLTd0C&pg=PT49&lpg=PT49&dq= Engine "Conception of the Junction sCYYSP0k&sig=ZvFajEiopwY89nT05YTmX114Lf4#P Transistor". 1948. [31] A Comparison Of Spike, Flash, Sper and http://www.computerhistory.org/ Laser Annealing For 45nm CMOS: semiconductor/timeline/ http://www.mrs.org/s_mrs/ 1948-conception.html Computer History sec_subscribe.asp?CID=2593&DID=109911&action= Museum - The Silicon Engine. 15 From Wikipedia, the free encyclopedia MOSFET [32] VLSI wiring capacitance http://www.research.ibm.com/journal/rd/ • BSIM 293/ibmrd2903G.pdf • Transistor models [33] D Soudris, P Pirsch, E Barke (Editors) (2000). Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop). • An introduction to depletion-mode Springer. p. 38. ISBN 3540410686. MOSFETs http://books.google.com/ • MOSFET Process Step by Step A Flash books?id=TGQxMLsGzVUC&pg=PA38&lpg=PA38&dq=%22wiring+capacitance%22&source=web&o slide showing the fabricating process of a [34] Michael Orshansky, Sani Nassif, Duane MOSFET in detail step Boning (2007). Design for • MOSFET Calculator MOSFET Calculator Manufacturability And Statistical Design: • Advanced MOSFET Issues [3] A Constructive Approach. New York • MOSFET applet Very nice applet that 309284: Springer. helps to understand MOSFET. http://www.amazon.com/gp/reader/ • MIT OpenCourseWare courses: 0387309284/ref=sib_dp_pt/ • MIT Open Courseware 6.002 - Spring 002-1766819-0058402#reader-link. 2007 -- Link to the intro electrical [35] Jean-Pierre Colinge, Cynthia A. Colinge engineering course at MIT on circuits (2002). Physics of Semiconductor and electronics. Devices. Dordrecht: Springer. p. 233, • MIT Open Courseware 6.012 - Fall Figure 7.46. ISBN 1402070187. 2005 -- Link to a more advanced class http://books.google.com/books?id=ZcDEtaught at MIT all about ENKh2gC&pg=PA233&dq=halo+MOSFET&as_brr=0&sig=q_IW6haw9G9-rBh9E_dmicroelectronics and MOSFETs i7rDbFc. • Georgia Tech BJT and FET Slides Slides [36] Eicke R. Weber, Jarek Dabrowski from a Microelectronic Circuits class at (Editors) (2004). Predictive Simulation of Georgia Tech Semiconductor Processing: Status and • CircuitDesign: MOS Diffusion Parasitics Challenges. Dordrecht: Springer. p. 5, Crude illustrations of MOS diffusion Figure 1.2. ISBN 3540204814. structure and sample circuit layouts to http://books.google.com/ minimize their parasitics books?id=oCH9tiY7VeoC&pg=PA5&dq=MOSFET+%22raised+source%22&as_brr=0&sig=61g3_KAM [37] Power Semiconductor Devices, B. Jayant Baliga, PWS publishing Company, Boston. ISBN 0-534-94098-6 See also External links Retrieved from "http://en.wikipedia.org/wiki/MOSFET" Categories: Transistor types This page was last modified on 16 May 2009, at 21:51 (UTC). All text is available under the terms of the GNU Free Documentation License. (See Copyrights for details.) Wikipedia® is a registered trademark of the Wikimedia Foundation, Inc., a U.S. registered 501(c)(3) taxdeductible nonprofit charity. Privacy policy About Wikipedia Disclaimers 16
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Submitted by admin 3390 days 18 hours 1 min ago
Comments added to RSS feeds
Now the commented items are added to the RSS feeds so that it's possible to see what have been commented recently.
Submitted by marc.battyani 3330 days 21 hours 51 min ago
unicode possibilities
It would be nice if cl-user would display unicode input for CJK text. With PCL and On Lisp getting new printings in Japan, it might be beneficial to attract more brain-share from that side of the world. Would this be considered out of cl-user.net's scope?
Submitted by charliemac 2426 days 15 hours 36 min ago
Perhaps it would be interesting to open up a "universities" category (or subcategory of Organization) to list universities that teach lisp?
Submitted by informatimago 2419 days 6 hours 52 min ago
re: universities
This is a good idea. Done.
Submitted by marc.battyani 2416 days 11 hours 6 min ago
re: unicode possibilities
I have to think about it.
The use of English as the standard language is prefered so that the information is useable by most lispers.
I don't mind some other language content though.
Submitted by marc.battyani 2416 days 10 hours 38 min ago
Change descriptions may accept invalid characters
Attempting to view the "Last Modified Items" RSS feed in the Google Chrome browser gives the error: "error on line 10 at column 2048: PCDATA invalid Char value 12". Adding the feed in Mozilla Thunderbird: "<feed URL> is not a valid feed."
Submitted by WalterGR 1543 days 17 hours 37 min ago
Repository access
Many sites have a link to view the repository such as:
Source code repository http://common-lisp.net/cgi-bin/viewcvs.cgi/?cvsroot=cl-semantic
however, I can't find any place that describes how to convert that link into something that can be used to actually check out the source code. I'm very suppressed this hasn't been an issue before.
Submitted by blake1024 1178 days 6 hours 18 min ago

subset: commoncrawl


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Mau Mau Rebellion in Kenya - Harvard "ThoughtCast" (video, 6:59min) by Caroline Elkins - one historian's perspective on human rights abuses during the Mau Mau Rebellion in Kenya
South Africa: Overcoming Apartheid, Building Democracy (MSU/NEH) - Interviews with South African activists, historical documents, rare photographs, and original narratives tell this story. Also seeWomen in the Movement (SAHA)
South African Truth and Reconciliation Committee
Voices from the Rwanda Tribunal(U of Washington) - interviews, videos, documents
Creative Arts
African Art in Brooklyn Museum,Art Institute of Chicago
African Life through Art: Cycles(Indianapolis Museum of Art) - Requires Flash, navigate via wheel near center of display
Art & Life in Africa (UI Mus. of Art)
ArtThrob - Contemporary Art in South Africa
Badilisha Poetry X-Change - audio archive of Pan-African poets organized by theme, country, language, and emotion
Caine Prize for African Writingsome winning stories online
Images of Commemorative Fabrics - digitized fabrics printed with images/text documenting events and people of historical, political, religious, economic, educational, and sociological significance to African societies.
One Day in Africa As Seen by 100 Photographers (requires Flash)


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Originally written on Wrestle Scoop | Last updated 11/18/14
- Wade Barrett posted the following Tout ordering fans to see his new movie, Dead Man Down, when it releases on March 8th. - According to The Hollywood Reporter, Summit Entertainment is projecting a $10 million to $12 million opening for Snitch which stars WWE Supestar The Rock. - Next Wednesday The Miz will be appearing on Conan to promote his new movie, The Marine 3: Homefront.
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Villa Del Palmar Beach Resort & Spa Cabo San Lucas
The beachfront Villa Del Palmar Beach Resort & Spa Cabo San Lucas is located less than 1.2 miles (2 kilometers) from downtown Cabo San Lucas, Mexico. Plaza Amelia Wilkes shops and restaurants are also positioned less than 1.2 miles (2 kilometers) away.
Hotel Features.
A nine-story atrium lobby features waterfalls, seashell motifs and a saltwater aquarium. Specializing in California and Italian fusion fare, the open-air beachfront Bella California affords stunning views of El Arco. Las Tortugas features daily themed buffets and nightly live entertainment such as Mexican folklore presentations. The resort serves a hot and cold breakfast buffet each morning (surcharges may apply).
Guests can relax at the resort's private white sand beach, accessed from the property. Beach umbrellas, towels and sun loungers are available for guest use. An on-site shopping plaza houses an ice-cream parlor, a clothing store, and a coffee shop equipped with 10 computers with Internet connections. The focal point of the resort is the three-pool complex that contains an adults-only freeform pool, an activity pool and a relaxation pool constructed with an infinity-edge spa tub. Four lighted tennis courts accommodate night matches. Non-motorized water sports are located on the beach, and the resort offers scooter and ATV rentals and horseback riding. A 10,000-square-foot (929-square-meter) European-style spa offers treatments such as the Sea of Cortez Discovery Massage and aromatherapy baths. A fitness center contains cardiovascular and strength-training equipment and offers aerobics and yoga classes. Kids in Paradise hosts supervised care for children ages 4-12. Property amenities also include tour assistance, luggage storage, laundry facilities and meeting/conference rooms. Villa Del Palmar Beach Resort & Spa Cabo San Lucas is a smoke-free property.
This Cabo San Lucas, Mexico resort offers 463 air-conditioned suites, each with a private balcony furnished with a table and two chairs. Views are of the garden and pool or the ocean. All rooms include kitchenettes or kitchens with two electric stovetop burners, full-sized refrigerator, minibar, microwave, blender, coffeemaker, pots and pans, service for four, and marble breakfast bar with barstools. Bathrooms feature travertine marble tub/ shower, hair dryer and painted porcelain accessories. Wired or wireless Internet is available for a surcharge.
Nice resort! I was under the impression I had booked a all inclusive package but that…
This hotel was a little more "kid friendly' than what we were looking for on our romantic…
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Hotel Info: 866-539-8117from $215
- Suite, 1 Bedroom
- Junior Suite
- Suite, 1 Bedroom
Recommended hotels
At a glance
Key facts
Hotel size
- This hotel has 463 rooms
- This hotel is arranged over 8 floors
- Check-in time starts at 3 PM
- Check-out time is 11 AM
- Express check-out
Required at check in
- Credit card or cash deposit required
- Government-issued photo ID required
- Minimum check-in age is 21
- Minimum Spring Break check-in age is 21
Travelling with others
- Children (12 years old and younger) stay free when occupying the parent or guardian's room, using existing bedding
- Babysitting/childcare
- Children's club
- Pets not allowed
Extra people
- Roll-away beds available, charges may apply*
- WiFi and wired Internet access in public areas *
- WiFi and wired Internet access in rooms *
- Airport shuttle *
- Free self parking
- Accessible parking
Other information
- Smoke-free property
- All-inclusive rates available
In the hotel
- Children's club
- In-room childcare (surcharge)
- Supervised childcare/activities
- Breakfast daily (surcharge)
- 5 restaurants
- Coffee shop/café
- Swim-up bar
- Poolside bar
- 24-hour room service
- On private beach
- Beach sun loungers
- Number of outdoor pools - 3
- Children's pool
- Health club
- Tennis on site
- Full-service spa
- Spa treatment room(s)
- Beach umbrellas
- Waterslide
- Spa tub
- Beach towels
- Swim-up bar
- Steam room
- Pool sun loungers
- Sauna
- Beach/pool umbrellas
- Arcade/game room
- Billiards or pool table
- Number of meeting rooms - 3
- Conference space
- Meeting rooms
- Computer station
- 24-hour front desk
- Concierge desk
- Tours/ticket assistance
- Limo or Town Car service available
- Dry cleaning/laundry service
- Laundry facilities
- Hair salon
- Free newspapers in lobby
- Luggage storage
- Wedding services
- Number of buildings/towers - 3
- Year Built 1992
- Elevator/lift
- ATM/banking
- Safe-deposit box at front desk
- Garden
- Disabled parking
- Accessible path of travel
- Accessible bathroom
- In-room accessibility
- Roll-in shower
In the room
- Climate control
- Air conditioning
- Ceiling fan
- Minibar
- Coffee/tea maker
- Iron/ironing board
- Hypo-allergenic bedding available
- Blackout drapes/curtains
- Sofa bed
- In-room massage available
- Separate sitting area
- Balcony
- Private bathroom
- Deep soaking bathtub
- Free toiletries
- Hair dryer
- Pay movies
- Premium TV channels
- Desk
- Free newspaper
- WiFi (surcharge)
- Phone
- Refrigerator
- Microwave
- Kitchen
- Stovetop
- Cookware, dishware, and utensils
- Daily housekeeping
- In-room safe (laptop compatible)
- Access via exterior corridors
Special features
All inclusive
Guests can book rooms at Villa Del Palmar Beach Resort & Spa Cabo San Lucas for a rate that is either for the room only or for all-inclusive. All-inclusive rates are higher because they include onsite food and beverages in the room rate (some restrictions may apply).
Gratuities and taxes
Gratuities and taxes are included.
Food and beverages
- All buffet and à la carte meals, snacks, and local beverages included
- Room service during certain hours
- Dining and beverage availability limited at one or more venues
- Surcharges for bottled wine
Activities and facilities/equipment
Land activities
- Fitness facilities
- Tennis
- Onsite entertainment and activities
- Onsite live performances
- Theme parties
Not included
- Airport transfers
- Childcare
- Laundry/dry cleaning services
- Minibar
- Premium and/or non-domestic beverages
- Premium food items
- Scuba-diving certification
- Scuba-diving excursions
- Spa/beauty facilities and services
- Wireless Internet access
- Offsite tours
Situated on the tip of the Baja Peninsula, the Desert Spa boasts views of the Sea of Cortez and the mountains. The 31,000 square foot spa and fitness center offers an array of rejuvenating treatments. Guests can enjoy massages, body wraps, facials, hydrotherapy, couples experiences and a full service beauty salon, as well as à la carte services and special spa packages. With the Desert Spa's exclusive line of desert-inspired body products, guests will be wrapped, bathed and pampered with fruit and herb extracts native to the Baja California area.
Children under 5 must be accompanied by an adult to visit the spa.
DiningBella California - This beachfront restaurant serves breakfast, lunch, and dinner. Guests can enjoy drinks at the bar.
Las Tortugas Restaurant - This poolside theme restaurant serves dinner only. Guests can enjoy drinks at the bar. Reservations are required.
Palmita Deli - Overlooking the garden, this delicatessen serves breakfast, lunch, and dinner. Open daily.
Tortugas Sports Bar - Overlooking the ocean, this sports bar serves lunch, dinner, and light fare. Open daily.
The Taco Bar - Overlooking the ocean, this restaurant specializes in Mexican cuisine and serves lunch and dinner. Open daily.
Villa Del Palmar Beach Resort & Spa Cabo San Lucas's small print
Also known as
- Villa Del Palmar Resort & Spa
- Cabo San Lucas Villa Del Palmar
- Villa Palmar
- Villa Del Palmar Cabo
- Villa Del Palmar Beach Resort And Spa
- Villa Del Palmar Cabo San Lucas
- Villa del Palmar Cabo Reviews
- Villa del Palmar Cabo San Lucas Reviews
- Villa Del Palmar Beach Resort & Spa Cabo San Lucas
- Villa Del Palmar
Only registered guests are allowed in the guestrooms.
Children under 17 years old are not allowed in the swimming pool, fitness facility, or spa tub without adult supervision.
Children under 5 years old are not allowed in the spa without adult supervision.
Reservations are required for massage services and spa treatments and can be made by contacting the property before arrival at the number on the booking confirmation.
The name on the credit card used at check-in to pay for incidentals must be the primary name on the guestroom reservation.
Optional extras
Late check-out can be arranged for an extra charge
Rollaway beds are available for an additional charge
Breakfast is offered for an extra charge of MXN 240 per person (approximately)
We have included all charges provided to us by this hotel. However, charges can vary, for example, based on length of stay or the room you book.


text: Version: (current) Description: Technical data plotting and visualization tool Operating System: Windows Macintosh Linux Availability Licensed for: Staff Brown-paid Faculty All Students License Managed: No Keyed: No License Text: Tecplot is licensed for Brown University users for teaching purposes only. Requirements Windows 7 (64-bit), 8.1; Macintosh OS 10.6.8-10.10 (Intel Core 2+, 64-bit only); Linux (unsupported) Be sure to close all applications and verify that your operating system meets the system requirements. Vendor Links Tecplot, Inc. View Tecplot Support Windows Installation Instructions (click to expand) Download Tecplot using link provided. After file extraction, you will be presented with several options about what and where to install. To install the entire suite to the default locations, click 'Full/Quick Install'. If you choose to install a single program to a location of your choice, enter the full installation path. If you would like to install additional programs from the Tecplot suite later, navigate to C:\BrownSW\tecplot-2013-win and run 'setup.exe'. Notes: When launching Tecplot RS, you may receive a dialog that says "The RSvariables.txt file was not found. Without it, the system will use a set of built-in defaults." This is normal behavior. Macintosh Installation Instructions (click to expand) Tecplot 2015 EX for Macintosh: Download Tecplot 2015 EX using the link provided. Select default options when any dialog box appears. To run Tecplot, double-click 'Tecplot 360 EX 2015 R1'. If you receive a License Manager Host dialog box, select Launch Tecplot. If you do not want to view this dialog box each time you launch Tecplot, uncheck the "Always Show this Dialog" checkbox and click on the Launch Tecplot button. Linux Installation Instructions (click to expand) Download Tecplot using the links (archive and license file) provided. Choose Installation option 1. - Install Tecplot Type "accept" at the end on the license agreement. (NOTE: It is easy to go past the end of the agreement and miss the opportunity to type in your response.) The installation script determines which platform to install. Go with the default option. The installation will ask you for the directory in which to install the package. Answer "No" to whether you want to install the license. After the installation is complete, insert the license in tecplotlm.lic which will be the top directory of the installed package. To use the package, you must configure the following: export TEC_360_2013=topdirectory of the installation export PATH=$PATH:/$TEC_360_2013/bin To run the package: "tec360" works directly on the workstation "tec360 -mesa" works from a remote connection


text:
Traditional agriculture--35
Expand Messages
- During the Middle Ages, wine growing in Slovakia reached a high level of development and became a specialized branch of agriculture thanks to German colonists, who contributed to the special character of this wine-growing culture.
Landlords' properties, vineyard properties of peasants, and the economies of vineyard towns were developed, and many institutions and legal standards originated during that time. These standards contributed to the wine industry's prosperity (vineyard rights, the rights of wine bars, the creation of guilds) and survived for a long time, some of them even into the 20th century. However, from very early on, wine growing was also seen as a resource of revenue.
In addition to the obligatory one-ninth portion [to the landlord?] and tithe [to the church?] of the harvest, it was necessary also to pay special fees for wine growing, toll fees for transporting the harvest from a foreign estate, and specific vineyard fees or an upper[??] fee, etc. The peasants' vineyard economy also supported the development of crafts and was the cause of agricultural day-laborers becoming a social group. Many legal institutions originated before the end of the 15th century, such as wine-making guilds and self-administration organizations headed by the village mayor (pereg).
War and uprisings in the 16th and 17th centuries damaged the wine-growing industry. Its recovery during the following period is demonstrated by the large amount of land used for vineyards, which in 1720 reached 57,000 hectares in Slovakia, over four times the present area [The book was published in 1997.]. This was a result of efforts to supply local and foreign markets with production from "Upper Hungary." However, the technology did not advance, although the working environments (wine-cellar, pressing shed) did improve.
All opinions my own,
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text:
To those opposing this amendment because it would add to the bureaucracy, keep in mind that schools chartered by the commission will receive substantially fewer dollars per student than almost all traditional public schools. The enabling legislation provides state money equal to the average local share of the 5 poorest districts in the state. At that savings per student, this amendment could be a net savings eventually.
More importantly, parents fed up with local schools are begging to send their children to charter schools that receive substantially less money per student. That is the strongest indication possible that those parents believe these charter schools can educate their children better and less expensively than the traditional public school system.


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