text:
Blue-Colored Berries in Massachusetts What Are they?
IÂm sorry that I donÂt have a photo to post with this, but ever since last Autumn IÂve been wondering about a particular plant in my yard that I havenÂt been able to identify. It is a deciduous shrub, about six feet tall, growing at the edge of the woods in moist soil. Its only distinguishing characteristic that I can remember is that it had clusters of blue-colored berries sometime between July and the winter. It certainly wasnÂt a blueberry bush, but aside from that, I have no idea what it could be. Any ideas?
Thank you!
Hmm, Viburnum have blue berries, but it also could be an invasive shrub such as Japanese Honeysuckle or Common Buckthorn, both which have dark blue berries...
Thank you Ellen! I think IÂve got a viburnum back there! Woot! I canÂt wait until it puts out some leaves so I can be sure.
I suspect that a few other berry-bearing shrubs IÂve got around the yard are Japanese honeysuckle. As soon as they flower IÂll know for sure  and onto the compost heap they go!
Privet also has small, dark blue berries - almost black, but not quite. It self-sows really freely around my area, and elsewhere in zone 6 and warmer. I don't want to use the "I" word, since I just read through a heated discussion on the subject on the shrubs forum.
Most (but not all) of my privet retained their leaves this winter. All but one of them are volunteers, as far as I know, one monster specimen (about 16' tall) looks like it was planted by the previous owner. Birds love it, it provides dense, twiggy cover and those berries, which are the source of the problem.
Viburnums have opposite branches and leaves - two branches emerge opposite each other, one on each side off a larger branch. I can't remember about privet or honeysuckle, but I know buckthorn has alternate, not opposite, branching. There is a Dover publication that has keys to winter twigs and fruit that you might be able to find at a bookstore or library.
IÂm about 90% certain that itÂs a viburnum IÂve got, because those berry clusters were mighty distinctive. IÂll be sure to check out the branch arrangement next time IÂm out here, babs - thanks!
Hmm. . . looks like that conspicuously round green shrub not far from the "viburnum" might be a privet. I will have to do some more research on that.
I took out a few Japanese barberries from the yard this weekend. That leaves me with one burning bush in the flowerbed and half a dozen other shrubs that I think might be Japanese honeysuckle or common buckthorn. Fortunately these invasives are in the minority in my yard, and I like having an excuse to bring out ye olde branch loppers! And having fodder for the compost heap. Mwahahaha!
I found a pair of young honeylocusts in the backyard on Saturday. And I know there will be a lot more stuff for me to identify in the Spring when IÂve got more than just twigs to go on. Gads, I love having a piece of wild property to play in!
I think some of my wild dogwoods have blue berries. The question is because they don't hang around very long for me to see them much. I think they are grey dogwoods, and they are definitely a squish plant. Not to the extent of the red twigs, but more than normal.
A plant that grows in the squish :-)
I have a swamp. After several years of trying to get things established in the swamp, I've found out there are considerable differences in what will grow with tiny differences in elevation. 'Squish' is ground that looks OK, but makes a squishing noise when you walk on it. Most 'wetland' plants are actually squish plants since they don't really like places with puddled water for long periods of time. The amount of wetland plants I've killed by planting them in water....
Aha! Makes perfect sense now. Thanks for the explanation.
I was especially curious because I'm looking for something tall for a screen along a very shady corner of my yard, and one of the plants on my list of possibilities is gray dogwood. Some of the interpretations of squish that sprang to mind gave me second thoughts about growing this.
Wendy - Great photo! Yours looks like a maple-leaf viburnum (V. acerifolium) which is only one of the kinds that grow wild around here. It never ceases to amaze me what a range of leaf shapes that viburnums have! Around here we also have V. alnifolium (hobblebush), V. cassinoides (witherod viburnum), and V. dentatum (arrowwood). They are all such great plants.
Hey Mad Gallica,
What else is growing in your "squish"? I too have a squish and would like to add some different plants. I have added a few viburnums to my wild viburnums and some lobelia (cardinal flower), Japanese primrose, pulmonaria, hydrangea, and monarda -- which will grow anywhere!
Hey Debrah, I've got some squish of my own, and so far I've identified skunk cabbage, witchhazel and poison sumac growing either in it or nearby. Hit me up next November if you would like some witchhazel seeds. I haven't yet learned how to collect seeds from skunk cabbage. If you want poison sumac seeds. . . I could hook you up with that, too. ;)
I rather like the term "squish"!
I bet Virginia Sweetspire (Itea virginica) would like squish conditions. Nice fragrant flowers, pretty fall color, will form a thicket, not fussy about light.
When we first moved here, most of the swamp was either red-twig dogwood, cattails or phragmites. All of them are extremely aggressive in a wet setting. In slightly higher places, there is some sort of wild pussy willow, what I think is arrowwood viburnum, wild winterberry, too much amur honeysuckle, coltsfoot and, of course skunk cabbage. I've planted lindera benzoin, viburnum trifolia, Hammalis virginiana, Rosa palustris, and more winterberry in relatively wet areas. Only the rose went into serious standing water. Slightly higher up, in areas that stay dry, but don't have a lot of root room before they hit water I've put a Little Girl magnolia, some hydrangea, and there are fairly large pin oaks, maples and ashes.
One of my biggest gardening obstacles is a fairly limy soil. Somehow it got into my brain that the acid lovers can't handle it because the minerals clog their vascular system. So they might do better provided with as much water as possible. This does explain why winterberry grows wild here, and why my pin oaks aren't chlorotic when it's a real problem locally. So there are things like the magnolia that wouldn't ordinarily be placed in a wet place, but I'm putting down there as an experiment.
Mad g:
You'll be happy to know that I planted a Magnolia Soulangelia (sp?) many years ago when it was only 30" tall. It is now 20-25' and gorgeous. I guess it likes its Squish conditions. So I bet yours will do well too. Its so nice to see those goWrgeous flowers in the spring. I think spring flowering plants are so much more welcome than any other seasons' just because we had to do so long without! Also, I have a nikko blue hydrangea and it does well in the Squish because it never gets dry. Of course, it only blooms when it doesn't get late winter frost.
Winterberry is a good idea. I'll think about that one for my winter interest.
I also planted a couple roses in my squish, but in the areas where there is less squish and more dry. LOL The roses I planted are William Baffin and New Dawn. Both are doing well. I was very surprised to see that. Some people say roses are soooo picky. Well, they sure like water!
Also, Hardy hybiscus does pretty darn good as well. And of course, daylillies.
How long has it been that you moved to NY? It's only about five years right?


text:
News Headlines
- Wed, Apr 01
- U.R.F. mode returns to League of Legends, featuring hilarious patch notes and a 99,999 RP icon
- ArenaNet fights Guild Wars 2 account fraud by limiting gold players can receive and send
- Tue, Mar 31
- Batman: Arkham Knight PlayStation 4 Limited Edition unveiled, plans for PS4 exclusive Scarecrow DLC
- April's PlayStation Plus strong with the indies as ever, Never Alone and Aaru's Awakening on PS4
- Assassin's Creed Chronicles trilogy heads to Asia and Russia in three downloadable side-scrollers
New Articles
Related Articles
Intel Core i5 750 & i7 870 Review - PAGE 9Pier-Luc Gendreau, Carl Poirier
- Monday, September 7th, 2009 Like Share
next: Lost Planet & Left 4 Dead »
Article Index
Sort by date: ascending descending
bphicks123 Sep 8, 09
read on where?
Zertz Sep 8, 09
Sort by date: ascending descending

subset: commoncrawl


text:
Inventors list
Assignees list
Classification tree browser
Top 100 Inventors
Top 100 Assignees
Electrical characteristic sensed
Subclass of:
438 - Semiconductor device manufacturing: process
Patent class list (only not empty are listed)
Deeper subclasses:
|Class / Patent application number
|Number of patent applications / Date published
|Utilizing integral test element
|Chip Packaging with Metal Frame Pin Grid Array - A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.
|Method for evaluating semiconductor wafer - The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer.
|Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage - A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.
|SUBSTRATE ETCHING METHOD AND SUBSTRATE ETCHING APPARATUS - A method for selectively etching a substrate includes providing a template having opening portions formed on an upper surface in a predetermined pattern and flow channels penetrating through the template from the opening portions to a lower surface of the template, filling an etching solution into the flow channels, coupling the upper surface of the template to a substrate such that the opening portions correspond to the predetermined pattern of through holes to be formed through the substrate, and supplying the etching solution onto the substrate through the opening portions of the template such that the through holes are etched through the substrate.
|Process management method and process management data for semiconductor device - A process management method for managing manufacturing variability of an interconnection included in a semiconductor device is provided. The process management method includes: calculating interconnect resistance and interconnect capacitance regarding an interconnection included in the semiconductor device, under a condition that manufacturing variability of a width and a thickness of the interconnection is expressed by points on a predetermined circle of equal probability of a joint probability density function; and defining, based on the calculated interconnect resistance and interconnect capacitance, a variation range of interconnect resistance and interconnect capacitance caused by manufacturing variability. The variation range is defined two-dimensionally in a coordinate system where a first axis represents interconnect resistance and a second axis represents interconnect capacitance.
|MODULAR FLOW CELL AND ADJUSTMENT SYSTEM - A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in order to accommodate various processes through a first section without having to completely disconnect and re-connect facilities to a second section.
|METHOD FOR INSPECTING SEMICONDUCTOR DEVICE - According to the present invention, a method for inspecting a semiconductor device includes the steps of carrying out a first test for inspecting characteristic of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test to semiconductor devices, which have been passed the first test as non-defective devices, for inspecting characteristic of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to semiconductor devices.
|MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer.
|System and Methods for Semiconductor Device Performance Prediction During Processing - Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.
|METHOD AND APPARATUS FOR WAFER TEMPERATURE MEASUREMENT USING AN INDEPENDENT LIGHT SOURCE - An apparatus is provided for measuring a substrate temperature during an etching process, comprising: one or more windows formed in a substrate supporting surface; a first signal generator configured to pulse a first signal; and a first sensor positioned to receive energy transmitted from the first signal generator through the one or more windows. A method is provided for measuring a substrate temperature during an etching process comprising: heating a substrate using radiant energy; pulsing a first light; determining a metric indicative of total transmittance through the substrate when the first light is pulsed on; determining a metric indicative of background transmittance through the substrate when the first light is pulsed off; and determining a process temperature.
|THIN FILM PROBE SHEET AND SEMICONDUCTOR CHIP INSPECTION SYSTEM - In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
|METHODS OF FABRICATING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.
|METHOD AND APPARATUS FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing the structural defect by supplying a bias voltage to the portion in which the structural defect exists.
|ENHANCED SENSITIVITY NON-CONTACT ELECTRICAL MONITORING OF COPPER CONTAMINATION ON SILICON SURFACE - Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface photovoltage and a vibrating Kelvin-probe, respectively. Differential measurements before and after activation enable the separations of the copper impurities from other surface contaminants.
|INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION - A method for increasing an electrical resistance of a resistor. A semiconductor structure that includes the resistor is placed in a chamber that includes a gas including nitrogen-containing molecules at an nitrogen concentration. A fraction F of an exterior surface of a surface layer of the resistor is exposed to the nitrogen-comprising molecules. A portion of the surface layer is heated at a heating temperature. A combination of the nitrogen concentration and the heating temperature is sufficient to nitridize the portion of the surface layer by reacting the portion with the nitrogen-containing molecules. Heating the portion of the surface layer includes directing a beam of radiation or particles into the portion of the surface layer heat the portion of the surface layer. The portion of the surface layer is nitridized by being reacted with the nitrogen-containing molecules such that an electrical resistance of the resistor is increased.
|METHOD OF MANUFACTURING SEMICONDUCTOR CHIP AND SEMICONDUCTOR MODULE - An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOM
|METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND REINFORCING PLATE - According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor substrate having a plurality of first pads is covered with a bonding material. The semiconductor substrate is attached to a reinforcing plate having a plurality of first through-holes corresponding respectively to the first pads. The semiconductor substrate is removed until becoming a predetermined thickness. An electrode film is formed on the semiconductor substrate. A remover of the bonding material is injected into the first through-holes so as to expose the first pads. A probe is in contact with the exposed first pads through the first through-holes so as to measure a current flowing between the probe and the electrode film. The remover is injected into the first through-holes so as to separate the semiconductor substrate from the reinforcing plate. The semiconductor substrate is diced into a plurality of chips.
|Method of fusing trimming for semiconductor device - Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors.
|PROBE CARD AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a probe card for LSI inspection that can achieve electrical conduction to electrodes on an LSI with a low load without damaging the electrodes and a structural body therebelow, even if the electrodes are arranged at a narrow pitch and in a complex manner. A contact terminal is formed in a truncated square pyramidal recess provided on a film-shaped probe. A dent is often formed on a surface of the film-shaped probe just above the contact terminal. A resin coating film is formed so as to eliminate the dent and flatten the surface of the film-shaped probe. At this time, it is preferred that an amount of cure shrinkage of a resin paste for forming the resin coating film is 0.1% or less.
|THIN FILM TRANSISTOR ARRAY SUBSTRATE WITH IMPROVED TEST TERMINALS - A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units.
|Landing Pad for Use As a Contact to a Conductive Spacer - A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.
|METHODS OF MAKING AND USING INTEGRATED AND TESTABLE SENSOR ARRAY - A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.
|MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a process for a semiconductor typically represented by a vertical power MOSFET, etc. of repeating various fabrications in a state of a thin film wafer with the thickness of the wafer being 200 μm or less, it is a standard procedure of conducting processing in a stage of bonding a reinforcing glass sheet to a device surface of the wafer (main surface on the side of surface) in the step after film thickness-reduction. However according to the study of the present inventors, it has been found that about 70% for the manufacturing cost is concerned with the reinforcing glass sheet. In the present invention, a stress relief insulation film pattern is formed to the peripheral end of the rear face of a wafer in which processing to the device surface (surface side face) of the wafer has been completed substantially and back grinding has been applied.
|METHOD AND SYSTEM TO DYNAMICALLY COMPENSATE FOR PROBE TIP MISALIGNEMENT WHEN TESTING INTEGRATED CIRCUITS - Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.
|Inspection System, Inspection Method, and Method for Manufacturing Semiconductor Device - The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.
|METHOD OF MANAGING SUBSTRATE - The electrostatic chuck is made up of: a chuck main body having electrodes; a chuck plate of a dielectric material and having a rib portion with which a peripheral edge portion of the substrate is capable of coming into surface contact, and a plurality of supporting portions which are vertically disposed at a predetermined distance from one another in an inner space enclosed by the rib portion; and a gas introduction means for introducing a predetermined gas into the inner space. When the substrate is held by the electrostatic chuck which is arranged to attract the substrate by the chuck plate and to form a gas atmosphere by supplying a predetermined gas into the inner space, a current value is monitored by causing an AC current to flow in a capacitance of the chuck plate through an AC power supply, a gas flow amount is monitored by causing the gas to flow through the gas introduction means, and a substrate state is managed based on a variation in at least one of the current value and the gas flow amount to prevent damages to the substrate.
|Test Patterns for Detecting Misalignment of Through-Wafer Vias - A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns.
|HIGH VOLTAGE SENSOR DEVICE AND METHOD THEREFOR - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.
|EDDY CURRENT SENSOR WITH ENHANCED EDGE RESOLUTION - An apparatus for monitoring the thickness of a conductive layer on a substrate includes a support to hold a substrate having a conductive layer, an eddy current monitoring system including a first plurality of core portions, and a motor to cause relative motion between the support and the eddy current monitoring system such that the substrate moves across the first plurality of core portions in a direction that defines a first axis. At least one core portion is positioned further from a second axis than at least two other core portions. The second axis is orthogonal to the first axis.
|METHOD FOR CONTROLLING THRESHOLD VOLTAGE OF SEMICONDUCTOR ELEMENT - A method for controlling the threshold voltage of a semiconductor element having at least a semiconductor as a component is characterized in including a process to measure one of a threshold voltage and a characteristic value serving as an index for the threshold voltage; a process to determine one of the irradiation intensity, irradiation time, and wavelength of the light for irradiating the semiconductor based on one of the measured threshold voltage and the measured characteristic value serving as the index for the threshold voltage; and a process to irradiate light whose one of the irradiation intensity, irradiation time, and wavelength has been determined onto the semiconductor; wherein the light irradiating the semiconductor is a light having a longer wavelength than the wavelength of the absorption edge of the semiconductor, and the threshold voltage is changed by the irradiation of the light.
|METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into a plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers.
|SEMICONDUCTOR PROCESS EVALUATION METHODS INCLUDING VARIABLE ION IMPLANTING CONDITIONS - Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.
|Semiconductor device and a semiconductor device manufacturing method - A semiconductor device for fingerprint sensors reduces a mounting area of the semiconductor device and improves a processing capacity of assembling and testing process. The semiconductor device has a functional surface that provides a predetermined function. A semiconductor element has a circuit formation surface on which a plurality of electrodes are formed and a back surface opposite to the circuit formation surface. A part of the circuit formation surface functions as the functional surface. Wiring is formed on the back surface of the semiconductor element. A plurality of connection parts extends between the circuit formation surface and the back surface of the semiconductor element so as to electrically connect the electrodes to the wiring. A plurality of external connection terminals are exposed outside the semiconductor device on a side of the back surface of the semiconductor element.
|SUBSTRATE SUPPORTING APPARATUS - A substrate supporting apparatus includes first and second shafts spaced by a distance that corresponds to or exceeds a width of a substrate, and at least one wire to support the substrate. The wire has ends coupled to respective ones of the first and second shafts. The wire is raised and lowered to place a substrate onto a lower electrode in a substrate processing chamber and to remove the substrate when processing is completed.
|Semiconductor device production process - A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads.
|Method of real-time monitoring implantation - A method of real-time monitoring implantation includes plotting a calibration curve for monitoring implantation first. Next, a testing substrate covered a photoresist is provided and then implanted. Since photoresist surface roughness will be changed after implantation, surface roughness change could be quantitatively determined by monitoring scattering light. Finally, the detected scattering light intensity is used to calculate the corresponding implantation condition by the use of the calibration curve.
|METHOD AND APPARATUS FOR MANAGING MANUFACTURING EQUIPMENT, METHOD FOR MANUFACTURING DEVICE THEREBY - Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices.
|Manufacturing Method for Partially-Good Memory Modules with Defect Table in EEPROM - A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.
|MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
|Plasma processing apparatus and plasma processing method - A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer.
|System and method for controlling a semiconductor manufacturing process - A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals.
|Methods and Apparatus For Thinning, Testing And Singulating A Semiconductor Wafer - A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.
|FORMING AND TRAINING PROCESSES FOR RESISTANCE-CHANGE MEMORY CELL - During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation.
|CONNECTION DEVICE AND TEST SYSTEM - To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
|PRODUCTION LINE FOR THE PRODUCTION OF MULTIPLE SIZED PHOTOVOLTAIC DEVICES - Embodiments of the present invention generally relate to a system used to form solar cell devices using processing modules adapted to perform one or more processes in the formation of the solar cell devices. In one embodiment, the system is adapted to form thin film solar cell devices by accepting a large unprocessed substrate and performing multiple deposition, material removal, cleaning, bonding, testing, and sectioning processes to form multiple complete, functional, and tested solar cell devices that can then be shipped to an end user for installation in a desired location to generate electricity. The system is adapted to receive a single large substrate and form multiple silicon thin film solar cell devices from the single large substrate.
|Apparatus and method for manufacturing semiconductor device - A method of manufacturing a semiconductor device includes depositing material on a wafer in a process chamber to form a thin film on the wafer, a by-product layer being simultaneously formed on an inner part of the process chamber, monitoring a change in thickness or mass of the by-product layer on the inner part of the process chamber during a process in the process chamber by using a QCM installed in the process chamber, and determining an end point of the process in the process chamber based on the monitored change in thickness or mass of the by-product layer in the process chamber.
|THIN FILM SOLAR CELL PROCESSING AND TESTING METHOD AND EQUIPMENT - A method of providing a plurality of classified photovoltaic articles, including the steps of providing a first photo-voltaic element that includes a plurality of photovoltaic articles on a continuous flexible substrate, forming a electrically insulating material on the first photovoltaic element at one or more predetermined locations, separating adjacent photovoltaic articles from each other, determining an efficiency of each photovoltaic article by measuring its current-voltage characteristics, and classifying each photovoltaic article according to its efficiency.
|METHOD FOR EVALUATING OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Many of the principles of an oxide semiconductor are still unclear and therefore there is no established method for evaluating an oxide semiconductor. Thus, an object is to provide a novel method for evaluating an oxide semiconductor. Carrier density is evaluated, and hydrogen concentration is also evaluated. Specifically, a MOS capacitor (a diode or a triode) is manufactured, and the C-V characteristics of the MOS capacitor are obtained. Then, the carrier density is estimated from the C-V characteristics obtained.
|METHOD FOR PROVIDING A NON-VOLATILE MEMORY - Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.
|IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA - A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
|PROBE CARD, SEMICONDUCTOR INSPECTING APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.
|DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, electrolytic solution is selectively jetted onto an imprint pattern, the electrolytic solution is jetted onto each shot or part of an area in a shot, an electrode is separated for each shot, and the electrode is switched according to a shot to be an inspection target.
|Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.
|ION IMPLANTATION PROCESS CHARACTERIZATION METHOD - A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion.
|CARBON-CONTAINING SEMICONDUCTING DEVICES AND METHODS OF MAKING THEREOF - Embodiments of the present invention relate to semiconducting carbon-containing devices and methods of making thereof. The semi-conducting carbon containing devices comprise an n-type semiconducting layer and a p-type semiconducting layer, both of which are positioned over a substrate. The n-type semiconducting layer can be formed by pyrolyzing a carbon- and nitrogen-containing polymer, and the p-type semiconducting layer can be formed by pyrolyzing an aromatic- and aliphatic-group-containing polymer. In some embodiments, the devices are solar cell devices.
|METHOD FOR CLEANING A SOLAR CELL SURFACE OPENING MADE WITH A SOLAR ETCH PASTE - A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.
|SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.
|METHOD FOR INSPECTING PHOTORESIST PATTERN - A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.
|FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
|CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER - The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
|SYSTEMS AND METHODS FOR MONITORING HETEROJUNCTION BIPOLAR TRANSISTOR PROCESSES - Disclosed are systems and methods related to monitoring of heterojunction bipolar transistor (HBT) processes. In some embodiments, a capacitance element can be fabricated during an HBT process by forming an emitter layer having material such as indium gallium phosphide (InGaP) over a gallium arsenide (GaAs) base layer, forming a barrier layer such as a tantalum nitride (TaN) layer over the emitter layer, and forming a metal layer over the barrier layer. Aside from the metallization of the emitter, the resulting capacitance element has a capacitance value representative of the thickness of the emitter layer. Accordingly, monitoring of such a capacitance value during various HBT processes allows monitoring of the integrity of the emitter layer.
|PACKAGING AND TESTING OF MULTIPLE MEMS DEVICES ON A WAFER - A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.
|Auto Routing for Optimal Uniformity Control - A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.
|METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING - Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.
|Analysis method for semiconductor device - An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam microscope analysis process shows that the abnormal region has a defect therein. After the focused ion beam microscope analysis process, an electrical property measurement step is performed to the abnormal region, so as to determine whether the defect in the abnormal region is a device failure root cause or not.
|POLISHING METHOD, POLISHING APPARATUS AND POLISHING TOOL - A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water (
|PROCESS OF FABRICATING A WORKPIECE USING A TEST MASK - A product workpiece can be processed to form product dice. A test mask can allow intentional changes to be made to a feature on the product workpiece to examine how the altered feature performs. Use of the test mask may be used or not used based on the needs or desires of skilled artisans. By using the test mask, a separate dedicated test structure is not required to be formed in a scribe lane or within an area that could otherwise be used for a product die. Thus, the sampling level by using the test mask can be varied. Also, separate test workpieces, which may not be processed using a significantly different process flow or at significantly different times as compared to product workpieces, are not required. The product workpiece with the altered feature can be electrically tested without the need to form test or bond pads.
|Cascaded-Based De-embedding Methodology - An embodiment is a method for de-embedding. The method comprises forming a primary structure in a semiconductor chip and forming an auxiliary structure in the semiconductor chip. The auxiliary structure replicates a first portion of the primary structure. The method further comprises determining a transmission matrix for each of the primary structure and the auxiliary structure based on measurements and extracting a transmission matrix of a first component of the primary structure by determining a product of the transmission matrix of the primary structure and an inverse of the transmission matrix of the auxiliary structure.
|Alignment method of two substrates by microcoils - Substrates to be aligned comprise microcoils arranged at the level of their facing surfaces. In an alignment phase, power is supplied to at least the microcoils of the first substrate, whereas the inductance of the microcoils of the second substrate is measured. The microcoils are preferably flat microcoils in the form of a spiral or a serpentine.
|THIN FILM SCRIBE PROCESS - A method and apparatus for improving a thin film scribing procedure is presented. Embodiments of the invention include a method and apparatus for determining a scribe setting for removal of an absorber layer of a photovoltaic device that improves contact resistance between a back contact layer and a front contact layer of the device.
|METHOD OF MEASURING RESISTIVITY OF SIDEWALL OF CONTACT HOLE - A method of measuring a resistivity of a sidewall of a contact hole formed in a semiconductor device, wherein said semiconductor device includes a first electrode formed on a substrate; a second electrode formed on the first electrode with an insulating film in between; a resist pattern formed on the first electrode and the second electrode; a contact hole formed in the first electrode and the second electrode; and an organic film deposited on the sidewall of the contact hole, includes the steps of: placing a probe needle on the first electrode and the second electrode so that the probe needle contacts with the first electrode and the second electrode several times; establishing electrical conductivity of the probe needle relative to the first electrode and the second electrode; and measuring the resistivity of the organic film between the first electrode and the second electrode.
|METHOD FOR REDUCING OCCURRENCE OF SHORT-CIRCUIT FAILURE IN AN ORGANIC FUNCTIONAL DEVICE - A method, for reducing occurrence of short-circuit failure in an organic functional device (
|METHOD AND APPARATUS FOR MANUFACTURING THIN FILM PHOTOELECTRIC CONVERSION MODULE - A method for manufacturing a thin film photoelectric conversion module comprising the steps of: (A) forming a plurality of divided strings by dividing a string, in which thin film photoelectric conversion elements provided by sequentially laminating a first electrode layer, a photoelectric conversion layer and a second electrode layer on the surface of an insulating substrate are electrically connected in series, into a plurality of strings by dividing grooves, electrically insulating and separating the first electrode layer and the second electrode layer one from the other and extending in a serial connection direction; and (B) performing reverse biasing by applying a reverse bias voltage to each of thin film photoelectric conversion elements of the divided string.
|METHOD OF FABRICATING AN ULTRA-SMALL CONDENSER MICROPHONE - In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced.
|CONTACTOR, TEST DEVICE FOR SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A contactor includes a contactor base material including a first material and a conductor film including a second material. The conductor film is formed only on a contact surface with an electrode of a semiconductor apparatus at a tip of the contactor film.
|METHOD OF SENSING A HIGH VOLTAGE - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In the method of manufacturing a semiconductor device, first, values of diffusion parameters of a semiconductor device are acquired in a middle of manufacturing the semiconductor device. Next, a target value of another diffusion parameter to be determined by a processing implemented in a subsequent process of the semiconductor device manufacturing process is calculated. The another diffusion parameter is calculated by substituting the acquired values of diffusion parameters and a desired value of an electrical characteristic of the semiconductor device into a predetermined prediction expression. The prediction expression is an expression showing a corresponding relationship between the electrical characteristic and a plurality of types of diffusion parameters of the semiconductor device. Subsequently, processing conditions for the processing implemented in the subsequent process to realize the target value is determined. Then, the processing to the semiconductor device in the subsequent process is implemented under the determined processing conditions.
|TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER - Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
|FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
|PROCESS ENVIRONMENT VARIATION EVALUATION - Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
|Power Network Stacked Via Removal For Congestion Reduction - A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.
|TESTING FOR CORRECT UNDERCUTTING OF AN ELECTRODE DURING AN ETCHING STEP - A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically conductive top layer. The probe-electrode structure of the invention provides a means to detect an undercutting of the first probe electrode in an etching step that aims at removing the top layer from regions outside the first probe electrode. An undercutting that exceeds an admissible distance from the first edge of the first electrode will remove the first top-layer probe section in the first probe opening, which causes a detectable change of the electrical resistance between the first and second probe electrodes.
|CHIP ID APPLYING METHOD SUITABLE FOR USE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called "mark forming mask") used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
|PROCESS CONDITION EVALUATION METHOD FOR LIQUID CRYSTAL DISPLAY MODULE - A process condition evaluation method for a liquid crystal display module (LCM) includes: a first step of obtaining a threshold power measuring pattern, an analysis sample for a cell bonding status in an LCD fabrication process, and obtaining a lower substrate sample by separating an upper substrate from the threshold power measuring pattern; a second step of supplying voltages on a gate pad on the lower substrate sample with sequentially increasing a voltage level by a predetermined unit by using an electrical device, and obtaining a threshold current and a threshold voltage by measuring currents at a drain pad whenever voltage increased by a predetermined unit is applied to the gate pad; and a third step of obtaining threshold power based on the threshold current and the threshold voltage, and thereby evaluating process conditions of the LCM.
|METHODOLOGY FOR EVALUATION OF ELECTRICAL CHARACTERISTICS OF CARBON NANOTUBES - The present disclosure relates to a structure comprising
|System and Method for Preconditioning Photovoltaic Modules for Performance Testing - A system and method for preconditioning a photovoltaic device is described. One embodiment includes a method for preconditioning a photovoltaic device, the method comprising applying a forward-bias to the photovoltaic device, wherein a forward-bias current is equal to or greater than I
|METHODS OF ADDING PADS AND ONE OR MORE INTERCONNECT LAYERS TO THE PASSIVATED TOPSIDE OF A WAFER INCLUDING CONNECTIONS TO AT LEAST A PORTION OF THE INTEGRATED CIRCUIT PADS THEREON - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.
|MANUFACTURING METHOD AND TEST METHOD OF SEMICONDUCTOR DEVICE - Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
|Fluid Ejection Device and Method - A fluid ejection device includes one or more digital data storage arrays having plural EPROM cells. A method for affirming performance adequacy of EPROM cells in the one or more arrays includes the steps of identifying a reference cell in each array, measuring a selected performance criterion for the reference cells, obtaining a reference criterion value, and evaluating the actual performance of at least one cell in each array with respect to the reference criterion value.
|Electro Chemical Deposition Systems and Methods of Manufacturing Using the Same - An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
|MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.
|MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention comprises: forming a semiconductor circuit including a first transistor with a first threshold voltage and a first drain-source current; applying a stress voltage to the first transistor to make at least one of a change from the first threshold voltage a second threshold voltage and a change from the first drain-source current to a second drain-source current; and shipping the semiconductor circuit while the first transistor is presenting one of the second threshold voltage and the second drain-source current.
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second grooves are formed in a semiconductor substrate having a first surface. The first and second grooves have substantially the same vertical dimension. The first surface has first and second regions surrounded by the first and second grooves, respectively. An actual resistance value of the semiconductor substrate between a first point on the first region and a second point on the second region is measured. The vertical dimension of the first and second grooves is calculated with reference to the actual resistance value.
|PRESSURE-SENSITIVE ADHESIVE SHEET AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE HAVING SAME - A pressure-sensitive adhesive sheet according to the present invention is a pressure-sensitive adhesive sheet in which a pressure-sensitive adhesive layer is provided on a base film, in which the base film contains conductive fibers, and in which an electrically conductive path is formed between the pressure-sensitive adhesive layer and the base film. With this structure, an electrical continuity test can be performed even in a condition where a semiconductor wafer or a semiconductor chip formed by dicing the semiconductor wafer is applied, and deformation (warping) and damage of the semiconductor wafer and generation of flaws and scratches on the backside can be prevented in the test.
|Deletable nanotube circuit - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.
|MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - As the thickness of the card holder for preventing warping of a multilayered wiring substrate
|Kind of Method of Constituting Light Source using Multiple Light-emitting units - A method for forming a light source by plurality of light-emitting units, includes: step (A), determining the number of the light-emitting units based on following factors: the factors include a maximum supply voltage of a power supply circuit and a working voltage of each of the light-emitting units; step (B), determining a set power of each of the light-emitting units based on a set power of the light source and the number of the light-emitting units determined in the step (A); step (C), fabricating or selecting each of the light-emitting units based on the working voltage of each of the light emitting units and the set power of each of the light-emitting units determined in the step (B); step D), forming the light source by connecting each of the light-emitting units obtained in the step (C) in series according to the number of the light-emitting units determined in the step (A). For the light source formed as the above method, the high efficient power supply with the maximum output voltage, to the light source load, can be realized and the same power supply circuit can supply power to the light source with different set power with maximum supply efficiency.
|CHARGE TRANSFER DEVICE - A charge transfer device
|GAP MAINTENANCE FOR OPENING TO PROCESS CHAMBER - A semiconductor processing apparatus includes a reaction chamber, a movable susceptor, a movement element, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable susceptor is configured to hold a workpiece. The movable element is configured to move a workpiece held on the susceptor towards the opening of the baseplate. The control system is configured to space the susceptor from the baseplate by an unsealed gap during processing of a workpiece in the reaction chamber. Purge gases may flow through the gap into the reaction chamber. Methods of maintaining the gap during processing include calibrating the height of pads and capacitance measurements when the susceptor is spaced from the baseplate.
|SEMICONDUCTOR DEVICE FOR MONITORING CURRENT CHARACTERISTIC AND MONITORING METHOD FOR CURRENT CHARACTERISTIC OF SEMICONDUCTOR DEVICE - A method for monitoring current characteristics of a semiconductor device includes forming an isolation layer and a well area over a substrate, and then forming a P+ area and an N+ area spaced apart by the isolation layer to define active areas, and then forming a gate oxide layer over the substrate including the P+ area and the N+ area, and then forming a polysilicon layer over one of the N+ area and the P+ area, and then connecting a electronic measuring probe to one of the N+ area and the P+ area and connecting a power terminal to the polysilicon layer, and then measuring the current characteristics of the semiconductor device using the polysilicon layer as a power pad and one of the N+ area and the P+ area as a pad.
|METHOD FOR FORMING AN OVER PAD METALIZATION (OPM) ON A BOND PAD - A method of making a semiconductor structure includes forming a bond pad, depositing by laser defined deposition a conductive pad, and attaching an electrical connector to the conductive pad. The bond pad is a portion of an integrated circuit. The bond pad includes an exposed portion. The bond pad functions as a contact to the integrated circuit. The conductive pad is deposited on the exposed portion and is confined within a bond pad region around the exposed portion of the bond pad
|Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates.
|METHOD FOR SETTING PREDEFINABLE PARAMETERS - A method for setting predefinable parameters is described, in which for an electronic component, for example a voltage regulator having at least one integrated circuit, the latter has an external connection, via which it is connectable to a programming device. For the latter, a so-called zero programming is provided in the manufacture of the integrated circuit, and predefinable parameters or settings are programmed in following the completion of the manufacturing process, in particular following the assembly of the component or the voltage regulator with the associated generator.
|STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
|DRY HIGH POTENTIAL TESTER AND SOLAR SIMULATOR TOOL - A method and apparatus for testing a photovoltaic substrate disposes the substrate on a support gantry with connection points such as vacuum cups. The gantry is actuated into a test position. A probe nest coupled to the gantry connects to a junction box on the substrate. A power supply applies voltage to the junction box, and an actuated frame contacts an edge region of the substrate to detect any breakthrough current. The actuated frame comprises a liner for maximizing contact with the edge of the substrate. The liner may be conductive, or may have a conductive surface. Current sensors coupled to the conductive liner of the frame detect any breakthrough current. A solar spectrum simulator provides solar spectrum radiation for testing the photovoltaic properties of the substrate.
|Methods and Systems For Controlling SiIicon Rod Temperature - Systems and methods are provided for controlling silicon rod temperature. In one example, a method of controlling a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process is presented. The method includes determining an electrical resistance of the at least one silicon rod, comparing the resistance to a set point to determine a difference, and controlling a power supply to control a power output coupled to the at least one silicon rod to minimize an absolute value of the difference.
|GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY - A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
|MEMS DEVICE AND FABRICATION METHOD - A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.
|PRODUCTION METHOD FOR OXIDIZED CARBON THIN FILM, AND ELEMENT HAVING OXIDIZED CARBON THIN FILM AND PRODUCTION METHOD THEREFOR - The production method for the oxidized carbon thin film of the present disclosure includes: a first step of preparing a carbon thin film and iron oxide that is in contact with the carbon thin film and contains Fe
|Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer.
|HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR PHOTORESIST STRIP APPLICATIONS - Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.
|Method for fabricating semiconductor device to which test is performed at wafer level and apparatus for testing semiconductor device - A method for fabricating a semiconductor device includes placing a semiconductor wafer on a stage, the semiconductor wafer having a plurality of ball-shaped external connecting terminals projected from a surface, bringing a probe card close to the semiconductor wafer placed on the stage to bring a plurality of probe terminals included in the probe card into contact with the external connecting terminals respectively, and applying a voltage to the semiconductor wafer through the probe terminal to perform a test of the semiconductor wafer. The probe terminals contact all the external connecting terminals.
|DEVICE MANUFACTURING METHOD - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
|APPARATUS AND METHOD FOR ELECTRICAL CHARACTERIZATION BY SELECTING AND ADJUSTING THE LIGHT FOR A TARGET DEPTH OF A SEMICONDUCTOR - The present disclosure provides methods and apparatus that enable characterization of an electrical property of a semiconductor specimen, e.g., dopant concentration of a near-surface region of the specimen. In exemplary method, a target depth for measurement is selected. This thickness may, for example, correspond to a nominal production thickness of a thin active device region of the specimen. A light is adjusted to an intensity selected to characterize a target region of the specimen having a thickness no greater than the target depth and a surface of the specimen is illuminated with the light. An AC voltage signal induced in the specimen by the light is measured and this AC voltage may be used to quantify an aspect of the electrical property, e.g., to determine dopant concentration, of the target region.
|ELECTRICAL ALIGNMENT MARK SET AND METHOD FOR ALIGNING WAFER STACK - An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via maybe electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.
|SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.
|SOLAR BATTERY PANEL INSPECTION APPARATUS, METHOD OF INSPECTING SOLAR BATTERY PANEL, AND METHOD OF MANUFACTURING SOLAR BATTERY PANEL - A solar battery panel inspection apparatus is an apparatus for inspecting a solar battery panel including a transparent insulating substrate having a main surface, and a transparent electrode layer, a semiconductor photoelectric conversion layer and a back electrode layer which are sequentially stacked and having an outer circumferential insulating region in which the main surface is exposed, to check the insulation performance of the outer circumferential insulating region. The solar battery panel inspection apparatus includes the first terminal to be brought into contact with the back electrode layer; the second terminal to be brought into contact with a region of or in proximity to an outer circumferential edge of the outer circumferential insulating region; one or more third terminals to be brought into contact with the outer circumferential insulating region between the first terminal and the second terminal; a voltage application unit for applying a voltage each between two terminals selected from these terminals; and a current detection unit detecting a current flowing between the two terminals to which a voltage is applied.
|METHOD FOR MAKING A REDISTRIBUTED WAFER USING TRANSFERRABLE REDISTRIBUTION LAYERS - A method of making redistributed electronic devices that includes providing a wafer having a plurality of electronic devices, each electronic device having a pattern of contact areas forming die pads. The method also includes forming redistribution layers on a temporary substrate having a pattern of contact areas forming wafer bonding pads matching the die pads and a pattern of contact areas forming redistributed pads different than the wafer bonding pads, the wafer bonding pads are coupled to the redistributed pads through a plurality of stacked conductive and insulating layers. The die pads are coupled to the wafer bonding pads, and the temporary substrate is removed. The wafer and redistribution layers are then divided into a plurality of redistributed electronic devices.
|DEVICE AND METHOD FOR FORMING ON A NANOWIRE MADE OF A SEMICONDUCTOR AN ALLOY OF THIS SEMICONDUCTOR WITH A METAL OR A METALLOID - Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.
|SEMICONDUCTOR DEVICE AND STRUCTURE - A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.
Patent applications in class Electrical characteristic sensed
Patent applications in all subclasses Electrical characteristic sensed


text:
Latest John Isner Stories
2014-08-28 08:25:49
The new revolution in muscle support and pain relief to get you back in the game MILWAUKEE, Aug.
2014-01-14 00:20:30
AUCKLAND, New Zealand, Jan.
American No. 1 and North Carolina Native John Isner to Host Charity Exhibition Featuring Andy Roddick
2013-10-25 23:21:20
4th Annual Ebix Charity Challenge Returns to Isner's Hometown of Greensboro, N.C.
2010-07-03 09:08:00
DAYTONA, Fla., July 3 /PRNewswire-FirstCall/ -- Records show he has endurance, but Jeremiah Weed wants to know if he has speed. On the heels of winning the longest match in the history of professional tennis, no man is more deserving of some "R & R" than tennis star John Isner.
2009-10-05 10:16:17
Gael Monfils and Stanislas Wawrinka claimed straight-set wins Monday in first-round play at the $1.23 million Japan Open tennis tournament in Tokyo. Monfils, seeded fourth, used three service breaks to dispatch Marsel Ilhan in 66 minutes.
Word of the Day
- The governor of a province or people.
The word 'ethnarch' comes from a Greek word meaning 'ruler of a tribe or nation'.


text:
'40 Days of Purpose' study underway
Have you ever wondered, "What on Earth am I here for?" Do you think you may have missed God's will for your life?
Join United Methodist Church for the "40 Days of Purpose" study, using the book "The Purpose Driven Life" by Rick Warren. Participants will learn God's five purposes for your life, then put the purposes into practice through the personal disciplines and group connections.
Are you a newspaper subscriber but you don't have a Digital Access account yet? https://secure.forumcomm.com/?publisher_ID=40&event=subscriber/lookup.
You will need your subscription account number and phone number. Not sure if you have an account? Email us at email@example.com and we can help you.