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Meet the expertsJo Lawrence – the pink plumber
You are setting up your female-only plumbing business after eleven years in the industry, what do you call it? Jo Lawrence laughs, ' Pink Plumbers of course! It came from talking to some of the mums at my son's judo class and when it...
Introduction to Careervision Training Limited
1 Plumbing course
Learning247 is your one-stop centre to learn all about online computer training, where you will learn via hands-on video based study.
Learning247 is your one-stop centre to learn all about online computer training, where you will learn via hands-on video based study.
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A really excellent DVD. Went into great depth on the subject with loads of pract...more
Special Price Offer - Now Only £36 - Limited Time Only Legionella Management Online Training Current legislation...
AT & F Solutions Ltd
1 Plumbing course
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Safeguarding Vulnerable Adults and Children
well laid out very easy to read and understand, good feedback at end of course t...more
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QST Worldwide
1 Plumbing course
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Quantity Surveying Training.ref.10 - Administration
This course was good, concise but full of data. Enjoyed it, will help me unders...more
Typical Ladies and Gents toilets in a commercial building, supply pipework, sanitary fittings, waste pipes, fittings, drain...
Paragon Training (Health and Safety)
1 Plumbing course
About Legionella Awareness Training Legionella is of increasing concern, make sure you and your staff are aware of the...
1 Plumbing course
Cases of Legionnaires' disease, caused by legionella bacteria, are fortunately rare. However, when they occur, they can be...
Skills2learn Ltd
1 Plumbing course
This training package is designed by colleges and e-learning experts for the education sector and is aligned to the core...
Training Pal
1 Plumbing course
Learning Objectives: At the end of the course, students will be able to: explain what Legionella Bacteria is and where it...


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This is great Daniel, raw and confronting, congrats
Love it!!! Was wondering where you had got too!
I love your creepy drawings!
such chaotic detail that comes together so well, amazing!
Love those eyes. They're almost fetal.
god you're brilliant
brilliant with a very suggestive title. you rock!
This has so much energy and movement!
wow this is pretty intense. I feel the movement as well.
came through your town late last year, nice place. great sketch. Is that a booga or a worm?
Crazy as always, more now!

subset: commoncrawl


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I keep reading the Iconia A500 has a nVidia GeForce GPU, does the TF have the same or does it use the Tegra 2 to render graphics? Just wondering if the A500 would render better.
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Nyack College Arts and Sciences News
Turk, Romaine and Cid discuss The Death of Ivan Ilych
Posted by Fernando.Arzola on Saturday November 17, 2012
The Men of Letters participated in its first Book Discussion event. The group examined Leo Tolstoy's The Death of Ivan Ilych at Saint Mary Magdalen Orthodox Church, NY, NY. The dialogue was thought provoking and passionate.
Dr. David Turk (Provost) facilitated the gathering. Also participating in the event was Dr. James Romaine (Associate Professor of Art History) and Prof. Alfredo Cid (Lecturer of Philosophy). Special thanks to our host, Russian Literature scholar, and Rector, Rev. Yakov Ryklin.
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- Percie McLain joins A&S as Administrative Coordinator
- Dr. Park initiates Nyack College Fishing Club
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- Dr. Park joins BIOL-O-GEE R.A.P. TEAM
- Division of Student Success Awarded Certification
- Dr. Poston and Pamela Code explore death, religion and science
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COLUMBIA Men's Perfect Cast Polo
|Eligible for Free Shipping, No Minimum! (see promotion details)
|Members of The League get 5% back when you spend $100! (see promotion details)
Product Details
Designed specifically with fishing in mind, the COLUMBIA® men's Perfect Cast™ polo features radial sleeves to accommodate the big arm moves required for casting. The midweight pique fabric wicks moisture and blocks UV rays, while rear shoulder vents enhance airflow for cool, dry comfort out on the water. Other details include rib trim at the collar and cuffs, as well as side mobility vents at the hem.
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- Fabric Content: 100% polyester
Additional Info
- Two-tone fabric
- Rib trim
- Side mobility vents
- Made in China
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- Breathable
- Comfortable
- Lightweight
Best Uses
- Warm Climate
Comments about COLUMBIA Men's Perfect Cast Polo:
This was gift for my son, he loves the shirts, he is very hot natured and the vents and breathability of the fabric is perfect for him. It does run large - if you wear a medium in most shirts, you will probably need a small in this shirt.
- Sizing:
- Feels full size too big
- Was this a gift?:
- Yes
- Comfortable
- Lightweight
- Not Stain Resistant
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- Casual Wear
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- Fishing Golfing
- Warm Climate
Comments about COLUMBIA Men's Perfect Cast Polo:
Love the feel and comfort
- Sizing:
- Feels true to size
- Was this a gift?:
- Yes


text:
Recessing the floating gate of a NVRAM cell within a substrate or semiconductor layer between isolation structures permits manufacture by a simplified self-aligned process of high yield and economy while supporting maximum integration density and reducing or eliminating severe topography of the control gate connections which are formed in strips having a generally planar lower surface and which are of improved robustness and potentially fine pitch. Impurity implants are facilitated by thicknesses of various material present during portions of the process and in various combinations which may be advantageously exploited to obtain tailoring of impurity concentrations and profiles of both NVRAM cells and damascene field effect transistors formed by similar and compatible processes.
1. A method of making a semiconductor device including the steps of:
forming a trench in a semiconductor substrate through an aperture in a layer of material formed on said semiconductor substrate,
forming an insulator layer on a surface of said semiconductor substrate within said trench,
filling said trench and said aperture with semiconductor material such that said semiconductor material protrudes above a surface of said semiconductor substrate,
planarizing said semiconductor material, said trench filling and planarizing steps being performed in accordance with a damascene process,
implanting material in said semiconductor substrate self-aligned with said semiconductor material protruding above a surface of said semiconductor substrate;
removing a portion of said semiconductor material in said trench;
depositing a further insulating layer in said trench over a remaining portion of said semiconductor material; and
filling a remaining portion of said trench and said aperture with further semiconductor material.
2. A method as recited in claim 1, including the further step of
implanting material into said semiconductor substrate prior to said step of filling said trench.
3. A method as recited in claim 1, including the further step of
forming an isolation structure in a surface of said semiconductor substrate.
4. A method as recited in claim 1, including the further step of
forming a nitride layer comprising said material on said surface of said semiconductor layer or substrate.
5. A method as recited in claim 4, including the further step of
forming a further nitride layer comprising said layer of material on a surface of said nitride layer.
6. A method as recited in claim 5, including the further step of
forming an oxide layer comprising said layer of material on said further nitride layer.
7. A method as recited in claim 1, including the further step of
planarizing said semiconductor material to said layer of material.
8. A method as recited in claim 4, including the further step of
planarizing an isolation structure to a surface of said nitride layer.
9. A method as recited in claim 6, including the further step of
planarizing said semiconductor material to said oxide layer.
10. A method as recited in claim 5, including the further step of
planarizing semiconductor material to said further nitride layer.
11. A method as recited in claim 1, wherein said trench is located between said implanted material.
12. A method as recited in claim 11, wherein said material filling said trench forms a gate structure of the transistor.
13. A method as recited in claim 1, wherein said implanting step includes a step of implanting said material in said semiconductor substrate through said layer of material formed on said semiconductor substrate.
14. A method as recited in claim 13, wherein said implanting step includes implanting said material in said substrate at a location adjacent to sidewalls of said trench.
15. A method as recited in claim 1, wherein said implanting step is performed after said filling step.
16. A method as recited in claim 1, wherein said insulating layer has respective ends which contact sidewalls of said trench, so as to isolate said semiconductor material within said insulating layer, the sidewalls of said trench, and a bottom of said trench.
17. A method as recited in claim 1, further comprising:
forming an isolation structure adjacent said trench, and
wherein said implanting step includes implanting said material so as to be selfaligned with said isolation structure.
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memories field effect transistors and, more particularly, to non-volatile random access memory (NVRAM) structures and their manufacture.
2. Description of the Prior Art
Semiconductor memory structures are well-known and designs thereof have been integrated at high densities, providing, at the present state of the art, several million dynamic memory cells or tens of thousands of static memory cells on a single chip along with decoding, addressing, sensing and driving circuits allowing data stored therein to be changed at will. Such memories and the speed of access they allow are indispensable to support the high speed of digital processors presently available. However, the maintenance of storage states of the cells requires at least constant application of at least stand-by power and, for dynamic memory cells, periodic refreshing. Since storage states are not otherwise maintained, such memories are referred to as being volatile.
So-called read only memories (ROMs) are not volatile but the contents thereof cannot be changed. ROMs are, nevertheless, useful for personalization of electronic devices and storage of basic operational programming of processors since they generally support very high speed access. Otherwise, other storage media such as magnetic disks, bubble memories and the like have generally been used for non-volatile storage of data when the capability of changing the data must be provided even if access to the data is generally much slower.
To partially overcome the slower access time of other storage devices and media, various caching schemes have been developed which are, in general, quite effective to support the function of available high speed processors. Nevertheless, delays may be encountered when data required by the processor is not present in the cache, reducing predictability of task completion time. Further, use of a cache does not provide freedom from other characteristics of the storage medium utilized such as the mechanical vulnerability of magnetic disk drives to wear, impact, vibration and the like. Expansion of cache capacity to avoid significant delays due to the number of cache misses which may be encountered requires a degree of processing overhead as well as the time to access the desired amount of information from main storage, particularly as compared with processor cycle time.
Non-volatile semiconductor structures are known and have been referred to as programmable read only memories (PROMs) in view of the fact that data can be written or programmed therein rather than being established during the fabrication of the device. More recently, designs of PROMs have allowed data to be changed by erasure and rewriting. These structures generally employ electron tunnelling phenomena through a thin dielectric layer. Each tunnelling operation, however, causes a finite amount of damage to the dielectric and the number of write and erase cycles which can be performed before failure has been limited. Accordingly, these devices have been referred to as electrically erasable programmable read only memories (EEPROMs or flash EEPROMs if all cells of a partition are simultaneously erased) since they are intended for applications in which data will be changed only rarely.
More specifically, memory cells of EEPROMs generally include a structure similar to that of a field effect transistor but having an insulated floating gate electrode to which a control gate is capacitively coupled. Thus, a low voltage on the control gate together with presence or absence of charge stored on the floating gate can allow the reading of the cell in accordance with the resultant conductance of the transistor while higher voltages on the control gate cause hot electron injection or tunnelling of electrons from the conduction channel to or from the floating gate for writing or erasure of the EEPROM cell.
Very recently, some electron tunnelling mechanisms (e.g. Fowler-Nordheim tunnelling) have been exploited in which the damage to the dielectric during write and/or erase operations is very much reduced. Together with improvements in dielectric quality and distribution of write and erase operations over the memory array, the number of write and erase operations which can be accomplished before device failure has become sufficient to the expected service lifetime of computers and other electronic apparatus in which such memories may be employed. Thus, such devices can be used much in the manner of random access memories and have come to be referred to as non-volatile random access memories (NVRAMs). The number of storage cells which may be provided on a single chip has also become comparable to that of static RAMs and approaches that of dynamic RAMs. The non-volatile random access memories (NVRAMs) nomenclature thus also connotes the potential further applications now possible with the practical removal of limitations on the number of write/erase cycles which can be performed without significant degradation of the tunnelling oxide.
It should be understood, however, that the basic structure of the NVRAM cell has remained effectively unchanged from the structure of an EEPROM cell although a different tunnelling mechanism may be exploited and the operating parameters correspondingly altered. The structure of a NVRAM cell is relatively complex and critical and development of high manufacturing yields consistent with high integration density has proven difficult. Moreover, the additional applications for which modern NVRAMs are currently suitable has increased the need for reduction of NVRAM cell size and increased integration density.
Tunnelling effects on which NVRAMs continue to rely for write and erase operations, however, requires a higher voltage than is required for read operations while high integration density requires small sizes of the memory cells. To avoid breakdown, latch-up and other known types of malfunctions, isolation structures are generally required between NVRAM cells and write and erase voltages are kept as low as possible consistent with correct operation. By the same token, narrow operating margins for write and erase voltages together with isolation structures such as shallow trench isolation (STI) and recessed oxide isolation (ROX), both of which employ an insulator within the substrate and may also extend above the substrate surface, have required formation of the floating gate and the control gate along the sidewalls of the isolation structure in order to develop an adequate so-called coupling ratio of the capacitances of the control and floating gates. In general, the floating gate is made to overlap a portion of the ROX or STI, covered with a blanket layer of interpoly oxide and a doped polysilicon gate layer applied thereover and patterned.
Since the control gate must extend over the floating gate where the floating gate, in turn, extends over an isolation structure, severe large step topography is unavoidable in the control gate and the interpoly oxide, as well. This step is sufficiently steep to allow formation of a sidewall during subsequent routine processing (if not prevented by additional process steps) or breaks in the silicide of which the control gate or a connection thereto may be partially comprised (e.g. overlaying a doped polysilicon layer with a refractory metal silicide having low sheet resistance to form a so-called polycide connector). Breaks in the control gate silicide severely compromise manufacturing yield since a control gate generally overlies and provides access to a plurality of NVRAM cells and a break thus isolates and prevents access to cells beyond the break in the control gate.
Nevertheless, it should be understood that the severe topography described above has generally been exploited to advantage in developing an adequate coupling ratio of capacitance of the control gate to that of the floating gate. A minimum coupling ratio must be maintained so that the capacitive voltage divider can adequately raise or lower the potential of the floating gate for tunnelling to occur to write and erase the NVRAM cell. There is thus a trade-off between the coupling ratio and the voltage which must be applied for reliable writing and erasure and, consequently, the size and spacing of other structures to avoid breakdown, latch-up and the like and, ultimately, between manufacturing yield and the integration density which can be achieved. Accordingly, some degree of compromise of manufacturing yield, integration density and design optimization has been tolerated in previous designs which has increased the cost and limited production and application of high density NVRAMs both at the package level and in various computers and other electronic apparatus.
So-called damascene processes for semiconductor manufacture are now familiar to those skilled in the art, particularly for the reliable formation of highly robust conductors at fine pitch. Essentially, a generalized damascene process comprises forming a groove or recess of desired dimensions or pattern in a substrate or semiconductor layer, filling the groove or recess by the deposition of a blanket layer of material and planarizing the blanket layer back to the original surface of the substrate or semiconductor layer. The planarization thus serves to separate the layer into a plurality of formations, such as conductors, in accordance with the original shape of the groove(s) or recess(es). During and after the planarization, the material in the grooves or recesses is supported on all sides, resulting in a highly robust structure even when comprised of very soft metals or other materials. Since the grooves or recesses are ideally formed lithographically beginning with a highly planar surface, high lithographic resolution and fine pitch are thus supported. Further, the planarization after blanket layer deposition and filling of the grooves or recesses provides a highly planar surface on which further lithographic processes may be carried out with high accuracy and resolution.
However, at the present state of the art, due to difficulties with trench filling, throughput of planarization processes and the like, damascene processes are generally limited to the formation of conductors in which the advantages of robustness and fine pitch are pronounced and not otherwise obtainable. Damascene processes are not widely used for device (e.g. transistors and capacitors) construction within a substrate or layer or with materials which do not reliably fill high aspect ratio grooves or recesses. For high manufacturing yields, surface formation processes such as deposition and etching or patterned implantation are generally preferred for high manufacturing yields in the formation of specific devices integrated on a chip.
It is therefore an object of the present invention to provide a new geometry for NVRAM cells allowing increased manufacturing yield at increased integration density while allowing maintenance or increase of operating margins at low write and erase voltages.
It is another object of the invention to provide an NVRAM cell structure which can be formed with fewer, less critical and more economical process steps while increasing manufacturing yield.
It is a further object of the invention to avoid severe interpoly insulator and control gate topography in NVRAM cells which may be integrated at high density in a manner compatible with the inclusion of other devices on the same chip without significant increase of process complexity.
It is yet another object of the invention to provide a process of manufacture which provides substantial flexibility in dopant implantation processes for both memory cells and transistors made by compatible processes, particularly allowing independence of source/drain doping and channel doping.
In order to accomplish these and other objects of the invention, a semiconductor device is provided comprising a substrate or layer having an isolation structure protruding therefrom, a gate insulator and electrode recessed within a trench in the substrate or layer with the electrode protruding above the substrate surface, and an implanted region located in accordance with an implantation energy and self-aligned with the trench.
In accordance with another aspect of the invention, a method of making a semiconductor device is provided including the steps of forming a trench in a semiconductor layer or substrate through an aperture in a layer of material, forming an insulator layer on surfaces of the semiconductor layer or substrate within the trench, filling the trench and the aperture with semiconductor material such that said semiconductor material protrudes above a surface of the semiconductor layer or substrate, and implanting material in the semiconductor layer or substrate self-aligned with the semiconductor material protruding above a surface of the semiconductor layer or substrate.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a cross-sectional view of a prior EEPROM or NVRAM cell structure,
FIG. 2 is a plan view of EEPROM or NVRAM cell layout,
FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 are cross-sectional views showing process steps in the practice of the invention and the formation of a damascene NVRAM cell in accordance therewith along section 1--1 of FIG. 2, orthogonal to a control gate conductor,
FIG. 14A is a cross-sectional view of a partially completed damascene field effect transistor which can be constructed employing the principles and processes of the invention,
FIGS. 19, 20, 21, 22, 23, 24, 25, 26 and 27 are cross-sectional views of the device in accordance with the invention along section 2--2, parallel to a control gate conductor at various points in the manufacturing process depicted in FIGS. 3-18, and
FIGS. 28, 29, 30, 31, 32, 33, 34, 35 and 36 are cross-sectional views of the device in accordance with the invention along section 3--3, of FIG. 2 orthogonal to the control gate conductor at various points in the manufacturing process depicted in FIGS. 3-18 and in the same direction but at the location of an isolation structure.
Referring now to the drawings, and more particularly to FIGS. 1 and 2, there is shown, in highly simplified cross-sectional form and plan view, respectively, an EEPROM or NVRAM gate structure 10 over which the present invention is an improvement. FIG. 2 is a plan view of the layout of the isolation structure 12 in the form of a grid and control gate 16 which is common to both the prior structure of FIG. 1 and the invention as will be described below. As to FIG. 2, however, the isolation structure is preferably a shallow trench isolation structure for practice of the invention rather than a recessed oxide structure shown in FIG. 1. However, a recessed oxide could also be employed in accordance with the principles of the invention.
In the structure 10 shown in FIG. 1, recessed oxide (ROX) 12 is used for isolation between adjacent gates. It is preferred that transistors including a floating gate for storage of charge be formed in very close proximity since the memory cells are programmed through series connections of the source and drain regions (in front of and behind the plane of the page of FIG. 1) and control gate electrode 16 of a plurality of such transistors. Close proximity of the NVRAM or EEPROM cells thus minimizes gate connector resistance as well as being generally necessary for high integration density. Therefore, isolation is generally necessary to minimize interaction between memory cells formed by those transistors in such close proximity.
In the EEPROM or NVRAM gate structure 10, a recessed oxide structure is formed and so called since a portion of the oxide 12 is recessed into the substrate 11. Regions between the ROX isolation structures are covered by a thin tunnelling oxide film 13. The floating gates 14 are preferably formed of doped polysilicon and extend not only over the tunnelling oxide but over the sloping sidewalls and a portion of the surface of the ROX isolation structures 12. The floating gates 14 are separated by a distance, d, at the upper surface of the ROX isolation structure 12 which governs the breakdown voltage.
The floating gates 14 and exposed portions of the ROX isolation structures are covered with a control gate oxide layer 15 and a second polysilicon layer which serves as the control gate electrode 16 and common connection. The area of the control gate oxide 15 between the control gate electrode 16 and the floating gate 14 establishes the capacitance therebetween. Therefore, it can be seen that the conventional structure imposes a trade-off between the capacitance value and the breakdown voltage for a given dimension L2 in a direction parallel to the substrate surface. Further, the severe surface topology of this structure tends to cause the control gate oxide (sometimes referred to as the inter-poly oxide) 15 to be of questionable quality in the encircled region 17 of the illustration of FIG. 1.
Poor quality oxide in this region reduces breakdown voltage and imposes a further requirement that ample spacing between floating gates be provided to obtain acceptable manufacturing yields. Moreover, the severe topography of the control gate 16 may cause breaks in regions 19 or support the unintended formation of sidewalls 18 by other processes. This circumstance will generally be aggravated if STI structures having vertical or more steeply sloped sides are employed even though such steeper sides may reduce dimension L2, as shown. It should also be noted that, due to the extent of floating gate 14, L2 must be wider than the separation of floating gates 14 and tends to reduce the area of the tunnelling oxide. Therefore L2 must be sized in accordance with both the ratio of oxide areas to obtain a desired capacitance ratio and also in regard to breakdown voltage and floating gate separation, adjusted for the possibility of poor quality oxide, in order to obtain satisfactory manufacturing yields.
The dimension L2 is thus a major portion of the "footprint" of an EEPROM cell which is not amenable to scaling to smaller sizes. This is particularly true since the very thin tunnelling oxide layer cannot be scaled in thickness consistent with reliability of formation; requiring certain minimum voltages to cause tunnelling and imposing limits on the minimum breakdown voltage which must be withstood by the device.
The invention simultaneously addresses the problems of breakdown, integration density and control gate connector topography notwithstanding employment of STI structures by forming NVRAM cells recessed within the substrate in the manner of a Damascene process and in a manner self-aligned with the isolation structures. Thus, process simplification is provided by the invention at maximum integration density while allowing maximum NVRAM cell area and coupling ratio and minimizing of the area of the isolation structure.
Referring now to FIG. 3-17, the process of forming a damascene NVRAM cell in accordance with the invention will be discussed. Specifically, in FIGS. 3 and 28, a substrate 30, preferably planarized by an oxide chemical/mechanical polishing process, is shown. A first nitride layer 31 is deposited thereon and patterned in accordance with desired locations 32 of shallow trench (or ROX) isolation structures. The STI trenches 32 are then filled and polished back to the nitride, forming the structure as shown in FIGS. 3 and 28 and having the general pattern illustrated in FIG. 2 in plan view. The nitride layer 31 has a high hardness and serves as a polish stop for polishing the STI fill.
Then, as shown in FIGS. 4 and 29, a second nitride layer 41 is deposited. The process for depositing nitride layers 31 and 41 is not at all important to the invention and numerous suitable techniques are familiar to those skilled in the art. Then, as shown in FIGS. 5 and 29, an oxide layer 51 is deposited, preferably by a tetra-ethyl orthosilicate process familiar in the art but, again, not critical to the practice of the invention.
Next, a control gate mask layer 61 of a suitable resist is applied (FIG. 6) and patterned as indicated in FIG. 7. The regions over which the patterned resist does not lie correspond to the control gate connections (i.e. located as shown by dashed lines 16 in FIG. 2), and, between STI structures (in front of and behind the plane of the page of FIGS. 6 and 7), define locations of the NVRAM cells.
To form the NVRAM cells, the oxide layer 51 is selectively etched in accordance with the opening 71 in control gate mask 62, as shown in FIG. 8, followed by selectively etching of both first and second nitride layers 41, 31, as shown in FIG. 9, to expose the substrate. FIG. 20 corresponds to section 2--2 and FIG. 30 corresponds to section 3--3 at the same point in the process shown in FIG. 9 for section 1--1.
As shown in FIG. 10, along section 1--1, and 21, along section 2--2, the substrate is etched with an etchant which is selective to the substrate material (e.g. silicon) and which does not significantly etch the edge of oxide layer 51 (which is otherwise masked by resist mask 62) or the STI oxide 32. This etch is continued to form a recess 100 in the substrate preferably having a depth of about 80-150 nm. A subsequent etch of both the substrate 30 and the STI oxide 32 (which could be done in separate selective etch steps although a single non-selective etch is preferred) of an additional 200-500 nm is then performed as shown in FIG. 11 and 31. This reduces the STI oxide structure height along section 2--2, as shown in FIG. 22, appearing as a notch therein in FIG. 31. It should be noted that the surface of the silicon substrate as shown in FIG. 22 along section 2--2 corresponds to the bottom of the silicon trench 110 in FIG. 11.
Once the damascene NVRAM cell trench 110 is thus completed, the control gate resist can be removed and, to remove any contamination from within the trench 110, an oxide is preferably grown and etched away. Then the tunnelling oxide 121 is grown within the trench to a desired thickness by any suitable process resulting in the structure shown in FIGS. 12 and 22. The preferred thickness is generally about 50 Angstroms but is not at all critical to the practice of the principles of the invention. As shown in FIG. 13 (and in an orthogonally taken cross-sectional view in FIG. 23), the damascene trench is filled by deposition of a layer of polysilicon which is polished back to the oxide 51 leaving a polysilicon strip 131 from which the floating gate will subsequently be formed.
It should be noted that the oxide 51 need not function as a polish stop since it will be later removed and the height of the polysilicon is not particularly critical to the final device since it will be etched back to much smaller dimensions within the trench although a particular height corresponding to the final thickness of oxide 51 may be exploited to advantage as will be discussed below. It should also be appreciated that the nitride layers 31, 41 and oxide layer 51 are in front of and behind the plane of the page in FIGS. 20-26 and therefore do not appear therein. Nitride layer 31 has been earlier etched away at the location of the STI structure (e.g. in the plane of section 3--3) in the course of formation thereof, as shown in FIG. 3 but the second nitride layer 41 appears in FIGS. 29-35 bounding the NVRAM cell trench 110 (located as shown by dashed lines 16 in FIG. 2 which also corresponds to the control gate electrode connection) while both nitride layers 31, 41, are seen in FIGS. 3-19 along section 2--2.
Referring now to FIGS. 14 and 32, the remainder of oxide layer 51 is selectively removed creating a polysilicon protrusion having a height above the surface of the nitride layer 41 equal to the thickness of the remaining oxide 51 of FIG. 13 after planarization by polishing. This protruding shape and height thereof is useful in limiting the depth within the polysilicon reached by the source/drain implant to be performed so that dopants/impurities which may be implanted in the polysilicon during the source/drain implant may be removed when the polysilicon 131 is etched to the dimensions of the floating gate as will be discussed below with reference to FIG. 15. Increased protection of the gate insulator 121 from implant damage is provided, as well, by the height of the protrusion. A timed etch is generally of sufficient accuracy although endpoint detection through optical emission spectroscopy or other techniques to more accurately form the floating gate could be based on the implant depth.
Source/drain implants are preferably then performed through the nitride layers 31, 41, and are thus effectively self-aligned with the polysilicon strip 131 and the STI structure 33. The implantation dose and energy should be adjusted in view of the dopant diffusion which will occur during a subsequent annealing process to place the source and drain junctions at approximately the bottom of trench 110. (FIG. 23 remains representative of the structure as it exists along section line 2--2 for the processes shown in FIGS. 12--14.) Alternatively, source and drain implantation and diffusion can be deferred until the point in the process shown in FIG. 18 after formation of a new polysilicon protrusion 171 with an oxide layer 181 thereover, as will be discussed below, and removal of nitride layers 31, 41.
Incidentally, the formation of a protrusion and related steps featured by the invention also has utility in the processing and structure of a recessed or damascene field effect transistor (FET) similar to the NVRAM cell but without provision of a floating gate (essentially the form shown in FIG. 14 before the floating gate is formed by etching back the polysilicon and deposition or growth of a control gate oxide). As is understood in the art, channel dopant concentrations and profiles are extremely important to the performance properties and threshold of field effect transistors as well as avoidance of latch-up, short channel effects (generally approached, in known field effect transistors formed on a semiconductor surface, by so-called lightly doped drain structures). However, optimal channel dopant concentrations are difficult to obtain in FETs formed at a substrate surface without affecting or being affected by the implant to form the source and drain regions. For example, raising the dopant concentrations under the source and drain regions increases the diffusion capacitance of the FET.
If a field effect transistor were to be formed by a damascene process, the channel would be recessed within a body of semiconductor material and impurities would be implanted at the bottom of the trench in which the gate would be formed as well as on either side of the trench/gate to form the source and drain regions as generally shown in FIG. 14A at 141, 142 and 143, respectively. Formation of these separate regions would generally require several distinct implantation steps with different dopants and, more importantly, at different energies. In this regard, it should be noted that in FIG. 11, the control gate mask 62 is present over nitride layers 31, 41, but that there is no layer formation on the interior of trench 110. In FIG. 12, the control gate mask has been removed and an oxide grown on the trench interior. In FIG. 13 the trench has been filled with polysilicon and the oxide layer 51 remains in place. In FIG. 14, the oxide 15 has been removed to leave a polysilicon protrusion 131 alluded to above while the nitride layers 31, 41, remain in place. In FIG. 18, the nitride layers have been removed while a protrusion has been formed to the thickness of the nitride layers. FIG. 18 also reflects diffusion of the source/drain implants.
Since impurity implant processes can be made through any of these layers mentioned in the preceding paragraph with suitable adjustment of the implant process energy and different layers are present in different combinations and thicknesses (which, with the exception of oxide 121, are all removed in the completed device) in the source/drain regions and in the channel/gate region, respectively, it can be seen that a variety of materials and thicknesses in different combinations are available and can be exploited as masks during implantation processes at various points in the process to tailor the implants.
Specifically, in the structure in accordance with the invention, the channel implant could be done at relatively low energy prior to formation of the polysilicon protrusion while the source and drain regions are masked by nitride, oxide and/or resist. After the protrusion is formed, the height of the protrusion allows higher energy source/drain implantation while effectively masking the channel. The variety and combinations of other layers in both material and thickness may permit implantation of the drain/source regions and the like concurrently with tailoring the channel profiles. The implantation of impurities in the polysilicon protrusion can also serve as a diffusion source for diffusion of the impurity into other surrounding structures.
It should also be appreciated that the ability to form high-performance transistors at high integration density by the same combination of processes by which the damascene NVRAM cells are formed also permits processing economies to be achieved in the development of decoders, drivers, logic and the like on the chip to support the function of the NVRAM array. It is only necessary to suitably segregate the processing of NVRAM cells and field effect transistors such that floating gates will not be formed and the gate oxide thickness optimized in the latter. Use of block-out masks at relatively low resolution during processes generally corresponding to FIGS. 15-17 is considered sufficient to segregate processing of field effect transistors and NVRAM cells.
Returning to the NVRAM cell structure, once the source/drain implants are completed, the polysilicon 131 and tunnelling oxide 121 are etched back to a desired dimension as shown in FIGS. 15, 24 and 33. It should be noted from FIG. 24 that this etching process separates the floating gates 131 at the STI structures 32. Then a control gate dielectric layer 161, preferably of a layered oxide-nitride-oxide (ONO) construction, as shown in FIGS. 16, 25 and 34 is applied.
The remainder of the damascene trench opened by the etching of the floating gate 131 described above with reference to FIG. 15 is again filled with doped polysilicon by deposition of a blanket layer followed by polishing back to the nitride polish stop layer 41 as shown in FIG. 17 and 35. This process leaves further polysilicon strips 171 as control gates and their connections, extending over the STI structures 32 as may be best observed in FIGS. 26. The polysilicon control gate electrodes can then have a protective oxide 191 grown or deposited thereon, preferably during annealing to diffuse the source and drain regions to desired junction profiles 142, and the remaining portions of nitride layers 31, 41 can be stripped to complete the structure shown in FIGS. 18, 27 and 36.
The remainder of the device, including contacts to the structure of FIG. 18 as well as other logic, decoders, level shifters and the like or even macros or complete processors can be fabricated by known methods, preferably in accordance with the damascene FET process described above or CMOS technology, on the remainder of the chip. It should be appreciated that while areas on which other such circuits are to be formed could be covered by a block-out mask during the above-described operations, since many of the materials and processes described above are common to the formation of CMOS devices and circuits, many of the above-described processes are compatible therewith and can serve to concurrently form damascene FET or CMOS structures. Accordingly, some manufacturing economies and reduction of heat budget can potentially be achieved.
Corresponding application and removal of block-out masks at low resolution and wide tolerance of registration accuracy is a relatively low-cost and high yield process when processing specific to NVRAM cells or support circuitry must be carried out to the exclusion of the other. Note also that the NVRAM cell processes described above require only a single mask 62 to define the control gate electrode locations; after which all other processes are self-aligned or derive patterning by planarization in accordance with the damascene process described above and thus are of extremely high manufacturing yield.
In view of the foregoing, it is seen that the above described process provides a novel damascene NVRAM cell fabricated within a substrate or semiconductor layer which is self-aligned with isolation structures and utilizing the entire area therebetween to assure suitable coupling ratio of the control gate and floating gate thereof and adequate operating margins at relatively low write and erase voltages. The same features also allow minimization of NVRAM cell size and maximization of integration density to the limit of scalability and minimum width of control gate conductors that can be produced lithographically. Self-aligned processes also reduce process complexity while increasing process economy and manufacturing yield. Severe control gate connection topography is avoided and, since the self-aligned processes do not require allowance for alignment tolerances, maximum integration density may be realized.
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
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Monica Clark
News Articles
Articles by Monica Clark
St. Mary's College gets its first lay presidentMar. 27, 2013 People
Wednesday marks 25th anniversary of International Day for the Eradication of PovertyOct. 17, 2012 Peace & Justice
Two groups, two paths for US women religiousMay. 26, 2012 Sisters' Stories
Occupy activists arrested in second takeover of San Francisco archdiocesan buildingMay. 2, 2012 People
San Francisco police arrest Occupiers who took over archdiocesan buildingApr. 4, 2012 Peace & Justice
Priest who inspired Cesar Chavez dies at age 88Mar. 2, 2012 People
California Supreme Court to decide on statute of limitations in abuse casesJan. 17, 2012 Accountability
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How late can I divide Pampas Grass?
l_w_davisMarch 4, 2013
I can see the new green shoots are coming out of the root ball now.
it's not more than about ten inches tall.
I am going to scalp them about a foot off the groud today.
is it still ok to dig them up, divide, and then replant even though green growth has already started?


text:
Earlier today the Australian Bureau of Statistics (ABS) released building approvals data for February 2015. After a record high monthly number of dwelling approvals in January 2015 approval numbers could not quite be matched in February although they remain at near-record highs. Over the month there were 18,768 dwelling approvals, down from 19,397 in January. […]
Dwelling approvals fall to the second highest month on record in February
The number of new residential property listings slows down in the lead up to the Easter long weekend
Each year, in the weeks leading up to the Easter long weekend, the number of new listings coming onto the market often slows down. This year has been no exception, with the number of residential properties being added to the market beginning to fall on a week-by-week basis. Across the combined capital cities, the number […]
Strong clearance rate and record highs for volume in three capital cities
CoreLogic RP Data National Auction Comment, week ending 29 March 2015 A desire by vendors to sell before Easter and the strong market this year has resulted in record volumes for the year in Sydney, Adelaide and Perth. The results show that the high volumes did not overwhelm demand. The auction market is clearly responding […]
The rate of population growth remains strong but continues to slow
The Australian Bureau of Statistics (ABS) released its demographic data for the September 2014 quarter yesterday. The data showed that over the quarter, Australia's population was recorded at 23.581 million persons having increased by 1.5% or 354,605 persons over the past year. The increase in population over the past year was actually the lowest increase […]
Records for auctions in 2015 in three capital cities
CoreLogic RP Data National Auction Preview, week ending 29 March 2015 This is a big week nationally for auctions with record volumes for 2015 expected in Sydney, Adelaide and Perth. The rate cut from nearly two months ago will now be having an impact on listings as vendors will have had sufficient time to both […]
Melbourne Auction Market preview for week ending 29 March
There are 1,459 auctions scheduled this week in Melbourne compared to 1,414 for the same time last year. The highest volume of auctions in a single suburb will be found in Reservoir where 29 are expected. There are 26 scheduled in St Kilda and 24 in Brighton. The compressed autumn auction market, the three weeks […]
One billion dollars a week on Melbourne property in 2014
Key points Over one billion dollars a week was spent of residential real estate last year Brighton recorded the highest spend, $842m Glen Waverley recorded a $233m rise In 2014 a total of $53.7b, over one billion dollars a week, was spent on Melbourne residential real estate. In 2014 a total of $53.7b, over one […]
The RBA's Financial Stability Review and analysis of the housing market
The Reserve Bank (RBA) released its bi-annual Financial Stability Review (FSR) earlier today. The document provides a guide as to the RBA's thoughts on the overall economy and potential risks. As you'd expect, the residential housing market features heavily in their assessment of financial stability and I will delve into some of the key take-outs […]
National clearance rate reaches 77.4% from weekend auctions
CoreLogic RP Data National Auction Comment, week ending 22 March 2015 After 6 weeks with a clearance rate in the mid to high 70's sellers in Melbourne, Sydney, Canberra and Adelaide can be quite confident of attaining a good outcome when selling at auction. A preliminary weighted average clearance rate of 77.4 per cent was […]
Auctions as a sales method have increased in all capital cities
CoreLogic RP Data National Auction Preview, week ending 22 March 2015 There are 3,003 auctions expected this week across Australia with 2,539 expected in capital cities. This is compared to 2,556 last week and 2,466 for the same week last year. With full data now available for 2014 it is clear that the proportion of […]
CoreLogic RP Data is Australia's #1 Property Information Provider. Our blog is maintained by CoreLogic RP Data's research director, Tim Lawless and Cameron Kusher who is CoreLogic RP Data's senior research analyst. We hope you find the information we post here useful and we welcome your comments and feedback.
Regards, The Team @ CoreLogic RP Data
- Negative gearing and its impact on the housing market December 13, 2012
- Dispelling the myths about our new Index methodology March 2, 2012
- There were 1,213,595 individuals with a negatively geared property over the 2010/11 financial year May 9, 2013
- Dwelling approvals fall to the second highest month on record in February April 1, 2015
- The number of new residential property listings slows down in the lead up to the Easter long weekend March 31, 2015
- Strong clearance rate and record highs for volume in three capital cities March 30, 2015
Tim's Tweets
- There may light at the end of the tunnel for the Aus Bureau of Stats with $250m injection of cash & merger with AIHW http://t.co/JrYMhMkzrr 1 month ago
- More pain at the ABS, first the labour force data now they want to cancel the 2015 Census & migration data delayed due to counting errors 1 month ago
- Unemployment rate up to 6.4% in Jan (6.1% in Dec), likely to counter balance some of the stimulus from lower rates http://t.co/zrWI519K1O 2 months ago
Cameron's Tweets
- @corelogicau clearance rate for Mel highest since june 2013, Syd clearance rate slightly lower than the 84.8% the previous week #ausbiz 13 hours ago
- Final @corelogicau auction clearance rates for last week, highest national clearance rate since Sep-09 #ausbiz http://t.co/BewOghlD7Q 13 hours ago
- RT @Wu_Tang_Finance: The world's worst person? http://t.co/kfx7SwVFsd 14 hours ago retweeted via Wu_Tang_Finance
CoreLogic RP Data on Twitter
- The latest indices shows capital city dwelling values moved 3.0% higher over the first quarter of 2015. http://t.co/7ZlYGbZFCO #ausproperty 12 hours ago
- Sydney dwelling values surged 3% higher in March, remaining capital cities were flat month. http://t.co/7ZlYGbZFCO #indices #SydRE 13 hours ago
- Home values across the combined capital cities increased by 1.4% in March 2015. http://t.co/7ZlYGbZFCO #homevalues #indices #ausproperty 1 day ago


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Hotel Bollero
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- I arrived here without incident on Friday. Charlie and sons were on a road rally in the Chevelle. Nancy took me with her to girls night in and we watched a couple of movies. Both tear jerkers but good ones, Nebraska and Still Mine. Saturday we picked up Trevor and Cristina followed us ...
... opportunities we, the delegates, will have are incredible. I will be meeting with leaders of schools, teachers and students and sharing my culture and experiences while learning about theirs. Japan is a country rich in culture and history...I'm so excited to experience it through JCCC. I will miss my children, boyfriend and family, but can't wait to embark on this journey and share my experiences with ...
A long weekend? Off to Chicago!
... Jill, but I know you'll agree with me on this one, ha ha!) We did however plan to go and cheer on everyone else who thought it a good idea to get up at dawn and prepare to run 42 km through city streets, I mean, what an awesome opportunity! Meanwhile, we had a show to go to, and Once was a wonderful night out. The theatre was truly magnificent, the foyer alone began to make up for the fact that I hadn't made it the art gallery. The photos don't begin to do it justice, and ...
24 Hours in Chicagoland
... Shore Drive, floored by the azure vastness of Lake Michigan. With temperatures promising to break records and the sky a vibrant blue, the shore felt almost Caribbean. By the time made it to Wrigley Field, the street heat was becoming unbearable. After a couple quick shots of Wrigley Stadium, we headed for the South Side of the city for a jaunt through the campus of the University of Chicago and over to Chicago's very ...
A day in the windy city
... symphony practice, pictures at the "Bean" and cooling off at the fountain.
River and Lake cruise of the city
Dawson knocking the arm off the dummy at the Nike Superstore while Maddie and Mom were shopping at the American Girl store on the "Magnificent Mile".
Al's Italian Beef-as featured on the Food Network
Riding the "L"
Freezing in the wind at the Tigers/White Sox ...


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Need help arranging furniture in the study!
sarj81January 4, 2013
I feel like we've tried everything and we always end up in the same place. We recently moved in and are also looking for ideas for additional pieces, bookcase? Recliner? Any help would be greatly appreciated!!
Nice space. My first reaction would be to move the desk out of the bay window and build a window seat there with storage beneath. Replace window treatments. Place the desk so that the view could be enjoyed while taking a break from working.
I also like the window seat idea and strongly agree with the windows! What do you suggest for window treatments?
This room is screaming for a u-shaped or l-shaped unit. A hutch along the back that can house a desktop computer if you need it to hide wires etc. then a desk in front facing out which floats in the space. If you don't need a desktop and only use a laptop you can put a table along the back wall to hold the printer etc. leave the file cabinet where it is, install the window seat and float the desk in front of the back table at a slight angle.
Dustyn Broyles
curtains or romans........I would say both. Put the Romans on the windows and then hang a rod on the outside of the window. If you are confused look up "curtains in front of bay window" on houzz. Then place the desk in the room where if seated there u can see the window to one side and the door on the other. A chair or two for guests And statement art would be great behind the desk. Great furniture wouldn't change it at all. Oh and love the wall color, so cheery. Good luck!
How about a library/office feel? How about floating the desk with the chair behind on the big blank wall? Then, a comfy chair/ottoman with a floor lamp reading nook at the bay window? You could put a credenza with book cases flanking behind the chair, then a nice piece of art in the center of the bookcases with a light above the art. This arrangement, with your furniture...The second photo is the bay window reading nook thought..not this furniture..just for arrangement.


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The Funeral of Mr David Thomas will take place on Thursday 26th March at 10 a.m. at Landican and 11.30 a.m. at Serpentine Road Family Church
OAKDALE PLAYGROUP@SERPENTINE A brand new playgroup has opened at Serpentine Road Family Church for 2, 3 and 4 year olds Ring 630 0105 for further details
All are welcome to join the Worship Services held at Serpentine Road Family Church. We have a varied pattern of Services – please see below for details of services. There are children's groups at the 10.45 service and families with tiny children are also very welcome. There is level access to all parts of the Church building. There is a loop system for the hard of hearing. Large print hymns books are available
March 15th
9.30 Chapel Communion
10.45 Family Worship led by the Rev Mike Smith
March 22nd
10.45 Family Worship and Communion led by Andrew Funnell
3 p.m. Messy Church
March 29th
10.45 Family Worship led by Phil Cookson
4 p.m. Chapel Communion
HOLY WEEK we join with our friends at Seacombe URC
Monday 30th March – Wednesday 1st April 6.30 p.m. for Reflection and Meditation Maundy Thursday for an Agape Meal Good Friday Service at 11 a.m.


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What's the biggest mess you've been in due to alcohol or narcotics?.
I've been sick all over my bed and slept in it after a full day on the beer followed by a joint... physically couldn't move.
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On my 20th birthday, I partied with some friends from work at a bar. I got tore up baddd, I don't remember exactly what happened but they took me to eat tacos later that night and I remember punching a rock wall and cars in the parking lot then apparently, I gave a girl from work a left hook to the body, bruising her ribs.
Later that week, I apologized to everyone but felt real bad. I almost decided to stop drinking completely.
Turns out, the ***** from work, drunk herself, fell and hurt herself but lied to everyone and blamed it on me.
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Once got so drunk and puked and **** my pants the same time.. Also fell in some waterwells, slept in bushes and got into a few brawls.
I like to think I'm older and wiser now
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Older and wiser?, **** that i won't be calming down for at least another 3 years.
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What kind of mess have i not been in cuz of that shi t? You name it, jail, ruined relationships, wrecked cars, court fees, thousands partying, lost jobs...etc
if i made 100k doing bad things, i probably spent 200k doing bad things...
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Important! Freebase will become read-only on March 31, 2015. More.
Glutathione peroxidase en
Glutathione peroxidase is the general name of an enzyme family with peroxidase activity whose main biological role is to protect the organism from oxidative damage. The biochemical function of glutathione peroxidase is to reduce lipid hydroperoxides to their corresponding alcohols and to reduce free hydrogen peroxide to water. [ - ]


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American Solutions for Business holds winter conference
American Solutions for Business (ASB) held its national sales conference in Orlando, Florida, Saturday through Tuesday, January 4-7. A total of 305 sales associates registered for the conference and more than 120 vendors participated in the ASB Vendor Expo.
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Roasted aubergine, tomato & basil pasta
Cooking timePrep: 5 mins Cook: 15 mins
Skill levelEasy
ServingsServes 2
Fast and filling, this pasta dish will bring a hint of the Mediterranean to your mealtime
Nutrition and extra info
Additional info
- Vegetarian
- kcalories
- 610
- protein
- 18g
- carbs
- 108g
- fat
- 15g
- saturates
- 2g
- fibre
- 9g
- sugar
- 15g
- salt
- 0.1g
- 1 large aubergine, cut into chunks
- 2 tbsp olive oil
- 2 fat garlic cloves, unpeeled
- 300g pack cherry tomatoes
- 1 tbsp balsamic vinegar
- 1 tsp caster sugar
- handful basil leaves, plus extra to serve
- 250g pasta such as penne or fusilli
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Making it meaty
Snip 4 bacon rashers into pieces and spread in a roasting tin. Add the garlic cloves, rubbed in a little oil, then roast as recipe left. Add the tomatoes, vinegar, sugar and 1 tsp dried thyme, then continue as recipe, swapping the basil for a handful chopped flat-leaf parsley.
- Heat oven to 220C/200C fan/gas 7. Toss the aubergine chunks with the oil and whole garlic cloves in a roasting tin with some seasoning. Roast for 10 mins, add the tomatoes, vinegar and sugar, then cook for another 5 mins. Meanwhile, cook the pasta, then drain.
- When the veg is tender remove the garlic cloves, snip off their ends and squeeze the roasted garlic onto a board. Mash with a fork, then stir this garlic paste back into the veg with the basil leaves – squashing most of the tomatoes as you go. Tip in the cooked pasta, stir everything together in the roasting tin, divide between 2 bowls, then scatter with a few more basil leaves to serve.
Recipe from Good Food magazine, August 2009
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Comments, questions and tips
I love aubergines so was looking for something quick and easy so made this. I made it with bacon but found it pretty bland and dry. I also found that mashing cherry tomatoes with a fork was pretty difficult without hot seeds squirting at me. Would possibly make again but add a few tablespoons of cream cheese to give it a sauce
Made this for myself and my 5 year old last night. Substituted spinach for the basil, added a bit of mozzarella and cooked for a bit longer. In the words of a 5 year old "scrumptiolicious".
This started with having an aubergine to use up and fancying something a bit different, will definitely cook again. Good versatile recipe.


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Real news. Real funny.
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Ice-T Celebrates Call of Duty Wins by Dancing with His D***
It's a good thing that the veteran rapper/actor doesn't livestream his video game sessions, huh? »
It's a good thing that the veteran rapper/actor doesn't livestream his video game sessions, huh? » 6/24/14 10:40am 6/24/14 10:40am
After his comments about recording a D&D audiobook, you may be under the impression that Ice-T thinks the venerable role-playing universe is whack. Nah, that'd be dead wrong. In fact, the rap legend says "that s**t sounds dope to me." » 2/18/14 12:30pm 2/18/14 12:30pm
So rap legend-turned TV star Ice-T recently turned up for an audiobook gig, without being told what the book actually was. "They didn't tell me this was a motherfuckin' Dungeons & Dragons book". » 2/05/14 10:00pm 2/05/14 10:00pm
Ice-T probably didn't like that last night's PS4 showcase in Late Night wasn't about Killzone: Shadow Fall and explosions, but rather the ever-so-charming Playroom demo software. » 11/14/13 9:00am 11/14/13 9:00am
Everybody knows that rapper/actor/Coco-lover Ice-T is a vocal video game enthusiast, right? Checking in on the game series that he's shouted out over the last few years—Call of Duty, Medal of Honor, Gears of War—it's probably safe to say that Ice-T's a fan of shooters, especially competitive ones. » 3/15/12 1:30pm 3/15/12 1:30pm
Like Gears of War on Facebook and the Ice-T voiced Aaron Griffin is yours to do with as you please in Gears of War 3 multiplayer. Use him! » 9/16/11 11:30am 9/16/11 11:30am
Ice-T, rapper, actor, original gangster, Gears of War fan and occasional unboxer, directs his taking things out of boxes talents at the limited edition Gears of War 3 Xbox 360 and one "big-ass Lancer." Yeah. Real talk. » 9/08/11 5:20pm 9/08/11 5:20pm
Renaissance man and Gears of War fan Ice-T will lend his acting and musical talents to Epic Games' new shooter, Gears of War 3. The rapper, actor and voice of Gears 3's Griffin has gotten the band (Body Count) back together for a special musical tribute, appropriately titled "The Gears of War." » 8/01/11 6:40pm 8/01/11 6:40pm
Ice T and Body Count's Gears of War 3 music video "Horde 2.0: Five Against All" will premier tonight on G4's X-Play at 6:30 PM ET/PT. » 8/01/11 1:20pm 8/01/11 1:20pm
As we all know by now, Ice-T voices a character in Gears of War 3. This minute-long montage of gameplay, courtesy of Gamespot, features him as "Aaron Griffin," and Ice-T's catch phrases over Griffin's attacks. Now we know why the actor/rapper was so fired up that he wrote this tribute to the game and performed it at… » 7/02/11 1:00pm 7/02/11 1:00pm
This is Ice-T's Body Count. Performing at a Gears of War 3 party in LA earlier tonight. That's a match made in heaven if ever I've seen one. » 6/08/11 2:29am 6/08/11 2:29am
Ice-T is a rapper, an actor and a huge gamer. The man loves Call of Duty, but he also knows that telling ladies your kill/death ratio probably isn't going to impress them. » 2/17/11 6:30am 2/17/11 6:30am
When I was thirteen, Ice-T was the baddest dude on the planet, rapping about pushing dope and killing cops. There were no musicians who seemed as hard as him. The guy was scary. Now? » 11/12/10 2:00am 11/12/10 2:00am
Body Count singer and star of Law & Order SVU, Ice-T, is one of the first to legitimately get his hands on a copy of Call of Duty: Black Ops. What does the rapper think of Black Ops' smell? » 11/08/10 7:30pm 11/08/10 7:30pm
Actor/rapper Ice-T's right there with you. Of course this was pre-patch.... right? As seen on FINALLEVEL's Twitter. » 10/28/10 4:00pm 10/28/10 4:00pm
Rapper and TV cop Ice-T is a man of strong opinions. He is also a man who loves him some video games. So what does he think of Medal of Honor's beta? » 7/30/10 3:30am 7/30/10 3:30am
You may recall last April, Ice-T and Epic Games' Cliff Bleszinski discussed casting opportunities for Gears of War 3, before that game was even announced. Last night, Ice let slip that he has a speaking part, but quickly retracted it. » 6/06/10 3:00pm 6/06/10 3:00pm
When rapper Ice-T plays Call of Duty multi-player, he's rollin', comin' through buildings, you gonna die. Oh really? » 12/29/09 5:00am 12/29/09 5:00am
All in a day's work for the
CSI Law & Order: SVU star. As Jace Hall admires Coco's plastic attributes, Ice gets killed by friendly fire, beckons for a soft drink, and then discusses casting decisions with Cliff Bleszinski. » 8/08/09 9:00pm 8/08/09 9:00pm


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he shouldnt even be considered for the starting centerfielder, but he will start there.
he shouldnt even be considered for the starting centerfielder, but he will start there.
"I hate SF."
-Mat Latos
Yes, on Opening Day Junior will be the CF'er. That's not saying he won't get looks in RF during Spring Training.
If They Start Him In Centerfield They Need To Have There Heads Examined.im Sorry But Ryan Is The Best Hustler They Have And He Should Be In Centerfield,he Can Get To Any Ball Rightcenter Or Leftcenter And That Is A Fact.and He Needs To Play Everyday Griffey Can Go To Right.i Dont Care Weather They Hurt Is Feelings Or Not We Are Trying To Win A Pennant Here.!!!!!!!!!!!!!!!!!!!!!!!!!!!!
What if this wasn't a rhetorical question?
All models are wrong. Some of them are useful.
Until Narron is fired, Griffey will be the Reds CF.
Baseball isn't a magic trick ... it doesn't get spoiled if you figure out how it works. - gonelong
I'm witchcrafting everybody.
Griffey willing to give right field a try
Manager Jerry Narron: 'He wants to do what's best for the Cincinnati Reds.'
By Hal McCoy
Wednesday, January 17, 2007
CINCINNATI The expected news is that Ken Griffey Jr. remains on schedule to be ready for spring training. The unexpected news is that right field may be in his future for the Cincinnati Reds.
Griffey and manager Jerry Narron have talked about the possibility of Griffey switching to right field and Griffey is open-minded about the possibility.
"Griffey is very open to doing what he can do to be on the field more," Narron said. "He realizes that Kirby Puckett moved (to right field) and that Cal Ripken, Jr. moved to third base.
"He wants to do what is best for the Cincinnati Reds," Narron added. "He realizes that to be on the field more he has to change positions."
Before moving, Griffey wants to be certain somebody better can play center field, the position Griffey has played since signing his first major-league contract in 1987.
Narron probably will play Ryan Freel and others in center and have Griffey play some right field the first couple weeks of spring training.
Said Narron, "If we started spring training tomorrow, Griffey would be in center field, but right field in spring training is a possibility.
"He was deeply disappointed that he missed September (dislocated toe on his right foot) in that we came so close and he wasn't able to help," Narron added. "I don't like to talk about what my players and I talk about, but I was very pleased with the way he sounded when we talked about this some late last year."
When the Reds report in mid-February, Griffey will be ready to play, according to team medical director Dr. Tim Kremchek.
X-rays showed that Griffey's broken left hand is healing as anticipated, and the hard cast was removed and replaced by a removable splint that the Reds' outfielder will wear for two weeks.
Griffey broke his hand three weeks ago while playing with his son, Trey, at their Florida home.
"It truly was nothing sinister," said Griffey's Cincinnati-based agent, Brian Goldberg. "It was a family thing, playing in the backyard with his kids and has nothing to do with a dirt bike. He wants to tell all the beat writers at one time what happened."
Small market fan... always hoping, but never expecting.
Yeah. I'm not sure how much power he really has. Lindner and JimBo are out of power or gone. He's got this year and next and then it's up to the Reds whether he comes back. Most fans feel he should move and if he resists, it looks like he's whining which never goes over well. The media is good to him when things are going well but don't usually support him whole-heartedly when things arent going well so he can't expect one of his bo-bos in the media to stick up for him. Freel is about as popular as he is now so it's not like Freel's some hired gun from out of town who came in to take his position away from him. Jr.'s fighting a losing battle if he resists too much.
The Rally Onion wants 150 fans before Opening Day.
I can't begin to express how glad I am that McCoy wrote that.
Despite the complaining here, that's a decent offseason.
He assembled a bullpen.
He got a shortstop.
He got Junior out of center.
He signed a defensive centerfielder (Crosby) to compete with the other two that he already had on the roster.
He didn't panic and trade Dunn.
He saved some money by swapping out the expensive catcher at the end of the bench who was going to whine about pt, for a less expensive option.
He made some decent ruleV and waiver pickups.
He didn't lose anybody off the 40 man roster with a major league future.
He signed a righthanded outfield/first base platoon bat.
He brought in a couple of guys to push for the fifth starter slot.
He's got decent cost control over just about everybody on the team for the next two years.
He avoided arbitration with his 4 starter and his catcher.
He didn't do all those things in the way that I would have done it, but he did a lot. Now if he can get Harang's signature on a 3 year deal, and he actually signs his draft picks, the offseason is a solid B+.
"Even a bad day at the ballpark beats the snot out of most other good days. I'll take my scorecard and pencil and beer and hot dog and rage at the dips and cheer at the highs, but I'm not ever going to stop loving this game and this team and nobody will ever take that away from me." Roy Tucker October 2010
If Jr will move to RF - lets go get a CF. Since the Phillies want to get rid of Leiber and want bull-pen in return. Shane Victorino would be my target.
Deno + Coffey = Leiber + Victorino
That sentence still bothers me somewhat. It tells me that unless Wayne acquires someone from outside the organization, Junior likely stays in CF. Apparently, Jerry doesn't view Freel or Deno as better in-house options in CF than Junior.Said Narron, "If we started spring training tomorrow, Griffey would be in center field, but right field in spring training is a possibility.
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This backsplash is ok..... right?
So, my prego crazy self decided to do a kitchen remodel. Granite (Juparana Delicatus) was installed last week and I lovvvveeeee it. Tile guy was here and installed what I picked for the backsplash. It's growing on me, but I have some doubts... I can't tell if just my hormones and realllly wanting to be done with this process. I didn't have the "i love it!!" reaction as I did with the granite
No grout yet, doing "mobe pearl".
(sorry about the rotation, if you click on this picture you can see it upright)
So I joined this group to ask you, internet strangers, can I leave this?
I think they work too. I think it's not the WOW reaction you got from your granite because it's a purposefully understated backsplash to make the granite the star. Or it could be your hormones. Or it could be that this kitchen reno stuff just makes you second guess every. single. little. thing. and (if you're like me) just beats you down emotionally.
(rough day around here...good...high points...but draining)
It's not grouted yet so now is the time it would be easiest to change your mind. If it was grouted, I wouldn't even suggest looking at other options.Your countertops are lovely & with your dark cabinets a plain white/off white might make your countertops pop more. I think the pattern in the backsplash is competing with your Delicatus.
This is a picture of Kellienoelle's kitchen, Delicatus granite, cherry cabinets & Crossville 4x12 porcelain tiles.
Another picture would be helpful.
While there is some competition, I think it depends what your goal and preferences are. Kellie's beautiful kitchen has a clean crisp look. Holly Kay's ever so lovely one is quieter and more mellow. The tile here seems a similar combination as yours.
Thank you all!! This is such an emotional process Cali quail! Friday when my grout couldn't go in and we couldn't start the floor and my tile people got the wrong bull nose piece for the THiRD time, there were definitely tears.
I do really like noelle's kitchen, and actually saw that picture on here as I was trying to figure out what I wanted. When I picked this tile, there was just the one piece that was the whitest/least movement and I wasn't smart(?) enough to realize what V4 means in tile. I wish they all looked like the one I choose on the board, but you've all made me feel much better :). DH approved tonight too, so for now crisis averted. Can't wait to see what you are all up to.
One more pic
Thanks all! Baby is due sept 20, so I'm starting to feel the urgency. We started tear out June 17. I really didn't know what to expect time wise, but waiting on the counters to be fabricated four weeks meant two weeks of stand still. Annoying, but I do love them. And living in small town America with limited suppliers/contractors has been a challenge. DH is not a handy man and wants nothing to do with this process. Ha ha
Hopefully I'll have some before and after real soon!
This post was edited by KarMar00 on Sun, Aug 10, 14 at 10:41
That's true. Thanks romy. That reminds me of my original backsplash plan... In the adjoining living room there is a fireplace with really cool whiteish stacked stone mantle. Initially I thought about doing stacked stone in the kitchen, but decided that would be too much. Instead I wanted to find a tile that had a stone like look... And didn't want to be glossy


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Students have been asked to quickly pass around the iPad and state why the love the Silicon Valley Program into the camera. The secret clock is running and who ever is holding the "hot potato" when the buzzer sounds, is chosen to be the awkward face of the thumbnail for this online video.
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Over 30 Years of Technology Excellence
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We are a computer networking firm located in the heart of Des Moines and we service customers throughout Des Moines and all the Surrounding Areas, as well as Central Iowa and on throughout the entire state of Iowa.
Founded in 1980, CST prides itself on a strong Iowa work ethic to provide our Iowa customers with professional, competent Network Consultation and Technical Services. Our Network Division provides complete computer network design, implementation, migration and repair services, as well as, hardware and software sales. We are authorized Microsoft, Novell, Cisco, Xerox, Compaq, HP and Dell Solution Providers.
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DexKnows Mobile profile for Combined Systems Technology, Inc. in Des Moines, IA


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Oklahoma State Fire Marshals Office
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Learn how to write your songs in Logic Pro. Get your demo ideas down quickly and polish them into songs worth presenting to your band mates, producer, publisher, or label.
"Since joining lynda.com, my technical skills and creativity have improved tremendously. Kudos for making learning fun." —Jim F.
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OP Senior Member
Thanks Meter: 102
474 posts
Join Date:Joined: Apr 2010Donate to Me
To use:
1. Install One More Clock v120_FINAL_FREE.apk
2. Extract the attached HoneycombLook.zip or HoneycombLook_1.1.zip(newer) to the SD card, into the OMC Folder. That's where every theme should have its folder and no other subfolders.
3. Go back to OMC, under "set widget theme" reload the theme catalog and choose the theme, and you're off.
4: If using with LauncherPro, if needed, you can improve performance by going to Preferences on your LauncherPro, select General Settings and check the "Enable Scrollable Widgets" box. OMC will work beautifully after that.
Version 1.1:
- changed the 3, 9, 1, 0 and 7 to resemble the honeycomb theme
- made the dividers whiter
- the whole theme file is now ~13 kb smaller
Version 1.0:
- initial release.
Screenshot from v1.1:
and from 1.0
Here is the real clock on the honeycombSDK:
Uploaded with ImageShack.us
Live footage: jump to 9:25
Last edited by nemuro; 7th February 2011 at 05:53 PM.


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Networked control system is new hot-point in control engineering. A new delayed model for networked control systems is presented, based on which an LQR controller is designed. A method of delays estimation online is also given. For the difficulty on implementation of LQR in NCSs with time-variant delays, the Mamdani intelligent logic with LQR controller is addressed. The stability of the networked control system is also given. Simulation results prove that the novel controller can make the system stable and robustly preserve the performance in terms of time-variant delays.


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StyleWatch SpecialLove Her Outfit! Star Looks to Steal
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Bath Hacked, just down the road from us in Bath, have organised a hack weekend as part of the impressive Bath Digital Festival.
The hack is themed around the City's past, present and future, and there are a raft of prizes for the best work. Seasoned and novice hackers are welcome but do sign up at [...]
Throughout the year Connecting Bristol and our partner organisations run a range of events where you can learn more about our digital inclusion agenda, Green ICT and connectivity in Bristol.


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Wickliff, who earns his Harvard law degree this month, assesses how his generation is handling the challenges facing young people in the U.S.
In celebration of Mother's Day, we highlight the reflections of past guests about their relationships with their moms.
The man behind a string of blockbuster comedies and author of Life's Operating Manual recounts events that prompted him to downsize his life in a major way.
The former Microsoft executive explains his mission to help transform the world by putting books in the hands of the world's children.
The writer and her Oscar-winning actress-mom describe how an encounter at a summer camp many years ago transformed both their lives forever.
Our special broadcast concludes with an examination of assumptions and possibilities for a better, more united tomorrow.
The national conversation on the challenges and opportunities facing America's 50-million-strong Latino community continues.
Our broadcast of this very special gathering challenges stereotypes and provides a deeper understanding of the increasingly powerful Latino community.
The pioneering creator of "community kitchens" describes how he plans to model the concept at L.A. Kitchen.
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Computed Tomography of the Lung
A Pattern Approach
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Preview (read now) Add to my own site Give this ebook to a friend Add to my wishlist Author's page Publisher's page
moreAs a result of the introduction of multidetector CT, very detailed images of the lungs can be obtained in every patient undergoing chest CT. Interpretation of the findings requires good knowledge and understanding of the CT signs of all the more common pulmonary diseases. In the first part of the book, the main appearance patterns of lung disease are described with the help of many colour drawings and high-quality illustrations. This approach will enable the reader to recognise these patterns and to interpret them in order to reach a diagnosis. In the second part, many typical cases are shown which will assist the reader in applying what was learned in the first part. This concise, easy to use and didactic book will help the radiologist in training to learn and understand the CT features of lung disease and is also recommended to more experienced specialists wishing to update their knowledge in the field. less
Springer; December 2007
202 pages; ISBN 9783540682608
Read online, or download in secure PDF format
Title: Computed Tomography of the Lung
Author: Johny A. Verschakelen; W. de Wever
202 pages; ISBN 9783540682608
Read online, or download in secure PDF format
Title: Computed Tomography of the Lung
Author: Johny A. Verschakelen; W. de Wever
Buy, download and read Computed Tomography of the Lung (eBook) by Johny A. Verschakelen; W. de Wever today!
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