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US 5724249 A Abstract A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.
Claims(18) 1. A self-resetting logic circuit comprising:
means operable for receiving an input data signal; means operable for performing a logical operation on said input data signal to produce an output data signal; means operable for outputting said output data signal; and means, coupled to said performing means, operable for disabling said logic circuit. 2. The circuit as recited in claim 1, wherein said disabling means prevents said logic circuit from dissipating power.
3. The circuit as recited in claim 1, wherein said self-resetting logic circuit includes means for precharging a node in said circuit to a predetermined level in response to receipt of a feedback signal from said outputting means.
4. The circuit as recited in claim 3, wherein said performing means includes at least one N-FET device coupled between said node and a ground potential, and wherein said disabling means includes a FET device coupled in series with said N-FET device between said node and said ground potential.
5. The circuit as recited in claim 3, wherein said disabling means prevents said predetermined level from being discharged to ground.
6. The circuit as recited in claim 4, wherein said precharging means includes a P-FET device coupled between a voltage supply and said node.
7. The circuit as recited in claim 4, wherein said self-resetting logic circuit is implemented in a multiplexor circuit and said disabling means includes a means operable for receiving a SELECT signal from a decoder circuit coupled to said multiplexor circuit, wherein said self-resetting logic circuit is disabled when said SELECT signal causes said FET device to turn off.
8. The circuit as recited in claim 1, wherein said self-resetting logic circuit is implemented in a multiplexor circuit and said disabling means includes a means operable for receiving a SELECT signal from a decoder circuit coupled to said multiplexor circuit.
9. A multiplexor circuit comprising:
a self-resetting logic circuit comprising a first means for receiving a first input data signal, a second means for receiving a second input data signal, a first selection means for selecting said first input data signal for output from said logic circuit, and a second selection means for selecting said second input dam signal for output from said logic circuit; and means for deselecting said first and second selection means so that neither of said first input data signal and said second input data signal is outputted from said logic circuit. 10. The multiplexor circuit as recited in claim 9, wherein said deselecting means further comprises:
means for determining that said first input data signal and said second input data signal are not to be outputted from said logic circuit; and means for signalling said first and second selection means to turn off. 11. The multiplexor circuit as recited in claim 9, wherein said self-resetting logic circuit includes means for precharging a node in said circuit to a predetermined level in response to receipt of a feedback signal from an output of said logic circuit.
12. The circuit as recited in claim 11, wherein each of said first and second selection means includes at least one N-FET device coupled between said node and a ground potential, and wherein said deselecting means includes a FET device coupled in series with said N-FET device between said node and said ground potential.
13. The circuit as recited in claim 12, wherein said deselecting means prevents said predetermined level from being discharged to ground.
14. A data processing system comprising a processor, a storage device, a memory device, an input device, and an output device coupled via bus, said processor including a multiplier circuit comprising:
means for receiving and decoding an instruction to perform a computation on inputted data; a data circuit for performing said computation; a multiplexor circuit for selecting which of said inputted data to send to said data circuit, said multiplexor circuit operating in response to received selection signals; a decoder circuit for sending said selection signals in response to receipt from said receiving and decoding means of data signals corresponding to said instruction; means implemented in said decoder circuit for receiving an additional data signal from said receiving and decoding means instructing said decoder circuit to signal, through said selection signals, said multiplexor circuit to not send any of said inputted data to said data circuit. 15. The system as recited in claim 14, wherein said additional data signal from said receiving and decoding means is in response to a receipt of no instruction by said receiving and decoding means.
16. The system as recited in claim 14, wherein said receiving and decoding means is a state machine.
17. The system as recited in claim 14, wherein said decoder circuit comprises a plurality of logical AND circuits receiving said data signals and said additional data signal.
18. The system as recited in claim 14, wherein said multiplexor circuit further comprises:
a self-resetting logic circuit comprising a first means for receiving a first of said inputted dam, a second means for receiving a second of said inputted data, a first selection means for selecting said first of said inputted data for output from said logic circuit, and a second selection means for selecting said second of said inputted data for output from said logic circuit, wherein said instructing means deactivates said first and second selection means so that said first and second of said inputted data is not sent to said data circuit. Description The present invention relates in general to data processing systems, and in particular, to self-resetting logic circuitry within a data processing system. A logic circuit is a circuit designed to perform a particular logical function based on the concepts of "and", "either-or", "neither-nor", etc. Normally, these circuits operate between two discreet voltage levels, i.e. high and low logic levels, and are described as binary logic circuits. Binary logic circuits are the basic building blocks of data processing systems and almost any electronic computing device. Binary logic circuits are extensively used in computers to carry out instructions and arithmetical processes. Any logical procedure may be effected by using a suitable combination of these basic gates. Because of their low power dissipation, complimentary CMOS (metal-insulator-semiconductor) field-effect transistors (FETs) are often used to construct such logic circuits. Because logic circuits are often cascaded in a plurality of connected stages, clock pulses are applied to the elements of a logic circuit to effect logical operations, i.e., drive the logical circuit. Referring to FIG. 1, there is illustrated a typical logic circuit, which may implement any logical function, having one or more Data In inputs and a Data Out output. A clock signal is inputted to the logic circuit in order to drive the Data In inputs through the logic circuit in order to effect the associated logical function implemented in the logic circuit upon the data inputs in order to arrive at the solution, which is outputted as Data Out. The periodic clock signal also serves to prepare, or precharge, the logic circuit so that it is ready for the next series of Data In inputs subsequent to outputting the previous Data Out. One problem with utilizing a clock signal to synchronize all logical operations within very large scale integrated (VLSI) circuitry is that the overall system clock signal may be subjected to noise and clock skew while being transmitted throughout the VLSI circuitry, resulting in a distorted and inaccurate clock signal incorrectly driving any particular logic circuit, which may ultimately result in inaccurate operation of the VLSI circuitry. Another problem is that traditional clocking for precharged circuits also requires the intersection of a "precharge phase" or "time" into the system. This time may decrease the overall system performance by requiring foot devices (also known as evaluate or interrupt devices) causing an increase in power and delay. Referring to FIG. 2, a solution to the foregoing problem is the use of reset circuit 20 in order to precharge logic circuit 21 to a ready state so that it can accept the Data In and perform the logical operation correctly. In such a design, a clock signal is not needed. Referring next to FIG. 3, there is illustrated a cascade of logic circuits 1, 2, 3, . . . N. The output Data Out is sent to reset circuit 20, which operates to reset each of logic circuits 1-N. Timing circuits 31, 32, 33 and 34 operate to properly time the resetting of the logic circuits 1-N so that the reset occurs at the proper time, e.g., after each logic circuit has performed its operation and outputted its result. Timing circuits 31-34 may comprise conventional buffer circuits. A more detailed diagram of a self-resetting logical circuit is illustrated in FIG. 4, wherein there is illustrated typical logic circuit 40, which is operable to perform a logical AND operation on the input data Din1 and Din2. The circuit, being made in the CMOS technology, has its P-channel FETs indicated by a rectangle with a diagonal line formed therein and a gate electrode arranged adjacent thereto and its N-channel FETs indicated by a rectangle without a diagonal line and a gate electrode arranged adjacent thereto. This convention will be followed through the various FIGURES. N-FETs 41 and 42 receive the inputted data. If either Din1 or Din2 is at a logical low level, then node 45 is at a logical high level resulting in a logical low level outputted as Data Out because of the transmission of the high level at node 45 through inverter circuit 43. If both of the inputs Din 1 and Din2 are at a logical high level, then N-FETs 41 and 42 will be turned on resulting in a logical low level at node 45 resulting in a logical high level being outputted at Data Out. Logical circuit 40 also includes P-FET device 44 coupled between node 45 and voltage supply VDD. Reset circuit 20 is coupled between the output terminal and the gate electrode of device 44. Reset circuit 20 may act to apply a low level signal to the gate electrode of 44 upon receiving the high level output from the output of inverter circuit 43. Thus, upon output of a high level signal from circuit 40, reset circuit 20 will result in a precharging of node 45 to a high level through the switching on of P-FET device 44. Circuit 40 is then ready to receive another set of input values for a subsequent logical operation. One problem with self-resetting dynamic circuit technology is that it implements an aggressive cycle time that leads to a corresponding high power dissipation, which is a difficult packaging and cooling challenge, as well as a high demand on the power supply when compared to previous generation CMOS logic circuitry. For example, within the multiply unit in the fixed point hardware in a microprocessor, the multiply unit spends a considerable amount of its time in a logical idle state. However, when the multiply unit is implemented with CMOS dynamic self-resetting circuitry, it is dissipating AC power as if it was fully utilized. This is understood by looking at a "typical self-resetting circuit" schematic in FIG. 11. With this type of circuit, the nodes 1101 and 1102 are unconditionally charged through reset P-devices 1103 and 1104, respectively, on every machine cycle. Also on every cycle, the evaluate N-type devices 1105 and 1106 driven by the SELECT input are turned on every cycle at which nodes 1101 and 1102 are discharged approximately 95% of the time. Thus, there is a need in the art for a technique to lower power dissipation within self-resetting CMOS logical circuitry whenever such a logic circuit is idle. The present invention solves the foregoing need by mining off a functional logical element within a processor or other logical VLSI integrated circuit when the element is idle so it will not dissipate power. Essentially, the present invention provides a "no select state" to a self-resetting logical circuit when that circuit is not needed. This "no select state" inhibits the self-resetting dynamic logic circuit from being evaluated so that the output node cannot be discharged to ground and no AC power is dissipated. The present invention is accomplished by "turning off" all of the SELECT inputs to a multiplexor circuit, which functions as a switching mechanism for sending data to be operated on by date flow circuits coupled to the multiplexor circuit. When the SELECT inputs are set to low values, the N-type CMOS devices they are coupled to are not turned on resulting in no dissipation of AC power to ground within the selected portions of the multiplexor circuit. The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIG. 1 illustrates a prior art logic circuit implemented with a synchronous clock signal; FIG. 2 illustrates a logic circuit implemented with a reset signal; FIG. 3 illustrates a cascading of logic circuits implemented with a reset signal; FIG. 4 illustrates a more detailed diagram of a logic circuit implemented with a reset signal; FIG. 5 illustrates a data processing system configurable in accordance with the present invention; FIG. 6 illustrates a CPU configurable in accordance with the present invention; FIG. 7 illustrates a portion of a fixed point multiplier circuit configurable in accordance with the present invention; FIG. 8 illustrates the decoder circuit of FIG. 7; FIG. 9 illustrates a portion of the multiplexor circuit illustrated in FIG. 7; FIG. 10 illustrates an exemplary data flow circuit; and FIG. 11 illustrates a prior art self-resetting logic circuit. In the following description, numerous specific details are set forth such as specific word or byte lengths, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art. Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. A representative hardware environment for practicing the present invention is depicted in FIG. 5, which illustrates a typical hardware configuration of workstation 500 in accordance with the subject invention having central processing unit ("CPU") 510, such as a conventional microprocessor, and a number of other units interconnected via system bus 512. Workstation 500 shown in FIG. 5 includes random access memory (RAM) 514, read only memory (ROM) 516, and input/output (I/O) adapter 518 for connecting peripheral devices such as disk units 520 and tape drives 540 to bus 512, user interface adapter 522 for connecting keyboard 524, mouse 526, speaker 528, microphone 532, and/or other user interface devices such as a touch screen device (not shown) to bus 512, communication adapter 534 for connecting workstation 500 to a data processing network, and display adapter 536 for connecting bus 512 to display device 538. Referring next to FIG. 6, there is illustrated CPU 510 comprising memory I/O 61, instruction dispatch circuit 62, a floating point multiplier and fixed point multiplier 63. The present invention may be utilized within any one of the foregoing elements within CPU 510 or within any other circuit in data processing system 500 where self-resetting CMOS logic circuitry is used. However, for illustration purposes, the following discussion of the present invention will be with respect to self-resetting logic circuitry in fixed point multiplier 63. Referring next to FIG. 7, an instruction from a dispatch circuit 62 in FIG. 6 is received by state machine 70 within multiplier 63. This instruction may include data and other coding operable for instructing multiplier 63 to perform a particular operation on selected data. The data may be transferred to multiplexor circuit 72 as indicated by the signals A1, A2, A3, etc. and their inverse signals. The data may be received from memory I/O 61. The instruction may also include one or more bits specifying the desired function to be performed on the inputted data. These bits will be used by state machine 70 to instruct decoder circuit 71 to send particular SELECT signals to multiplexor 72 for choosing which data input signals to send to data flow circuits 73. The signals from state machine 70 to decoder 71 are noted as X and Y signals and their inverse signals. Referring next to FIG. 8, there is illustrated a typical implementation of decoder circuit 71 wherein the aforementioned X and Y signals and their inverse signals are inputted into AND circuits 80-83 so as to produce the SELECT signals Sel1, Sel2, Sel3, Sel4. Thus, the instruction received by state machine 70 will be used by state machine 70 to signal multiplexor 72 through decoder 71 which of the inputted data signals to transfer to data flow circuits 73. Referring next to FIG. 9, there is illustrated a typical implementation of a portion 90 of multiplexor circuit 72, wherein the SELECT signals are coupled to N-type devices in series with N-type devices associated with several of the inputted data signals. For example, if the Sell signal is asserted, then data input signals al and the inverse of A1 will be transferred as signals A and the inverse of A to data flow circuits 73. Circuit 90 is configured as a self-resetting circuit in much the same manner as described above with respect to FIGS. 2-4. Referring next to FIG. 10, there is illustrated circuit 100, which may be one of data flow circuits 73, which in this example implements an AND logical operation on input signals A and B. It can be readily seen by viewing circuit 90 in FIG. 9 that a dissipation of AC power will result during every machine cycle of processor 510, since each such circuit 90 within multiplexor circuit 72 will receive one or more of the SELECT signals regardless of whether or not it is desired that any of the signals inputted into circuit 90 are to be sent on to data flow circuits 73. The idea of the present invention is to implement a "no select state" that inhibits specified self-resetting dynamic logic circuits from being evaluated so that the output node cannot be discharged to ground and no AC power is dissipated. In other words, if none of the SELECT signals sent to circuit 90 are asserted, then there is no way for the voltage signal residing at nodes 91 and 92 to be dissipated to ground since the N-type devices associated with the SELECT signals are turned off. The way this is done is to add signals Z (and maybe the inverse of Z) from state machine 70 to decoder circuit 71. As shown in FIG. 8, only the Z signal is required in this example, and it is inputted as a third input to each of AND circuits 80-83. If this Z signal is not asserted, then none of SELECT signals Sel1, Sel2, Sel3 or Sel4 will be asserted and therefore power dissipation will not occur within circuit 90. State machine 70 provides this Z signal by observing the particular coding provided within the instruction so that state machine 70 does not assert the Z signal, in this example, when state machine 70 determines that there is no need to process any of the data inputted to multiplexor 72 on through to data flow circuit 73. For example, an instruction may be received by the integer unit's instruction decoder, which turns on the proper bit fields to be correctly interpreted by the receiving execution units. Upon receiving the multiply instruction, the instruction decoder in multiplier 63 decodes it to one of four multiply instructions, namely a 64�64 multiply, a 32�32 multiply, a 16�16 multiply, or no multiply. Also, the no multiply instruction is a default state for all other non-multiply instructions to multiplier 63. The first three multiply instructions out of the instruction decoder upon receipt by state machine 70 will generate the correct "X" and "Y" SELECT signals along with a "Z" signal that will be turned on. These three signals will then be received by decoder 71, which feeds SELECT signals to multiplexor 72 to in turn generate the corresponding correct SELECT signals to multiplexor 72 for the required multiply operation. For the no multiply case, the "Z" signal will be turned off by state machine 70, and hence the receiving decoder 71 will inhibit all SELECT signals to data flow mutliplexor 72. In summary, when there is no need to provide any functionality of data flow circuits 73 (e.g., fixed point multiplier 63 is not required) and thus there is no instruction to perform such logical operations, state machine 70 will un-assert the Z signal so that none of the SELECT signals are asserted. The concept of the present invention may be implemented with any size multiplexor circuit and can be further extended to other circuit types beyond fixed point multiplier 63. Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Patent Citations
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State EmployeesNC appeals court sides with state retireesSubmitted by WWAY on Tue, 06/17/2014 - 12:50pm.READ MORE:
A North Carolina appeals court says former state Chief Justice I. Beverly Lake and other retired state employees can continue their legal fight over health insurance coverage.
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More than 3,200 North Carolina state employees have received pay increases from a special fund created by the General Assembly to adjust salaries to retain workers in high-demand fields and for increased job responsibilities.
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subset: commoncrawl


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Blog Posts Tagged with "Decisioning"
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June 17, 2012 Added by:Thomas Fox
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Melville's "Bartleby the Scrivener" and Infosec
May 26, 2012 Added by:Rafal Los
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The Future of Algorithms
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The Information Security OODA Loop Part 4: Decide
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News: Kruger Gallery Chicago Reopens in New Lakeview Location
Lakeview, News etc., Painting No Comments »This Friday, January 16, Kruger Gallery Chicago (KGC) reopens in its new 1,300-square-foot space in Lakeview at 3709 North Southport with a solo exhibition of new work by Chicago-based artist Heather Green. Kruger was previously located in River North where, owner and director Mikelle Kruger explains, it has been dedicated to an avant-garde model that art can be a mediator for political and social change and showcasing emerging artists working with an array of design and media. After an initial six-month run in 2011 as a sort of pop-up gallery in the River North arts district, Kruger took three years off to focus on siting a more permanent home. Read the rest of this entry »


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1940 Packard 120 4 door sedan w/dual side mounts. Street Rod project, Chevy 350 engine, 700 R4 automatic transmission, power steering, power windows,. Have... More
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Genre/Form: | Electronic books |
Additional Physical Format: | Print version: Panchenko, Dmitry. Sherrington-Kirkpatrick Model. Dordrecht : Springer, ©2013 |
Material Type: | Document, Internet resource |
Document Type: | Internet Resource, Computer File |
All Authors / Contributors: |
Dmitry Panchenko |
OCLC Number: | 828794271 |
Description: | 1 online resource (162 pages). |
Contents: | The Free Energy and Gibbs Measure -- The Ruelle Probability Cascades -- The Parisi Formula -- Toward a Generalized Parisi Ansatz. |
Series Title: | Springer monographs in mathematics. |
Responsibility: | Dmitry Panchenko. |
This book explores core ideas underlying the Parisi solution of the Sherrington-Kirkpatrick model for spin glasses, including the recent solution of the Parisi ultrametricity conjecture and a conceptually simple proof of the Parisi formula for free energy.
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From the book reviews: "The monograph under review is concerned with the Sherrington-Kirkpatrick (SK) model of spin glasses. ... The monograph deals with a notoriously difficult subject. Nevertheless, the author takes care to explain the ideas behind the proofs, which makes the text pleasant to read. It will most certainly remain a reference for years." (Jose Trashorras, Mathematical Reviews, April, 2014) Read more...
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NIT, Karnataka Admissions In October 2014 (www.nitk.ac.in)
Posted On Tuesday, October 28, 2014 By admin. Under Notifications
Karnataka National Institute of Technology (Technology) 2014 - 15 Ph.D. Applications are invited for admissions.
Details ...
* Ph.D.
Specializations: Civil Engineering and Applied Mechanics & Hydraulics, Mechanical Engineering, Electrical Engineering, Electronics & Communication Engineering, Chemical Engineering, Metallurgical & Materials Engineering, Mining Engineering, Physics, Chemistry, Humanities-Social Sciences & Management, Mathematics ...
Karnataka Institute of Leather Technology Admissions In June 2014 (www.kiltbangalore.ac.in)
Posted On Wednesday, July 2, 2014 By admin. Under Diploma cources
Bangalore, Karnataka Institute of Leather Technology (KLIT), Diploma, PG Diploma, Certificate Courses Admission.
Details ..........
1) Diploma in Leather and Fashion Technology
Duration: three years.
Number of seats: 45
Qualifications: Candidates must be eligible for the class or equivalent.
2) Post Graduate Diploma
Sections: Leather processing, footwear, leather goods and garment technology.
Duration: ...
Karnataka Veterinary, Animal and Fisheries Sciences University Admissions In July In July 2014(www.kvafsu.kar.nic.in)
Posted On Friday, July 18, 2014 By admin. Under Notifications
Bidar, Karnataka Veterinary, Animal and Fisheries Sciences University (KVAFSU) Applications are invited for admission to the MBA course.
Details ......
Master of Business Administration (MBA)
Specialization: Food Business
Number of seats: 40
Duration: two years.
Qualifications: dairy technology / Veterinary Science / Veterinary Science and Animal husbandry / Fisheries Science ...
Karnataka MBA NIT Admissions In November 2014 (www.nitk.ac.in)
Posted On Tuesday, November 25, 2014 By admin. Under Notifications
Suratkal National Institute of Technology Karnataka (Knit-K) has issued to the MBA program in 2015.
Details .......
2015 MBA program
Number of seats: 64
Duration: 2 years.
Candidates should be 50 per cent marks in any degree. CAT / GMAT qualify.
Option: CAT / GMAT score is based on a select group discussion and personal interview ...
Posted On Friday, May 30, 2014 By admin. Under Notifications
JSS Mysore University ( JSSU) JSS Medical College Is Inviting For MBBS Course With Application.
Details ..........
MBBS Program - 2014
Duration: 5 Years
Qualifications: Biology, Chemistry, Physics subjects to be passed by 50 per cent marks in Inter. Medical Board of Karnataka Under Graduate Entrance Test - 2014 must be applied.
Choices: Karnataka ...
Kanpur University Online scholar ship
Posted On Friday, July 11, 2014 By admin. Under
Scholarship Admission Test to study MD Physician at ZSMU, Ukraine, Europe : JNTUH
Posted On Sunday, July 21, 2013 By admin. Under University Tags: Admission Test, Amp, Application Forms, Applications, Dd, Divya, Favour, Important Dates, India, Jawaharlal Nehru, Jawaharlal Nehru Technological University, Last Date, Scholarship, Scholarships, Selection Process, State Medical University, Submission, Ukraine Europe, Zaporozhye State Medical University
Applications are invited for Scholarship Admission Test for those candidates who took admission 2012/2013 & 2013/2014 academic years in MD Physician (Equivalent to MBBS in India) at Zaporozhye State Medical University of Ukraine, Europe with Jawaharlal Nehru Technological University Hyderabad:
Selection Process: Selections will be based on the Scholarship Admission Test.
How ...
Admissions In KVAFSU In July 2014 (www.kvafsu.kar.nic.in)
Posted On Wednesday, July 16, 2014 By admin. Under Notifications
Bidar, Karnataka Veterinary, Animal and Fisheries Sciences University (KVAFSU) Applications are invited for admission to the MBA course.
Details ......
Master of Business Administration (MBA)
Specialization: Food Business
Number of seats: 40
Duration: two years.
Qualifications: Dairy Technology / Veterinary Science / Veterinary Science and Animal husbandry / Fisheries Science ...
Vellore Institute of Technology Engineering Entrance Examination (VITEEE-2013) :Admissions
Posted On Tuesday, April 16, 2013 By admin. Under Examinations Tags: Admission, Ascending Order, Bihar, Btech, Chennai, Counseling, Dubai, Entrance Examination, Fee Waiver, Institute Of Technology, Kuwait, Nbsp, Provisions, Rajasthan, Registrations, Scholarship, Tamil Nadu, Technology Engineering, Toppers, Vellore Institute Of Technology
Vellore Institute of Technology Engineering Entrance Examination (VITEEE-2013) 1,66,978 candidates have registered for VIT Engineering Entrance Examination (VITEEE) to be held from April 15 to 24, 2013 for admission into the BTech programme offered by Vellore Institute of Technology (VIT) University, Vellore, Tamilnadu.
For the first time the Computer Based Test (CBT) ...
IIIT Bangalore: Admission into Ph.D. Program
Posted On Thursday, January 24, 2013 By admin. Under Notifications Tags: Academic Work, Application Fees, Application Forms, Btech, C Electronics, Challan, Class Degree, Electronics City, Eligible Candidates, Hosur Road, Last Date, Letters Of Recommendation, M Tech, Masters Degrees, Personal Interview, Preferred Selection, Program Applications, Research Letters, Sbi Bank, Technical Discipline
Applications are invited from the eligible candidates for admission into Ph.D. Program for the Academic Year 2013 at International Institute of Information Technology Bangalore (IIITB).
• First class degree in a technical discipline (B.E., BTech, or equivalent)
• Candidates with first class Masters degrees in the mathematical sciences (e.g. an M.Sc. in ...


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Ft. BraggArmy helicopters make stop in Port City before flight home to Ft. BraggSubmitted by Marissa Jasek on Mon, 10/01/2012 - 10:28pm.READ MORE:
If you hear military helicopters flying over town this week, don't be alarmed. They're on their way home. An Army Combat Aviation Brigade arrived at the Port of Wilmington and will be flying back to Fort Bragg throughout the week.
Full story... » Police: Unlicensed teen hits Ft. Bragg soldierSubmitted by Katelyn Supa on Thu, 06/30/2011 - 6:28am.READ MORE:
Police say a wreck involving an
unlicensed teen driver who turned in front of a motorcycle has left
a Fort Bragg soldier in serious condition.
Full story... » NC-based troops heading to HaitiSubmitted by WWAY on Thu, 01/14/2010 - 4:09pm.READ MORE:
The support is part of President Obama's promise to provide an all-out rescue, including military and civilian emergency teams from across the US.
Full story... » |
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What does DBS mean in Telecom?
This page is about the meanings of the acronym/abbreviation/shorthand DBS in the Computing field in general and in the Telecom terminology in particular.
Find a translation for DBS in other languages:
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What does DBS mean?
- direct broadcast satellite(Noun)
- a television satellite that broadcasts directly to the final recepient/viewer, to a home satellite dish.
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"DBS." Abbreviations.com. STANDS4 LLC, 2015. Web. 28 Feb. 2015. <http://www.abbreviations.com/term/39524>.
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Watch "Nachalo (1970)" Movie Online
A film-in-film story set in a provincial town in Russia. Pasha (Churikova) is an amateur actress who plays a witch at a local club...
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KoKoBlushMakeup Artist Female London, England, United Kingdom My MM URL: http://www.modelmayhem.com/kokoblush
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About MeKoKo|BlushHaving had a keen passion for makeup for many years, I decided this was the route I would take in which to pursue a career. I believe that makeup not only enhances beauty, it brings out oneâs confidence â when we look good, we feel even better! Makeup is an art which allows us to showcase our features. After working for a prestigious American cosmetics company and receiving great response from clientele, I chose to further enhance my skills by training from the London College of Fashion and have since taken to Freelancing and specialising in both fashion and beauty make-up. I want to create visions that dreams were made for and encourage the world to share the same passion for makeup as I do. Select TFP work will be considered if the concept will benefit my portfolio and allow me to showcase my work. I am looking to work alongside photographers, models and designers that will help to inspire me and aid in creating something truly amazing. Based in London, but willing to travel provided that expenses are compensated for. Paid assignments will receive priority. I am available for Fashion, Runway and Editorial work, as well as Bridal hair and makeup. Please only contact me if you are genuinely interested in collaborating. Thanks! Komal x CreditsSKY TV ChannelMiss SenZasianal 2009 The Model's Portal Photographers: Joanna Briggs (#750463) Andrea Rossi (#872014) Nardip Singh (#660919) Ali Khan Misha Meghna @ Mokouri Models: Hema Kiya Kansara Raheela Mohammed (#1257982) Kelly Stelfox (#691978) Erika Kayleigh Ann (#620046) Sonia Sidhu (#1473404) Amber Tunio (#1247901) Yasmin Akbar (#1474449) Vaishali Pipalia (#1140266) Jia Jia Lia Wu Anna Wojcik Natalie Edwards Terence Dormer Amanda Reed Friends |


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Only the roles you can apply for are shown below.
Animator needed for a fantasy action short film - US
All states, United States
An Animator is needed for a fantasy action short film. Estimated film length is 5 minutes
A short animated film with a fantasy action aspect to it. I want the film be be like Disney's Fantasia where there is no sound effects and no dialog. Only the score makes the sound effects needed with it's creative instruments. The cartoon animation would be completed first and then the score would be added after. I am looking for a Tim Burton style world of animation that will give the film a colorful and intriguing look. Please contact me for more information.
All minors must be accompanied by a parent or guardian.
I need someone who can draw/create and animate a short cartoon film.
Anyone from United States


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I encountered a strange problem this week that I can't explain: I switched my application to use the signed version of some third party assemblies (Xceed Grid and some of their other components) and the application start time went into the toilet. Each time the application loaded a signed assembly, it took 30 seconds to load. Application start went from 5 seconds to over 90 seconds. What the heck is going on here?!
Some other info:
- This is a WinForms app running under .NET 3.5 SP1.
- The computer had no internet connection (on purpose, for security).


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Hi Mommy Bloggers... Introduce yourself!My name is Carla and I'm new on mommy bloggers. Please introduce yourself and tell me what your blog is about. I look forward to hearing fr… Started by Carla |
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Looking to promote your blog?It is that time again! Finally Friday blog hop This week there is also a Google + hop! Started by Loressa |
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Looking to promote your blog?Flock together Tuesday Blog hop is now open! http://momsbestnest.blogspot.com/2012/01/flock-together-blog-hop-124.html Started by Loressa |
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Follow me! I follow back!I am always looking for new followers! Will follow back! http://lifescuriouswisdom.blogspot.com Leave me a comment so I can be sure to foll… Started by Loressa |
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Share What You Do With My ReadersHello ladies. If you would like to showcase your businesses, products, services, krafts or blogs to my thousands of readers to help increa… Started by Cynthia ~ The Girlz Korner |
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Promote, Link up, and Network w/The Blog Entourage!If any of you ladies haven't already, please join The Blog Entourage at http://theblogentourage.blogspot.com I have a linky directory for b… Started by Christina Anne Williams |
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So the temperature got up to 4 degrees here in Delhi yesterday, which was also my day off, so I decided to venture out into the garage for a bike related project!
Turned out as good as I had hoped.
The Polished Avalanche :D
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text: Search results Listings are for East Coast. For local listings, Enter zip code or Sign in Go Display: All Results TV Shows Movies Actors Directors Only show HD Only show new episodes We found the following shows with actor/director: "Bianca Kajlich" in the next 14 days. Rules of Engagement Next episode: The Challenge Wed 3/4 2:30 AM 103 WSBK (Cbl) 30 minutes TV-14 Russell ropes his new assistant Timmy into helping him win a bet. View in TV Listings 1-Click Record 1-Click Season Pass Record with options 10 Things I Hate About You (1999) Wed 3/11 12:45 PM 126 HBO (Cbl) 1 hour, 45 minutes PG13 A pretty, popular student can't date until her rebellious older sister gets a suitor of her own. View in TV Listings 1-Click Record Record with options


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Discussions Replied To (1) | Replies | Latest Activity |
"I'm a newbie and I decided to keep it simple to begin with. I know I'll want to show…"MamaShujaa replied Nov 10, 2008 to How Often Do You Update the look of your blog? |
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Jan 4, 2009 Reply by Kailani |
What will you do this weekend? Get out and enjoy the weather or stay in for a leisurely weekend?
Join the conversation to win our daily prize. And, see Friday's winner!
Mom Bloggers for Social Good is a global coalition of 2000+ mom bloggers who currently span over twenty countries and who care about spreading the good news about the amazing work non-profit organizations and NGOs are doing around the world. Want to make a difference? Please join us!
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Annie? Is that you Annie?
How the hell did you miss that?
Rihanna seen here arriving at the auditions for Disney's "The Little Mermaid VI: King Poseidon's Baby Mama Adventure"
She needs a big purse for her first aid kit.
The very definition of high maintenance.
It must be stressful going through life with a gun pointed at your titty all the time.


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I was just reading some things on the internet about the bionic and really looking into the new post that motorola posted on their site about the new version of the bionic. I believe that we may possibly see the bionic come out with vanilla android such as the og droid. They stated the same award winning features in their new post and also all these updates that they spoken off on their twitter. And i also believe that there is still a surprise that moto is not telling us and all these leaked documents are not showing.Does anyone else believe this and would anyone change their opinion on the pricing if this is true. Sent from my DROID3 using DroidForums
Nope. Not happening. It's going to be a "3D" version of Moto Blur. And when I say "3D" it's not like the EVO 3D or like Avatar in 3D it's just some 3D type effects when navigating the user interface.
from what I've read, it should be pretty similar to the experience on the Droid 3, which means that "blur" things will be there, but they won't be as obnoxious or noticeable as they used to be. Sent from my DROID2 using DroidForums


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Different approaches:
Finding faces in images with controlled background:This is the easy way out. Use images with a plain monocolour background, or use them with a predefined static background - removing the background will always give you the face boundaries. The rest is easy going... Finding faces by color:If you have access to color images, you might use the typical skin color to find face segments. The disadvantage: doesn't work with all kind of skin colors, and is not very robust under varying lighting conditions... Finding faces by motion:If you are able to use real-time video, you can use the fact that a face is almost always moving in reality. Just calculate the moving area, and here you go. Disadvantages: What if there are other objects moving in the background? Using a mixture of the above:Combining several good approaches normally yields an even better result. Here are some works on that: Finding faces in unconstrained scenes:Well here we go - this is the main thing, the top of them all, the most complicated thing maybe in whole object recognition: Given a black and white still image, where is the face? Humans can do it, so where's the perfect algorithm that can do it, too? Here is some work on it: There seems to be a revival of edge-based methods, using geometric models. Two top performing methods have been published in the early 2000s: The breakthrough in face detection happened with Viola & Jones. Using a cascade of "weak-classifiers", using simple Haar features, can - after excessive training - yield impressive results. This approach is now the most commonly used algorithm for face detection. A basic implementation is included in OpenCV. A nice visualization of the algorithm can be found here. |
The Face Detection Homepage. By Robert W. Frischholz |


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370km northwest of Kuala Lumpur, Penang is an amalgamation of state and island. The island's interior consists of a densely forested interior while the coast is punctuated by a series of bays and beaches connected by a winding road. Lining Penang's coastline are abundant seafront lodgings ranging from simple budget-friendly A-frame huts to sprawling five-star luxury ventures with guestrooms that face the ocean and offer breathtaking views.
The wildly popular Batu Ferringhi (Foreigner's Rock), a hippy-haven in the 1970s, is now a five-star resort territory and though expansion has taken its inevitable toll, the coastline is still gorgeous and the nightlife scene here is the best on the island. Alternatively, Tanjung Bunggah – located 12km from Georgetown – remains one of the island's main developments and features a string of properties with isolated beaches.
Copthorne Orchid Hotel Penang is a fun, laid back and modern hotel set along Tanjung Bungah, offering a true seaside-vacation feel due to its secluded location.
Penang | Hotels | Tours | Maps | Photos | Forum |
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Vocera Chief Medical Officer Bridget Duffy Keynotes At Top Global Health Conferences
SAN JOSE, Calif., June 10, 2013 /PRNewswire/ -- Vocera Communications, Inc. (NYSE: VCRA), the leading provider of solutions that address critical communications and productivity challenges facing healthcare, hospitality, retail and other mobile work environments, today announced that M. Bridget Duffy, M.D., chief medical officer at Vocera will keynote at two upcoming top global health conferences. At both events, Dr. Duffy will explain why now is the time for organizations to create an experience-based culture that restores the joy to medicine and will outline how to use technology to close gaps in patient communication. Dr. Duffy will draw on her experience as the nation's first chief experience officer to explore the connection between quality, safety and patient experience.
(Logo: http://photos.prnewswire.com/prnh/20120711/MM39184LOGO)
Dr. Duffy will speak at the following conferences in June:
- Canadian College of Health Leaders Conference ( Niagara Falls, Ontario; June 10 - 11, 2013) is Canada's largest gathering of health system decision makers, including trustees, chief executive officers, directors, managers and department heads. Dr. Duffy will deliver her keynote: "Leadership for Person and Family-Centered Health Systems," at 9:00 a.m. EDT on Tuesday, June 11, 2013.
- HIMSS Europe's La Revolution Numerique ( Strasbourg, France; June 18 - 19, 2013) is HIMSS Europe's first mini CIO Summit in France, solely dedicated to French speaking CIOs. Dr. Duffy will deliver her keynote: "Humanizing the Delivery of Medical Technology," at 2:45 p.m. CET on Tuesday, June 18, 2013.
M. Bridget Duffy, M.D., is the chief medical officer of Vocera. Prior to joining Vocera, she served as the founder and CEO of ExperiaHealth and as chief experience officer of the Cleveland Clinic, the first senior position of its kind in the nation, where she led the institution in establishing patient experience as its top strategic priority. She is a frequent speaker on the subject of why the patient experience matters and how it impacts clinical outcomes. Her work has earned her the Quantum Leap Award for taking the risk to spur internal change in her field and has led her to be featured in HealthLeaders magazine as one of "20 People Who Make Healthcare Better." Dr. Duffy attended medical school at the University of Minnesota. She completed her residency in internal medicine at Abbott Northwestern Hospital in Minneapolis, Minn., where she created and served as medical director for one of the first "hospitalist" services in the country. Dr. Duffy also served as medical director of Medtronic, Inc.
About Vocera Communications Vocera is the leading provider of mobile communication solutions that address critical productivity and safety challenges facing healthcare, hospitality, retail and other mobile work environments. One of the fastest growing mobile technology companies, Vocera is widely recognized for developing smarter ways to communicate that improve patient and customer satisfaction. Exclusively endorsed by the American Hospital Association, Vocera® Voice Communication, Secure Messaging, and Patient Experience solutions are installed in more than 1,000 organizations worldwide. Vocera is headquartered in San Jose, Calif., with offices in Tennessee, Canada, and the United Kingdom. For more information, visit www.vocera.com and @VoceraCom on Twitter.Check Out Our Best Services for Investors
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Demographic Change and Gender Inequality: A Comparative Study of Madhya pradesh and Karnataka
Gender equality and empowerment of women is today recognized globally as a key element in the achievement of progress in myriad areas, the charter of the United Nations signed in 1945 was the first international covenant that proclaimed gender equality as a fundamental right. Millennium Development Goals and Main Targets for 2015 (UN, MGDs, 2005) recognize promotion of gender equality and empowerment of women is pivotal to its realization. In this paper an attempts is made to understand the demographic changes and gender inequality in the States of Madhya Pradesh and Karnataka. The analysis is primarily based on secondary data culled out from Census of India reports and other published documents. The gender gap in index of deprivation (IOD) of CLDI was lower in Karnataka than M.P. Karnataka's Sex ratio is also distinctly better than that of M.P. Similarly, men and women in Karnataka have better longevity over that of M.P.
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Length: | 19 pages |
Date of creation: | 2004 |
Date of revision: | |
Handle: | RePEc:sch:wpaper:183 |
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Staff Reporter
Fair price shops to sell other items also
DINDIGUL: Roads leading to several villages in the district would be upgraded to improve connectivity.
To begin with, roads connecting Moolachatram, Sempatti and Chettipatti would be renovated at a cost of Rs.16 crore, said the Minister for Revenue, I. Periasamy.
Distributing colour television sets to beneficiaries at Nelamalaikotti village, near here recently, he said that more rural road works would be taken up this year.
Steps also would be taken to sell other products, besides essential commodities in fair price shops.
Later, the minister distributed television sets to 727 beneficiaries.
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