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The "America's Most Literate Cities," continue to work their way through the local press around the country. Cities like Memphis, Cincinati, Columbus and Rochester, all did well, The Mad City and Minneapolis are happy.
and at least Tucson is better than Phoenix, but El Paso Ranked Last. El Pasoans explain their rank in the reading study with some good reasons. The language, economic and social barriers along the U.S.-Mexico border. Many cities with large populations of immigrants and non-native English speakers ranked in the bottom quarter of America's Most Literate Cities study. Eighteen of the bottom 20 cities were in California, Arizona, Florida and Texas."If you look at the top 20 cities, there's no real pattern," Miller said, but he said that the bottom 20 cities are clearly more minority -- and that education levels, native languages and economic conditions in those cities probably play bigger roles.The Study also ranked Public Libraries, putting Akron at #1, followed by Kansas City, St. Louis, Pittsburgh, and my old home, Columbus.
For the second year in a row, El Paso (TX) ended up near the bottom of a list ranking literarcy in 79 of the largest cities in the US. Twenty-two variables including education, newspaper circulation rates; library resources; magazine and journal publishers; and other public documents. While Mayor Joe Wardy questioned the accuracy of the study, given El Paso's border status, he acknowleged that the city need to work on literarcy.
Carol Brey-Casiano, director of the El Paso Public Library and President of the American Library Association also commented:
"As a community, we have to make the commitment that we're going to continue to support libraries," Brey-Casiano said. "We're probably one of the number one tools you have in your tool kit to address these literacy issues."
More from the El Paso Times.
It's that time of year again, time to Rank America's Most Literate Cities. Minnesota's largest city and the Tex-Mex border town are at opposite ends of the spectrum in the study, which examines the extent to which residents of the nation's 79 largest cities behave in literate ways -- such as buying newspapers and books or borrowing library materials.
Indianapolis falls in the top half, ranking 27th overall; Fort Wayne placed 45th.
The country's largest cities appear well into the bottom half of the rankings: New York is 49, Chicago, 58, and Los Angeles, 68. Coverage all over the place.
Most literate cities 1. Minneapolis 2. Seattle 3. Pittsburgh 4. Madison, Wis. 5. Cincinnati 6. Washington, D.C. 7. Denver 8. Boston 9. Portland, Ore. 10. San Francisco
The real literacy crisis has less to do with the number of people reading than with the narrowing range of books that Americans actually read. According to the report, all of ``one in six people reads 12 or more books in a year.'' Half the population never looks at any fiction, poetry or plays. This is, obviously, just pathetic. And what the NEA report fails to say is that most of those people have chosen the very same 12 books, starting with ``The Da Vinci Code,'' followed by a) the latest movie tie-in, and b) whatever Oprah Winfrey has recommended lately.
Read this interesting opinion at The Register-Guard.
JB writes "http://yourdictionary.com/library/misspelled.htmlDid you happen to catch the misspelling of MISSPELLED in the title? It is one of the words on the list.LIBRARY makes the cut, too. (Do you cringe as I do when people say LIBERRY?)"Dr. Language has provided a one-stop cure for all your spelling ills. Here are the 100 words most often misspelled ('misspell' is one of them). Each word has a mnemonic pill with it and, if you swallow it, it will help you to remember how to spell the word. Master the orthography of the words on this page and reduce the time you spend searching dictionaries by 50%.""
The Detroit Free Press reports on an experimental program designed to improve reading readiness in disadvantaged inner-city preschoolers. Parents are paid in cash for their involvement, to the tune of $10 per hour.
Omaha, Nebraska is starting a One City, One Book program called, Omaha Reads. The library nominating committee narrowed public nominations down to six finalists. The people of Omaha are being asked to vote for the final selection via a ballot that was in the newspaper or on the website. Has anyone heard of another city that actually had people vote for the final book in one of these programs?
Entertainer Dolly Parton has succeeded where many legislators and politicos have not. Tennessee has finally granted sufficient funding for a state-wide program entitled the "Imagination Library", which will guarantee that every child in the state will receive one book a month from birth to age five, which has proven to be the most critical time for children to develop an interest in books.
Here's the story from the Tennessean.
According to reading educators, students can improve their SOL (Standards of Learning) scores by increasing their non-fiction reading. Story here from the The Virginian Pilot
Douglas Reeves, founder of the Center for Performance Assessment, a national education organization, believes nonfiction reading and writing drives improvement on tests, and laments an "overexposure" to fiction, that presumably leaves students "ill-equipped to absorb facts."
In her capacity as an international reading advocate, beloved Australian children's author Mem Fox shares a few thoughts on how children develop a love of reading.
As the second most literate country (next to Finland), Australia can boast about the number of children reading for pleasure (68%) and the significant number of boys that enjoy reading. Fox discounts the new government regulations that will allow extra reading credits for children that don't pass required tests in primary school as a cart-before-the-horse remedy; instead, she insists that reading aloud from birth to age three is what is most critical in developing a love of books.
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Estate agents and letting agents in Rhyl
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- RT @Owenmeowenyou: Happy St David's day. walesonline.co.uk/lifestyle/fun-… http://t.co/urQG1hLdix 2 hours ago
- One of Jan Klapicky's fantastic drawings currently on show @AA_EventsList - highly recommended http://t.co/5gnCM4EZKK 1 day ago
- RT @iainmacwhirter: This should have been Scotland's parliament. It will now be sold as a luxury hotel after wasting £440m down the hill. h… 1 day ago
- Last night the BBC broadcast a long Be Creative promo before announcing a series which is just the Great British Bake Off but for painting. 1 day ago
Tag Archives: London
The Journey of an Accidental Unionist
A few weeks ago, I went to see a play about Scottish independence in the Stratford that doesn't sit upon the Avon but the Stratford that sits not far from Westminster. I cycled there from my place in Hackney and … Continue reading
Squarepusher and the Geometry of Sound
In one of Arup's London offices is an array of speakers designed to help architects and acoustic engineers hear how the designs of their spaces will sound when complete. It's called an ambisonic array. Virtual sound models for proposed concert … Continue reading
Posted in Design, Engineering, Technology, Uncategorized
Tagged arup, London, london design festival, sound, squarepusher, tom jenkinson, trafalgar square
2 Comments
The Airport Guy
The all-to brief appointment of Daniel Moylan as chairman of the London Legacy Development Company marks a sea-change in the development landscape in London. His departure, after just 7 weeks, marks the end of an 8 year period during which … Continue reading
Posted in Engineering, Urbanism
Tagged airport, boris johnson, London, mayor, moylan
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Inspiration: Nigel Peake
I have been following the work of illustrator Nigel Peake since I published his student thesis in the Scottish architecture magazine Prospect just before he won a Silver Commendation in the RIBA President's Medal in 2005. Since then he has … Continue reading
Posted in Architecture, Art, Engineering, Uncategorized
Tagged blackfriars, bridges, kennington, London, nigel peake, vauxhall
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A Very British Torch Relay.
As the organisers of the London Olympics propose ever more stupid stunts that the Olympic Torch must perform during the Olympic torch relay – zip-wire over the Tyne, abseiled down a tower in Grimbsy, taken in a steamer across Lake Windemere, … Continue reading
Posted in 2012, Pageantry
Tagged athletics, britain, kevan gosper, London, Olympics, torch, torch relay
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Reaching for My Revolver
Will Gompertz on the Today programme this morning said that the arts has "always been embedded in the idea of hosting the Olympics.' As portions of the £80m Cultural Olympiad were officially announced – a group of artists to create … Continue reading
Posted in 2012, Art, Urbanism
Tagged 1948, 1976, corridart, cultural olympiad, de coubertin, London, london 2012, montreal, nero, ode to sport, Olympics, tony hall
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A Cathedral Dedicated to Excrement
As London's sewer system accepts into its gaping maw a huge autumnal deluge, it is worth sparing a thought for those who created it. The Metropolitan Board of Works was created in 1855 to improve the cities infrastructure 'under the … Continue reading
Posted in 2012, Architecture, Engineering
Tagged Architecture, Bazalgette, design, John Lyall, London, Metropolitan Board of Words, Olympics, sewage, Urbanism
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Apple Day is Saturday at Ravalli County Museum
McIntosh Apple Day at the Ravalli County Museum in Hamilton is the largest gathering of people in the Bitterroot Valley in October, and it's easy to see why.
McIntosh Apple Day at the Ravalli County Museum in Hamilton is the largest gathering of people in the Bitterroot Valley in October, and it's easy to see why.
This year, the Ravalli County Museum's lawn has been a little more crowded on Tuesdays because of work on the American Legion Park in Hamilton. The museum has hosted the Tuesday at 12 free noontime concert series during its summer run and that included the Bitterroot Community Band (see photo) last Tuesday
The music this week in the Tuesday at 12 concert series in Hamilton will be Mudslide Charley.
Again, on July 23, the free concert will be on the Ravalli County Museum lawn. The remodeled American Legion Park (one block away) is welcoming all the kids to the playground and the splash deck, but the lawn seems a little stressed
Continuing a discussion on how we view nature through time, Jim McKusick, Dean of the Davidson Honors College at the University of Montana, will present the "Poetics of Nature" in a free speech Thursday, July 18, at the Ravalli County Museum
The Ravalli County Museum lawn was crowded with about 150 people as Chip Jasmin entertained on July 9th at the free Hamilton concert series, Tuesday at 12.
Jasmin said it was great fun, seeing his friends in the crowd in the summer musical treat
One of the Bitterroot's favorite performers, Chip Jasmin, will be on the lawn Tuesday at 12 at the Ravalli County Museum.
He is the latest presentation from the Tuesday at 12 Concert Series and if you've got kids in school in the valley, they probably will want to go see him
The original tunes of "Britchy" will be the Tuesday at 12 presentation July 2nd.
The Missoula-based singers will be at Hamilton's Ravalli County Museum lawn from 12 noon to 1 p.m. for the free concert series
This week, the Ravalli County Museum again hosts the free noon hour concert in Hamilton - Tuesday at 12.
The music June 25th will come from the Celtic Knots, with an Irish flair for the audience. The concert series is at the museum lawn due to reconstruction of American Legion Park
A rare opportunity is happening at the Ravalli County Museum, starting Saturday evening - "Thomas Cole" Wild Land and the Birth of the American Landscape."
The national touring exhibit has been set up in the past couple of weeks in the old District Courtroom of the Hamilton museum at South 3rd and Bedford and the grand opening will be at 6 p
John Schiever sang his songs and opened the concert series for Tuesday at 12 in Hamilton this summer.
The June 18th performance was the first for the series at a location other than American Legion Park


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US 7334109 B1 Abstract A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.
Claims(10) 1. A method of generating computer instructions for a processor comprising:
accessing stored context of present operating state of said processor to determine if a segment check operation can be eliminated when executing a memory access;
issuing a segment check instruction if said stored context does not indicate said segment check operation can be eliminated when executing said memory access, wherein said segment check instruction initiates said segment check operation;
accessing said stored context to determine whether a base add operation can be eliminated when executing said memory access; and
issuing a base add instruction if said stored context does not indicate said base add operation can be eliminated when executing said memory access, wherein said base add instruction initiates said base add operation to generate a linear address for said memory address.
2. A method as recited in
determining during execution of said memory access that said segment check operation can be eliminated; and
in response to said determining during execution, suppressing execution of said segment check operation.
3. A method as recited in
determining during execution of said memory access that said base add operation can be eliminated; and
in response to said determining during execution, suppressing execution of said base add operation.
4. A method as recited in
5. A method as recited in
determining during execution of said memory access that said base add operation can be eliminated; and
in response to said determining during execution, suppressing execution of said base add operation.
6. A method as recited in
7. A method of generating computer instructions comprising:
issuing a sequence of instructions comprising memory accesses, said issuing the sequence of instructions comprising:
issuing segment check instructions that initiate segment check operations for respective ones of said memory accesses; and
issuing base add instructions that initiate base add operations to generate linear addresses for respective ones of said memory accesses; and
performing an optimizing operation on said sequence of instructions, said performing the optimizing operation comprises accessing stored context of present operating state of a processor.
8. A method as recited in
9. A method as recited in
10. A method as recited in
Description This patent application is a continuation of and claims the benefit of U.S. patent application Ser. No. 09/930,625 entitled �Method and Apparatus for Improving Segmented Memory Addressing�, by Anvin et al., filed on Aug. 15, 2001, now U.S. Pat. No. 6,851,040. 1. Field of the Invention This invention relates to computers and, more particularly, to a methods and apparatus for increasing the speed of access of segmented memory. 2. History of the Prior Art Modern general purpose computers are typically designed to manipulate large amounts of data under control of a large number of application programs. To accomplish this, both the application programs and a large portion of the data are stored in some form of memory which may be viewed as a part of the computer. This memory includes main memory which is typically some form of random access memory that the processor accesses to execute the instructions of each application program; various caches which provide faster access for the processor to instructions and data that typically have been more recently used; and longer term memory such as hard drives, floppy disks, and other devices typically associated with the processor by way of an input/output bus. Any of these different forms of memory may store the instructions and data which are necessary to execute an application program. However, each of these individual parts of memory is a different structure usually physically separated from the other parts which make up the storage system of the computer. At some times, a particular piece of data or an instruction may reside in any one or more of these parts. Where the data or instruction resides is typically controlled by a memory control portion (unit) of the computer. The memory control unit decides where the information should be stored depending on whether the information is currently being manipulated by a program, the size of the various parts of the storage system, and other factors. In order to access data and instructions, a processor uses an address which is unique to the physical position at which the data or instruction is stored in each part. This is referred to as a physical address. Since the storage systems of individual computers vary in type and size and since both data and instructions may be stored at various physical addresses at different times while a program is being executed by a single computer, a programmer does not know when writing a program where any element of data or any instruction will be stored in any computer that is to execute the program. As a consequence, a programmer and the compiler software use what are referred to as logical addresses in designating storage addresses for elements of the various operations that are being programmed. These logical addresses must then be translated into physical addresses by the memory control unit of each computer in order to access the data and instructions in the parts of the storage system of a computer as the program is being executed. Various computers accomplish address translation in different ways. Computers designed to run more advanced operating systems such as Unix utilize what is often referred to as a flat system of addressing for memory. A flat memory system essentially starts at address zero and runs sequentially to an end address. Usually, the memory storage which is addressable is larger than main memory so that the physical addresses of main memory usually only take up some limited portion of the addresses of the storage system. The memory control unit controls the information that is to reside in main memory through a memory control system called paging. Main memory may be logically divided into fixed-sized portions referred to as pages. When a computer running such a system begins operating, it places those system processes necessary to control computer operations in main memory at predetermined addresses. When a particular application program is started, the memory controller determines the addresses of the instructions of that program necessary to operate the program at a starting level and copies page-sized portions of those instructions into portions of main memory not in use by the operating system. As more data and instructions are required to execute the application program, the memory control unit copies the additional information from long term memory to main memory in page-sized portions. The determination of memory address is made through the use of page tables which are stored in main memory as part of the operating system. These page tables respond to a logical look-up address by providing a physical address at which a page in which the data and instructions are actually stored. The page table entries which provide physical addresses also furnish the various properties of the pages such as whether. They are readable and writable, and the level of priority necessary for an access among other things. Sometimes information already in main memory must be removed to provide space for new pages of information being copied from long term memory. In such a case, the memory controller makes sure that any newly-changed information being removed from main memory is updated in long term memory before it is removed. The process of determining a physical address from a logical address is relatively easy for a processor to accomplish rapidly with a flat memory system because the manipulations necessary to the address conversion are so simple. On the other hand, by far the largest number of computers in existence allow the use of a different type of memory control. These computers are based on the X86 family of computers designed and built by (amongst others) Intel Corporation of Santa Clara, Calif. The original X86 processors were quite simple and designed to make use of a very small amount of memory storage. All of that storage was in main memory. The operating system and any application program to be executed were loaded to main memory from floppy disks and then run from main memory. A complicating factor of early X86 machines was the need to keep different parts of the information necessary to a program isolated from other parts during operation so that data and instructions would not be corrupted. This required that some form of priority system be adopted which would allow different portions of main memory to be isolated from one another. The system used, called segmentation, was largely derived from the segmentation scheme used by the computers running the Multics operating system from Honeywell Corporation. The segmentation system continues today with legacy code written for certain operating systems such as Microsoft Windows 3.1 and its successor systems. With segmentation, different portions of main memory can be designated as segments having different properties. Thus segments can be assigned for data, for instructions, and for stacks. Different segments can be made accessible only by the system, by the system and application programs, and so on. The different segments can be made read-only, read/write, and given other properties. By placing different types of information in different segments, interference can be reduced. In order to make this system work, segments are assigned physical addresses beginning at some offset from the start of main memory and continuing for some predetermined length. Then, a memory address for information stored in a segment includes another offset from the beginning of the particular segment to the position at which the addressed information is stored. The use of segmentation in the memory design of early X86 processors designed by Intel and others required that logical addresses be translated into the physical addresses assigned by a memory controller implementing the segmentation system. This required the memory controller to keep track of where each segment began and the length of the segment in order to enable such a translation. The same requirement continues for legacy code written to utilize the segmentation process. The memory controller utilizes a series of descriptors stored in tables, a global descriptor table and one or more local descriptor tables. Each such descriptor table is itself a segment with a beginning (base address), a length, and properties. The descriptors in each table indicate where the related segment begins in memory, its length, and its properties. A descriptor is accessed and stored in one of a limited number of descriptor registers so that the segment information is available for use by a processor for address translation. To utilize this information to access memory, the logical addresses provided in the X86 system includes a reference to the segment in which the information is stored and an offset into the segment. A typical instruction is assumed to refer to a segment; for example, an access of data is assumed to be to the standard data segment stored in the DS descriptor register. A reference to a segment having a descriptor already stored in a descriptor register allows an immediate access to the base using the beginning and length information once a properties check has been done. Additional sets of descriptor registers are provided which can be explicitly selected by the referencing instruction. In most cases, before a descriptor can be used for a memory reference, it needs to be loaded into a segment descriptor register. A segment descriptor to be loaded into a segment register is identified by a segment selector which can be determined from an explicit instruction to index into one of the descriptor tables to access a descriptor. A segment selector includes an indication which of two descriptor tables is to be used for deriving a descriptor; it also includes an index into the designated table and a priority level for the addressed memory. The descriptor found indicates where a segment begins and ends and its characteristics. In earlier versions of the Microsoft Windows desktop operating system, segmentation was used to overcome the limited address space available on early X86 processor implementations. Ultimately, it was found necessary to implement paging in order to make the system viable for applications of larger sizes (which were easily digested by its processor competitors). When paging was added, the segmentation system was maintained so that legacy software could run on the more modern X86 systems. Keeping the segmentation memory system requires that two address translations be done when paging is enabled. First, segmentation cannot be disabled so logical addresses assigned in an application program have to be translated to �linear addresses� using the segmentation system. In prior art systems, this translation is accomplished by processor hardware through a relatively complicated set of steps that are an integral part of each individual memory reference. Then once the segmentation process has completed, the linear addresses are translated to physical addresses. This makes the process of memory addressing a very tedious one in modern X86 systems. Furthermore, the act of loading a segment descriptor from memory into a segment register (which needs to be done prior to using that descriptor) is itself complicated, involving using a segment selector to determine a descriptor table to be utilized, indexing into the table determined to derive a segment descriptor, determining from the selector whether the properties of the access match the properties of the descriptor derived, and finally placing the descriptor into the desired segment register. The X86 architecture has two fundamental segmentation-related operations: ordinary (segmented) memory references that use a segment descriptor already loaded into the processor, and instructions to load a segment descriptor into the processor. In prior art X86 implementations, loading a segment descriptor is carried out by a single complex instruction. Likewise, all memory references always include the steps of checking the limit and permission of the accessed segment, and adding the segment base address to the logical address in order to form a linear address. In practice, not all of these steps are always needed. For example, many modern operating systems use primarily a �flat� address model, where the base address of most segments is zero. Adding a base address is unnecessary in this case, yet the hardware to perform the base add still consumes power, complicates the hardware design, and contributes to the cycle time of what is likely a critical path in the processor. Likewise, a given sequence of X86 instructions may contain several memory references to the same segment. Even barring any a priori knowledge about that segment's properties, it is in principle sufficient to check the segment's access permissions once, rather than redundantly for each memory reference in the sequence. Thus, a problem faced by modern X86 systems utilizing segmentation is that the number of steps required for the segmentation based addressing and loading operation are numerous and slow the operation of the computer significantly. It is therefore desirable to provide improved methods and apparatus for accelerating the segmentation-based addressing process in an X86-based computer. The present invention is realized by a method for implementing a segmentation addressing operation by providing a first logical address and a segment, deriving a linear address from the logical address and the segment in a first discrete sub-step in which the properties of a logical address are checked to determine whether those properties are consistent with the criteria for addressing the segment, and a second discrete sub-step of performing a base add operation to determine the linear address. In an embodiment of the invention, the derivation of a linear address of a segment descriptor is divided into a first discrete sub-step in which the properties of a segment selector are first checked to determine whether those properties are consistent with the criteria for addressing a first descriptor table, and a second discrete sub-step of performing a base add operation to determine a linear address. Dividing the derivation of segmented addresses into a series of individual discrete sub-steps allows those sub-steps to be scheduled and optimized by a compiler, and even completely eliminated in many instances in which prior art arrangements are forced to carry out a complete accessing operation. These and other features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views. As described above, in prior art X86 systems, the segmentation addressing process has been accomplished in response to a single instruction the steps of which are inevitably carried out each time a logical address is presented. The process is very expensive. By breaking up some of the segment-related operations into their respective sub-operations, it is possible to expose these sub-operations to compiler optimization, and eliminate redundant or unnecessary operations. This approach relies on a trusted compiler (or other translation or code generation system) to insert enough checks to maintain the original X86 segmentation semantics, especially the segment protections. It is especially useful with a processor such as the Crusoe� processor designed by Transmeta Corporation of Santa Clara, Calif. which performs the trusted translation dynamically and in software. However, the spirit of the present invention is equally applicable to systems where translation or code generation is performed statically, or in hardware. The various properties of a flat memory system allow improvements to be made in the process of accessing memory. In a flat memory system, the number of steps needed for implementing a memory access even when segmentation is functioning may be significantly reduced. For example, if a segment uses the entire memory available, then the usual segment checks for segment size may be eliminated. Furthermore, if a flat segment is (in general) both readable and writable, the other checks typical to a memory access are also unnecessary. Moreover, with segment base addresses being zero in a flat system, no base add step is required. With prior art hardware implementations of the memory access process, it has been impossible to make use of the ability to eliminate portions of the segmentation process. However, the present invention presents a method and apparatus by which both the processes of (segmented) memory access and segment descriptor loading may be accelerated. As a part of the implementation of the present invention, the single instruction utilized by prior art hardware implementations for accomplishing a (segmented) memory access is separated into three individual parts, a segment check operation (implemented by a SEGCK instruction), a base add operation (implemented by one or more general mathematical instructions), and a traditional RISC-processor style (non-segmented) memory access. In other words, the sub-operations of segment size and permissions checking, and segment base addition, which in prior art X86 systems are an integral part of a memory access instruction, have been split off into individual instructions that can execute in the processor's general arithmetic (rather than memory) unit(s). The segment check instruction (which appears in a number of forms depending on the particular segment and type of access involved) carries out the various checks which are required for that particular segment and type of access. These checks include permission checks which determine that the type of access is allowed, and that the access attempted is allowed by the segment properties; and a limit check which determines that the access is within the segment limits. The base add operation simply performs the arithmetic to add the offset to the segment base. All sub-operations are available for compiler optimizations, including but not limited to common subexpression elimination, loop invariant removal, and strength reduction. Furthermore, in a system that allows recovery from out-of-order or overly conservative exceptions, segment checking can be further optimized by replacing multiple checks for individual accesses to the same segment but at different offsets relative to a given base register with a single check for an access that encompasses all offsets and sizes of the individual accesses. For example, three memory references of four bytes each at offsets 4, 8, and 12 relative to the stack pointer can be checked by a single SEGCHK of 12 bytes at offset 4 relative to the stack pointer. If it is known a priori that the segment being accessed includes all of memory, that the segment is (in general) both readable and writable, and that the priority level of the access is sufficient, then the steps of the segment check can be eliminated. If it is known that the base of the segment is zero, then the individual steps of the base add operation can be eliminated. In order to allow elimination of these steps, provision is made for storing context from which the present operating state of the processor may be determined. A special context register is provided in which is stored, for each of a number of segment registers, information referred to as �base zero� and information referred to as �friendly.� In one embodiment, each of the base zero and friendly information requires a single bit in the register. In a first condition, the base zero information for a given segment register indicates that the segment being held in that segment register has a segment base of zero. In a second condition, the base zero information indicates that the segment does not have a base address of zero. In a first condition, the friendly information for a given segment register indicates that the segment held in that segment register can be both read and written (or else is a code segment and can be read; code segments are usually not writable in the X86 architecture), that the segment is �grow up,� and that it is present and unlimited. In a second condition, the friendly information indicates that the segment does not have these attributes. Therefore, when generating code to be run in a specific processor context (see Since the prior art method of carrying out a memory access in hardware requires that each of the permission checking and base add steps be accomplished whenever any access is attempted, the ability provided by the invention to eliminate these steps drastically reduces the time required for executing code in systems which utilize segmentation processes in addressing memory. It should be noted that the effect of a SEGCHK instruction could be emulated by a sequence of traditional RISC-style compare and branch instructions. However, by providing segment check instructions in hardware, the present invention allows the cost of segment limit and access checking to be drastically reduced in comparison. And unlike the prior art hardware process which requires that all of the steps of segment checking and base addition be carried out without fail, the present commands allow each individual portion of the process to be optimized and even entirely eliminated. Again, other embodiments may choose to aggregate different sub-steps into a single operation, e.g., they could provide an instruction that performs the work of both a SEGCHK and base-add in one step. Another embodiment might combine the base-add and (non-segmented) memory access into one instruction. Finally, it is possible for an embodiment to use the �friendly� and �basezero� information to dynamically suppress segment checks and/or segment base additions in hardware and thus save power or accelerate processor operation. (This is in contrast to the methods discussed above, which statically omit redundant operations, by not generating instructions for them in the first place.) Another complex X86 operation related to segmentation is the loading of a segment descriptor into a segment register. That operation consists of the following steps: given a segment selector, decide which of two tables contains the segment descriptor identified by the selector; compare the selector against the limit of the chosen table segment, raising an exception if necessary; check the access permissions to the selected table segment, raising an exception if necessary; compute the linear address of the descriptor in the chosen table; load the descriptor from memory; and parse the descriptor and store it (and/or information derived from the descriptor) in a specified segment register. As described above, since the process of providing a new segment which may be accessed in itself requires an access of a discrete segment in memory (i.e., a descriptor table), the new commands described above can be used to accelerate the segmentation process. However, an additional improvement allows the process to be even further accelerated. This additional improvement relates to the provision of another new instruction, an address generation instruction called AGENS. The new address generation instruction, like the other new instructions, provides a hardware implementation of a process which otherwise is quite time consuming. As described above, in prior art X86 systems, the process of loading a segment descriptor into a segment register has been accomplished by accessing a memory address in a descriptor table which is stored in its own individual memory segment to derive a descriptor defining a newly-accessible memory segment. Typically, the process is accomplished by a single instruction the steps of which are carried out in hardware. Although the particular instruction may vary, the instruction carries out the individual steps by using a segment selector to determine a descriptor table to be utilized, indexing into the table determined to derive a segment descriptor, determining from the selector whether the properties of the access match the properties of the descriptor derived, loading the raw descriptor from memory, and finally placing the descriptor (and/or derived information in a segmentation register of the descriptor cache). To accomplish this in software, the lookup code has to be conditioned on the table in which the descriptor is found. So the process has to look at the selector for the table indicator, compare that indicator with two possibilities to see which table is involved, and then branch to the one of two sets of code for the particular table, and execute the particular code selected. To facilitate scheduling and software-pipelining of segment descriptor loading operations, we introduce two new instructions, AGENS and WRSEG The address generation instruction computes the address of a descriptor in a descriptor table, given a segment selector. As has been described above, a segment selector in X86 processors is used to derive a descriptor which provides a segment address and properties. A selector includes information regarding the particular descriptor table to be used, an offset into the descriptor table, and a highest priority level to be used for accesses to the segment. However, the selector may not be available in the pipeline soon enough to allow its contents to be used in the manner described above without stalling the pipeline. The AGENS instruction accomplishes the segment check for a descriptor table and does the base add to obtain the descriptor address. However, the segment check for a descriptor segment may be less precise than that for a normal memory access since a descriptor table never contains more than 64K bytes, is always �grow up� in nature, and is always accessed in aligned 8-byte quanta. The AGENS instruction is actually one of a pair of instructions illustrated in For example, if the AGENSG (global) instruction is executed, and the table indicator of the selector is for the global descriptor table, then the selector offset is added to the global descriptor table base found in the global descriptor table register ( The AGENSL (local) instruction functions in a similar manner to return (in the destination register) either a descriptor address in the local descriptor table if the table indicator reads local or the alternate input of the instruction if the indicator reads global. Thus, after executing both the local and global AGENS instructions, with the alternate input of the second AGENS instruction being fed the output of the first AGENS instruction, either an exception has been raised (indicating that the selector specified an illegal value), or the destination register (dest) holds the linear address of the descriptor specified by the segment selector. If it can be statically determined which table will be accessed, one of the AGENS instructions can be eliminated. At this point, a (non-segmented) load instruction can be used to load the raw descriptor from memory, at the linear address computed by the preceding AGENS instructions. The use of the AGENS instructions provides for very rapid generation of descriptor addresses so that the addresses are available well within the time limits set by the system pipeline. A final instruction, WRSEG, moves the thus loaded segment descriptor (and/or information derived from the descriptor) into a specified segment register. Concurrently, the WRSEG instruction also examines the raw descriptor and determines whether the segment's base address (as specified in the segment descriptor) is zero, and whether the segment is �friendly�. That information is then used to update the processor's above-mentioned context register. Again it is to be noted that the current invention relies on a trusted compiler to synthesize the X86 segment descriptor operation from the available sub-operations (which in this embodiment include AGENS and WRSEG instructions), and to insert enough checks to maintain the original X86 semantics. Finally, note that different embodiments of the current invention may choose to aggregate different sets of sub-operations of segment loading into a single instruction. For example, the functions of AGENS and subsequent load from the computed linear address might be combined into one instruction. Yet another embodiment might combine the load from memory with the WRSEG operation. The descriptor values held in the registers of the descriptor cache are furnished as a result of a segment descriptor parsing operation whether software or hardware (shown as block 32). The manner in which the parsing operations are carried out is well known to those skilled in the art. As may be seen, the parsing of the descriptor values is affected by the context in which the processor is operating, and in turn affects the context. Context values are stored in a context register 34 and provide input to the parsing operation. The results of parsing also often affect the context of the processor operation and changes may be effected by input to the context register 34 from the parsing operation. In addition to the descriptor registers already described, an additional pair of registers are included in the descriptor cache 30. These are a register 35 which stores the segment selector, property indicators, and limit value for the global descriptor table: and a register 36 which stores similar values for a local descriptor table. Moreover, two additional registers 37 and 38 are provided which receive the base values for the global descriptor table and the local descriptor table, respectively. Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow. Patent Citations
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oil industry BibliographySee A. Sampson, The Seven Sisters (1975); D. Yergin, The Prize (1991). Sections in this article:
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Retired executive from Silicon Valley. Now I am an amateur photographer.
Mike has completed online and offline ID verification.
Very comfortable home with a lot of space. Only mishaps were very slow Internet and difficulty getting the sauna to work. House also was low on supplies (no dishwashing liquid, few dishwasher tablets, no paper towel).
We have two families that travel each year to ski at NorthStar. This was a great location. The house slept our 3 girls and 4 adults with beds to spare. We enjoyed the size of the place, lots of space for storage and dropping coats and gloves and boots in the large entry way. We used the hot tub and enjoyed ourselves thoroughly. Great location and a good time!
The reservation was canceled 8 days before arrival. This is an automated posting.
Excellent cabin in an excellent location 10 minutes from Northstar ski resort. The cabin was extremely spacious and comfortable with nice extra amenities, and had plenty of kitchenware for cooking and feeding our group. House rules were clearly laid out so there was no ambiguity as to how to check out or what was expected of us. We thoroughly enjoyed our stay and would love to stay here again in the future.
The house is situated in a very nice neighborhood and is big and very comfortable. Everything was as described on the website. Also the kitchen is very well equipped for many people. It is a great place and I would definitely recommend it to everyone!! Skiing in Lake Tahoe is really great. We liked Squaw Valley the best. Northstar is definitely overrated, I would not go back there. Sugarbowl is great for beginners and for advanced skiers, so it is great if you have both in your group. There is a beginners pass for only $35 at Sugarbowl. We arrived before the check in at 4pm and wanted to leave some bags in the garage. I called Mike to ask him if this was possible. He was not too friendly on the phone but it was alright to leave the bags.
I did not mean to be unfriendly but it is a bit upsetting when a guest arrives 6 hours before their scheduled check-in time and only 15 minutes after the previous guests had departed. I expected a call asking for permission to do this before the guest enters the property rather than after they did so.
Since we had stayed here before, we knew that the listing was advertised! We had another great stay in Michael's house. Since our last stay, some updates had been made such as a new washing machine, and new flooring. It was all great! We will definitely be back!
Property was as described, clean, spacious, with all the amenities you would need, would definitely stay again and recommend. Down Stairs has a bonus room with more beds and good for kids, has a nice cast iron heating stove, though the roof seems to have a some patch work from some leaks, (pretty common in a winter cabin). Back yard is not fenced in so if bringing doggies, make sure other neighbors dogs are not out.
Michael is an amazing host. The studio is beautiful, clean and tranquil. We enjoyed our time here very much and hope to come back. Michael is very accommodating and always available to help us when we needed. He even bought us a knife and a BBQ grill so that we could prepare little meals. It was heavenly. Thank you so much, Michael.
The house is very comfortable. It's away from the bustle of Lakeshore, but close to King's Beach. We had a great time.
Thank you for the valuable feedback. I agree with all of your points. The DSL is slow. It's fastest speed ATT offers in this (website hidden) will be replaced---it is ancient. Carpet is being removed this month a new wooden floor will replace it. Not sure about the smell in the bathroom but I will check it out. Hope your stay again the next time you are in Tahoe.
We really enjoyed the home. Perfect location for us, quiet but close to the lake.


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Total Members: 29886 Total Images: 29420 Total Rated: 25177 Total Votes: 752654 Total Downloads: 2548196 Total Comments: 150389
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.................................no comment i doh wah waste meh time
no......buh ah still get ah mahoghany
I studyin de poor quality pic & de gorgeous gyul who hidin behind bad quality photos... Am...but maybe "gorgeous" waz too strong a word?!?!?....
think dis the worng pic....forgive me dey....dat was messed up hair...sorrie
dat bed looking rel ramfle up..she was nice and busy..lol looking descent


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Winnipeg Free Press - PRINT EDITION
Need UN, just not this one
EDMONTON -- The international community has been busy in recent months with a variety of crises at the forefront of state security agendas.
Tensions on the Korean Peninsula are high, the ongoing civil war in Syria is leading to ever-increasing body counts, the instability incurred as a result of failed peace-building experiments in Iraq and Afghanistan is leading many to question the purpose of long-term intervention deployments, the likelihood of nuclear weapons being attained by both the DPRK and Iran is very real, and economic disaster in various corners of the world are all serving to demonstrate the society of states have numerous immediate issues to cope with.
Through it all, one body that has recently come under fire for its actions, or in most cases inactions, is the United Nations.
In its efforts to address humanitarian crises, halt nuclear proliferation, and affect underdevelopment, the UN has been, for the most part, an abject failure.
States follow the guidelines of the UN and international law when it serves their interests, and the various agencies under the UN umbrella consistently fall short in their efforts to improve the quality of life for those living in the worst situations imaginable.
Yet, even in light of these shortcomings, there is no doubt international society needs the UN now just as much as it did in 1944-1945 when it was formed. The problem is we have lost sight of what the UN is supposed to be doing and the limitations of its structure.
The UN was created in an effort to prevent the outbreak of a third world war, and to also prevent the outbreak of nuclear war during the tense years of the Cold War. Never was the UN intended to be a body through which every social issue on the global agenda would be addressed.
Learning from the failed experience of the League of Nations and also recognizing the inherent statism of the international system, the UN was created to provide spaces for states to talk with each other and reduce levels of misperception and distrust that largely contributed to the outbreak of war in both 1914 and 1939.
More idealist notions of what the UN could achieve were, of course, part of the UN's structure, as seen in the desire for an International Court of Justice, the economic and social council and even the General Assembly, but by placing the greatest power in the decision-making of the Security Council, dominated by the five victors of the Second World War, it was immediately evident the UN's purpose was focused on maintaining the balance of power between powerful states and very little more.
Further, keep in mind the UN is premised on two foundational principles that often work against efforts at addressing social issues, those being collective security and the protection of national sovereignty. By making the UN an institution that enshrines the sanctity of states and their independence, it is readily apparent why the UN is constrained on a daily basis from being the body capable of fixing every issue in the world.
The limitations of the UN's structure have not absolved the UN from being burdened with issues it cannot possibly deal with. Look no further than the eight millennium development goals articulated by the General Assembly in 2000. These goals, agreed upon by all UN member states at the time, presented a vision the UN would strive for by 2015. They are:
1. Eradicating extreme poverty and hunger
2. Achieving universal primary education
3. Promoting gender equality and empowering women
4. Reducing child mortality rates
5. Improving maternal health
6. Combating HIV/AIDS, malaria, and other diseases
7. Ensuring environmental sustainability, and
8. Developing a global partnership for development.
Clearly there is little hope of these goals being universally achieved by 2015, though limited progress has been made in some areas.
It is worth considering, however, whether such overtly utopian goals should be the focus of a body now falling short in helping to maintain stability and order in international society. The world still needs the UN but we require it to do what it was intended for, not to be a forum for idealist goals that will never be met.
Robert W. Murray is an adjunct professor of political science in the department of political science at the University of Alberta.
--Troy Media
Republished from the Winnipeg Free Press print edition April 19, 2013 A11
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Suzanne McGregory
TheVIPPaparazziPhotographer Male Boston, Massachusetts, US
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About MeI desire to create classic, contemporary, and culturally iconic images.I have been shooting photography (both digital and film) for 10 years. I have work both on location and in a studio setting. I've photographed the gamut... from celebrity paparazzi and magazine editorial work to model portfolios. My goal is to work with models to expand their portfolios. I am passionate, professional, and strive to mine my creative talent and seek to work with others who desire likewise. I am available to shoot on location, in a studio depending on model preference. I live in Upstate NY, and travel frequently throughout the Watertown, Utica, Syracuse, Boston, MA and New York regions. Please feel free to contact me! Lists
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Files | Size | Format | Description | View | |
ubc_2006-0691.pdf | 3.833Mb | Adobe Portable Document Format |
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Title: | Examining relations among accuracy of social self-perceptions, reactive and proactive aggression, peer intimacy, and peer group integration in early adolescence |
Author: | Vergel de Dios, Maria Celina |
Degree | Master of Arts - MA |
Program | Human Development, Learning and Culture |
Copyright Date: | 2006 |
Abstract: | The purpose of the present study was to examine the relations among accuracy of social self-perceptions, reactive and proactive aggression, peer intimacy and peer group integration for boys and girls in early adolescence. Participants included 335 boys (n = 175) and girls (n = 160) in the fifth through seventh grades. Teachers rated students on reactive and proactive aggression. Self- and peer nominations on a range of social behaviours (prosocial and noncompliant) were collected. Participants provided self-ratings of their peer intimacy and peer group integration. Results revealed that girls had lower reactive aggression, greater peer intimacy, and more accurate social self-perceptions on both prosocial and noncompliant behaviours compared to boys. Findings additionally indicated that inaccurate self-perceptions of one's noncompliant behaviours were related to both reactive and proactive aggression for boys and girls. However, among boys only, more accurate self-perceptions of their prosocial behaviours was linked to problematic peer experiences involving higher proactive aggression and less peer intimacy. |
URI: | http://hdl.handle.net/2429/18315 |
Series/Report no. | UBC Retrospective Theses Digitization Project [http://www.library.ubc.ca/archives/retro_theses/] |
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...would you have favored starting Newton from day one or would you have preferred he sit his rookie season, get adjusted to the pro game and start in year two?
Don't get the question.....
Having a bad OL and no run game in 2012.....doesn't mean Cam somehow wasn't ready. The 2011 record book shows he was.....he just doesn't have coaches and a complete team around him.
What does he need to get adjusted to on the bench?


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Target Shops: Kirna Zabete Lookbook Fall 2012
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We already knew Target was king of designer collaborations — its Target Shops launch had us giddy from the get-go. Now they're sweetening the news of their upcoming Kirna Zabête Target collection with a first glimpse of the Fall lookbook. True to its downtown boutique vibe, Kirna's collaboration comprises statement prints, like leopard-print dresses (and hats!), leather separates, and quintessential ankle boots to finish every look. In total, we're talking nearly 100 pieces from $10 to $200, launching online and at a Target near you on Sept. 9. Click on for the complete lookbook — aka all the reasons we're marking our calendars.
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When I think back on grade school, my mind is flooded with fond memories of new beginnings. A new school year with a new teacher brought about the idea of being surrounded my new classmates, new friends, and most notably, a slew of new school supplies. Sure meet-the-teacher was an exciting experience, but I most […]
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I recently returned from the Middle East, where Food for the Hungry (FH) is serving those fleeing the Syrian civil war. In Beirut, I shared some strong Lebanese coffee with Pastor Jihad – a man who is ministering, and in fact, sacrificing prayer, time and money to care for his former enemies, the Syrians. This […]
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Sláinte to Irish Whiskey, Icons of Whisky Rest of World, Bourbon, Travel Retail Glenmorangie
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Published August 2002.
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Solar Stocks With More Bankruptcy Risk Than Energy Conversion
Chew noted that gross margins of 0% to 15% for Chinese solar module makers could linger through the first three quarters of 2012, meaning many companies will continue operating on a profitless basis even if they guide to higher shipments. While polysilicon, wafer and solar cell prices have rebounded from early 2012 lows, solar panel prices have not rebounded.
"The Chinese solar stocks are up an average 79% 2012 YTD, largely on growing optimism on demand stemming from Germany, the U.S., China, and the U.K. While we expect 1Q shipment guidance to be healthy and in turn possibly buoy the stocks near term, the margin outlook will be of greater importance," Chew wrote.
For U.S. solar companies, in particular, without the support of the Chinese banking system, the risk is more pronounced that assets currently receiving some value from stock investors -- even at share values lower than $1 -- will go lower yet, and ultimately be worth nothing.
Solyndra, the most high profile of all the recent solar bankruptcies, recently
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Avoiding milk curdling in tomato sauce
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I want to try one of Hazzan's Bolonese sauces with Muir Glen plum tomotoes recipe. But she calls for whole milk and tomatoe in the recipe and I'm concerned the whole milk will curdle. Can I avoid curdling by using: cream cheese, cream/Half-n-Half, or making a Mornay sauce instead of whole milk?
I'm not familiar with the Bolognese recipe you're referring to, but most of the recipes I've tried specifies that let the milk and beef cook down before you add the tomatoes. Also, most authentic bolognese sauces require very little tomato (maybe 1 cup of mashed plum tomatoes at the most, which works out to about 2 or 3 plum tomatoes).
With the milk and beef cooked down and the few tomatoes added at the last part of the cooking process, you shouldn't have any issues with curdling.
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re: sylvan
I believe you are worry about milk curdling due to the acidic nature of tomatoes, right? Beside the "cooked down" mentioned by dave, I believe adding tomato slowly (in steps) to warm milk help. Add a bit tomato and stir, add a bit and stir.
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re: sylvan
1 1/2 cans! Wow!
Is this recipe on the web? I'd like to try it out. :-) I'm always looking for new bolognese recipes.
I tried one recipe where I misread the tomato portion... 2 canned tomatoes. I thought it meant 2 cans of tomatoes when all it was asking for was 2 tomatoes.
re: dave_c
Here's the Hazan recipe that, I believe, is pretty standard.
It calls for 1-1/2 CUPS not cans.
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re: dave_c
re: cassoulady
+1 altho I've only done it a few times...but in VERY large quantities, i.e., 4 or 5x. This recipe is a classic for a reason. All OP needs to do is follow it and will likely be quite happy.
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re: cassoulady
The milk finally did "blend" in after initially curdling and it turned out fine. Next time I'll use half-and-half or cream, though.0 -
re: cassoulady
It did turn out great but I won't use milk next time. I'll use half-and-half or cream.0-
re: sylvan
If you follow the recipe as it's printed in her book(s), you'll be fine. I would not substitute cream etc. Check it out in the library if you don't have.
re: cassoulady
+1. I'm not sure why you're worrying ahead of time. Zillions of people follow Hazan's recipe for a reason. It makes the most incredible sauce imaginable.
i don't know, exactly: but the old adage says, "add the red to the white, and you'll never be blue." I think the mornay is a fine idea.


text:
LJWorld.com weblogs 'Hawks in the NBA
The week that was: Markieff Morris nets career-high; Brandon Rush blows up; Josh Selby sent back to D-League
- Markieff Morris (Phoenix Suns) scored a career-high 22 points in 26 minutes on Sunday against the Cleveland Cavaliers. Keef seemingly hit everything en route to a 108-83 win and went 9-for-12 from the field and 2-for-3 from long-range. He scored nine in a row for the Suns during the second quarter, pushing a three-point Phoenix lead to 11. He finished the game with five rebounds and a block (full stats here). A rookie, Markieff is still as inconsistent as they come, though, and he went scoreless in two other games over the last week — a 113-111 win over the Indiana Pacers on Friday and a 107-100 loss to the San Antonio Spurs on Tuesday. He played six and seven minutes respectively in those games. He also sat out on Wednesday with flu-like symptoms, and the Suns lost to the Los Angeles Clippers, 103-86 (game stats here).
After starting off his NBA career scorching hot — 9.2 points per game on 49.3-percent shooting, 58.3-percent threes in his first 10 games — Keef hit the proverbial "rookie wall" and cooled off to less impressive 38.9-percent overall and 38.1-percent three-point averages for the season. Part of that is due to a freezing cold 10-game stretch during February and March, in which he shot just 22.2 percent from the field during a 10-game stretch. In 15 March games, Markieff has averaged just 5.0 points, 37-percent shooting and 30 percent three-point shooting.
The good news is that the Suns are close to breaking into the tight Western Conference playoff race. After Wednesday's games, they were 25-26, sitting in 10th place, yet only 4.5 games back of the fourth place team in the conference (top eight advance to the playoffs).
- After going on a tear in much of February and March, Milwaukee Bucks center Drew Gooden has started to drop a few duds in between his double-doubles and triple-doubles. Gooden was his usual self in a 112-92 blowout win over the NBA's punching bag, the Charlotte Bobcats, on Friday. But his 14 points, 12 rebounds (including six offensive boards) and four assists in 25 minutes (full stats here) were the exception, rather than the rule, for the recent Eastern Conference Player of the Week. A day later, on Saturday against the Indiana Pacers, Gooden made just three of his 11 shot attempts with six rebounds, three assists and three blocks in 21 minutes as the Bucks were on the opposite end of a big beating, losing 125-104 (full stats here). Things got worse on Monday, when Gooden played some questionable defense, made just two of nine shots and airballed two others for six points, five rebounds and one assist in 22 minutes as the New York Knicks won, 89-80 (full stats here). Gooden's offensive game reappeared on Tuesday against the Atlanta Hawks, when he scored 16 points with five rebounds and five assists in 35 minutes in a 108-101 win (full stats here). Unfortunately, it was quantity, not quality, that produced those numbers, as Gooden made just five of 16 shots and got six more points with a perfect outing at the free throw line. Over the last five games, Gooden's shooting has dropped to 30.6 percent, or an average of 3.8 makes on 12.4 attempts. His average for the season sits at 43.2 percent.
- Before a three-point outing on Wednesday against the Chicago Bulls, Atlanta Hawks guard Kirk Hinrich had been thriving in his starting role, scoring in double figures for five straight games. That five-game span, which was the longest of this season in which he's started 16 games, began with a 10-point performance against Cleveland on March 21. Friday, Hinrich drilled four three-pointers en route to 14 points, four rebounds and three assists in 38 minutes as the Hawks beat the New Jersey Nets, 93-84 (full stats here). On Saturday, Hinrich put up 10 points, seven rebounds and two assists in 32 minutes against his former teammates on the Washington Wizards, and the Hawks won, 95-92 (full stats here). Sunday brought a bonkers four-overtime 139-133 Hawks victory over the Utah Jazz in which Hinrich had 12 points, five assists and two rebounds in 44 minutes (full stats here). And then, after a one-day break in the action, he put together a 10-point, four-assist, two-rebound performance in 37 minutes as the Hawks lost to the Milwaukee Bucks, 108-101 on Tuesday (full stats here). With five games in six days — and heavy minutes to boot — it's not surprising that Hinrich's production faltered a bit on Wednesday against the team that drafted him out of KU in 2003, the Chicago Bulls. He played 28 minutes and added three rebounds and two assists, but the Bulls stomped the Hawks, 98-77 (full stats here).
- Miami Heat guard Mario Chalmers seems to have come down with March Madness. And not the good kind. Since returning from the All-Star break at the end of February, Chalmers has averaged just 7.1 points on 34.3-percent shooting and 30.4-percent three-point efficiency. Compare that to pre-All-Star numbers of 11.1 points per game off of 51.2-percent overall and 45.6-percent three-point shooting, and the slump is even more surprising. In fact, Chalmers has scored in double figures in just five of the 14 games this month.
One of those games came on Monday in a 105-90 loss to the Indiana Pacers, when Chalmers heated up for 13 points in 27 minutes. Chalmers coughed up the ball three times in the first quarter before settling down, and he finished with four rebounds, three steals and a single assist (full stats here). In the two games before that, Chalmers put up a pair of three-point duds. He shot 1-for-5 with two rebounds, two assists, a block and three turnovers in 25 minutes during a 103-87 whooping at the hands of the Oklahoma City Thunder on Sunday (full stats here). And on Friday, March 23, Chalmers was 1-for-7 with one rebound, four assists, three steals and a turnover in 31 minutes as the Heat beat the Detroit Pistons, 88-73 (full stats here).
Chalmers' struggles are a bit concerning for the Heat, especially as the postseason approaches. As the Sun Sentinel's Ira Winderman wrote after Monday's game:
Chalmers simply has to be play well, because he's the Heat's only playoff-level point guard.
- Deadly, do-it-all Boston Celtics forward Paul Pierce looks to be finishing the month of March with a bang. Pierce scored 20 points on 7-for-11 shooting (3-for-4 threes) with nine rebounds, five assists and just one turnover in a 99-86 loss to the Philadelphia 76ers on Friday (full stats here). On Sunday, Pierce paced the Celtics to an 88-76 win over the Washington Wizards with 21 points, eight rebounds and three assists (full stats here). Rolling from one porous defense to the next, "The Truth" absolutely demolished the Charlotte Bobcats a day later on Monday as the Celtics won, 102-95. Pierce scored a season-high 36 points on 10-for-20 shooting and a ridiculous 15-of-18 at the free-throw line. He also pulled down 10 rebounds for the double-double and chipped in four assists, three steals and three blocks to round out his dominant performance (full stats here). The shots didn't fall as kindly on Wednesday against the Utah Jazz, but Pierce still made 6 of 16 attempts and 7 of 7 free throws for 20 points, six rebounds, an assist, two steals and a block as the Celtics took down the Jazz, 92-84 (full stats here).
Highlights of Pierce blowing up the Bobcats:
- Nick Collison (Oklahoma City Thunder) played a season-high 30 minutes and scored 11 points in a crazy 149-140 double-overtime victory over the Minnesota Timberwolves on Friday. Collison added three rebounds, three assists, three steals and a block while also having to contend with Timberwolves All-Star Kevin Love, who lit up the Thunder for 51 points (full stats here). In the 22 minutes that Collison and Love shared the court, Love collected three fouls, turned the ball over three times, missed both three-point attempts and made 4 of 9 shots for 12 points. In the 28 minutes while Love played in a Collison-free zone, the Timberwolves big man had a cool 39 points — on 12-of-18 overall shooting and 7-of-9 three-pointers – just one turnover and zero fouls. Collison's one block also came on Love with 1:46 left in the second overtime. It erased a potentially game-tying layup, and Minnesota did not score again until 11 seconds left, with OKC already up by 11. Yay, defense.
Collison made an equally important play at the end of the first overtime, when he set a monster screen for teammate Kevin Durant, who drilled a game-tying three-pointer. And this play, unlike the block on Love, got the patented Nick Collison "badass screens with a Rick Ross track playing over it" treatment:
Collison followed up his highlight-reel game with a pair of quieter performances in victories on Sunday and Tuesday. On Sunday, Collison had two points and two assists in 18 minutes as the Thunder beat the Miami Heat, 103-87 (full stats here). In 19 minutes on Tuesday, Collison scored six points with one rebound in a 109-95 win over the Portland Trail Blazers (full stats here).
- Don't tell Golden State Warriors swingman Brandon Rush that his team should be tanking to get a better draft pick. The fourth-year pro has been on fire lately, setting season-high numbers in multiple categories and doing everything he can to keep his team alive. Rush scored 11 points with four rebounds in 27 minutes on Saturday as the Warriors beat the Sacramento Kings, 111-108 (full stats here). A day later as the Warriors took on the Portland Trail Blazers, Rush scored in double-digits again, putting up 10 points, but this time he also pulled down a season-high 11 rebounds and blocked a season-high four shots. The Warriors lost, 90-87 (full stats here). Undiscouraged, Rush came back on Tuesday and dropped a season-high 23 points on the Los Angeles Lakers. He also grabbed three rebounds, blocked two more shots and had 11 points in the third quarter alone as the Warriors tried to mount a comeback from 16 down, but the Lakers won, 104-101 (full stats here). Rush stayed hot on Wednesday against the New Orleans Hornets, scoring 12 points with three rebounds, a steal and a block, but the Warriors lost again, this time 102-87 (full stats here).
After Tuesday's game against the Lakers, Warriors blogger Adam Lauridsen lauded Rush for his defense on Kobe Bryant and wrote:
With Monta Ellis gone, Brandon Rush is now the most capable penetrator on the team. That may not be saying much, but it's an important role nonetheless. When the Warriors are struggling to connect from behind the arc, they need Rush and others to look for higher percentage looks. That was exactly what Rush did during his monster second half — storming his way to 21 points in just over 21 minutes. The energy and aggressiveness Rush brought to the team was infectious. Much like McGuire, Rush's defensive effort — blocking shots and closing out on perimeter players — helped spart a quick pace at the offensive end. The Warriors climbed back into the game starting from the inside and working out, and by letting their defense generate offense. That's how good teams recover from cold stretches or hot opponents — not looking to win it all back in a few easy-way-out threes, but by chipping away at it through stops, work in the paint and trips to the line. The Warriors — and Rush in particular — deserve credit for fighting the right way against the Lakers despite the early, discouraging deficit.
Cole Aldrich (Oklahoma City Thunder) did not play (coach's decision) on Friday in the Thunder's 149-140 double-OT victory over the Minnesota Timberwolves. He did see one statless minute of time on Sunday in a 103-87 beatdown of the Miami Heat, and then missed his only shot and grabbed three rebounds in three minutes as OKC took down Portland, 109-95 on Tuesday.
Josh Selby (Memphis Grizzlies) did not play (coach's decisions) in a 101-85 loss to the Los Angeles Clippers on Saturday or a 102-96 win over the Los Angeles Lakers on Sunday. Then, on Monday, Selby was assigned to the Grizzlies' D-League affiliate in Reno for the second time this season. Earlier in the year, Selby played four games with the Bighorns and averaged 21.5 points, 5.5 rebounds and 3.3 assists.
Xavier Henry (New Orleans Hornets) went scoreless in 17 minutes against the San Antonio Spurs on Saturday. Henry missed all four of his shots but collected two rebounds and an assist as the Hornets lost, 89-86 (full stats here). On Monday, Henry hit two of his five attempts and four of six free throws for eight points, two rebounds and a steal in 22 minutes against the Los Angeles Clippers. The Hornets lost again, 97-85 (full stats here). New Orleans finally won, though, on Wednesday, as they beat the Golden State Warriors, 102-87. Henry had eight points, a rebound and a steal in 22 minutes of action (full stats here).
Marcus Morris (Houston Rockets) did not play (coach's decisions) in any of the three games since an eight-point stint on March 22 against the Golden State Warriors. Marcus sat out Saturday as the Rockets lost to the Dallas Mavericks, 101-99; Monday, as the Rockets beat the Sacramento Kings, 113-106; and Tuesday, as the Rockets lost again to the Mavs, 90-81.
D-League update
- Julian Wright (NBA D-League - Austin Toros) scored 18 points on 8-for-11 shooting and 2-of-2 free throws on Friday as the Toros beat the Maine Red Claws, 112-82. Wright added five rebounds and two assists in 31 minutes (full stats here). A night later, he duplicated his line in a rematch with the Red Claws, scoring 18 again on 8-for-11 shooting. This time, he hit just two of six free throws, but he double-doubled with 11 rebounds and six assists as the Toros coasted to a 116-77 victory (full stats here).
Wright highlights, below (at :16, 1:32, 2:02)
Brady Morningstar (NBA D-League - Tulsa 66ers) played just 11 minutes and scored five points on Friday as the 66ers lost to the Iowa Energy, 101-95 in overtime. Morningstar took just three shots (all three-pointers) and made one. He also chipped in two assists (full stats here). On Saturday, Morningstar did not play (coach's decision) as Oklahoma City Thunder guard Reggie Jackson joined the D-League affiliate for a one-game tune-up. The 66ers beat the Energy, 100-87 (game stats here). With Jackson back in OKC, Morningstar played his now-normal 11 minutes again on Tuesday against the Bakersfield Jam. He scored five points again and added one assist (full stats here).
In the first game of his second developmental assignment, Josh Selby (NBA D-League - Reno Bighorns) scored 18 points on 18 shots Wednesday, and his team lost, 117-89. Selby hit just 6 of 18 attempts, 3 of 8 three-pointers and was 3-for-3 from the foul line. He also had four rebounds, a steal, a block and two turnovers while not registering a single assist in 29 minutes (full stats here).
Jayhawks in upcoming NBA games
7 p.m., TNT, Mario Chalmers and the Miami Heat vs. the Dallas Mavericks
9 p.m., Xavier Henry and the New Orleans Hornets vs. the Portland Trail Blazers
9:30 p.m., TNT, Nick Collison, Cole Aldrich and the Oklahoma City Thunder vs. the Los Angeles Lakers
6 p.m., Mario Chalmers and the Miami Heat vs. the Toronto Raptors
6:30 p.m., Kirk Hinrich and the Atlanta Hawks vs. the New York Knicks
6:30 p.m., Drew Gooden and the Milwaukee Bucks vs. the Cleveland Cavaliers
7 p.m., Marcus Morris and the Houston Rockets vs. Josh Selby (D-League assignment) and the Memphis Grizzlies
7 p.m., Paul Pierce and the Boston Celtics vs. the Minnesota Timberwolves
9:30 p.m., Brandon Rush and the Golden State Warriors vs. the New Jersey Nets
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- KU Lawrence campus asked to give up $9.4 million, mainly for medical school March 4, 2015
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Weekend Promo: Deponia 95% off, up to 75% off Tropico, Port Royale, Settlers and more at GOG.
Title screen
Loading screen
You can interact with citizens
This is the game menu, your private rooms
Here you receive items from the shop or other players as gifts
Your armory
Your wardrobe
An example of some weird outfit. You can change the colors of your clothing to your liking.
The multiplayer options
Your statistics
Your trusty companion in Albion ... your dog
You can also interact with your dog like calling for him or throwing balls
Citizens who like you may offer you presents, as indicated by a gift icon above their head
A small encampment full of brigands
Hobs in the distance ...
... lets fight them
A small manor owned by you as indicated by the golden icon
Game supports multiplayer where you can travel with another player though Albion
The detailed map of a location also shows quests (as usual indicated by the exclamation mark)
Another area to explore, this time an industrial one
You can buy houses to increase your income
A shop in the market
A store selling clothes.
One of the mini games, this time pressing the correct button as indicated by the colored bar
Every citizen has it's own opinion of the hero
The entrance hall of your castle
Your throne were you decide the fate of Albion later on.
And there is your (well one of many) lovely wife, which you can either divorce or kiss
We decide to kiss
One of your children in another town
You can also shop haircuts to change your appearance
Another mini game .. chicken run
Time to sweat in the desert
Hey, my hat just looks like yours
Ho matey!
Attacking people in the town changes their opinion of you
and some will cower in fear
while others just will hate you
You can either melee with hammers or axes
or shoot the enemies with rifles and pistols


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Not the best massage ever, but Ok. Scalp massage oil was a bit hot. Nice footbath. Wonderfully decorated. Clean facilities and sauna. Lovely robes and slippers provided.
Not the best massage ever, but Ok. Scalp massage oil was a bit hot. Nice footbath. Wonderfully decorated. Clean facilities and sauna. Lovely robes and slippers provided.
A true day spa experience with full locker room (showers/sauna). Decor and ambiance is top-notch. My therapist definitely knew his stuff. I had the muscle melt and it did!
Have been going here for years and it still is my favorite place for wellness and relaxation in Portland.
I have been to the Dragon Tree many times over the years. My massage yesterday was so bad that I will not be going back. I came in (and explained to the therapist) that I was there for some neck and back pain. She literally never touched my back during a full hour massage. Despite my explanation of the pain,... More
I received a gift card for Dragontree and had never heard of it, until then. I booked a massage and 30 minute facial. Roxanne was my massage therapist. She immediately asked for feedback and made me very comfortable to tell her what I liked and wanted in my massage. I felt relaxed with all my kinks worked out by the... More
I was lucky enough to receive a gift certificate to The Dragontree from a colleague at work. Feeling a bit overwhelmed by the long and complicated menu of services, I finally chose the "Custom" spa package which consists of an hour-long body massage, a foot bath in combination with focused neck and shoulder work, and finally, a facial. In between... More
My husband and I had the most memorable experience at The Dragontree spa. Having a regular massage or body treatment has been part of our lifestyle for over 35 years, additionally we like to experience new places when we travel. The Dragontree hits all the marks, wonderful treatment menu, experienced and friendly staff, relaxing environment and all at a great... More
Loved my masseuse, Matt. Loved the atmosphere. Prices were pretty good too!
I received a great facial from Kerry. The service was excellent an very relaxing. We will certainly come back. I'm not really a spa person but I felt very comfortable and relaxed. Go here if you are staying in Portland.
I'm not a spa expert, but I loved the Dragon Tree. Really cozy and adorable. I had a body scrub, my first, and it was fab. Definitely would recommend it.
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