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Giedraitis family
From Wikipedia, the free encyclopedia
Giedraitis (Polish: Giedroyć) is the name of a Lithuanian noble family, most probably dating back to the time of Mindaugas, although it has no connections with him. No reliable information about the earliest members of the family has survived; when the family name started to appear in written sources in the early 15th century, the precise connections between all its members were already impossible to establish. According to the 16th century Lithuanian Chronicle, they are descendants of duke Giedrius, a brother of Narimantas and Grand Duke of Lithuania Traidenis.
Many family members were important figures in Lithuanian and Polish history and culture.
The family's original domain was the Lithuanian town of Giedraičiai.
Notable members[edit]
- Jerzy Giedroyc (1906 - 2000), Polish writer and political activist
- Vera Gedroitz (1870 - 1932), Lithuanian princess, surgeon and amateur poet.
- Coky Giedroyc, English film director (Sherlock)
See also[edit]
External links[edit]
- Genealogy of the Giedraitis family
- (Lithuanian) A bit on family by Lithuanian historian Zenonas Ivinskis
This biographical article about a member of the Lithuanian nobility is a stub. You can help Wikipedia by expanding it. |
This Lithuanian history-related article is a stub. You can help Wikipedia by expanding it. |


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US 5432748 A Abstract A solid state peripheral storage device receives an LSN address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units which are made out of solid state floating gate storage cells. In addition, a microsequencer controls the operation of the translation of the mapping of the LSN to PSN. Through the use of the mapping of LSN to PSN, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, the microsequencer has error recovery routines to further enhance the reliability of the peripheral device.
Claims(10) 1. A solid state peripheral storage device for interfacing with a computer providing a logical sector signal, said device comprising:
means for translating said logical sector signal into a physical sector signal; memory means for storing data signals, said memory means comprising a plurality of floating gate storage cells, and means for addressing said memory means with said physical sector signal for reading the data signals therefrom in two modes: wherein in a first mode each of said addressed floating gate storage cells is sensed longer than in the second mode. 2. The device of claim 1 further wherein said means for translating translates said logical sector signal into a new physical sector signal in the event said floating gate storage cells in said memory means at an address defined by said physical sector signal are defective, and wherein said addressing means addresses said memory means with said new physical sector signal.
3. The apparatus of claim 1 further comprising:
means for correcting error in said data signals written into or read from said memory means. 4. The apparatus of claim 3 wherein said correcting means comprises means for applying a Reed-Solomon code to said data signals.
5. The apparatus of claim 3 wherein said correcting means comprises means for applying a CRC code to said data signals.
6. The apparatus of claim 3 wherein said correcting means comprises means for applying a redundant Hamming code to said data signals.
7. The apparatus of claim 1, wherein said translating means comprises a random access memory means for random access translating said logical sector signal into a physical sector signal.
8. The apparatus of claim 7 wherein said random access memory means further comprises a plurality of floating gate storage cells.
9. The apparatus of claim 1 wherein said translating means contains one mapping entry between each logical sector signal and physical sector signal, wherein each mapping entry has the same size.
10. The apparatus of claim 9, wherein said translating means translates said logical sector signal into said physical sector signal by multiplying said logical sector signal by the number of bytes per mapping entry.
Description This is a divisional of application Ser. No. 07/977,697, filed Nov. 13, 1994, U.S. Pat. No. 5,359,570. This application is submitted with a microfiche appendix having Exhibits A and B and containing copyrighted material, Copyright 1992, Silicon Storage Technology, Inc. The appendix consists of Exhibit A: one (1) microfiche with eighty-five (85) frames and Exhibit B: one (1) microfiche with ten (10) frames. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever in the appendix. The present invention relates to a peripheral storage device employing floating gate solid state cells as the storage medium. More particularly, the present invention relates to such a device and a method of operating the device. Peripheral devices to a computer are well known in the art. One prior art peripheral device employs magnetic medium as the storage medium. This is evidenced by hard disk drives and floppy disk drives. Hard disk drives can be erased and programmed many times. In addition, they can store a large capacity. Another type of peripheral storage device using solid state memory is the Read Only Memory (ROM). ROM's can be programmable once or read only. Solid state memory devices have the advantage that they consume less power and have faster access time. However, unlike magnetic medium, they cannot be erased and programmed repeatedly. More recently, as scale of integration has increased, floating gate solid state memory devices have been suggested as being useable in a peripheral storage device. Floating gate memory devices have the advantage that they can be programmed and erased, electrically, thereby, exhibiting the advantages of ROM memory, i.e., low power consumption and faster access, along with the writeability of magnetic medium. In addition, as integrated circuit fabrication scale increases, greater density can be achieved. However, one problem of using the floating gate solid state memory device is that the chip must be virtually defect free. Since the price of each memory chip is dependent upon its yield (the inverse of defect), more stringent requirement of defect free means low yield and high price per chip. In anticipation of solid state memory storage devices proliferating, a standard, PCMCIA, has been adopted to set the electrical and mechanical interface requirements between a solid state storage peripheral device and a computer system. A solid state storage device which interfaces with a computer and receives a first address signal therefrom has a memory containing a conversion table to translate the first address signal into a second address signal. The device also has a solid state memory which comprises a plurality of floating gate storage cells. The device has means for addressing the plurality of floating gate storage cells by the second address signal to supply data signals thereto from the computer or to retrieve data signals therefrom for the computer. Finally, the device has means to change the conversion table from a first address signal to a third address signal in the event the floating gate storage cells in the memory at the second address signal are defective. FIG. 1 is a block level schematic diagram of the solid state memory storage device of the present invention. FIG. 2 is a block level system diagram of a system comprising a computer, memory and other units for connecting and interfacing with the solid state memory device of FIG. 1. FIG. 3 is a detailed schematic block diagram of the microsequencer portion of the peripheral device shown in FIG. 1. FIG. 4 is a block level diagram of a self bootable solid state memory storage device of the present invention. FIGS. 5a and 5b are different embodiments of the controller portion of the solid state memory storage device of FIG. 4. Referring to FIG. 1 there shown a schematic block level diagram of a solid state memory storage device 10 of the present invention. The device 10 is a peripheral device for use with a computer system, shown in FIG. 2. Typically, a computer system 12, has a CPU 14 which addresses a memory 16 to store or to retrieve data therefrom. In addition, the system 12 comprises a peripheral device 18 such as a HDD (hard disk drive), a display 20, and an I/O unit 22, such as a keyboard. As is well known in the art, where the system 12 is a IBM PC compatible system operating under PC DOS or MS DOS operating system, a software called a device driver 24 must be loaded into the memory 16 to enable the CPU 14 to address the device 10, of the present invention. A copy of a device driver 24, suitable for use with an IBM PC compatible computer 12 operating PC DOS or MS DOS or other similar operating system is set forth in Exhibit A. The driver 24 can be loaded into the memory 16 from the HDD 18 or, as will be seen, even from the device 10 itself. Referring to FIG. 1, the device 10 receives data signals along a data bus 34 from the system 12. The data bus 34 is supplied to a data register 35, a Logical Sector Number (LSN) register 36, a command (CMD) register 38, and a status (STS) register 40. In the preferred embodiment, since the device 10 interfaces with an IBM PC compatible computer 12, the data bus 34 is 16 bits wide. The data register 35 is 16 bits wide. The LSN register 36, and the CMD register 38 are all 8 bits wide. The STS register 40 is 1 bit. The device 10 also receives address signals along an address bus 30 from the system 12. The address signal 30 are supplied to an address decoder 32. From the address decoder 32, command signals 42 are supplied to the STS register 40, CMD register 38, LSN register 36 and data register 35 to gate or clock-in the data signals into one of those registers. In the preferred embodiment the address bus 30 is 3 bits wide. The data register 35 is a dual port register 35 which stores the data signals supplied from the system 12 to be stored in the device 10. In addition the data register 35 also serves to buffer the data signals from the device 10 to be supplied to the system 12. The LSN register 36 contains the logical sector number to which the data in the data register 35 is to be stored in the device 10 or is the location from which data from the device 10 is to be retrieved. The CMD register 38 contains the command of either read or write, i.e., to retrieve data from the device 10 or to store data into the device 10. Finally, the STS register comprised of 2 bits, is a status register containing the response status code after the device 10 had executed the command contained in the CMD register 38. The status register contains a READY bit and an ERROR bit. READY bit indicates that the device 10 has completed the command in the CMD register 38 and is ready for the next command. ERROR bit indicates that an error has occurred for the command just attempted to be executed. The data from the data register 35 is supplied to a dual port SRAM 44. The SRAM 44 has two ports: one port in communication with the data register 35 and another port which is accessible by a multiplexed data/address bus 46. The bus 46 is a bus which supplies multiplexed data signals and address signals thereon. Finally, the dual port SRAM 44 is also accessed by an internal control bus 48 which is supplied from a microsequencer 50 (to be discussed hereinafter). The microsequencer 50 sets the bits in the STS register 40. In addition, the microsequencer 50 receives the contents of the register 38. The LSN register 36 is connected directly to the data/address bus 46. The microsequencer 50 is in communication with a ROM 52 which contains microcode, a copy which is set forth in Exhibit B. The microsequencer 50 issues microaddress along a microaddress bus 54 to the ROM 52 and receives microcode instructions from the microcode ROM 52 along a microcode bus 56. The microsequencer 50, as previously discussed, issues commands along an internal control bus 48 which is supplied to a plurality of units: counters 60, comparator 62, scratch pad register 64, CRC unit 66, and ECC unit 68. Each of the above-mentioned units 60-68 is connected to the data/address bus 46 and receives data therefrom. The counter 60, comparator 62, CRC unit 66, and the ECC unit 68 operates on the data signals from the data/address bus 46 and provides an output thereof supplied on the test bus 70. The test bus 70 is supplied back to the microsequencer 50. Finally, the microsequencer 50 supplies control signals along an external control bus 72. The device 10 also comprises a MAP ROM 74. To which the external control bus 72 and the data/address bus 46 are connected. Finally, the external control bus 72 and the data/address bus 46 are supplied to a plurality of solid state memory storage units 80 (A-N). Each of the memory units 80 comprises a plurality of floating gate storage cells of the type, such as disclosed in U.S. Pat. No. 5,029,130, and assigned to the present assignee. In the preferred embodiment, the MAP ROM 74 is also the same as the memory units 80. Referring to FIG. 3, there is shown a detailed block level circuit diagram of the microsequencer 50 of the device 10. The 8 bits from the CMD register 38 are supplied to a first multiplexer 82. The first multiplexer 82 also receives 8 bits from the output of a stack register 86 with its associated stack counter 88. The multiplexer 82 also receives 8 bits from an incrementer 84. Finally, the multiplexer 82 receives 8 bits from the next microcode program counter (NEXT13 MPC) register 92. The multiplexer. 82, therefore, receives four sets of 8 bit inputs and selects one of the eight bit inputs as the output thereof. The multiplexer 82 is switched based upon the output of the micro-opcode decode 94. Since there are four inputs to the multiplexer 82, 2 bits from the micro-opcode decode 94 are necessary to select the appropriate input as the output of the multiplexer 82. The output of the multiplexer 82 is supplied to a microcode program counter 90. The counter 90 merely stores the input thereto. The output of the counter 90 is supplied to the incrementer 84 which increments the counter 90 by one. Thus, the output of the incrementer 84 is normal "sequential" flow, and as previously discussed, is supplied back as one of the inputs to the multiplexer 82. The output of the counter 90 is also supplied to the stack register 86 and is stored therein. Depending upon the address of the stack13 top counter 88, one of the four registers 86 is selected as the output and is supplied as the input to the multiplexer 82. This is the conditional or unconditional branch flow. Finally, the output of the counter 90 is supplied as the microcode address for the microcode ROM 52. For each address of the microcode ROM 52, the microcode data signal stored at the address 52 is supplied as a 32 bit microinstruction back into the microsequencer 50. The microcode comprise of 32 bits, has the following format: xxxaaaabbbbbbbbcccccccccrrrrwwww The opcode, comprised of the three left most significant bits (xxx), are supplied to the microopcode decode 94 for decoding. The next four contiguous bits (aaaa) are supplied to a condition multiplexer 96. The next eight bits (bbbbbbbb) are the address for the microcode. These eight bits (bbbbbbbb) are also supplied to the internal bus 48, to be supplied to the counters 60. The next nine bits (ccccccccc) are supplied along the external bus 72. The remaining eight bits comprised of four bits (rrrr) for read control and four bits (wwww) for write control are supplied also along the internal bus 48. The two status register bits are shared among these eight bits. The eight bits (bbbbbbbb) for addressing the microcode are supplied to the NEXT13 MPC register 92. The output of the NEXT13 MPC register 92 is, as previously discussed, supplied back to the input of the multiplexer 82. The test bus 70 from the counter 60, comparator 62, CRC unit 66 and ECC unit 68 comprises 16 bits and are supplied to the condition multiplexer 96. The four condition multiplexer bits from the microcode are used to switch the condition multiplexer 96 and to select the particular bit or bits out into the micro-opcode decode 94. In the operation of the device 10 of the present invention, as previously discussed, in the preferred embodiment, the device 10 operates with a IBM PC compatible computer 12. As is well known for peripheral devices to be used with an IBM PC compatible system 12, the system 12 communicate with a peripheral device through address sectors. In the preferred embodiment, a sector is 512 bytes of consecutive data stream. The system 12 can communicate with the device 10 using Logical Sector Number (LSN) as the address to identify a particular sector location. The device 10 must then convert the LSN address into a Physical Sector Number (PSN) address to locate the address in the memory units 80 where the data is to be retrieved or where the data from the system 12 is to be written into. In the operation of the device 10, if we assume that an application software desires to read data from the device 10, the application program would issue an interrupt to the DOS operating system. As is well known in the convention of DOS operating system, the DOS operating system would send a fixed, predetermined LSN data signal along the data bus 34. The address signal on the address bus 30 would be chosen to cause the data on the data bus 34 to be stored in the LSN register 36. This would be followed by a READ command which would be stored in the CMD register 38. The system 12 will then wait in a loop and then periodically poll the status of the STS register 40 until the READY status bit is set indicating that the device 10 has completed the operation. The microsequencer 50 after detecting a READ command in the CMD register 38 would reset the READY status bit to "0" in the STS register 40. The data in the LSN register 36 would then be supplied onto the data address bus 46. The microsequencer 50 will then cause the external control bus 72 to activate the MAP ROM 74 to cause the data on the data/address bus 46 to be used as an address signal in the MAP ROM 74. From the address supply by the LSN register 36, the MAP ROM 74 would read out the content of the data at that address. This would correspond to the address of the PSN which is the address of the sector in the memory units 80 (a-n). The PSN data is then supplied along the data/address bus 46 and is stored in the scratchpad register 64. The microsequencer 50 will then use the PSN data from the register 64 as the address for the memory units 80 (a-n). The location as specified by the address of the PSN data would correspond to the Directory of the root level. One sector full of Directory data from the memory unit 80 (a-n) is then read out along the data/address bus 46 and stored in the dual port SRAM 44. An error detection method (to be described hereinafter) is applied. If there is no error, the microsequencer 50 will then set the READY bit in the STS register 40 to "1" to signify to the system 12 that the READ operation has completed. The system 12 would periodically check the status of the READY bit If it is set to "1" then it indicates to the system 12, that the device 10 is ready for another command. If there is an error, and it is not correctable, the ERROR bit in the STS Register 40 is set to "1". Finally, if the error is correctable, an error correction scheme is employed (to be discussed hereinafter). The system 12 will then retrieve the data from the dual port RAM 44, through the data register 35 and to its memory 16. DOS operating system would attempt to match the file name with the data from the Directory. If the file name is found in the Directory, the data associated with the file name is an LSN address with an offset in the File Allocation Table (FAT). The FAT table is stored at another fixed LSN location. The FAT table is retrieved in a similar manner from the memory units 80 (a-n). Based upon the offset LSN address associated with the file name from the Directory, DOS will then calculate the sector number (which equals LSN for the start of the FAT table plus the offset LSN address) to obtain a resultant LSN number. The resultant LSN number is then transmitted to the device 10 and stored in the LSN register 36. Another READ operation would then commence all as previously described and the sector of data from that LSN address is retrieved. From the FAT table the offset LSN address determined by the Directory is read to determine if it is the LSN address of the last sector or if it is the address to the next sector. If the content of the FAT table at the offset location is less than FFFF then the content at the offset is an address of the next sector. The next sector is calculated by adding the LSN of the starting location of the FAT table to the relative LSN value. Data from that sector is then retrieved all as previously discussed. If the content of the FAT table is equal to FFFF, then the sector is the last sector in the file. The foregoing description of the Directory and FAT entry and their LSN address is well known from DOS convention. In a write operation, the system 12 transfers an LSN address along the bus 34 to be stored in the LSN register 36. Thereafter, the system 12 transfers a sector of data from its memory 16 into the dual port SRAM 44, through the data register 35 of the device 10. The system 10 would then issue a WRITE command to the CMD register 38. The system will then stay in a waiting loop until the microsequencer 50 has changed the STS register 40 indicating that it has completed its operation. The microsequencer 50 would then retrieve the command from the CMD register 38 and if it is a WRITE command it would reset the READY bit to "0" in the STS register 40. The microsequencer 50 would then address the MAP ROM 74 using the address from the LSN register 36. From the MAP ROM 74, the data which is the corresponding PSN would then be read out of the MAP ROM 74 and would be stored in the register 64. Programming of the memory units 80 based upon the address from the PSN data stored in register 64 would then be performed. The PSN data from the register 64 would first be supplied along the data/address bus 46 as the address thereof to the memory unit 80. This would be followed by one sector full of data. Depending upon the design of the memory units 80, programming can be performed on a byte-by-byte basis or on a multiple byte basis. In the current preferred embodiment, programming is done on a byte-by-byte basis. After each byte is written into the memory unit 80, it is then read back for verification. This is accomplished by reading the data from the memory unit 80 and supplying it along the data/address bus 46 into the comparator 62. The comparator 62 would compare the data written into the memory unit 80 with the data read from the memory unit 80 from the same address location. If the comparison shows the data was programmed correctly, the microsequencer 50 then moves onto the next byte. If the data was not stored correctly, then the microsequencer 50 writes the data back into the memory unit 80 applying more programming pulses. By applying more programming pulses, it is well known that in floating gate storage devices more charges would be attempted to be stored onto the floating gate. This then would be followed by another read verification step. Again, if the data was correctly written into the memory unit 80, the microsequencer 50 would then proceed onto the next byte. If no error were found, the microsequencer 50 would then set the READY bit in the STS register 40 to "1" signifying that it has completed its operation. If an error were found, the microsequencer 50 would then apply an error correction method (discussed hereinafter). Because the storage cells of the memory unit 80 are of the floating gate type, errors in the storage cell can result from the charges on the floating gate decaying. This decay process can be divided into two stages. First, the charges stored on the floating gate can decay somewhat but still retain a charge, although it takes longer using the sense amplifier to determine whether it is a stored "1" or "0". In another stage of decay, the charges on the floating gate have decayed to a level where it has permanently changed the state of the storage cell from a "charged" to a "discharged" state. In this case, a permanent data error has occurred. To correct errors of the first type, the device 10 offers two modes of read operation: a normal read and a slow mode read. In a normal mode read, if the data read from the memory unit 80 still results in data error, then the same address is read again in a slow mode. The slow mode read would cause the sense amplifiers to be turned on longer permitting the lower amount of charge stored on the floating gate to differentiate the charge level between a "1" or a "0". As for the errors of the second type, each sector of data is written into the memory unit 80 with its associated error correction code (ECC). In one embodiment, the ECC is a Reed-Solomon code which applies 88 bits for each sector of data. In another embodiment, the ECC for a sector of data is encoded with CRC error detection. Finally, as will be shown, another embodiment of ECC is the use of redundant Hamming code. Since each sector of data is written into the memory unit 80 with its associated ECC code, and since it is possible to detect under certain circumstances when the error has arisen, the device 10 can operate on the data to correct the error. The error correction can be one of three following methods. 1. In the first method, data from the memory unit 80 is read in the normal mode. If the error persists, the data from that sector is re-read in a slow mode. 2. In a second method, the sector data is first read in the normal mode. If error persists, this is followed by attempted correction on the sector of data using ECC correction scheme. Thereafter, if error persists, then the same sector of data is read in the slow mode with ECC applied thereto. 3. Finally, in yet another method of error correction, the data is first read in a normal mode. If error persists, this is followed by a re-read of the sector data in the slow mode. If error persists, the data in the just read slow mode is operated upon by the ECC unit 68 to correct the error therein. Finally, if error still persists, then the data from the sector is read again in the normal mode with the ECC correction applied thereto. Apart from error correction of the data, since the memory unit 80 has portions of it written more frequently than other portions, different error recovery schemes are used to protect different portions. Since both the directory sector and the FAT sectors are retrieved frequently and are written into frequently (updated when a new file is written into the device 10), these sectors containing system information are stored in memory units 80 (a-n) redundantly. That is, 2�512 bytes are stored for each sector of system data. For system data, redundant Hamming code for error recovery is applied. In the redundant Hamming code, one byte of system data is stored as four bytes, in the following manner. 1 byte data+4 bits Hamming Code+4 bits inverted Hamming Code=2 bytes or 1 Unit A Redundant storage of Unit A, i.e. Unit A+Unit B, results in 4 bytes. These four bytes of system data are stored in the memory unit 80 either sequentially, i.e. Unit A+Unit B, or in separate sectors. Since the Hamming code has the ability to detect and to correct a single bit error but only has the ability to detect two bit errors, each two byte unit (A or B) has the ability to determine whether its own data has one or two bits of error. Thus, when system data is read back from the memory unit 80, the following scheme is used to determine the best data: ______________________________________ Unit A Unit A Unit A Correct 1 bit error 2 bit error______________________________________B Correct Unit A Unit B Unit BB 1 bit error Unit A corrected A corrected BB 2 bits error Unit A corrected A un-usable______________________________________ where each unit (A or B) is two bytes wide comprising of one byte of system data followed by the four bits of Hamming code and the four bits of inverted Hamming code. During the read operation, after each sector of data is read out of the memory unit 80 and is stored in the dual port SRAM 44, the microsequencer 50 applies the foregoing error recovery schemes (whether it is ECC or CRC for data or redundant Hamming code for system data) to determine if error exists in the data just read. If the data cannot be recovered, the microsequencer 50 sets an ERROR bit in the STS register 40. However, if the data can be corrected, the microsequencer 50 looks in the MAP ROM 74 for a new unused PSN sector. The microsequencer 50 would then cause a new mapping of the LSN sector address stored in the LSN register 36 to the new, unused, fresh PSN data. This mapping would in essence be the storage of the new PSN number in the MAP ROM 74 in the address from the LSN register 36. Thereafter, the microsequencer 50 would automatically cause the data in the dual port SRAM 44 to be stored back into the memory unit 80 at the new PSN sector address. Similarly, during a write operation, as each byte of data is written from the SRAM 44 into the memory unit 80 and is then read out and is compared to the data from the SRAM 44, if an error were found and the microsequencer 50 had already applied more programming pulses to attempt to store larger amount of charges onto the floating gate, then the microsequencer 50 would look up in the MAP ROM 74 to find a fresh unused PSN sector. The microsequencer 50 would then start all over again to write the same data into the new, unused PSN sector. When this is done, the microsequencer 50 would update the correspondence of the LSN from the LSN register 36 to the new PSN sector. Henceforth, access to the LSN would cause the microsequencer 50 to retrieve data from the new PSN address. A unique feature of the present invention is the use of the MAP ROM 74 to provide a mapping between each LSN address with the PSN address. The MAP ROM 74, as previously discussed in the preferred embodiment, can also be made of the same floating gate storage cell memory as the memory unit 80. The MAP ROM 74 contains one mapping entry between each LSN and PSN. Each mapping entry has the same size so finding a mapping entry for each LSN is simply multiplying LSN by the number of bytes per mapping entry. This provides the fastest .mapping speed in identifying PSN when the number of initial manufacturing defect or the number of bad rows replacement after usage in the memory unit 80 is high. With this MAP ROM 74, the microsequencer 50 can replace a defective sector in the memory unit 80 with an unused good sector whenever an error is detected. This replacement is accomplished by simply modifying the MAP ROM 74 translation table. Furthermore, as discussed heretofore, this translation under certain circumstances is done automatically without user intervention or knowledge. Thus, to the system 12, the storage in the memory unit 80 is always contiguous and is good, because every LSN mapping entry always points to a good PSN entry. However, if the device 10 runs out of "good" physical sectors to replace the defective physical sectors, then the device 10 will have discontiguous Logical sectors, similar to the conventional peripheral storage devices. In that event, however, the device 10 can be reformatted to again achieve contiguous logical sectors. Furthermore, each of the memory units 80 can be partitioned into two areas during a high level DOS format operation. The two areas of the user accessible areas are "normal data area" where normal data sectors are used to store usage data and a "reserve area" where reserved sectors can be used to replace defective data sectors when found. Thus, to the user, virtually the same amount of user usable data sectors is always present. As is well known, prior to use, the device 10 must be formatted, similar to formatting a hard disk drive. This formatting can be accomplished at two levels: at a system level which is performed by a routine from the operating system. In addition, the device 10 can be formatted at a "low-level". Initially, the device 10 is tested or formatted right after manufacturing. The device 10 is tested for retention failure reliability, among others. Each of the storage cells in the memory units 80 is stored with charges on its floating gate. Thereafter, the device 10 is subject to manufacturing screening tests, such as baking and voltage stress test on each of the storage cells in each of the sectors. If charges are not retained on the floating gate of the storage cell, or if the storage cells do not pass the other manufacturing screening tests, such as voltage stress, then the sector is deemed a "bad" sector. The "bad" sectors are marked with an indicia, such as by storing a data pattern of "00" in each byte of the sector. Thereafter, during the software format of the device 10, the software format program reads the bytes of all the sectors, and if a majority (or some other pre-set percentage) of the bytes are stored or marked with the data pattern of "00" then the sector is "bad" and the address of the "bad" sector is recorded in the MAP ROM 74. The address of the "bad" sectors are then no longer usable to map LSN to PSN. In subsequent low-level format, after the device 10 has been in use, formatting test is performed on "non-bad" sectors. A "non-bad" sector is a sector whose address is not marked as being "bad" as stored in the MAP ROM 74. Because the data pattern of "00" or other indicia, may be actual data, the determination of whether a sector is "bad" or is "non-bad" cannot be made by looking at the data pattern or the indicia from the memory unit 80. The determination is made by looking at the addresses stored in the MAP ROM 74. Each of the floating gate storage cell of a "non-bad" sector is erased. Data is then written into the bytes of the "non-bad" sectors by the microsequencer 50 using the following parameters to carry out the write operation. 1. The microsequencer 50 causes a nominal erase time (ET) to be used. A longer erase time means that each of the storage cells can be erased into a "1" state more strongly and can be easier to be sensed as a "1". The erase time has the same effect on all cells. 2. A nominal write time is WT. A longer write time means that each of the storage cells in the memory unit 80 will be written to a "0" state more strongly and is easier sensed as a "0". However, it is also more likely that a "0" state can disturb other adjacent storage cells. 3. A nominal read sensitivity value is RN. Read sensitivity is set by the sensing circuit design. As previously discussed, in the device 10 of the present invention, the sensitivity can be increased by increasing the time period for the sense. Another possible value for read sensitivity is "RM" which requires that each of the storage cells be written with a "0" stronger than a normal "0" to be sensed as a "0". 4. Data pattern from the system 12 can be anything. However, when writing into the storage cells 80, some particular data patterns are easier to fail during a write operation than others, depending upon the circuit design of the particular memory unit 80. In particular, OF or FO are the most sensitive patters for the device 10. To boost the reliability of the device 10, the "good sector" selection process must guarantee that after the selection, the chance of the microsequencer 50 write failure using the nominal ET, WT and RN values should be minimized. The following is a selection criteria to achieve this goal: ______________________________________Testing Erase Write Data ReadGoal Time Time Pattern Sensitivity______________________________________Write w/maximum 1/2 * ET 1/2 * WT 0 RMbitWrite w/sensitive 1/2 * ET 1/2 * WT 0F and F0 RMdata patternWrite w/disturb 2 * ET 2 * WT FF and 7F RNdata pattern______________________________________ Note: The choice of data pattern and timing factor should be varied according t the characteristics of memory units 80. Thus, in subsequent low level format after manufacturing, different data patterns are written repeatedly into each of the bytes of the "non-bad" sectors. The data pattern from each of the bytes of the "non-bad" sectors is read and is compared to the data pattern written into those bytes. If the comparison results in an incorrect match between the data pattern read and the data pattern written into the "non-bad" sectors, then those sectors are also deemed "bad" and the address of those sectors is written into the MAP ROM 74 as additional "bad" sectors. Alternatively, if the comparison between the data pattern read from each of the bytes of the "non-bad" sector correctly matches the data pattern written into each of those bytes, then that physical sector address is stored in the MAP ROM 74 as a usable sector to which a logical sector address is mapped. As previously discussed, in the device 10 of the present invention, it is used for the system 12 operating with a device driver 24 in its memory 16, as shown in FIG. 2. The device driver 24 is typically loaded from a hard disk drive 18 or some other type of peripheral device. Referring to FIG. 4 there is shown another embodiment of the device 110 of the present invention, called an EECARD with a self-contained device driver 24. The device comprises the device 10 with its data and address ports all as previously described and shown in FIGS. 1 and 2. In addition, the device 110 comprises a ROM 24, PROM or floating gate memory storage. The memory 24 would contain the device drivers 24. Finally, the EECARD 110 would also contain a controller 112. The EECARD 110 is a self "booting" type in that upon start-up, the device driver from the ROM 24 is loaded through the controller 112 into the memory 16 of the system 12. Thereafter, the controller 112 is switched such that the data and address buses from the system 112 are then directed towards the device 10. The EECARD 110 can be of the type satisfying the specifications for the PCMCIA standard. Referring to FIG. 5a, there is shown one embodiment for the controller 112. In the embodiment shown in FIG. 5a, data from the system 12 is supplied to a multiplexer 114 which is controlled by the contents of a register 116. The data in the register 116 controls the operation of the multiplexer 114. Once the device driver from the memory 24 has been loaded into the memory 16, the multiplexer 114 is switched so that the data bus is then connected directly to the device 10. Referring to FIG. 5b, there is shown another embodiment of the controller 112, which is the preferred embodiment. Data to and from the system again, is supplied to a multiplexer 114. The multiplexer 114 is connected to the memory 24 and to the device 10. A particular address line from the system 12 is supplied to the multiplexer 114 and is used to set the multiplexer 114. In the preferred embodiment, address A17 is used to select a multiplexer 114. Lower order address signals, i.e. address signals from A0-A16 are supplied directly to the memory 24 and data therefrom is read out onto the system 12 into its memory. Thereafter, higher order addresses with A17 set to 1 is then used to address the device 10. There are many advantages to the device 10 or 110 of the present invention and the method of their operation. As can be seen, because of the unique nature of the MAP ROM 74, the memory units 80 do not have to be 100% defective-free from manufacturing defects. Through the use of the MAP ROM 74 mapping LSN to PSN, defective sectors can be mapped out of the memory unit 80 without any loss or penalty. Furthermore, as the storage cells are used and as they degrade in performance, various recovery schemes are provided automatically so that to the user, the device 10 remains as defective-free as when originally first used. Finally, through the use of redundant storage in the memory units 80, more sensitive system data can virtually be guaranteed their readability and reliability for storage. Patent Citations
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AYP/Poulan Authorized Substitution The part number 121021X has been changed to part number 532150546. While the new part may look different, this is a AYP/Poulan approved substitution. Please note that the price and availability shown is for the new part number 532150546. |
Brand | AYP/Poulan |
Old Part Number | 121021X |
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Condition | New |


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Tag Archives: Stony Burk
NPR's Living on Earth 10 Minute Segment on Highpointing
NPR's Emmett FitzGerald has a wonderful 10 minute segment featuring Roy Wallen and Stony Burk at Jerimoth Hill.
Posted in General
Tagged Highpointers in the News, Rhode Island, Roy Wallen, Stony Burk
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Hoosier Hill Bench Vandalized
We're getting the report from Stony Burk that a bench at Hoosier Hill that had been added as a Scout Eagle Scout project has been vandalized.
Club's Summit Register Initiative
Ever wonder what happens to those registers you sign on summits? Thanks to an initiative mostly from highpoint liaison chairman Stony Burk the Club has begun saving historic registers. He just turned over the reigsters from Granite and Borah Peaks … Continue reading
Stony Burk's Car Mileage Hits 345,345 (largely repeatedly driving to highpoints)
Stony Burk, the highpoint liaison, takes his job seriously literally repeatedly driving to highpoints in his Jeep Cherokee "Cynthia Rose." He puts up mileage that car companies can only dream of. Here's 345,345.


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Blog Archive
Posted by Meg Schwamb on 2011/06/08 02:43 CDT
On May 5 and 6, I had a run on the WIYN (Wisconsin-Indiana-Yale-NOAO) telescope, a 3.5 m telescope, the second largest telescope on Kitt Peak in Arizona.
Posted by Meg Schwamb on 2011/05/25 08:30 CDT
The last decade has seen an explosion in our understanding of the solar system with the discovery of the largest Kuiper belt objects (KBOs) of comparable size to Pluto.
So far, no moons found at Ceres or Vesta
Posted by Emily Lakdawalla on 2011/04/15 02:37 CDT
Since the Galileo mission discovered tiny Dactyl circling Ida in 1993, quite a lot of asteroid systems have been found to be binary; there are even a few triples. So it's quite reasonable to guess that two of the biggest asteroids, Ceres and Vesta, might also have satellites.
Welcome to Carnival of Space #191
Posted by Emily Lakdawalla on 2011/04/05 11:25 CDT
Welcome, everyone, to the Planetary Society Blog for the 191st Carnival of Space! Every week, a different webmaster or blogger hosts the Carnival, showcasing articles written on the topic of space.
Checking in on Jupiter: the belt is coming back
Posted by Emily Lakdawalla on 2011/03/25 03:46 CDT
Since it's been several months since I last took a look at Jupiter, I thought it was time to see what's up with the South Equatorial Belt.
A dog-bone-shaped asteroid's two moons: Kleopatra, Cleoselene, and Alexhelios
Posted by Emily Lakdawalla on 2011/02/23 12:47 CST
Asteroid (216) Kleopatra has been interesting to astronomers for a long time because its brightness is highly variable, but it seems to get more interesting every time somebody looks at it with a new instrument. This week a paper was published in Icarus revealed that it's 30 to 50% empty space.
Close approach to Earth turns Apollo into Aten
Posted by Emily Lakdawalla on 2011/02/08 12:49 CST
Last week we got buzzed by a very small asteroid, something that happens fairly often. But there were several details that made the close approach of asteroid 2011 CQ1 worthy of note.
Jupiter's outbreak is spreading
Posted by Emily Lakdawalla on 2010/11/22 11:03 CST
Jupiter, always a pretty sight in the sky, is now worth visiting every day; the "outbreak" that heralds the return of Jupiter's formerly red, now fadedsouth equatorial belt is expanding and multiplying.
Posted by Emily Lakdawalla on 2010/11/11 10:48 CST
Jupiter's faded belt may be coming back.
DPS 2010: Pluto and Charon opposition surges, Nix and Hydra masses, Pluto and Eris compositions
Posted by Emily Lakdawalla on 2010/10/25 11:18 CDT
An awful lot of the talks in the Pluto session on Tuesday morning, October 5, at the Division of Planetary Sciences meeting spent more time focusing on how bad weather conditions were during the astronomers' attempts to view Pluto as it occulted background stars than they did on any measurements or science that came out from the data.
The August 20, 2010 Jupiter fireball -- and the March 5, 1979 one
Posted by Emily Lakdawalla on 2010/08/24 11:36 CDT
Following up on the story I first posted on August 22, the Jupiter impact fireball first noticed by Japanese amateur astronomer Masayuki Tachikawa has been independently confirmed by two other Japanese astronomers.
Yet another Jupiter impact!? August 20, seen from Japan
Posted by Emily Lakdawalla on 2010/08/22 05:03 CDT
Yet another Jupiter impact!? August 20, seen from Japan
Posted by Emily Lakdawalla on 2010/05/10 05:22 CDT
Via Daniel Fischer's Tweet about a blog entry by Astro BobI learned of something which should be obvious to anyone who has trained even a rather small telescope on Jupiter over the past few weeks: one of its iconic stripes is just plain gone.
Posted by Timothy Reed on 2009/06/15 03:56 CDT
Timothy Reed explains how optical telescopes are tested for gravity sag, and the methods used to counteract or compensate for it.
Posted by John Spencer on 2009/06/08 01:49 CDT
Taking a look at Jupiter's moon, Io, from Hawaii.
Farewell to Hubble, Obama Calls, Astronauts Testify to Congress as Shuttle is Set to Land
Posted by Ken Kremer on 2009/05/22 05:13 CDT
Farewell to Hubble, Obama Calls, Astronauts Testify to Congress as Shuttle is Set to Land
An Auspicious Week for Astronomy
Posted by Mark Adler on 2009/05/11 11:54 CDT | 1 comments
On Monday, if all goes well, we will launch the Space Shuttle to rejuvenate one the greatest scientific missions launched on or off the Earth: the Hubble Space Telescope.
Mapping Mars, now and in history
Posted by Emily Lakdawalla on 2009/02/26 04:23 CST
Planetary cartographer Phil Stooke has been working on a cool project to compose and compare maps of Mars that show how we saw the planet throughout the Space Age.
Treasures from Mars' ancient history
Posted by Emily Lakdawalla on 2009/01/28 12:06 CST
In which I discover Earl Slipher's Mars: The Photographic Story.
No Longer Boring: 'Fireworks' and Other Surprises at Uranus Spotted Through Adaptive Optics
Posted by Emily Lakdawalla on 2004/11/11 07:10 CST
Uranus has the unfortunate reputation of being the most boring planet in the solar system. But where it appeared to be a nearly featureless, hazy blue ball to Voyager 2, it is now blooming dozens of clouds that are visible to the sharp-eyed Keck II Telescope.
Our Curiosity Knows No Bounds!
Become a member of The Planetary Society and together we will create the future of space exploration.


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Cats cannot scream.
44 Responses to "Screaming"
A scream is a loud vocalization in which air is passed through the vocal cords with greater force than used in regular vocalization. Likely this kitten does not posses the lung strength or necessary vocal chords to adequately yell
Like or Dislike: 4 5
Does it really matter that much, it's just a website.
Like or Dislike: 4 1
I stand corrected.
Like or Dislike: 5 2
wow, MLIA, not NKIA sorry
Like or Dislike: 2 3
What I love to do is show up at web-sites with pictures of cats and talk about how wrong the pictures are.
Like or Dislike: 2 2
I agree with Katie. We shouldent be mocking others on their mistakes or lack their of. We should all be noting on the averageness (I know thats not a word) of the cats in the photos presented.
Like or Dislike: 2 2
This cat is probably not screaming. Most users of this website probably do not have doctorates in English nor in specific educational subcategories thereof. The internet is full of people who do not have doctorates in many subjects.
Like or Dislike: 3 4
I know they can't ACTUALLY scream, but I've heard meows VERY SIMILAR. My cat didn't like this HUGE cat named Oliver and she was sitting on one side of the window and my cat on the other. Katie, my cat, sounded like she was screaming, though it was a loud meow in a screaming sort of sound…
Like or Dislike: 3 2
Well yeah cats can't scream. But if you accidentally step on it you will know that screaming is for pussies.
Like or Dislike: 3 2
Why are people so arrogant as to think that animals cant do -anything- that humans attribute to themselves? Cats -can- scream even if the sound doesn't form a word, and they do scream quite loudly if someone hurts them.. and that is still perfectly ordinary of a cat. Still, nothing to LOL about there.
People, however, are much more amusing in their screwups: Yes, people should be more observant before pointing out others' flaws, and perhaps be nicer to each other in any respect; yes, grammar is spelled with an A; yes, grammar involves a measure of logic and failure to notice things can in fact lead to poor grammar; yes, this entire post is just as egregious as this website.
now that's worth LOL'ing over. Have fun pointing out the obvious for yourselves, and verbally abusing each other.
Like or Dislike: 4 1
Cats CAN indeed scream.
Link here.
o.0Like or Dislike: 1 0
for pointing out how silly this all is!!!!
Like or Dislike: 1 1
Maybe they can't scream per se, but they can try really hard. I'll try to capture that particular vocalization next time I give mine a bath. It's difficult as I'm usually trying to keep them from disemboweling me, but I'll try.
Like or Dislike: 1 1
maybe it is, maybe it's not. All I can say is it's VERY cute!
Like or Dislike: 0 0
Haha nice one..
Like or Dislike: 0 1
actually cats can scream….here's evidence http://www.youtube.com/watch?v=kbltrZe2274
Like or Dislike: 0 0
Cats can scream and make many other noises quite similar to human sounds such as crying. Screaming and crying are only a couple of human like sounds cats can make.
Like or Dislike: 0 0
My cat has never screamed but that is a video on youtube that I have seen before. They can scream. Case closed.
Like or Dislike: 0 0
I beg to differ. cats can scream. once my mom was bathing our cat gandualf, and he flipped out (as cats do not like water) and it sounded like someone was screaming. but it was a cat screaming, not a human.
Like or Dislike: 0 0
There are certainly numerous particulars like that to take into consideration. That is a nice point to deliver.
Like or Dislike: 0 0
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Like or Dislike: 0 0
Good article , thanks and we want more! Added to FeedBurner as well
Like or Dislike: 0 0
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Like or Dislike: 0 0
Would you be all in favour of exchanging hyperlinks?
Like or Dislike: 0 0
There are some interesting points on this article but I don't know if I see all of them center to heart. There's some validity but I'll take hold an opinion until I look into it further. Good article , thanks and we want more! Added to FeedBurner as well.
Like or Dislike: 0 0
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Like or Dislike: 0 0
More people need to read this and understand this aspect of the story. I cant believe you're not more popular.
Like or Dislike: 0 0
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Like or Dislike: 0 0
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Like or Dislike: 0 0
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A Resting Place For Beloved Pets.
6400 Bentley Av
Billboard - The latest coupons and news on this business!
Attended cremations are growing in popularity. Call for a consultation.
For over 80 years, Hinsdale Animal Cemetery and Crematory in Willowbrook, IL, has honored the memories of our beloved companions and family members—our treasured pets. Our beautiful, exquisitely-landscaped grounds offer the serenity to reflect on the love that our furry friends brought into our lives.
Hinsdale offers a choice of dignified options with which to remember your pet:
• Burial
• Cremation
• Memorialization
We offer two types of cremation, private or memorial. When we perform a private cremation, only one pet at a time is in our crematory. All of the pet's ashes, and only that pet's ashes, are returned to the owner. The included urn is plain, white plastic; however, we do offer many other urns as an option. If an owner chooses to, they can be present for the private cremation of their pet.
Call Hinsdale Animal Cemetery and Crematory today for more information.
Category: Pet Cemeteries
Peaceful, Respectful, Dignified by Wendy - 11/09/2011
My dog died after being with us for almost 16 years. The staff was amazingly caring and respectful. She received better care than some people I have known (and she deserved it; she was a wonderful friend). We watched them gently enter her into the crematorium for cremation. You could tell that this is more than a job for the owners. You can tell that they are really good people.
Thank You for your kindness by Mike & Kara Ward - 09/05/2010
We would like to thank all the staff at Hinsdale Animal Cemetery for their compassion and professionalism. We recently had our beloved cat Tabby cremated there, and we immediately were met at the door, and put at ease.A very peaceful setting along with compassionate staff make a very difficult day, less stressful. We thank you sincerely and will definitely use your services again with our beloved pets, which deserve the best. Thank You,Mike & Kara Ward"Tabby Ward "
Serving: Willowbrook IL, Dupage IL (Metro), Near West IL (Metro), South IL (Metro)
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Assurances: Licensed, Certified, Insured, Bonded, Accredited, References Available, Locally Owned
Language: Spanish Speaking
DexKnows Mobile profile for Hinsdale Animal Cemetery And Crematory in Willowbrook, IL


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Excel No. 11 Blades for Exacto/Racer's Edge style hobby knives (100)
With your purchase, receive at no cost:
This is a package of No. 11 blades for Exacto and Racer's Edge style
hobby knives. The blades are made from Carbon Steel for a very long
lasting and extremely sharp edge. These blades are perfect for cutting
and trimming, as well as for cutting masking material when painting
lexan R/C bodies.
This is a bulk pack of blades and contains 100 blades.
This is a bulk pack of blades and contains 100 blades.
This product was added to our catalog on August 24, 2009.


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(200 quotes found)
"It's an unbelievably exhausting show to perform. Each guy carries as much text as any major character in any other play."
Charles Fee
"Forgive me for not writing but this man is exhausting."
Wallis Simpson Duchess of Windsor
"We regret, repent, and remorse only when we have lost exhaustively."
Kazeronnie Mak
"Only the really plain people know about love-the very fascinating ones try so hard to create an impression that they soon exhaust their talents."
Katharine Hepburn
"He is exhausted and would die in prison if he stays in captivity another year."
Badia Aref
"If you are tired of starting over, then stop giving up."
Marie Muhammad
"Being unable to say no can make you exhausted, stressed and irritable."
"Enhance your life or exhaust your life. Choose one."
Rodel Natividad Casio
"The price of the ticket is exhaustion."
Andy Murphy
"I exhausted everything, ... If it was supposed to happen it would have happened. It just was not supposed to and I'm comfortable with that."
Allan Houston


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Emerald cut engagement rings is both classic and elegant as they are one of the most versatile cuts available for your diamond. Not only is an emerald cut incredibly beautiful, but it can also be styled beautifully with almost any setting. Gems that have been shaped into an emerald cut feature both the sheen and clarity of any beautiful ring.
Historically, this attractive rectangular cut has been used to show off the beauty of richly colored gemstones for over 300 years. Within the last century, emerald cut engagement rings have made a beautiful impact on proposal trends as this unique shape can also show off the beauty of a near perfect stone. This signature cut contains 58 facets in total, with 25 on the Crown and Pavilion, and an additional eight on the Girdle. The unique effect caused by these prominent edges draws the eye inward to the stone, which enhances the sparkle and clarity of the diamond.
Any setting, whether uniquely modern or classically traditional, can show off the beauty of emerald cut engagement rings. In order to get the most sparkle from your diamond, putting it into a four prong setting can be an excellent way to allow a great deal of light to shine straight through. Emerald cut diamonds can also be incredibly beautiful on their own as a solitaire or centered among side stones for a more traditional look.
These beautiful diamonds are striking on the finger of any confident and lovely individual. Emerald cut engagement rings is perfect for fun loving risk takers who have a soft spot in their heart for anything vintage. These stunning, rectangular shaped diamonds can be an elegant throwback to the 1940s when these stones were very prominent among many beautiful young women.
Emerald cut diamonds is a classic and beautiful cut for any modern or traditional style of engagement ring. Choose below from our many available emerald cut engagement rings.


text:
Ben & Skin
Eagles Carve Up Cowboys
Thanksgiving disappointment overflowed for the Cowboys Thursday at Jerryworld as the Eagles left little doubt about who is in charge of the NFC East.
Ben & Skin Show: 2015 Dallas Mavericks Anthems
With the Dallas Mavericks kicking off the 2014-15 NBA regular season, the crew of the Ben & Skin Show debut their Mavs Anthems! Listen and vote for the one you think is the best:
Video: Ben & Skin's Beer Mile Challenge
It's was epic! Ben & Skin's crew got out and did the 'Beer Mile'
5 Reasons DeMarco-Claus Can't Be Benched
The idea that Jason Garrett should punish DeMarco Murray for his fumbling problems is laughable for the following 5 reasons:
Ben and Skin Show 2014 Cowboys Preview Songs
It's the debut of the Ben and Skin show 2014 Dallas Cowboys Preview Songs. Check out the tunes and vote for your favorite below!
Eddie Gossage On The Tony Stewart Incident
Head Honcho at TMS, Eddie Gossage calls into the show for insight on the Tony Stewart incident from Saturday night
Ben Remembers Friend, Colleague Richard Durrett
His legacy is one of extreme kindness, a relentless work ethic and an undeniable love of family. Hard to do much better than that.
Michael Young
Michael Young was listening to the show and decided to call in and talk some basketball.
Why The Cowboys Need To Give Dez 'Megatron' Money Now!
The Cowboys need to sign Dez Bryant immediately. Today. Do it now. Pay him just as much as the highest paid WR in football.
Romo Discredits The 'Romo Curse'
The Cowboys quarterback has attended countless games this offseason. And the common thread? Every team has lost — or at least, that's the perception.
East Texas Sports Boys
The East Texas Sports Boys return by calling the author of a Johnny Manziel book. Will shots be fired???
Video: K&C's Wheel of Misfortune Egg Slurp Sacrifice
The Fan's The K&C Masterpiece teamed up with Jeff Cavanaugh of the GBag Nation and Kevin Turner from the Ben & Skin Show to make a sacrifice to the playoff gods for the Dallas Stars and the Mavericks.


text:
Start learning with our library of video tutorials taught by experts. Get started
Teaches basic keyboard and interface shortcuts, as well as little-known navigational, dialog box, and tool shortcuts.
Learn to use InDesign's tools for working with long documents such as books and tables of contents.
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Covers the basics of character and paragraph formatting, paragraph and character styles, nested styles, and baseline grids.
Covers all the basic principles of InDesign CS2, from getting to know the workspace and tools to using advanced new features.
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more from our members »


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Jennifer Aniston Launches Living Proof Web Series
Jennifer Aniston Talks "What Not to Do" With Hair
Jennifer Aniston stepped out in NYC to launch her new Living Proof web series, Good Hair Day, yesterday. She's a spokesperson for — and an investor in — the brand and is taking her duties to the next level with her three-part web series, in which she joins experts, including her hairstylist Chris McMillan, and real-life women on the street to talk hair. In a teaser video for the series, Jennifer explains why the cause is important to her, stating, "Good hair days matter to women because . . . we're women." The first episode, "Obsessions," airs today with two more, titled "Confessions" and "Lessons," being released later this month.
We caught up with Jen and Chris at yesterday's press day. During our chat with Jen, she reflected on what she's learned about hair over the years. She said, "I had great hair as a kid, and my mom said, 'You're not allowed to touch your hair until you're 13,' and the first thing I did was cut it all off. I learned that my hair really was a pain in the butt — sort of wide and unmanageable. I learned all my lessons in my younger years of what not to do." Read the entirety of POPSUGAR's Jennifer Aniston interview!
— Additional reporting by Jessica Cruel
- Ingrid Michaelson has called it quits with her husband — Us Weekly
- Kelly Clarkson makes surprising American Idol admission — HuffPost Celebrity
- Look what Gwyneth Paltrow Instagrammed last night — Lainey Gossip
- Scarlett Johansson comments on that John Travolta encounter — Dlisted
- What is Shia LaBeouf doing with his look? — JustJared
- Kim Kardashian reveals another interesting outfit — Hollywood Tuna
- Here's how Britney Spears spent her night — Pink Is the New Blog
- Someone else shared a picture of Chelsea Handler's boobs — The Superficial
- Have you heard Kylie Minogue's new single? — popbytes


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52 of 54 people found the following review helpful
Very versatile.,
Verified Purchase(What is this?)
This review is from: Daffodil ULT300 Dual Powered USB Light - 28 Bulb Reading Lamp with Desk / Headboard Clamp and Flexible Gooseneck - Battery (4xAA Not Included) or USB Power - 3 Brightness Levels - PC and MAC Compatible (DIY & Tools)
Having tried the type that plugs into a usb socket, and found them difficult to position and very wobbly being supported only by the usb socket, this model is a totaly different kettle of fish. Having a spring loaded clamp built in, it supports its own weight easily and can be plugged into the usb or run off 4 AA cells, rechargable or standard. With 3 levels of light available it is easy to select one that suits your own needs. Even set to minimum there is enough light to work with in a darkened room,and set to the medium setting provides ample illumination, with good ecconomy if used on batteries. The flexible stem is very slim and holds any position that it is bent to positively. The spread of light is quite wide and covers the keyboard easily which makes positioning the lamp less critcal. The lamp head is quite slim and with the leds recessed into it there is no sideways light spill to annoy other people and no glare to the opperator. To sum up, works well, well made, its versatillity means that it is equally suited to crafters, model makers, dress makers, sewing machine operators etc. Rember the old saying, buy cheap buy twice. At the price I think its good value.
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The 'blood diamonds' which Naomi Campbell allegedly received from former Liberian president Charles Taylor have been handed over to authorities in South Africa.
The British supermodel took the stand at The Hague, Netherlands on Thursday (05Aug10) as part of Taylor's ongoing war crimes trial to face allegations she accepted the illicit gems - which are used to fund conflicts - after a dinner party thrown by Nelson Mandela in 1997.
Campbell claimed she didn't know what the "dirty stones" were or who had given them to her, while prosecutors claim the rocks were in fact blood diamonds, used to finance the 1991-2002 Sierra Leone civil war.
The catwalk beauty claimed she didn't keep the stones, but handed them to her friend Jeremy Ratcliffe, the former chief executive of the Nelson Mandela Children's Fund, to "do something good with".
Ratcliffe has now issued a statement revealing he kept the diamonds as he didn't want to involve his charity in any possible illegal activities, but recently turned them over to police in South Africa. He also confirmed he would be willing to testify at The Hague if necessary.
The statement reads, "Three small uncut diamonds were given to me by Naomi Campbell on... September 26, 1997... In the end I decided I should just keep them."
A spokesman for the South African police, Musa Zondi, confirmed to the AFP that the stones had been received: "They were handed over to the police and now they have been sent to the diamond board for authentication. Obviously there has to be an investigation, but first we have to wait and get the diamonds authenticated before we can say anything."
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US 7299285 B2 Abstract A system uses a resource locking token to allow various processes to have exclusive access to a system resource. The process that receives the token then requests that a local database be updated/synchronized with a master database. The process continues checking the synchronization status every time it gets the token. When the process receives the token and the synchronization is complete, the local database is accessed and the data is used in accessing the system resource. The token is then returned to the system.
Claims(1) 1. A system for resource sharing and database synchronization, the system comprising:
a plurality of application processes, each process having an assigned priority level and sharing a resource locking token, at least one process having a low priority level;
an operating system that controls distribution of the resource locking token among the plurality of processes, the resource locking token being passed to a first process of the plurality of processes in response to the assigned priority level;
a local database that is synchronizable with a master database; and
a local controller capable of executing the plurality of application processes such that a low priority process receives the resource locking token, requests synchronization of the local database with the master database after receiving the resource locking token, returns the resource locking token to the operating system if synchronization is not complete, accesses the local database by the low priority process after synchronization is complete, accesses the resource by the low priority process in response to data from the local database, and returns the resource locking token to the operating system.
Description The present invention relates generally to the sharing of system resources. System resources, such as printers, processors, modems, memory, and even other applications, may be shared amongst various system applications/processes. For example, a communication process may share a modem resource with an email process. However, typically only one system process can access the resource at any one time. If a lower priority process is using a system resource, other higher priority processes are locked out until the lower priority process has relinquished control. Systems that employ databases can have one master copy of the information contained in the database and multiple �local� copies. The local copies may be exact copies of the master database information or the local copies may be a subset of the information that is stored in the master database. In order for the local databases to have the most up-to-date information from the master database, the local databases must be periodically synchronized with the master database. For example, if the master database is updated with new information, the local databases typically will not have this-new information until the databases are synchronized. One problem with synchronizing databases in a system is that a lower priority process may have a system resource locked while waiting for a local database to synchronize. While the lower priority process has the system resource locked, higher priority processes cannot use the resource. There is a resulting need in the art for a prioritized system that enables system processes having different priority levels to share a system resource. The embodiments of the present invention encompass resource sharing and database synchronization. The method first receives exclusive access to the resource. Synchronization of a local database with a master database is then requested. The method then checks the synchronization status until synchronization is complete. Data from the local database is then read and the shared resource is accessed with the data. The exclusive access to the resource is then returned to the controlling system for distribution to other processes. The embodiments of the resource sharing with database synchronization of the present invention provide prioritized access to a shared system resource. Additionally, a low priority process does not lock out other higher priority processes from the resource while waiting for a local database to be synchronized. Subsequent discussions of the various databases of the embodiments of the present invention refer to synchronization of the databases. Synchronization and updating of the databases are considered to be substantially similar tasks and the terms can be used interchangeably. Each statistic in the database may be referred to as an object or element. For example, in one embodiment, if the data stored in the database includes statistics on the quality of service of a communication link, one object stored in the database is a bit error rate for each link that is coupled to the master database. Other types of objects/elements include link downtime, link bit rate, and subscriber information. In alternate embodiments, the database is used for storing information that is not related to communication link quality of service. In such embodiments, the objects/elements are not communication link related. The types of objects/elements stored in the database do not limit the present invention. The master database (101) is coupled to multiple local databases (105-106). The embodiment of The local databases (105-106), in one embodiment, have the capacity to hold a substantially equivalent copy of the data that is stored in the master database (101). In another embodiment, the memory capacity of the local databases (105-106) is such that only a smaller subset of the data stored in the master database (101) will fit in the local databases. The databases (101, 105, and 106) of the present invention are stored in some form of memory. In one embodiment, the database memory is of the type used for temporary storage of data such as random access memory (RAM). The database memory may also be of the type used for permanent storage of data such as read only memory (ROM), programmable read only memory (PROM), and/or memory cards. Other types of database memory may include semiconductor, magnetic, optical, or storage media. The storage media memory can include hard disk drives, floppy disk drives, optical drives, removable solid-state memory cards, or any other type of storage media. The storage media may be fixed or removable from a database system. The master database (101) and the local databases (105-106) are coupled through a background synchronization block (110). As described subsequently, the background synchronization block (110) provides a method by which the local databases (105-106) are updated with data from the master database (101). In one embodiment of the present invention, the objects stored on the local databases each have a flag that indicates a synchronized or not synchronized status of the object. In one embodiment, the flag indicates either �pending� or �ready�. The �pending� flag indicates that the object has not been synchronized with the master database and, therefore, may not be accurate and up-to-date. The �ready� flag indicates that the object has already been successfully synchronized with the master database. In one embodiment, the �pending� and �ready� flag takes the form of a single bit of data. For example, if the flag is a logic 0, the flag is set for �pending�. If the flag is a logic 1, the flag is set for �ready�. Other embodiments may use other flags to indicate the �pending� and �ready� states. The �pending� and �ready� states are for illustration purposes only. Alternate embodiments may use other states that perform substantially the same function as the states of the present invention. For example, in one embodiment, a �pending� flag is set by a bit set to a logical 1. If that bit is not present, then the object has been synchronized and is considered �ready� for processing. The various processes (201, 203, and 205) of the embodiment of The above-described processes are for illustration purposes only. There may be any number of processes that can take the form of any process/application that is executable by a controller. Additionally, while the low priority process is illustrated as accessing a local database, alternate embodiments have other priority processes accessing the local database. The resource locking token (200) may take the form of a binary semaphore or some other type of token. In one embodiment, the token (200) is controlled by the operating system. The operating system determines the priority of each process (201, 203, and 205) and passes the token to a particular process based on that priority. The higher priority processes receive the token before the lower priority processes. Once a particular process has the token, other processes are locked out from accessing the resource. When the process is finished with the resource, the token is passed back to the operating system in order to be passed to another process. The token passing may be accomplished in various ways. In one embodiment, the operating system assigns a portion (e.g., a bit) of a memory cache to each process for one particular resource. When the bit for a particular process is set, that process now has access to the resource to the exclusion of the other processes. Once that bit has been reset and the bit for another process has been set, the token has been passed to that process and it now has exclusive use of the resource. This token passing process is for illustration purposes only. Alternate embodiments accomplish the token passing in other ways. In the subsequently discussed embodiment, the resource sharing and database synchronization method is initiated from the low priority process (205) of the embodiment of The token sharing method is initiated by the low priority process at state A (301) where a request to synchronize a local database with a master database is requested (303). One embodiment of a background synchronization method of the present invention is illustrated in The method then goes to state B (307) where it is determined if the background synchronization of the local database has been completed (309). If the synchronization has not been completed, the process exits and the low priority process returns the token (315) for use by another higher priority process. If the synchronization process has been completed, the process reads and processes the data from the local database (311). The type of processing performed depends on the function performed by the low priority process that is accessing the local database. In one embodiment, the low priority process is responsible for tracking error statistics of a communication link. The low priority process then accesses the shared resource that is locked (313) to other processes. If the shared resource is a data port, as discussed above, the low priority process accesses the data port (313) in order to transmit data from the local database through the modem or other device coupled to the data port. The method then returns to state A (301) where the entire method is repeated. For example, the database synchronization is requested (303), a check for synchronization is done (309), and the token is returned (315) for use by the next process. In one embodiment, the local databases start off empty and the synchronization method loads the requested objects into the requesting local database memory. In another embodiment, the local databases already have objects in memory that are overwritten by objects requested from the master database. While the subsequently described method refers to one local database, the same method may apply to each of the 1-N local databases. One local database is used for illustration purposes only. The status flags of any of the local database objects are set to �pending� (401). A request is made for synchronization of the local database with the master database (405). In one embodiment, in the request for synchronization (405), the request is to synchronize the entire local database or only a desired group of objects. For example, the group of objects to be synchronized may include only the bit error rate and the down time and not the other objects stored in either the master or local databases. In one embodiment, the objects to be synchronized are downloaded from the master database to the local database. These downloaded objects then replace the older objects in the local database. In another embodiment, the objects to be synchronized are operated on by a process that determines whether the local database objects are more recent or whether the master database objects are more recent. If the local objects are the most recent, these objects overwrite the objects in the master database. If the master database objects are more recent, the objects from the master database overwrite the older objects in the local database. If the objects to be synchronized are not already present in the other database, they are written to that database. The local database, in one embodiment, requests synchronization using a request command from a card controller that is transmitted over a data bus. Such a configuration is discussed subsequently with reference to As the objects are transferred to the local database, their associated status flags are changed (407) to �ready� or some equivalent indication. The status flag of the last object in the group of objects to be synchronized is checked (410). If the status flag is �pending� (415), read access to the local database is blocked (416) so that objects that have not been synchronized cannot be read and processed. In one embodiment, this blocking is accomplished by a memory read subroutine not permitting access until the last object has a �ready� flag. Other techniques, that are well known in the art, may be used to block access to the memory until the database is synchronized. The present invention is not limited to any one technique. The method then returns (425) to the database access method that initiated the request for synchronization. In an alternate embodiment, each of the status flags of each synchronized object is checked. If any of the objects to be synchronized still has a �pending� flag set, access to the local database is blocked and the method returns to the initiating method. With the synchronization method of the present invention, a controller running various processes is not tied up waiting for the synchronization method to be completed only periodic checking is required to determine the status of the synchronization. If the status flag of the last object, or all the objects, in the group is checked and found to be set to �ready� (415), the objects in the local database are read and processed as required (420). This system includes a management card (500) that is responsible for controlling the system of the present invention. In one embodiment, the master database is maintained on the management card (500) or other type of controller card. One embodiment of the management card (500) is described subsequently with reference to Line cards 1-N (501-503) are coupled to the management card (500) through a multi-drop bus or backplane (504). In the communication system embodiment, line cards 1-N (501-503) are modems that support data services that are provided to customers. The local databases of the present invention are maintained on the line cards. In one embodiment, the resource sharing and database synchronization is performed on each line card (501-503). Each line card (501-503) is coupled to a communication link (521-523 respectively). The communication link may be a T1 line, a DSL line, a wireless link, or any other form of communication link depending on the type of data services provided by each line card. The communication system of the present invention is not limited to any one form of communication link. The communication links (521-523) couple their respective line card to a remote line card (505-507) that is located at the customer's site. Remote line cards 1-N (505-507) are the same type of modem as the respective line card to which it is coupled. In other words, if line card 1 (501) is a DSL modem, remote terminal 1 (505) is a DSL modem. In one embodiment, a remote user computer (510) is coupled to the remote line cards (505-507). The remote user computer (510) can then communicate over its communication link (521) with the network to which the system is connected. In one embodiment, a local user computer (515) is coupled to one or more of line cards 1-N (501-503). The local user computer (515) enables a computer operator to interface with the system for maintenance and operation of the system. Both a local user computer (515) and a remote user computer (510) can access their respective local databases to which they are coupled. The local and remote user computers can then initiate the background synchronization method of the present invention. The system of the present invention is not limited to a communication system as illustrated in In one embodiment, the controller (601) of the management card executes an embodiment of the resource sharing and database synchronization method. In such an embodiment, the management card controller (601) is responsible for passing the token that controls access to the shared resource. Memory (603) is coupled to the controller (601) to store data for use by the controller (601). The memory (603) might be any of the types described above as the database memory. In this embodiment, the memory (603) stores the master database of the present invention. Input/Output (I/O) connections (605) enable the controller (601) to communicate with the other cards of the system. The I/O connections (605) might include circuit card contacts such as connectors, circuit card fingers, or other types of connections. In one embodiment, the local controller (701) is responsible for passing the token that controls access to the shared resource. Memory (703) is coupled to the controller (701) to store data for use by the controller (701). The memory (703) might be any of the types described above as the database memory. In this embodiment, the memory (703) stores the local database(s) of the present invention. Input/Output (I/O) connections (705) enable the line card to communicate with the management card as well as other cards of the system. In one embodiment, the I/O connections (705) include circuit card contacts such as connectors, circuit card fingers, or other types of connections. Modem function circuitry (707) provides the line card with the ability to communicate over communication links with other modems. Modem operation is well known in the art and is not discussed further. The modem function circuitry (707) is coupled to the controller (701) and enables the local communication system to communicate over the communication links with remote modems that are coupled to computers. In summary, the embodiments of the resource sharing and database synchronization of the present invention provide a system that has a shared resource with the ability to minimize the time that higher priority processes are locked out of the resource. Therefore, high priority and critical processes/applications are less likely to become suspended. Additionally, since system resources can be shared, system efficiency increases. Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein. Patent Citations
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Maxim Mostovoy
Maxim Mostovoy is a condensed matter theorist with interests in magnetism, multiferroics, and strongly correlated systems. He received his Ph.D. in 1998 from the University of Groningen. He worked at the Max Planck Institute for Solid State Research (Stuttgart), was appointed to the Mercator professorship at the University of Cologne and held visiting positions at the Hahn-Meitner Institute (Berlin) and RIKEN (Wako, Saitama). He is currently an associate professor at the Zernike Institute for Advanced Materials (Groningen).
Helicoidal magnetic order induces a record high electrical polarization.


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What does TPS mean in Unit Measures?
This page is about the meanings of the acronym/abbreviation/shorthand TPS in the Miscellaneous field in general and in the Unit Measures terminology in particular.
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"TPS." Abbreviations.com. STANDS4 LLC, 2015. Web. 2 Mar. 2015. <http://www.abbreviations.com/term/119652>.
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Film Review: Cowboys and Aliens (2011)
SYNOPSIS: A spaceship arrives in Arizona, 1873, to take over the Earth, starting with the Wild West region. A posse of cowboys are all that stand in their way. REVIEW: The buzz on "Cowboys & Aliens" seemed to herald it as THE Summer blockbuster to see this year. After all how could it go wrong? Daniel Craig (007) and Harrison Ford (Indiana Bones..I mean Jones) playing the two lead roles. A glut of great character … Continue reading


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I bought a brand new trek 7.1 hybrid bike one week ago, its perfect thanks god but i have only my concern, as i noticed a slight movemt ups and downs of the cassette when rotating idle in the air, and for sire it happens when i ride, what could be the cause for this? Is this danger to ride with?
Bearing in mind that the movement is about 1 melimeter only not more than that


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Lyrics Depot is your source of lyrics to Running the Loping by Smog. Please check back for more Smog lyrics. |
Running the Loping LyricsArtist: SmogAlbum: A River Ain't Too Much to Love Laughing at things i think of Getting off on the pornography of my past Lighting matches and dropping them Into a wet glass It's summer now and it's hot And the sweat pours out And the air is the same as my body And i breathe my body inside out With sunlight around my skin turns brown And you wouldn't know me from your pa Or Adam or Allah But I haven't changed No I haven't changed Day is all that resolves All we need is here on earth About every other day Scratchmarks on my knees since I've been running The bramble lee When I'd much rather be wanting to be Running the loping Peace on your hand Don't be silly But peace on my body When tired and beaten All we need is here on earth About every other day Oh to live in the country With a chicken and those other things Where the hills loping Where the dress and the hair in the river Undulating To take a wife and no paper Never again to wonder Did that rapper rape her All we need is here on earth About every other day
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IPhone 4, IOS 4 Offer Deeper Enterprise Support
While other analysts have praised improvements in iOS 4, one deficiency noted by Forrester Research analyst Ted Schadler and Jack Gold of J.Gold Associates is that IT shops are unable to automatically push policy and software updates to iPhone users, meaning users would have to click a button to receive an update, leaving the IT shop to trust users to do so. Gold has called that deficiency a "barrier to iOS adoption" for banks and regulated companies.
The new iOS 4 software will ship on iPhone 4 units available June 24 but can also be added for free to the iPhone 3GS and 3G on June 21, Jobs said, expanding potential enterprise benefits to more users with older iPhones. The 3G phones will not be able to use the iOS 4's multitasking functionality because of hardware constraints, Jobs added.
Multitasking is a big enterprise plus, according to Gartner. Apple told Gartner analysts that multitasking will enable background processing functions such as playing audio while surfing the Web or playing a game. But background processing also means users can get a voice-over-IP call and have a conversation while using another application. IOS 4 also provides a battery-efficient way to monitor locations when users move between cell towers that Apple has called a "great way for social networking apps to keep track of users and their friends' locations."
Other background functions that could matter to enterprises include push notifications (to receive alerts from remote servers even when an app isn't running); local notifications (an app can now alert users of scheduled events and alarms in the background without any servers); task finishing (if an app is in midtask when the user leaves it, it can now keep running to finish the task); and fast app switching (a developer can build in functions to allow users to leave an app and come right back to where they left off, without a need to reload the app).
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