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Water Events
Population, Health, and Environment Approaches in Tanzania
July 19, 2011 // 3:00pm — 5:00pm
Environmental Change and Security Program
Tanzania's rich marine and terrestrial biodiversity makes it one of East Africa's environmental gems, but the country is predicted to be the fifth most populous country by 2100, and its rapid population growth threatens to outstrip its ability to provide for its citizens. Two population, health, and environment (PHE) projects currently operating in Tanzania seek to meet people's needs for income and healthcare, while protecting the environment that supports them.
Yemen Beyond the Headlines: Population, Health, Natural Resources, and Institutions
May 18, 2011 // 8:30am — 3:30pm
Environmental Change and Security Program
"Ultimately, whether Yemen is able to achieve its goals for social and economic development, will, to a large extent, depend on its future population growth and size," said Gary Cook, senior health advisor at the U.S. Agency for International Development, in his opening address at an all-day conference on the role of population, health, natural resources, and institutions in Yemen's political crisis.
Book Launch: Human Population: Its Influences on Biodiversity
May 11, 2011 // 3:00pm — 5:00pm
Environmental Change and Security Program
Measurements of "human population density and growth can be used to identify changes in the viability of native species, and more directly, in changes in ecological systems or habitat quality," said Richard Cincotta, consultant at the Environmental Change and Security Program and demographer-in-residence at the Stimson Center, speaking at the book launch of Human Population: Its Influence on Biological Diversity.
Energy Demand vs. Water Scarcity: The Dilemma Facing the U.S. and China
May 06, 2011 // 12:00pm — 1:15pm
Wilson Center on the Hill
The confrontation between growth, water, and energy is readily visible in both the U.S. and China and is virtually certain to grow over the next decade. Leading experts examined the energy-water "choke points" that are tightening around the world's two largest economies and how the dilemma affects energy and environmental policy choices facing the U.S. Congress.
Hydropower, Pipelines, and Petroleum: The U.S.-Canada Energy Relationship [Duke University, Durham, North Carolina]
April 13, 2011 // 8:30am — 3:00pm
Canada Institute
The Canada Institute co-sponsored a conference held at Duke University that assessed ways to balance North American energy, security, and environmental goals.
Integrating Development: A Livelihood Approach to Population, Health, and Environment Programs
April 07, 2011 // 3:00pm — 5:00pm
Environmental Change and Security Program
Rural communities in developing countries understand that high population growth rates, poor health, and environmental degradation are connected, said Population Action International's Roger-Mark De Souza. An integrated approach to development – one that combines population, health, and environment (PHE) programs – is a "cost-effective intervention that we can do very easily, that responds to community needs, that will have a huge impact that's felt within a short period of time," said De Souza, who was joined by three other experts to discuss how to improve current efforts to expand the PHE approach.
Managing the Planet's Freshwater
February 23, 2011 // 2:00pm — 4:00pm
Brazil Institute
Karin M. Krchnak, Director, International Water Policy, The Nature Conservancy; Dann Sklarew, Sustainability Fellow, George Mason University; Moderator: Paulo Sotero, Director, Brazil Institute
Changing Glaciers and Hydrology in Asia: Developing a Blueprint for Addressing Glacier Melt in the Region
November 16, 2010 // 9:00am — 11:00am
Environmental Change and Security Program
A new report highlights the complexity of the issues surrounding glacier melt in Asia, and the critical need to prepare today for future environmental changes.
Asia's Growing Crisis of Floods and Droughts
October 19, 2010 // 12:00pm — 2:00pm
China Environment Forum
The Greater Himalayas, whose glaciers supply seasonal water flows to some 40 percent of the world's population, are a climate change hot spot. Panelists at this event co-sponsored by Asia Society and China Environment Forum address the many threats that melting glaciers pose to Asia.
A New Approach to Social Policy: Measuring Access to Opportunity
September 30, 2010 // 12:30pm — 2:30pm
Latin American Program
This seminar explored the Human Opportunity Index, designed to measure difference in access within and among countries of the region.


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Shelled By Tank This iraqi insurgent gets the hell blown out out of him by a tank. 1/1/2005 12:00:00 AM 403,511 684
Iraq Incoming Mortars Insurgents are firing mortars at US troops in iraq. 3/4/2005 12:00:00 AM 232,419 443
Terrorist Mortar Malfunction These asshats are launching mortars when thankfully one malfunctions and... 10/31/2008 12:00:00 AM 92,112 164
Effects of Shell Shock Just some of the effects of shell shock from the world war. 1/11/2008 12:00:00 AM 81,270 30
Defective Mortar Shell A defective mortar shell doesn't fire properly and sends these soldiers... 11/22/2013 12:57:07 PM 16,629 24
Scramble Hard Boiled Eggs Inside Their Shell I wonder how many of you will break the egg inside your shirt? 3/30/2013 11:04:08 AM 15,516 39
A Tank Shell With Your Name On It A rebel fighter watches as a tank rolls up and fires a shell directly at... 10/19/2014 10:30:02 AM 11,993 14
Frightening Footage of Ukraine Getting Shelled By Russian Rebels It can be pretty scary when rockets start raining down all around you. 2/11/2015 12:23:44 PM 11,910 24
Idiot Lights Mortar Off His Junk He sets his balls on fire as a result. 8/14/2014 10:10:57 AM 10,443 33

subset: commoncrawl


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License & Identifications
A medical license is required for a doctor to practice medicine in a particular state. Requirements vary by state but most require, at a minimum, post-graduate training in the doctor's specific specialty. An NPI number is a national identifier unique to an individual health care provider and is managed by the Center for Medicare & Medicaid Services (CMS).
Learn more about Dr. Louise Bozzetti:
View the full profile to get information on:
- Qualifications
- What's important to you
View full profile
Specialties & Research
Dr. Louise Bozzetti, MD is board certified in Psychiatry.
Similar doctors nearby
- Additional Information
- Dr. Louise Paul Bozzetti MD is a male Psychiatrist and practices in Psychiatry.
- Where does Dr. Louise P. Bozzetti practice?
- Dr. Louise Bozzetti has 1 office location.
Dr. Louise Bozzetti practices Psychiatry near Riverside, CA.
See Riverside Psychiatrists.


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A couple from my buddies bachelor party this past weekend. It was a awesome time and the little obv was throwing a killer wave.
A couple doubles.
Results 1 to 10 of 227
Thread: July 2013 Picture Thread
Threaded View
07-15-2013, 10:13 AM #11-Mark
14 Mojo - Waiting patiently for my build date.
02 Mobius LSV ---- Sold and always will be remembered as the one that started it all.
"Hey you only live once"


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Browse All Departments
ST Racing Concepts Transmission/Center Skid (Silver)
With your purchase, receive at no cost:
This is the optional silver ST Racing Concepts Transmission/Center Skid for the Traxxas Revo monster truck. Made from high quality aluminum and CNC machined for weight reduction, our Center Transmission Cover/Skid plate protects the center transmission while the extended cover piece covers and protects the center rear driveshaft.
This product was added to our catalog on February 29, 2008.


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CheckoutSubtotal (USD):
does not include shipping and tax
30-day limited warranty
List Price $120.95, Orig.Price $99.95 Save $15.00 (15%)
Want it delivered 03-03-2015?
Order it in the next 0 hr and 20 min
and choose Next Day Air Morning at checkout.
Create an online reviewand share your thoughts with other customers
Things I liked:Excellent replica of my 9mm CZ 75 p-07. Excellent service by PyramidAir. Things I would have changed:Nothing Things I liked:Nice weight feels and looks like the real deal. Things I would have changed:Nothing What others should know:About 80 to 100 shoots befor you change the c02. Things I liked:Appearance and weight of the real thing. Blowback. Easy on CO2. I got sixty-six accurate shots with one cartridge. Reasonably good trigger pull. Things I would have changed:Make the rear sight fully adjustable. I wedged a small rectangle piece of .040 thick styrene under the rear sight to correct for a low point of impact. What others should know:This gun is very accurate but I only tested it from a rest at five to seven yards. It's lots of fun and great practice for the real thing. Show Other ReviewsCreate an online review and share your thoughts with other customers
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Compatible with ASG CZ 75 P-07 Duty CO2 Pistol |


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Duro Olowu For JCPenney Collection | Pictures
Shop It Now — Duro Olowu's Printastic JCPenney Collection
Our Spring shopping itch has taken a turn for the worse thanks to Duro Olowu's newly debuted collection for JCPenney. With bright statement prints and bold colors aplenty, the designer — whose wares have been worn by First Lady Michelle Obama — created a collection filled with covetable (and affordable!) pieces to add to your Spring arsenal. "I wanted to create looks that were based on my ideas of American classics, all with a global flair," Olowu told us. "I think America already has a tradition of classics — the perfect pants, the perfect trench coat — and I wanted to give it that extra oomph." The extensive lineup features clothes, shoes, accessories, and housewares all priced under $100. It doesn't get any better than that, folks. Peruse the lookbook in the slideshow, then click over to jcp and get shopping.
- You're going to love these brand-new Kanye outfits — HuffPost Style
- Lupita Nyong'o's 15 greatest style moments will blow you away — Lucky
- Emily Current and Meritt Elliott created a denim destination — Who What Wear
- Wait — SkyMall may not be gone forever — The Cut
- The surprising new alternative to leather — InStyle
- Is Björk going to top our list of style icons this year? — Racked
- You need this Louis Vuitton look in your closet stat — SheFinds
- Will people still choose Gucci with Alessandro Michele's takeover? — Style.com
- How to pack light for the chicest city in the world — Man Repeller


text: Unfortunately, I have a 40 mile trek to work, and usually at least 1 stop on the way, hence the reason I holster. I typically use an IWB, but for the trip I picked up a paddle OWB for the ease of being able to remove when I get to work. Just got to remember to do it when I get there. I already pulled both my office key and my safe key off my key ring so I can follow what NC Bullseye said earlier.


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Lunch & Dinner dailyFeatures
- Parking lot
- Dress code: Casual
- Full bar
* Click here for rating key
Li Wah Restaurant Review: Though many AsiaTown restaurants offer dim sum, Li Wah is one of the best (and it's a good place for dim sum rookies, too). In addition to an array of dim sum (our faves are the shrimp dumplings, chive cakes, sticky rice and the steamed barbecue pork buns), Li Wah also offers more elaborate mains. We like going with a large group --- mostly because there are too many dishes on the menu that we don't want to miss. If you're not in the mood for dim sum, we suggest the house special lo mein or roasted duck. For dessert, try the custard tarts: warm miniature pies with a flaky crust and eggy center. |
Check out the 2014 edition of GAYOT's Annual Restaurant Issue, which features the Top 40 Restaurants in the U.S., Rising Chefs and more.


text: Got internet and a new petSo my internet is finally up and I can now show you guys my new pet. I adopted a California Kingsnake. I don't have a gander yet but I'm trying to pick out female and male names until I can get an appointment to have it sexed. Any suggestions would be awesome. Anyway it's VERY tame. Even when it's flicking it's tail (What they do as a warning to stay away) I can scoop it up and carry all over the house or even outside. Not to mention this is such a beautiful snake. I adore the fact my snake has blotches rather the typical bands.Some cool facts, This snake is named because it eats other snakes. Some owners even feed these guys rattlesnakes rather rats or mice. This being said the kingsnake is immune to most snake venom. They don't ever get very big as far as snakes go though.


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We found 2 sites within 24 miles of Rookhope In Weardale with 1 bookable
Middleton-in-Teesdale, Co. Durham, England Show on map |
Microlodge | 5 x | From £99/€125.62/AU$181.85/$159.34 per night |
Durham, Co. Durham, England Show on map |
Want to see more? We're only showing the sites that are bookable on Pitchup.com.
Show campsites and holiday parks that aren't bookable through Pitchup.com...


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VIEWS: 16 PAGES: 1 CATEGORY: Business POSTED ON: 11/14/2010
Ohio Employee Patent Ownership document sample
VA-WOC APPOINTEE INTELLECTUAL PROPERTY AGREEMENT This agreement is made between _____________________ and the Department of Veterans Affairs (VA) in consideration of my without compensation (WOC) appointment by the VA Medical Center at the Cincinnati, Ohio, (VAMC) and performing VA-Approved Research (as defined below) utilizing VA resources. This agreement is not intended to be executed by WOC appointees exclusively performing clinical services, attending services, or educational activities at the VAMC. 1. I hold a WOC appointment at the VAMC for the purpose of performing research projects, evaluated and approved by the VA Research and Development Committee (VA-Approved Research), at that VAMC. 2. By signing this agreement, I understand that, except as provided herein, I am adding no employment obligations to the VA beyond those created when I executed the WOC appointment. 3. I have read and understand the VHA Intellectual Property Handbook 1200.18 (Handbook) [available at http://vaww1.va.gov/vhapublications/ViewPublication.asp?pub_ID=403 ], which provides guidance and instruction regarding invention disclosures, patenting and the transfer of new scientific discoveries. 4. Notwithstanding that I am an employee or appointee at _________________________, I will disclose to VA any invention that I make while acting within my VA-WOC appointment in the performance of VA-Approved Research utilizing VA resources at the VAMC or in a VA-approved space. 5. I understand that the VA Office of General Counsel (OGC) will review the invention disclosure and will decide whether VA can and will assert an ownership interest. Every effort will be made to issue a decision within 40 days of receipt of a complete file. OGC will base its decision on whether VA has made a significant contribution to the invention, to include my use of VA facilities, VA equipment, VA materials, VA supplies, and VA personnel, as well as assessment of the potential of the invention. 6. IF VA asserts an ownership interest based on my inventive contribution, then, subject to Paragraph 7 below, I agree to assign certain ownership rights I may have in such invention to the VA. I agree to cooperate with VA, when requested, in drafting the patent application(s) for such invention and will thereafter sign any documents, recognizing VA's ownership, as required by the U.S. Patent and Trademark Office at the time the patent application is filed. 7. VA recognizes that I am employed or appointed at the entity named in paragraph 4 and have obligations to disclose and assign certain invention rights to it. If that entity asserts an ownership interest, VA will cooperate with it to manage the development of the invention as appropriate. 8. If a Cooperative Technology Administration Agreement (CTAA) exists between the VA and the mentioned entity in paragraph 4, this Agreement will be implemented in accordance with the provisions of that CTAA. ______________________ _________________________________________________________ Date Signature _________________________________________________________ Date ACOS for Research


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Pacific Rim - 15 Minute Making Of Special FeaturetteReported by Outsiders - 02:43 PM 2013.07.10
Check out a nearly 15-minute Making-Of Special Featurette for Guillermo del Toro's rock-em, sock-em clash of the giants spectacular, "Pacific Rim" starring Charlie Hunnam, Idris Elba, Rinko Kikuchi, Charlie Day, and Ron Perlman. This latest special combines some of the footage from the recently released vignettes, plus a whole lot more, to give fans an inside look on what it took to create del Toro's giant-sized monsters on the big screen. "Pacific Rim" will have special advanced screening beginning on Thursday evening, and shall open wide on Friday. When legions of monstrous creatures, known as Kaiju, started rising from the sea, a war began that would take millions of lives and consume humanity's resources for years on end. To combat the giant Kaiju, a special type of weapon was devised: massive robots, called Jaegers, which are controlled simultaneously by two pilots whose minds are locked in a neural bridge. But even the Jaegers are proving nearly defenseless in the face of the relentless Kaiju. On the verge of defeat, the forces defending mankind have no choice but to turn to two unlikely heroes--a washed up former pilot (Charlie Hunnam) and an untested trainee (Rinko Kikuchi)--who are teamed to drive a legendary but seemingly obsolete Jaeger from the past. Together, they stand as mankind's last hope against the mounting apocalypse. Pacific Rim stars Charlie Hunnam, Idris Elba, Rinko Kikuchi, Charlie Day, Ron Perlman, Max Martini, Robert Kazinsky, Clifton Collins, Jr., Burn Gorman, Larry Joe Campbell, Diego Klattenhoff, Brad William Henke Release: July 12th, 2013
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UPDATE: Troy Topnik, ActiveState's Technical Communications Manager, has provided s step-by-step guide to setting up your own Stackato Cluster on Amazon EC2 in a recent blog
ActiveState is pleased to offer Stackato's secure multi-tenancy capabilities for those of you deploying to the HP Cloud.
The ActivePython AMI comes with a demonstration Django app that runs with the MySQL database engine by default. Since a lot of people prefer PostgreSQL, we thought we'd demonstrate how to install the software and change the configuration.
Python on the Cloud: Best Practices for Application Deployment on the Cloud
Date: Wednesday, March 16, 2011 Time: 11 am PST/ 2 pm EST
Take advantage of Amazon's Free Usage Tier with our new 10G ActivePython Ubuntu AMI


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Hamilton Island Triathlon
This event has already taken place | |
DATE: | 16 Nov 2013 |
TYPE: | Triathlon |
LOCATION: | Hamilton Island, QLD |
WEBSITE: | Visit site |
Perfectly situated on the edge of the Great Barrier Reef, amongst Queensland's 74 Whitsunday Islands, Hamilton Island provides an idyllic backdrop for the Fujifilm Hamilton Island Triathlon. The undulating landscape of Hamilton Island's interior, of which 70% is preserved, and surrounding turquoise waters offer the perfect setting for the event's competitive 750 metre swim in Catseye Bay, a 20km cycle around the southern part of Hamilton Island encompassing the airport runway and a 5km run around the marina and resort sides of Hamilton Island. |
Have you found an error with the information for this event? Please let us know.


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Our Holly Days is another one of our beloved Pearistas. Holly decided to create a DIY Elf-ing Treat using Pear Tree's Christmas notelettes. We love homemade Christmas gift ideas and we wanted to share this one with our readers. Enjoy!
J & I have the sweetest neighbors. They are always bringing over toys for the boys to play with & sneaking them Squeez-It's on hot days. Sometimes they bring their cat out to let the boys pet her & they always stop to listen to their stories.
I think elf-ing your neighbors is such a sweet idea & it's a tradition that J & I decided to start with the kids this year. I had some extra apple butter from the batch I made, so we decided to use it for the neighbors' elf treat. And Pear Tree's sweet new Christmas Notelettes & Christmas gift tags/personalized stickers are perfect for elf-ing!
Isn't this just the sweetest little thing? Anything that is miniature is automatically 10x cuter. Besides, homemade apple butter. I went ahead & brushed off both my mom win & awesome neighbor shoulders for this one.
Clearly, I need a chalkboard intervention, because I chose these chalkboard Christmas Notelettes for our elf gifts. And I loved the woodsy feel of these Christmas gift tag stickers. I know the point of elfing is to be anonymous, but we live in a super rural town & we didn't want to skeev people out, so we added our family name with both the stickers & Notelettes.
I wrote a quick little note on the inside about some ways to enjoy apple butter & thanking them for being, "sweet," neighbors. Get it? Eh? EH?!?!? BECAUSE APPLE BUTTER IS SWEET, YOU GUYS!!!
I put the burlap on top of the lid & had J screw the cap on because my pregnant hands were not cooperating with me. Then I stuck our personalized sticker on top of the burlap, making sure the edges fell underneath the lid for extra security. I strung the ornament onto the raffia & then wrapped it around the lid, tied it into a knot & voila! Santa should hire me.
Lastly, I printed out the elf instructions/sign so my neighbors didn't think I was some kind of holiday obsessed whackadoo could play along if they decided to.
The kids all marched the elf gift over to our neighbors' house while they were away at the store. They came home an hour or so later & thanked us for the sweet surprise. Collin was very proud of the, "pwesent," he gave to them.I really enjoyed our experience with Pear Tree & can't wait to share our Christmas Cards with you guys when we get them! They have some of the most adorable little designs & ideas.
Homemade Christmas gift ideas can be fun for all the family to enjoy. Read Holly's full post and all the DIY instructions at www.ourhollydays.com.
Latest posts by Dani (see all)
- Our Most Unique Graduation Announcement Ideas - February 25, 2015
- Our 5 Most Popular Baby Announcement Ideas - February 23, 2015
- Unique Designs for Girl Dresses - February 21, 2015


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US 6941530 B2 Abstract A method of cross-mapping integrated circuit ("IC") elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.
Claims(11) 1. A method for determining probe points from a physical layout of an integrated circuit ("IC") having multiple layers of material representing the physical layout of the IC, comprising:
(a) retrieving a plurality of layers of said IC from the layout;
(b) performing computational operations on the plurality of layers to produce artificial locator cells that are not physically present in the IC and which have coordinates useable in probing; and
(c) perturbing a logic state of the circuitry located at the coordinates of the artificial locator cells using an optical probe.
2. The method of
3. The method of
the physical layout includes elements of a reference library; and
said step of performing computational operations on the plurality of layers to produce said artificial locator cells operates to place at least one artificial locator cell within at least one element of the reference library.
4. The method of
5. The method of
6. The method of
7. A probing apparatus used in testing ICs, comprising:
a processor;
a monitor coupled to said processor;
a storage device coupled to said processor;
a probe controllable by said processor;
memory coupled to said processor and containing software that positions the probe to a coordinate of an IC using coordinate information from a correlation list, wherein the correlation list comprises coordinates of artificial locator cells that are not physically present in the IC, and the correlation list also contains the corresponding connection information of the artificial locator cells from a netlist; and
the probe operable to perturb a logic state of circuitry a point located at the coordinates.
8. The apparatus of
9. A computer readable storage medium for storing an executable set of software instructions that are executable by a processor, said software instructions being operable to position a probe to a desired probe location on an IC, said software comprising:
(a) means for processing a physical layout representing the IC into a plurality of layers;
(b) means for performing computational operations on the plurality of layers, wherein the computational operations produce at least one artificial locator cell not physically present in the IC and having coordinates used in probing;
(c) means for correlating the artificial locator cell's location to the desired probe point, comprising generating a correlation list, wherein the correlation list maps net names to possible probe locations; and
(d) means for reading a net name and determining from a correlation list the desired probe location; and
(e) means for perturbing a logic state of circuitry a point located at the coordinates.
10. The computer readable storage medium of
11. The computer readable storage medium of
the physical layout of (a) comprises elements of a reference library; and
said means for performing computational operations on the plurality of layers of (b) operates to place at least one artificial locator cell within at least one element of the reference library.
Description Not applicable. Not applicable. 1. Field of the Invention The present invention generally relates to integrated circuit design. More particularly, the invention relates to techniques for cross-mapping integrated circuit design formats. 2. Background Information The ubiquitous presence of integrated circuits ("ICs") in almost every electronic device is testament to their importance in today's society. An integral part of producing ICs is "failure analysis," which is the determination of why product failure is occurring. For example, if an IC has a current leakage path on an input/output pin, the pin may be deemed defective, but the actual root cause of the leakage current may still be unknown. Furthermore, it can be extremely difficult to determine exactly what is causing the defective IC to fail, especially when the IC has been packaged. IC technology trends only exacerbate this problem, as the number of transistors contained in each successive generation of ICs doubles approximately every eighteen months and more routing layers are required to connect tightly packed circuit elements. Methods for determining the root cause of the defective ICs may involve many levels of abstraction. For example, testing a packaged IC would entail high level of abstraction, whereas testing different points on the surface of the IC would entail a more detailed level of abstraction. Thus, the particular analysis used to determine the root cause of the problem is commensurate with the nature of the failure since some problems may be determined by testing the packaged IC, and other problems would require testing at the surface of the IC. The basic functional testing of a packaged IC may be as simple as applying a voltage to the power pins, observing the level of current drawn by the packaged IC and checking that the current falls within specified limits. On the other hand, it may be necessary to test the operation of a specific circuit element (e.g., a single transistor) while the IC is operating, which, can be quite cumbersome when the IC is packaged in a "flip-chip" package because physical access to desired points on the IC via traditional probes is not possible. Referring now to However, packaging methods exist that orient the IC with the frontside 10A (which contains the circuitry) facing down. This is called "flip-chip" packaging. One technique used in testing specific circuit elements that are not physically accessible with traditional probes uses an optical microscope/probe such as that described in, "Novel Failure Analysis Techniques Using Photon Probing With a Scanning Optical Microscope," by E. I. Cole Jr. et al., which is incorporated herein by reference. In general this technique uses an optical probe that produces infrared light to perturb the state of individual circuit elements (i.e., altering a transistor's state from "on" to "off," or vice versa) without actually making physical contact with the frontside of the IC. In order to accommodate the wavelengths of light used in the optical probe, the probe is directly applied to the backside of the IC, which, in a flip-chip arrangement, requires that the top of the flip-chip package be removed so as to expose the backside of the IC 10 to the light from the optical probe. Nevertheless, although the ability to probe any desired point is satisfied using an optical microscope/probe, finding the desired point in the IC to direct the probe to can still be like finding a needle in a haystack because physical access to the frontside of the IC is not available for viewing and navigating the optical probe. In addition, although the optical probe is capable of producing an image of the IC through the backside, often this image is not detailed enough to use in navigating the IC while looking for the desired probe point. This problem is only exacerbated by the millions of devices integrated in today's ICs, and thus, navigating the optical probe from an imprecise image can make it difficult to locate and probe the desired point. In order to effectively use the optical probe, the desired point that needs to be perturbed is first found on the computer-automated drawing ("CAD") representation of the IC. This CAD representation of the IC depicts the arrangement of the various metal and polysilicon materials used in actually building the IC in the fabrication facilities (or "fabs"), and is a reproduction of what is seen when viewing the IC through a microscope. Therefore the CAD representation serves as a good "road map" for finding a desired point on the actual IC that is being tested. For example, the actual fabricated IC can be on the order of 9 mm2, while the CAD representation can be printed as large as desired (e.g., 2 m2). Further, the CAD representation is computer based making it easier to track the connectivity of electrical devices in determining the point of interest and generate the coordinates of that point. However, correlating between the point of interest on the CAD representation or "road map" and the actual IC in a non-flip-chip arrangement can be difficult because of the density of the electrical devices, and can be even more difficult in a flip-chip packaging arrangement because of the imprecise image obtained from the optical probe as described above. In addition to encountering problems, With optical probing arrangements, navigating through the various integrated structures in an IC using other probing methods can be problematic also. For example, invasive probing techniques using fine probing needles (e.g., on the order of 1 μm) may not be able to probe down to desired probe points on the IC because of interference from adjacent integrated structures, such as metal routing layers. This can be especially problematic in high-density areas of the IC, and becomes more problematic with each successive version of ICs as more routing layers are used. Thus, a need exists for an effective mechanism to direct any probe to a desired point in on an IC with minimal interference from adjacent structures. The problems noted above in large part are addressed by using "artificial locator cells" to cross-map the coordinates from the layout view of the IC and provide probe locations with minimal interference from adjacent structures. An artificial locator cell refers to a cell that is deliberately placed into the CAD representation, but is not used in fabricating the IC. In one embodiment the different layers of the layout have different computational functions performed on them in order to furnish possible probe points. For example, the polysilicon layer and the diffusion layer may have the NAND function performed on them so that the result generates polygons that represent the drain and source regions of MOSFETs. Alternatively, the polysilicon and diffusion layers may have mathematical operations performed on them such that the coordinates of where the two layers abut are revealed for probing. Nets used to interconnect circuit elements (e.g., logic gates, transistors, resistors, capacitors, etc.) of the IC could then be determined by examining the connections of these drain and source regions, and disregarding regions which are connected to power and ground rails. The coordinates of the generated polygons would then comprise points of interest to be used when probing a failing device. These coordinates may be saved in a file so that a probing tool may navigate to the desired coordinates more effectively. Preferably, the process of generating the artificial locator cells that correlate to IC locations is accomplished using software. In one embodiment, the computational operations are performed on the highest level layout of the IC after the circuit elements have been instantiated from a reference library. Accordingly, the artificial locator cells are then placed in this highest level layout. Alternately, the artificial locator cells may be placed in varying degrees of layout hierarchy. As such, in another embodiment, the circuit elements contain the artificial locator cells prior to being instantiated in the highest level layout. For example, if a NAND gate is being instantiated into the higher level layout, it may already contain artificial locator cells over the regions representing the inputs and outputs of the gate. Upon instantiation into the higher level layout, the software could combine the outputs of one gate with the inputs of another gate to represent one single net that could be probed. Regardless of the method of placing the artificial locator cell into the layout, or at what level of hierarchy the locator cells exist, all of the artificial locator cells preferably are compiled into a list using software. The software may also correlate the layout and artificial locator cell coordinates in the list to a netlist containing net names. Also, the software may consolidate multiple artificial locator cell coordinates that represent the same net such that the list generated is reduced in size. A probe may then be used to perturb and/or measure a point located at these coordinates, wherein the point may be referenced by net name, and a probing apparatus determines the coordinates using the net name. Accordingly, the possible probe points indicated by the artificial locator cells preferably indicate probe points with minimal interference from adjacent structures. In another embodiment, a probing apparatus is used in testing ICs. The apparatus preferably comprises a central processor, a monitor, a storage device, a probe and software that positions the probe to a desired point using coordinate information from a correlation list. The list comprises coordinates of artificial locator cells and their corresponding connection from a netlist. Artificial locator cells are preferably determined using computational operations on a plurality of layers that are representative of the physical layout of the IC and may provide locations with minimal interference from adjacent integrated structures. The user of the apparatus would have the ability to specify the coordinates or the net name to position the apparatus to the desired point. Upon locating a point the probe may then perturb and/or measure its electrical characteristics. For a detailed description of the preferred embodiments of the invention, reference will now be made to the accompanying drawings, wherein like parts throughout the drawings are marked with the same reference numerals: Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, semiconductor companies may refer to processes, components, and sub-components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to . . . ". Also, the term "couple" or "couples" is intended to mean either a direct or indirect electrical or wireless connection. Thus, if a first electrical element couples to a second electrical element, that connection may be through a direct electrical connection, or through an indirect electrical or wireless connection via other devices and connections. The term "IC" refers to an integrated circuit fabricated upon a semiconductor substrate that has been diced. The term "device" refers to an IC that has been packaged for use on a circuit board. The "frontside" of the IC refers to the side of the IC that includes electrical devices that have been processed onto its surface through a series of fabrication steps. The "backside" of the IC refers to the side opposite the frontside and generally does not contain electrical devices. Thus, a frontside analysis technique is an analysis performed using the side of the IC that has been processed and now contains electrical devices, whereas a backside analysis technique uses the side of the IC that has not been processed to contain devices (also known as substrate side). The term "flip-chip" refers to a method of packaging ICs such that the frontside of the IC faces downward and the backside faces upward when placed into the package. The term "netlist" refers to a list of electrical circuit elements as represented by a schematic and its interconnections. The term "physical layout" or "layout" refers to a CAD image or CAD view of an integrated circuit comprising various layer, which either directly or indirectly represent mask steps in the fabrication process. The term "extraction" refers to a process where the layout is transformed from different layers of arranged polygons into a netlist of electrical circuit elements. The term "artificial locator cell" refers to a structure that is deliberately placed into the CAD representation, but is not used in fabricating the IC. The artificial locator cells may be combined to form an artificial locator layer. The artificial locator cells are formed by performing computational functions on layers in a CAD representation that are used for fabricating the IC. To the extent that any term is not specially defined in this specification, the intent is that the term is to be given its plain and ordinary meaning. A preferred embodiment of the present invention provides cross-mapping capabilities between the coordinates from a CAD representation of an IC, and coordinates of desired probe points of the actual IC by generating artificial locator cells at the coordinates of the desired point. An "artificial locator cell" refers to a structure that is deliberately placed into the CAD representation, but is not used in fabricating the IC. Accordingly, the different layers of the CAD representation have different computational functions performed on them in order to generate the artificial locator cells and thereby furnish possible probe points. The resulting polygon coordinates preferably comprise points of interest to be used when probing a failing device. These points of interest are preferably the regions of abutment of at lest two layers of the layout. Prior to delving into the preferred embodiments of the present invention, it is helpful to give a cursory review of IC design and implementation, and failure analysis techniques. A more detailed presentation of related concepts can be found in "Principles of CMOS VLSI Design," pp. 381-464, by Neil H. E. Weste et al., which is hereby incorporated by reference. IC design begins with the abstract concept of accomplishing some function, which will require certain sub-operations. For example, a digital signal processor design will require, among other things, clock generation circuitry, memory, etc. The abstract concept is transformed in the design phase to a schematic or "netlist," which may represent simple designs including several hundred transistors, or more complicated designs including millions of transistors. During the transformation of an idea to an actual netlist, the netlist is simulated and tested to verify that the abstract concept is in fact being performed by the netlist within specified goals. For example, the netlist of the digital signal processor may be simulated to ensure that clock generation circuitry delivers the proper timing signals at the appropriate time. Once the simulation is complete, a CAD representation or "layout" of the netlist is constructed using CAD-based software. In general, the layout represents the series of steps performed in a fab so as to construct integrated devices (e.g., transistors, resistors, and capacitors) on a semiconductor substrate in a hierarchical manner. Referring now to By using positive charge and negative charge transistors, basic logic functions can be implemented such that as a signal is applied to the input terminals of the transistors, they change from either conducting electricity or being "on," to not conducting electricity or being "off" For example, transistors 20A and 20B have their input terminals (called "gates") coupled together using polysilicon and forming a net labeled NETA. While the polysilicon serves many purposes, it can be thought of as a wire to conduct electricity between the gate terminal of the NMOS 20A and the PMOS 20B. When a voltage is applied to NETA, NMOS 20A and PMOS 20B react to either turn on or off in a complimentary fashion, such that when NMOS 20A is on and conducting electricity PMOS 20B is off and not conducting electricity, and vice versa. The NMOS 20A has a terminal (called the "source") that is coupled to the ground bus 24 using a metal line and a contact (where the contact facilitates the connection between the metal line and the n-diffusion region). On the other side of the gate terminal another terminal (called the "drain") of NMOS 20A is coupled to the drain terminal of the PMOS 20B. The drain terminals of NMOS 20A and PMOS 20B are shown coupled together using a metal line (and a contact to make connection between the diffusion regions and the metal line). This common connection between the two drain terminals is labeled NETB. A polysilicon line couples to this metal line with a contact and serves to further connect the output of inverter 20 to the input of inverter 22, or the gate terminals of NMOS 22A and PMOS 22B of inverter 22, thereby forming NETB. On the other side of the gate terminal of PMOS 20B, the source terminal of PMOS 20B is connected to the power bus 26. A processing defect is also shown in As described above, After a layout of the IC is generated all of the blocks are wired by hand and/or, by using software routing programs. At this point, two versions of the design exist, the netlist version that has been simulated and has passed the desired tests, and the physical layout version, which, due to metal wires shorting together or not making full contact with their intended connection point, may contain a myriad of connection-type errors. Manufacturers use the physical layout, and discrepancies between the physical layout and the simulated netlist can cause the manufactured part to be built differently than the netlist that has passed the desired tests, which is undesirable. Therefore, a layout-versus-schematic ("LVS") check is completed, traditionally using software, to ensure that there are no discrepancies between the physical layout and the netlist/schematic, which has been simulated. In performing a LVS check, the physical layout undergoes a conversion from a CAD view containing arranged polygons (e.g., Extraction is generally performed by taking the database representing the physical layout (e.g., After the layout is successfully extracted, the extracted version of the design is ready to be compared to the netlist by the LVS software, which may also associate the different net names from the netlist to the extracted version of the layout. As mentioned above, failure analysis may involve different levels of abstraction, with more invasive approaches used in situations where the actual defect may be elusive. For example, a failure analysis engineer may start by performing a high level test on the input/output pins of the device, where the pin may undesirably be stuck at Vdd or ground. This information often gives a general idea of where the root cause of the defective pin is located on the IC so that more detailed techniques can be employed to determine the root cause of failure. For example, invasive failure analysis approaches may be used to probe the IC with a probe needle or non-invasive optical probe techniques may be used. A preferred embodiment of the present invention provides cross-mapping capabilities between the coordinates from the CAD representation of the IC and coordinates of desired probe points of the actual IC by generating artificial locator cells at the coordinates of desired points in the extracted netlist. The artificial locator cells may represent areas with minimal interference from adjacent structures. Multiple artificial locator cells may be generated at various desired locations on the IC, where the artificial locator cells are placed into an artificial locator layer similar to other layers that are present (e.g., the polysilicon layer). Computational functions can be performed on the various layers (e.g., polysilicon and diffusion), in order to define artificial locator cells and devices for use in identifying the location of a desired point for probing. The coordinates of the polygons resulting from the computational functions performed comprise points of interest to be used when probing a failing device. For example, by performing the NAND function on the polysilicon and diffusion (both the n-diffusion and the p-diffusion) layers of the layout, the drain and source of transistors may be defined. As illustrated in Referring now to Referring now to In another embodiment, the LVS connectivity information may be used to correlate the names of the nets (e.g., NETA, NETB, and NETC) to the actual artificial locator cell designating the coordinates for probing that net, and this correlation information may be saved to a file. In this manner, the failure analysis engineer may be able to refer to specific net names for probing purposes and have the coordinates associated with those net names (which are derived from individual artificial locator cells) provided to the probe tool automatically from the file that contains the cross-mapping information. In yet another embodiment, the list of artificial locator cells referencing a node may be consolidated. For example referring to In addition, since reference libraries (including logic gates) are often used in synthesizing designs as described above, the logic gates within the library may already have artificial locator cells in them before the design is extracted. For example, when IC 10 is synthesized, it may instantiate physical layouts of logic gates that already contain artificial locator cells. Thus, in one embodiment the artificial locator cells may be included in the logic gates prior to instantiation, whereas in another embodiment, the artificial locator cells may be added at a higher level layout after the logic gates have been instantiated. Regardless of the level of hierarchy at which the artificial locator cells are applied, a compiling step is preferably performed so that the coordinates of the artificial locator cells are mapped to net names in a correlation file. Thus in probing the IC, net names may be referred to and the probing apparatus may locate the desired probe point using the correlation file. In another embodiment, as shown in By and large, cross-mapping between the CAD representation of the IC and the coordinates of desired probe points of the actual IC may be accomplished by generating artificial locator cells (preferably during the extraction and LVS check), at the coordinates of the desired points. Performing computational functions on the different layers of the CAD representation generates the artificial locator cells, which may be later formed into artificial locator layers at the highest level representation of the layout. The coordinates of the artificial locator cells may be correlated to the names of nets during the LVS check, and this correlation information may be stored in a file, which may later be used when probing. By including and correlating the net names in this manner, a probing apparatus may now locate the coordinates of the net names upon specification of a net name. The artificial locator cells may be generated on cells before they are instantiated into the layout, or the layout may have computational functions performed on it to generate the artificial locator cells. By cross-mapping probe points between the actual IC and the CAD representation, probing flip-chip packaged ICs may be tested more efficiently. The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, one of ordinary skill in the art having the benefit of this disclosure would recognize that actual extraction (as typically used in LVS operations) is not necessary for producing the artificial locator cells, and that processing the layout prior to performing the computational operations would suffice. In addition, a user may also manually insert the artificial locator cells into the layout without the aid of software. Also, the computational operations discussed above may be performed on layers other than diffusion and polysilicon, including more than two layers. In this manner, it is possible to implement an artificial locator cell over any terminal of any circuit element (e.g., nodes of resistors, transistors, capacitors, etc.) allowing any point on the IC to be probed. Furthermore, as would be familiar to one of ordinary skill in the art, the specific computational operations performed are not limited to the Boolean or mathematical functions and may be any combination of the complex algorithms serving to minimize interference from adjacent layout structures. In fact, depending on the desired probe points multiple layers may have multiple computational functions performed on them concurrently. Additionally, although this disclosure centers on CMOS devices and processes, one of ordinary skill in the art would recognize that artificial locator cells would provide useful in other technology types (e.g., Bipolar, Bi-CMOS, etc.) Also, the principles described herein may be applied to a variety of probing techniques (e.g., both invasive and non-invasive) so as to facilitate directing the probe to a desired point on an IC with minimal interference from adjacent structures. It is intended that the following claims be interpreted to embrace all such variations and modifications. Patent Citations
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