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KTM Country Inc. 3825 W.11th Ave. Eugene, OR 97402 541-688-5881
We are waiting to serve your KTM service and parts needs! We have a large stock of OEM KTM spare parts, KTM aftermarket accessories, and dozens of new KTM motorcycles in stock! We ride what we sell and our passion bleeds orange into everything we do!
Here are the bikes we currently have in stock... updated 02-20-2015
- '13 250xc-f DEMO bike. 60 hours, special EFI mapping, great bike for beginner or expert!!- $5000!!!
- '14 85sx- You CAN afford the best bike in it's class!!!! Call us! $4,300.00 OTD! Left over so you save money! Call for our nutty price!
- '15 690 Duke white- ABS Call us for a GREAT price! Such a fun machine!!!
- '15 690 Duke black ABS
- '15 1190 Adventure R- Just WOW!
- '15 1290 Super Duke R- 2 Orange beasts available now, our only 2 this year!
- '15 85sx - Please call us for our too low to print price!
- '15 250sx - You can add a "full factory" BUD exhaust pipe by HGS for an extra $350! Sweet!!!
- '15 250xc-f - Please call us for our too low to print price!
- '15 250xcf-w - Please call us for our too low to print price!
- '15 250xc-w - Very light and nimble, w/ PDS suspension, a computer, and lights.
- '15 350sx-f - The hottest motocross bike on the planet!
- '15 350xc-f - Perhaps the most popular race bike in the US!
- '15 350xcf-w - Easy to ride, and nice and quiet!
- '15 450sx-f - Massive power in a friendly package that is all about motocross! Crazy great price!
- '15 450xc-w Always a popular model in the NW!
- '15 500 EXC- For the first time in three years, we have several in stock! STREET LEGAL!


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US jury orders Palestinian groups to pay bombing victims $218.5m
A jury found two groups liable for six shootings and bombings between 2002 and 2004 in the Jerusalem area.
A jury found two groups liable for six shootings and bombings between 2002 and 2004 in the Jerusalem area.
Palestinians must liberate themselves but, against a powerful enemy, they need any help they can get.
The South African transition from apartheid is not a model for Palestinians, given the ANC government's current state.
The US has criticised the ICC's preliminary probe into war crimes allegedly committed by Israel in Gaza as "counterproductive to the cause of peace".
The United Nations has confirmed that Palestine will be a member of the International Criminal Court from April 1, heightening tensions with Israel.
A UN resolution for a Palestinian state and the end to the Israeli occupation fell short of being adopted by the Security Council.
A source in the Public Investment Corporation, a shareholder in Woolworths, says the company invests money from the Government Employees Pension Fund.
The synagogue slaughter in Jerusalem this week has introduced a tense new dimension to the conflict in the region.
While Israel expressed shock at the attack, Hamas has praised it, calling for more following the suspicious death of a Palestinian bus driver.
France follows other countries, such as Sweden and Britain who held votes this year, on whether or not to recognise Palestine as a state.
The group urged Israel to respect the rights of Palestinians, and demanded the country probe violations committed during repeated assaults on Gaza.
The latest poll reflects what appears to be an ever-diminishing appetite for a two-state solution on both sides of politics.
Sweden's new centre-left government will recognise the state of Palestine, a move that will make it the first major European country to take the step.
Reserve soldiers in Israel's surveillance unit said they won't spy on Palestinians under occupation, drawing attention to the ethics of the practice.
The Palestinian Authority has assessed the cost of rebuilding Gaza after the seven-week war with Israel, including houses, schools and industry.
Despite the ceasefire taking effect, there seems to be little incentive for both Israel and Palestine to continue peace and statehood talks.
Hamas suffered heavy military losses during its 50-day conflict with Israel, but it has still emerged with enhanced political standing, say analysts.
Israel has announced plans to expropriate 400 hectares of Palestinian land in the Bethlehem area in the south of the occupied West Bank.

subset: commoncrawl


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El33tonline Tuesday News Wrap: 8 January 2013
Written by: / / No Comments
We're not even eight days into the new year and already the world is buckling with the weight of new game announcements and hardware reveals, and today we learned about the existence of no less than two exciting games and yet another attempt to distract the course of the evolution of game technology.
Great times, for sure, and you can get up to speed on these games and announcements with a collection of news, trailers, screenshots and special features in our round-up of El33tonline headlines from today:
Generation VI: Nintendo announces full 3D Pokemon X and Y for 3DS
A taste of the future? Valve and Xi3 team up for Steam-based mini PC
The Walking Dead tops Metacritic's 'best-reviewed' list for 2012
Naruto Shippuden: Ultimate Ninja Storm 3 dated for March, action-packed trailer released
Need for Speed: Most Wanted Wii U dated for Japan, supports GamePad-only play
Tomb Raider multiplayer gameplay revealed in latest 'Final Hours' video
Take control of your fears in Dead Space 3 with Kinect – demonstration video reveals voice commands
Exciting Remember Me trailer delivers fight sequences you won't forget
What news caught your eye today?
Tags: bioshockinfinite, el33tonline, el33tonlinenewswrap, legomarvelsuperheroes, pokemonx, pokemony, rememberme, thewalkingdead, tombraider


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Lunch & Dinner dailyFeatures
- Parking lot
- Dress code: Casual
- Full bar
- Kid-friendly
- Outdoor dining
* Click here for rating key
El Rodeo Restaurant Review: Diners are drawn to El Rodeo because its Mexican fare is cheap and delivered fast. Homemade salsa and chips are complimentary and assorted fajitas and chimichangas are house favorites. There are plenty of vegetarian meals on the lengthy menu, too. |
Check out the 2014 edition of GAYOT's Annual Restaurant Issue, which features the Top 40 Restaurants in the U.S., Rising Chefs and more.


text:
Wicked Tickets
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Defy Gravity in 2015 with Wicked!
The most magical show on Broadway is on tour again in 2015, so it's never been easier to see
live at the Gerswhin Theatre or a stage closer to home! Great tickets are available for every performance on the schedule (which can be found below), so whether you're a Broadway superfan or you're just looking to catch the most talked-about show of the last decade, you're in luck. Check out the production info below to learn more about any upcoming performance, and be sure to get your
Wicked Tickets
before they're all gone!
Find Wicked Tickets:
Wicked in Atlanta
Fabulous Fox Theatre - Atlanta
Atlanta, GA (Georgia)
March 2015
Wicked in Baltimore
Hippodrome Theatre At The France-Merrick PAC
Baltimore, MD (Maryland)
April 2015
Wicked in Birmingham
BJCC Concert Hall
Birmingham, AL (Alabama)
June 2016
to July 2016
Wicked in Columbus
Ohio Theatre - Columbus
Columbus, OH (Ohio)
August 2016
to September 2016
Wicked in Dayton
Mead Theatre At Schuster Performing Arts Center
Dayton, OH (Ohio)
April 2015
to May 2015
Wicked in Denver
The Buell Theatre
Denver, CO (Colorado)
June 2015
to July 2015
Wicked in El Paso
The Plaza Theatre - El Paso
El Paso, TX (Texas)
May 2015
Wicked in Houston
Sarofim Hall - Hobby Center
Houston, TX (Texas)
July 2016
to August 2016
Wicked in Kansas City
Music Hall Kansas City
Kansas City, MO (Missouri)
October 2015
Wicked in Los Angeles
Pantages Theatre
Los Angeles, CA (California)
March 2015
Wicked in Louisville
Kentucky Center - Whitney Hall
Louisville, KY (Kentucky)
November 2015
to December 2015
Wicked in Miami
Ziff Opera House At The Adrienne Arsht Center
Miami, FL (Florida)
March 2015
Wicked in Milwaukee
Uihlein Hall Marcus Center For The Performing Arts
Milwaukee, WI (Wisconsin)
November 2015
Wicked in New York (Broadway)
Gershwin Theatre
New York, NY (New York)
March 2015
to September 2015
Wicked in Portland
Keller Auditorium
Portland, OR (Oregon)
August 2015
Wicked in Seattle
Paramount Theatre - Seattle
Seattle, WA (Washington)
July 2015
to August 2015
Wicked in Tempe
Gammage Auditorium
Tempe, AZ (Arizona)
August 2015
to October 2015


text:
Performance golf ball fitting focuses on finding the best ball for your game and lowering your score.
Titleist offers the most precise club fitting experience in the game.
Need to customize headwear, gloves, bags, or golf balls?
Track your stats. Get video tips. Set goals for your golf game.
My Hole in One
First One
Fathers Day Special
Unlucky day
My Fires Hole in One
My first hole in one
Second one just as sweet
I Just Laughed Hole in One
Finally my first hole in one
Posted: December 31, 2012
It was all over the water distance, one of those greens with an island , I was afraid I was going to lose one of my best balls, The Titleist DT Solo. I used an extra club, the ball hunted the flagstick, hit the stick and sat on top of the hole, then the wind moved the stick and the ball dropped in. I could not be sure until I went on the green and picked the ball out of the hole.
Posted: December 30, 2012
It was a day were I shot a 34 on the front of a par 72 with a bogey. I then birdie the par 5 10th and was really thinking I can challenge my low round of 65 coming to a long 214 yard par 3. I had a right to left quartering wind with the flag back left. I pulled a 3 iron feeling a stock swing will get me on the green that was fronted by water all the way to the green. I found that I had flushed the shot and it took one bounce and then it was gone for my 3rd hole in one, all being with a Titleist Golf Ball! I was thinkinking this was my day, little did I know I would go bogey, bogey,(no suprise after a hole in one)and then eagled a par 5! I finished with a strong 67 and was very happy with that! I am so happy I could share this story with you. r/ Wayne (Loyal Titleist Golf Ball Player)
Posted: December 29, 2012
Playing in our regular Friday group hit 8 iron 165 yards and he hit once and went in hole for second hole in one. I play with MB Titleist irons.
Posted: December 28, 2012
I was playing golf with a buddy of mine and a friend of his. When we got to the 7th hole it felt like I had already lost 10lbs in sweat and the wind was blowing hard right to left. I figured I would need to club up and play it out to the right and let the wind and my draw let it come back left. Stepped up and swung away and watched it do exactly what I wanted it to do, start right and come slowly back left, at that time my buddy says "thats going to be a hole in one" and 10 seconds later it lands 2 feet past the cup and spins back in. I couldn't believe I had just gotten my first hole in one.
Beautiful day in Palm Desert on North Course. Uphill par three slight wind. Ball hit 10 feet in front of hole and went in hole.


text:
Ugh. Wedgies suck. Like reverse camel toe.
I dont' care what they say about your drinking, PAz….you look fine to me.
She's like the way I describe the lady at the rub n tug to my friends. Just sexy enough to be believable, but never pretty enough to make eye contact with. In other words, I'd throw her a hundy for a handy.
Whatever happened to less is more…completely different take on things…
Her best angle. Why put up with butterface when you can have butt?
An evening gown for a daytime stroll, makes sense.
That's one hungry ass.
desperate attention seeker, thy nam is Paz.
er, name.
it looks like she has cords coming out of her butthole.
I tell ya Robin, her whole asshole was hanging out!
It looks like her ass is trying to eat the dress.
You'd look more favorably on her if you saw her fucking in Boardwalk Empire. NO ONE who doesn't totally love fucking in real life can fake it like that in movie.


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Some want to see Osama bin Laden's body, but releasing photos risks further anti-U.S. sentiment. / Associated Press
When the U.S. military released pictures of the bodies of Saddam Hussein's slain sons in 2003, it was to prove that they were dead and to stem attacks on U.S. soldiers in Iraq.
Photos of Osama bin Laden's body, however, present some thornier issues.
The Obama administration was still debating Tuesday whether to release the gruesome images of bin Laden's corpse, balancing efforts to demonstrate to the world that he was dead against the risk that the images could provoke further anti-U.S. sentiment.
But CIA Director Leon Panetta said Tuesday that a photograph would be released.
"The government, obviously, has been talking about how best to do this, but I don't think there was any question that, ultimately, a photograph would be presented to the public," Panetta said in an interview with "NBC Nightly News."
Some doctored images purporting to be bin Laden already have surfaced on the Internet. And the FBI also warned Tuesday to use caution upon receipt of e-mails that purport to show photos or videos of bin Laden's death because some are being used to spread viruses.
National security law experts had mixed opinions, expressing many of the same concerns as the Obama administration.
"I would advise against releasing the photos," said John Radsan, a national security law expert, former assistant general counsel for the CIA and now a professor at William Mitchell College of Law in St. Paul, Minn.
"It will be seen as disrespectful or intended to humiliate by some audiences, and I doubt that it will satisfy the skeptics," said Radsan, a former Detroiter whose parents were born in Iran. "We are a visual society, and people want visual confirmation. But, at times, we have to take the word of our government, our military and our intelligence agencies."
But Imad Hamad, regional director of the American-Arab Anti-Discrimination Committee in Dearborn, said he has no problem if the government releases the photo.
"I'm fine either way," he said. "I can understand the logic that says we want to see the body ... but it could also spark more violence."
Troy attorney Shereef Akeel, an Egyptian American and Muslim, said: "It would have been more gratifying if the man had been hauled in alive to face justice."
Akeel acknowledged the trade-off between giving families of victims closure and a sense that justice has been done and inflaming terrorists to pursue more mayhem.
Asked if he would like to see the photo, Akeel said: "To me, it's not meaningful. I'll take the administration's word for it."
So will Paul McNulty, a former U.S. deputy attorney general under President George W. Bush. The onetime No. 2 official at the Justice Department said he believes the government got the right man -- and he doesn't need to see any photos as proof.
"The credibility of what has occurred seems to be self apparent, and I don't think the government should react too quickly to any expression of that kind of skepticism," he said. "I think they've made a very credible case for what has occurred."
Contact David Ashenfelter: 313-223-4494 or email@example.com. Free Press news services contributed to this report.


text:
Page Showing 1-10 of 78 Results
Avg. Customer Rating (Based on 78 Reviews)
Write a Review | Back to Product Page
By Myrna C. from Dorado, PR on 2/22/2013
Mi nena de 6 años le encanta, después de probar otros gorros este le encanto, no se le sale. Excellent
Swim Cap
By Kim from Wisconsin on 11/19/2014
The original cap ripped after wearing it only 3 times but Swim Outlet saw my review and automatically reimbursed me then sent a new one! The new one is working well. Excellent customer service, thank you so much!!
Not big enough
By Swim mom from Virginia on 8/4/2013
Good quality material but barely fits my 8 yr old's head and not my 11 yr old's head at all. Should have gotten adult size
Great for long hair!
By Nancy C. from Vancouver, Canada on 1/21/2015
I bought 2 of these caps (pink and purple) for my 4yr old daughter who has extremely long, thick hair (down to her bum), as she has swimming 2x per week and the chlorine is hard on her hair/a pain to wash & comb out. I didn't think it would work as 1) Her hair is just MASSIVE, and 2) I have never put a swim cap on in my life. Well I was pleasantly surprised as this cap worked really well! I was able to twist her hair around in a loose bun, and tuck it up quite easily. Very happy with this product, and would recommend this.
Great quality!
By Tgraef84 from Chicago, IL on 1/15/2015
I am an adult but have a small head, adult swim caps are always too big. This cap is the perfect size!
swim cap
By happyswimmer from Montreal on 1/12/2015
I ordered two caps for my kids. The delivery was relatively fast and I'm happy with the quality of the merchandise
sporti silicone kids swim cap
By sdmsunshine from Cleveland ohio on 1/24/2014
Fantastic fit over any hairstyle
By Claudia A. from West Orange, NJ on 7/16/2013
My 6 yr old niece loves it!
Best for kids
By Swimmer58 from Boca Raton FL on 2/26/2015
I am an adult with a small head and short hair. I wear the Speedo junior caps and they fit great. I was looking for a cap that matched my suit and chose the sporti cap. The color matches and the price rocks, bot it feels a bit small/short on the sides. I worry about it coming off during my workout which I didn't with the Speedo junior cap. Great value.
not bad
By Alice from Wisconsin on 2/25/2015
The cap stays on better than some but her hair is still wet after swimming.


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Located in downtown Seattle's biotech corridor, Seattle Children's Research Institute is pushing the boundaries of medical research to find cures for pediatric diseases and improve outcomes for children all over the world. Internationally recognized investigators and staff at the research institute are advancing new discoveries in cancer, genetics, immunology, pathology, infectious disease, injury prevention and bioethics, among others. As part of Seattle Children's Hospital, the research institute brings together leading minds in pediatric research to provide patients with the best care possible. Seattle Children's serves as the primary teaching, clinical and research site for the Department of Pediatrics at the University of Washington School of Medicine, which consistently ranks as one of the best pediatric departments in the country. For more information, visit http://www.seattlechildrens.org/research.
2.13.15 - On the Pulse
Seattle Children's is my home. From the previously trademark blue bubble letters, the giraffes (which were recently replaced...cont.
2.12.15 - On the Pulse
The first thing Dr. Michael Cunningham noticed was the crowding. Hundreds of African mothers and their young children,...cont.
2.11.15 - On the Pulse
Children who need a heart transplant face a frightening waiting game before a donor heart becomes available. They must live...cont.
2.23.15 - Press Release
2.5.15 - Press Release
12.9.14 - Press Release


text:
I have been on a baby booties kick for weeks now. It didn't help that I read this fellow 'Being Pregnant' blogger's 15 of my favorite shoes for little baby feet post, and caught the booty bug.
I am finding baby booties everywhere I go, attaching pictures of baby booties to my Pinterest page. I'm obsessed with baby booties and shoesies. I think there's a name for this disorder.
I know that most babies, especially infants, don't NEED shoes like the ones I am currently desiring, but… C'MON, how could you deny a precious little one the joy of being adorable and cooed at all day long while wearing these…
Scope out the booties/shoesies after the jump!


text:
US 20040174944 A1 Abstract The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware. Advantageously, the present invention dynamically adapts to achieve the best performance possible under the actual operating conditions.
Claims(1) 1. A system for digital system performance enhancement that receives an input signal and a first clock signal, said system comprising:
clock control logic that receives the first clock signal and generates a second clock signal and a third clock signal, wherein said second and third clock signals have a frequency that this an integer fraction of the first clock signal frequency; a first digital synchronous network responsive to the first clock signal and the input signal, and provides a first output signal; a second digital synchronous network substantially identical to said first digital synchronous network, wherein said second digital synchronous network receives said second clock signal and the input signal, and provides a second output signal; a third digital synchronous network substantially identical to said first digital synchronous network, wherein said third digital synchronous network receives said third clock signal and the input signal, and provides a third output signal; and comparison and selection logic responsive to said first, second and third output signals to determine if a fault has occurred in the computation of said first output signal, wherein if a fault has not occurred said comparison and selection logic provides a system output signal indicative of said first output signal, wherein if a fault has occurred said comparison and selection logic provides said system output signal indicative of said second output signal. Description [0001] This application claims priority to U.S. Patent Application Serial No. 60/429,736, filed Nov. 27, 2002, and is a continuation-in-part application of U.S. Patent Application Serial Number Ser. No. 09/672,128, filed on Sep. 27, 2000, which claims priority to U.S. Patent Application Serial No. 60/156,219, filed on Sep. 27, 1999, all the aforementioned applications being incorporated by reference in their entireties. [0002] The invention relates to the field of digital electronic systems, and in particular to synchronous digital electronic systems. [0003] Computers, including their central processing units (e.g., Intel Pentium), cell phones, microwave ovens and practically every electronic device manufactured today uses digital hardware to operate. Digital circuits that compute a result based solely on the state of the circuits' current inputs are said to be constructed of combinational logic. Combinational systems can be used in many applications, but for any interesting digital system to be realized the system must base its output on both current inputs and the system's prior outputs or state. [0004] There are two types of digital systems with �state� to be held in some in a memory device; hence these systems are often referred to as systems with memory. The first type, asynchronous digital systems, change state as soon as an input changes its value. Modeling, designing and verifying asynchronous systems has in practice been found to be extremely difficult, even with modern asynchronous techniques. An advantage of digital systems is that they operate as fast as the logic delays allow. [0005] A second digital system type is a synchronous system, in which the state only changes at times determined by a global system clock (i.e., in synchronism with the clock). For example, consider a Intel Pentium III processor with a basic on-chip (CPU) clock that oscillates 500 million times a second (i.e., 500 MHz); the processor only changes its state at the start of one or more of those oscillations. The synchronous approach facilitates the design, construction and use of digital systems. [0006] However, an inherent difficulty and performance penalty with synchronous systems is that the duration/period of the clock must be large enough to handle worst-case operating conditions and manufacturing tolerances. This period is typically at least two times the length nominally required by the typical (common) operating and manufacturing tolerances. Therefore, the performance of such a digital systems is often half or less than what it would be but for the worst-case. [0007] A digital synchronous system 20 can be represented by a block diagram model illustrated in FIG. 1. The components of the system include combinational logic 22 (CL) and flip-flops or latches (FF) 24. The latches 24 hold the current/present state of the system. Each latch typically stores one bit of information. As known, a flip-flop only changes its contents or state when a clock signal makes a transition. The same clock goes to all the latches. The combinational logic 22 has no clock input or feedback loops: a change in one of its inputs propagates to one or more outputs with a delay due only to electrical circuit and speed-of-light constraints. A latch 24 also has a propagation delay, but from the clock transition to a change in its output. [0008] The system 20 operates by using the combinational logic 22 to compute the Next State (NS) of the system from its present state and the current values of the inputs to the system. The next state is then stored in the latches 24 when the clock transitions, and the process repeats. In order for the system to function properly, the computation must propagate through the combinational logic and appear at the inputs to the latches before the relevant transition of the clock occurs at the latches. [0009] If the exact delays through the logic and latches were known, the clock frequency would be set to the inverse of the sum of the delays, and the system would operate at peak performance (as measured by computations per second). However, the delays are not constant, but vary with differences in the manufacturing process, variations in the power supply voltage, variations in the operating temperature and humidity, as well as other factors. As a result of these variations, and the necessity to guarantee the operation of the digital system in the worst-case situation (e.g., temperature extremes), the clock speed is set to a lower, more conservative value than is necessary in most, typical cases. Consequently, the average user experiences significantly lower performance than is actually necessary. [0010] Therefore, there is a need for a faster synchronous system architecture. [0011] Briefly, according to an aspect of the present invention, the frequency of a system clock is automatically increased until a system error is detected, then the frequency of the clock is automatically slightly reduced to a value that does not cause system errors. [0012] Briefly, according to another aspect of the invention, the frequency of a system clock is automatically increased until an unacceptable number of errors are detected, and then the frequency of the clock is automatically slightly reduced so the number of detected errors is less than the unacceptable number of errors. [0013] The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. [0014] In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware. [0015] Advantageously, the present invention dynamically adapts to achieve the best performance possible under the actual operating conditions. [0016] In another aspect, the invention comprises a Timing Error Avoidance (TEAtime) system that includes structure that uses extra logic with the delay of the longest path between pipeline registers to test on a cycle-by-cycle basis whether or not the system clock is too fast or too slow. If a signal applied to the input of the delay test logic appears at the output of the test logic within the time of the machine's slowest path, the system will provide a signal to speed up the system clock speed. Alternatively, if the signal applied to the input of the delay test logic appears at the output of the test logic at a greater time than the machine's slowest path, the system will provide a signal to slow down, minus a safety margin, the system clock speed. Since the characteristics of the delay test logic (delay, etc.) mirrors those of the main logic (they are realized close together on the same chip), the system Clock adapts both to dynamic environmental conditions, including temperature and operating voltage, as well as to statically-varying manufacturing conditions. [0017] These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings. [0018]FIG. 1 illustrates a functional block diagram of a digital synchronous system; [0019]FIG. 2 illustrates a first embodiment of a digital system according to the present invention; [0020]FIG. 3 illustrates a timing diagram for the system illustrated in FIG. 2; [0021]FIG. 4 illustrates a first alternative embodiment of the present invention; [0022]FIG. 5 illustrates a timing diagram for the first alternative embodiment illustrated in FIG. 4; [0023]FIG. 6 illustrates a second alternative embodiment of the invention; [0024]FIG. 7 illustrates a timing diagram for the embodiment illustrated in FIG. 5; [0025]FIG. 8 illustrates a block diagram of a timing error avoidance system; [0026]FIG. 9 is a more detailed block diagram illustration of the timing error avoidance system illustrated in FIG. 8; [0027]FIG. 10 is a block diagram illustration of the timing checker circuit illustrated in FIG. 9; and [0028]FIG. 11 illustrates a timing diagram for the embodiment illustrated in FIG. 10. [0029]FIG. 2 illustrates a first embodiment of a digital system 30 according to the present invention. The digital system 30 includes two copies 20 a, 20 b of a main digital synchronous system 20 illustrated in FIG. 1, wherein each of the copies 20 a, 20 b operates at half the speed of the main digital synchronous system 20. One of the copies replicates the results of the main digital synchronous system 20 in odd cycles, while the other copy replicates the results in even cycles. The two half-speed systems 20 a, 20 b are operated one main system cycle out-of-sync with each other. Both of the half-speed systems' 20 a, 20 b outputs on lines 32, 34 respectively are compared with the main system output on the line 36 in alternate cycles using comparators 38, 40. If there is a difference between the two outputs (e.g., between the signals on lines 32 and 36), an error is detected and selection logic 42 selects the output signal from the half-speed system, assuming of course the error was caused by the higher speed system (i.e., system 20). One cycle of operation is lost for every correction necessary; this is referred to as a miscalculation penalty. [0030]FIG. 3 illustrates a timing diagram for the system 30 illustrated in FIG. 2, the first three cycles of operation (i.e., 0-2) are for the case when no errors occur. The numbers within the individual signal timing charts indicate which computation the signal is working on or holds at that time. At the end of cycle three 52 (at the asterisk), a comparison of the signal CL.0 (half-speed) on the line 34 with the signal Q_sys on the line 36 indicates an error in computation 3. The system 30 then stalls one cycle, with the next state remaining at 3 in cycle 3 (see 54), which it gets from CL.0, having the correct version of computation 3, and the system resumes operation with the correct result. In cycles 3 and later the ideal computation numbers are shown without parentheses, and the actual (with delay) computation numbers are shown with parentheses. [0031] The half-speed systems 20 a, 20 b must not be operated faster than the original worst-case system speed to help ensure error-free computation to compare the high-speed main computation with. This solution requires approximately three times the hardware of the original system. [0032] It is possible to modify the solution to allow performance increases greater than a factor of two. For each increment of factor increase (e.g., increment of one from 2�to 3�), another copy of the hardware must be used. Further, the slow comparison systems use a clock that is an increment of factor slower, e.g., in the 3�performance increase case, the third-clock system (not shown) operates at a third of the frequency of the main system clock. For each increment of factor increase, the miscalculation penalty increases by a cycle (e.g., for the 3�case the penalty is two cycles). Other cases are handled accordingly. Note that all of the clocks in the overall system are synchronized. [0033] As the frequency increases, the basic performance of the system increases, but at some point the degradation in performance due to the miscalculation penalties from an increasing error rate offsets the basic (clock rate) performance, decreasing the overall performance. Therefore, the system 30 determines the maximum performance point, and adapts to changing conditions to determine the best performance given the actual system operating conditions and manufacturing tolerances of the components therein. The system utilizes a control technique to adjust the system clock frequency in real-time. The basic operation of such a system may be biased towards increasing the clock rate, and receive information from the comparators of the timing error detection circuitry. The system clock drives a counter having a clock enable function. The counter is disabled when an error is detected (in the case of our performance doubling example, this is for one cycle per error). Therefore, the overall absolute averaged count rate of the counter is a direct measure of the system's performance; as errors increase, it counts less often, although at a faster rate�the same dynamics as those of the invention's performance. [0034] The smoothed output of the counter is fed back into the system's clock generator, adjusting the frequency of the clock appropriately. If the averaged counter output is low, it increases the clock frequency (and the counter output also increases) until the averaged counter output begins to decrease; the frequency is then incrementally lowered, increasing the counter output, until the output starts to decrease again, at which point the frequency reverses course once again. That is, the frequency of the clock increases while the derivative of the performance (integrated counter output) increases; when the latter decreases, the clock frequency is decreased; when the performance begins to increase again, the clock frequency is once again increased. [0035] The base digital synchronous system 20 (FIG. 2) is duplicated, and the outputs of the two copies 20 a, 20 b (FIG. 2) are compared every cycle. The clock frequency increases until the copies 20 a, 20 b (FIG. 2) differ in their results. The system 30 then backtracks to a known good state, and operation resumes. [0036] This technique assumes that given the statistical variations in the manufacture of the two copies 20 a, 20 b, one copy will fail at a lower frequency than the other. If they both fail at the same time and in the same way, no error will be detected, and the system 30 will malfunction. There are actually cases in which a finite error rate in such a system can be tolerated. For example, if such a DSP device were manipulating an image and failed once during the image, potentially only one pixel of the image out of around a million pixels total would have an incorrect value, and no one would notice. [0037] For mission critical applications this technique would not be suitable. However, the technique may be modified to function with any probability simply by continuing to add copies of the original digital system to the modified system, and comparing all of the outputs. In such a method voting techniques can be used. These systems have been used (e.g., in the Space Shuttle), but to enhance reliability rather than improve performance. Therefore, existing systems may have their performance improved by increasing their clock rate to an acceptable error (tolerated) rate level using the control system technique according to an aspect of the present invention. [0038] This embodiment of the invention was tested using programmable hardware in conjunction with a variable frequency clock generator to provide a piece of combinational logic. Specifically, a 32-bit adder was built using a commercial-off-the-shelf Field Programmable Gate Array (FPGA). The inputs to the 32-bit adder came from registers using the same clock. There were also two registers on the output of the adder. The first was loaded one cycle after the input registers to the adder are loaded with test data. The second was loaded two clock cycles after the inputs were loaded. A comparator compared the outputs of the first and second output registers, hence at times differing by one cycle. Two one-bit registers were on the comparator output, to save (i.e., sample) the comparison output at different times. Therefore, the major basic elements of the invention were modeled. For each event, two random numbers were applied to the inputs of the adder at the same time. The output of the adder was latched both one and two clock cycles later. By adjusting the clock frequency and looking at the output register results, and the comparator results, it was determined when the adder produced correct results, and if correct/incorrect operation was detected by a slower system (i.e., the second register, which gives the adder twice the time to compute its result). The overall system was driven and examined by a host computer, which further verified the additions. [0039] The primary experiment determined the frequency that the system can operate at without error, or rather, with very few (all tolerated) errors. As a base frequency, we used the results of the design tools that indicate the adder (in the system, that is, including register delays) can operate at about 33 MHz (33 million adds per second) assuming worst case conditions. That corresponds to a clock period of about 30 nanoseconds. [0040] The experiment was performed a number of times. Each pass included performing twenty different additions on random numbers at one operating frequency. The system was initialized to a low frequency. The clock oscillator was variable from about 360 KHz to 120 MHz. A host computer sets the frequency, and used a bisection algorithm to quickly find the highest operating frequency with no errors among the twenty additions. [0041] After the first run, the operating frequency was determined to be about 60+MHz. However, certain aspects of the data indicated that the system may actually be operated faster; the comparator was actually too slow. The experiment was run again allowing the comparator more time to operate (but still looking at the two output registers clocked at the original times). The operating frequency increased to about 95 MHz. Therefore, a factor of approximately three improvement in adder performance was realized. [0042] A problem performing quick additions is the necessity to allow for the carry to propagate from the least significant bit (LSB) to the most significant bit (MSB), in the worst case. However, the worst case rarely happens with random data. Further, although the probability of a carry out of any particular bit is about �, the probability of having carries propagate over multiple bits decreases exponentially with the number of bits. A typical �maximum� propagation length of 8-9 bits was estimated, and that is almost exactly what we found in the twenty (20) random pairs of addends and augends (adder inputs) of the experiment. Hence, the worst case propagation length of 32-bits (in this case) is no where near seen in typical data, and the output of the adder actually settles in much less time than one might think. [0043]FIG. 4 illustrates a first alternative embodiment 70 of the present invention. This embodiment may be realized at the gate and latch level or at the register level. The system illustrated in FIG. 4 has a hardware cost that increases at the same rate as the performance (e.g., about 2�hardware cost for 2�performance increase, while the power also increases by a factor of about two). This solution is also easier to build and does not increase the amount of logic (gate delay) in the critical path. This solution is applied at the functional level in a pipelined system. FIG. 5 illustrates a timing diagram for the first alternative embodiment system 70 illustrated in FIG. 4. [0044] For the purposes of describing this embodiment, and certainly not by limitation, it is assumed that the system is pipelined. In a pipelined system (common in today's processors), the work of the original combinational logic is divided up into several sections/stages. Each stage does part of the work of the computation, but at different times. As known, a classic pipelined system operates in the same fashion as an assembly line, i.e., many products are being constructed in the line at any given time, but each is at a different point in the construction process. Although it takes about the same time to perform a single computation, many computations can be in process at the same time, realizing a type of parallelism and thus improving performance. [0045] Referring to FIG. 4, the system 70 includes two identical copies of the original system, adding comparators, and clocking adjacent stages on alternate system clock cycles. The two copies use complementary clocks at corresponding stages. The two half-speed clocks are skewed by one system clock cycle, as shown in FIG. 5. Referring to FIG. 5, the timing diagram illustrates the timing when no errors occur, and also the system timing when an error has been detected at the output of R1, in section A. (FIG. 4). [0046] Referring again to FIG. 4, assume that the hardware illustrated in the diagram is part of the system's overall pipeline (e.g., an Intel Pentium II microprocessor has about twelve stages in its pipeline). Pipelining allows a higher speed clock to be used than otherwise. The primed (′) hardware is a copy of the unprimed (top) hardware. [0047] The operation of the system 70 is as follows. Inputs to the overall system come in at the system clock rate. Note that at least as far as this hardware is concerned, there is no actual clock operating at the full rate. The inputs go to each pipeline 72, 74 in alternate cycles. At time 0, an input is latched into latch R0 76 by the signal clk.0 on line 78. The first computation occurs in combinational logic block CL1 80, and is latched one system cycle later at time 1 into latch R1 82 by the signal clk.1 on line 84. The signals clk.0 and clk.1 run at half the rate of the overall system clock. [0048] Therefore, the computation in the combinational logic block CL1 80 as latched in latch R1 82 takes one system cycle. However, block CL1 80 does not have its inputs changed until time 2 (see FIG. 5). At end of the second cycle, the output of latch R1 (one cycle computation time) is compared with the current output of the combinational logic block CL1 (two cycles of computation time, hence the guaranteed correct answer). If the two results, slow one and fast one, are equal the signal good.1 on line 88 is true indicating that the fast computation is correct and no corrective action needs be taken. At time 2 (see FIG. 5) the output of the second computation, from combinational logic block CL2 90, is latched into latch R2 92. Similar operations happen in the rest of the pipeline A stages, as well as in pipeline B. Results leave pipeline A (and B) at a rate one-half of the overall system clock rate, where the system clock rate is twice as fast as the system clock rate without the invention. [0049] However, there are two pipelines, so results are produced at 0.5*2*2=2 times the rate of the original system. [0050] If a miscalculation occurs, we then have the timing of the lower diagram 94 illustrated in FIG. 5. In this case, the latch R1 82 has latched incorrect results from the combinational logic block CL1 80. This is detected at the end of time 2 by comparator 87, which provides a signal value on the line 88 indicating that the signal good.1 is false. Therefore, the combinational logic block CL2 90 also has an incorrect answer, so the signal clk.0 on the line 78 is disabled for all of pipeline A at time 2 (see FIG. 5). The combinational logic block CL1 80 is still computing the same result for inputs IA1, and therefore at time 3 (see FIG. 5) the latch R1 82 latches in the correct result from the combinational logic block CL1 80. The combinational logic block CL1 80 has had more than two cycles to compute its result, which is thus correct. This correct result is now in the pipeline, and normal high-throughput operation resumes. Therefore, pipeline A has suffered a miscalculation penalty of two system clock cycles. Overall, this may lead to a system miscalculation penalty of one cycle, but if we require that the outputs from the two pipelines be in order, pipeline B must also be stalled by two system cycles, and hence we assume the penalty is two cycles for a miscalculation in this embodiment. [0051] If typical delays are one-third the original system's worst-case delays, and we thus would like to improve performance by a factor of three, a third copy of the system would be needed, with three clocks running at a third of the system clock rate, which is itself running three times faster that the original system clock. Note that the power required to operate the new system also increases proportionally to the performance increase. The miscalculation penalty also increases proportionally to three cycles. [0052] An advantage of the system illustrated in FIG. 4 versus the system illustrated in FIG. 2 is that the embodiment in FIG. 4 does not require selection logic (see 42 in FIG. 2), which allows a faster clock, or rather, does not increase the delay through a stage. [0053] Referring still to FIG. 4, inputs to new computations alternate entering pipeline A and pipeline B every cycle. Similarly, the output from the overall system alternates coming from pipeline A and pipeline B every cycle. Also note that as described above, the two pipelines are independent (i.e., a computation in one pipe does not depend on a computation in the other pipe). [0054]FIG. 6 illustrates yet another embodiment 100 of the invention. Notably, the embodiment 100 illustrated in FIG. 6 realizes a 2�performance for less than a 2�increase in hardware cost, while power increases by a factor of four. A major feature of this embodiment is its applicability to all digital systems, via the general digital system model illustrated in FIG. 1. [0055] Referring to FIG. 6, this embodiment is premised on creating a mini-version of a proportional pipe, but constructing the stages' combinational logic in a different manner. Assuming the original combinational logic block CL illustrated in FIG. 2 is split it into two equal-delay combinational logic sections CLa 102 and CLb 104 (i.e., we increase the pipelining by a factor of two). This allows the clock frequency to be doubled, and using a two-phase clocking system the implicit system frequency can be increased by another factor of two. However, since we only get a result every complete pass through the pipeline (i.e., every two implicit system clock cycles), the overall performance increases by a factor of two. [0056] This embodiment splits the combinational logic block 22 illustrated in FIG. 2 into two blocks 102, 104, wherein each block includes its own staging register 106, 108 respectively, as in a pipeline, except the stages are clocked on alternate system cycles. The system 100 also includes comparators 110, 112. The implicit system clock frequency is 4� the original. The explicit (physically existing) stage clock frequencies of the solution are 2� the original system clock frequency, and the same as the new explicit system clock frequency. [0057] The system 100 also includes error handling logic 120 to control the unit and handle errors. The error handling logic generates a signal LDR.a on line 122, which is the synchronous load enable line for the register Ra 106. The register Ra 106 is loaded when the signal LDR.a on the line 122 is true and the register Ra's clock goes from 0 to 1. Therefore, the register is loaded when either there was an error out of the combinational logic block CLa 102, and the logic block CLa needs more time to compute its result, or when the prior stage produced a valid result without extra delay. The technique for generating the signal LDRb on line 124 within the error handling logic is similar. [0058]FIG. 7 illustrates a timing diagram for the embodiment illustrated in FIG. 5. Notably, the two half-speed clocks clk.a and clk.b are skewed by one implicit system clock cycle. The explicit system clock is the same as the signal clk.a. The top diagram 126 (FIG. 7) illustrates the timing when no errors occur, while bottom diagram 128 illustrates the timing when an error has been detected at the output of the latch Ra 106 (FIG. 5). The nomenclature: �s1a� indicates that state 1, part a (the first half of the original state) is being computed. [0059] As with the embodiment illustrated in FIG. 4, the performance of the system illustrated in FIG. 6 can be increased by increasing the number of sections of the system. For example, to increase the performance by a factor of three, the combinational logic would be split into three sections, each ending in a register clocked by one distinct phase of a three-phase clock. [0060] A base 32-bit adder would require the same overall combinational logic (combinational adder itself) and at least two 32-bit registers for the inputs (64-bits of registers total), and in some cases an additional 32-bit register for the output, although in a pipelined system the output register would be counted as part of the next stage. An adder based upon the embodiment in FIG. 6 would use 92-bits of registers and three ten- or eleven-bit comparators. Making a rough assumption that one-bit of comparator costs the same as a one-bit register, the total hardware cost for the embodiment illustrated in FIG. 6 125-register-bit equivalents. [0061] A timing error avoidance system 800 is shown in FIG. 8 and comprises standard logic and analog element, an up/down counter 802 to drive a digital-to-analog converter (DAC) 804, which in turn generates an analog voltage to drive a VCO 806 that sets the frequency of the system clock on a line 808. In the example system, the counter 802 is always changing, and by at most one, up or down. With advances in VLSI technology, all of these elements should be realizable on the same chip as the system. Note that since there is an explicit feedback loop from the system clock to the counter's setting, the absolute value of the counter 802 is not important, only that it be able to go up and down in response to commands from the timing checker 810. [0062] The timing error avoidance system 800 is constructed by determining the critical path between register elements within a digital machine. For example in a pipelined CPU, this includes determining the slowest (clock-period determining) stage, and the critical (longest, time-wise) path through that logic and constructing a one-bit wide version of that logic in which a change at the one-bit version's input from a logic 0-to-1 or a 1-to-0 propagates all the way through to the end of the logic. This delay test logic is not connected to any of the regular logic of the machine. However, the delay test logic nominally has the same delay as the worst case path through the machine. Drive the delay test logic 814 with alternating 1's and 0's, the latter synchronized with the system clock on the line 802. The location of this test input corresponds to the output of the beginning pipeline register of the slowest pipeline stage in a CPU. At the end of every cycle, if the test data has not reached the output register of the pipeline stage before the system Clock edge, then the system is operating slower than it might, and the system Clock frequency is increased. If, however, the test data has reached the output register, then the system Clock frequency is getting close to the system's limit, and thus the system Clock frequency is reduced. [0063] In order to show the simplicity of the main timing error avoidance circuitry, we provide low-level details of its realization in FIG. 9. The alternating 1's and 0's are created by a flip-flop 902 wired for toggle operation. The delay test logic 814 includes a one-bit slice through an address multiplexor, the CPU's register file, the bypass multiplexor used for operand forwarding in the CPU to reduce data dependencies, and a zero-detecting comparator across the data path width. [0064] An exclusive-OR gate 906 normalizes delayed signal on line 908 to present a signal on line 910 to timing checker 810 with the same polarity regardless of the output of the toggle flip-flop 902. The delay of the delay test logic 814 is adjusted at system design time to be slightly greater than that of the aforementioned critical path to give a suitable safety margin. This is a relatively simple procedure when a high-quality logic simulator is used in the design process. In the case of our example CPU system a structural simulation was performed on the CPU running the test program. From this simulation, we obtained both the worst-case operating frequency for a non-timing error avoidance (baseline) CPU, and checked the performance of the timing error avoidance logic to ensure that the system clock frequency was reduced before the timing constraints of the regular CPU logic were violated. This ensured timing error avoidance. [0065] There is one place in the timing error avoidance system illustrated in FIG. 9 where system failure can occur�this is at the start of the timing checker 810, where the delayed signal is latched into a flip-flop. Since the delayed signal can be positioned anywhere in time, and is not synchronized with the system clock on line 914, there is the possibility that the delayed test signal could change value at the same time as the signal is being latched in the timing checker 810. This may result in metastability at the output of the timing checker 810, in which the physical value of the logic output signal on line 916 of the timing checker flip-flop is neither 0 or 1. It is well known that metastable signals can stay in this state indefinitely, leading of the value by the rest of the system logic. [0066]FIG. 10 illustrates an embodiment of the timing checker circuit 810 that addresses raised in the preceding paragraph. The timing check circuit 810 samples the delay test signal D 1 on line 910, at two different times. Then, for a single cycle, only one of flip-flops Q1 1002 or Q2 1004 can possibly be in a metastable state. That is, flip-flops 1002, 1004 cannot both be metastable in the same cycle, since the delay test signal on the line 910 only changes value at most once in a cycle. The output of the logic looking at flip-flip Q1 1002 and flip-flop Q2 1004 to determine up or down clock frequency changing is only sampled long after a metastable condition can begin, as long as the frequency change increment is kept suitably small. The timing checker logic ensures that no metastable condition propagates past the sample point. For example, see FIG. 11 case 3, for an example of the handling of a metastable condition. Cases 1 and 2 show more typical frequency increasing and decreasing, respectively. [0067] As shown in FIG. 10, a signal from the VCO is input on line 918. This signal is input to two serial gate delays to generate the system clock on line 920. [0068] The timing error avoidance logic is relatively inexpensive. For example, for a 32-bit CPU the hardware cost of the delay test logic is less than {fraction (1/32)} of the cost of the slowest pipeline stage. The variable frequency oscillator adds only a small cost. [0069] If a CPU or other digital system has two or more pipeline stages of similar delay, they can all be treated as described herein for the single stage case, with a �decrease Clock frequency� signal from any of them having priority for the setting of the Clock frequency. [0070] Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention. Referenced by
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Phoenix Suns
Phoenix Suns sign Shavlik Randolph, waive Slava Kravtsov
The Phoenix Suns made some moves with their frontcourt Saturday as they prepare to make a playoff push with 24 games left.
According to a tweet from the team, the Suns have signed 30-year-old power forward Shavlik Randolph for the rest of the season. The 6-foot-10, 236-pound forward has played for Philadelphia, Portland, Miami and Boston over his six-year career. He last played with the Celtics in 2012-13, appearing in 16 games.
The Raleigh, N.C., native has averaged 2.7 points, 2.7 rebounds and 47.5 percent shooting in 111 games played since he entered the league in 2005.
To clear the way for Randolph, the Suns waived backup center Viacheslav "Slava" Kravtsov. In his second year in the NBA, the Ukrainian big man appeared in 20 contests for Phoenix, putting up one point and 0.9 rebounds in three minutes per game.
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- Al McCoy, Hall of Fame Voice of the SunsAl talks about the Suns' win over Denver and looks ahead to how they can beat the Thunder.
- Ryan McDonough, Suns general manager Ryan McDonough talks about the progress of Alex Len and the Suns playoff chances.


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Butler's Lives of the Saints – Saint Columba of Sens, Virgin and Martyr
The New Paris Breviary fixes her death either in 258 or in 273. The latter date reduces it to the journey which Aurelian took into Gaul in that year, when he gained a great victory at Chalons. She suffered at Sens. Her relics were kept in the Benedictin abbey till they were dispersed by the Huguenots, together with those of many other saints kept there, as Baillet observes. Saint Owen, in his life of Saint Eligius, mentions a chapel which bore her name at Paris.
MLA Citation
- Father Alban Butler. "Saint Columba, Virgin and Martyr". Lives of the Fathers, Martyrs, and Principal Saints, 1866. Saints.SQPN.com. 19 December 2013. Web. 5 March 2015. <>


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Graduate News
The Color Master
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Royal Subject to Citizen
September 26, 2013U.S. Ambassador to Saudi Arabia James B. Smith witnessed firsthand the changes that took place in his region as the Arab Spring movement gained traction in 2010 and spread throughout the Arab world. These two words emerged as…
'The Art of Living'
September 19, 2013Brainwaves by the Sea
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Ready for a rivalry
Thursday, December 27, 2012 2:13 PM
Freedom wide receiver Pete Hernandez (7) leads the team onto the field before the Nov. 3 game against Liberty at Bethlehem Area School District Stadium.
Liberty football team beats rival Freedom, 41-1
K.J. Williams has a birthday to remember as Liberty High School football team beats rival Freedom
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The Juice Pack Helium for iPhone 5 marks a new achievement in light, thin battery cases from mophie. Its sleek design protects your iPhone from drops and scratches while providing plenty of extra power.
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The Juice Pack Air offers you the convenience of a fully protective, form-fitting case with an extended built-in rechargeable battery for your iPhone; all in an ultra-thin, lightweight, low-profile design.
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The Juice Pack Air offers you the convenience of a fully protective, form-fitting case with an extended built-in rechargeable battery for your iPhone 4S or iPhone 4; all in an ultra-thin, lightweight, low-profile design.


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Top Apps
- Audio & Video
- Business & Enterprise
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- System Administration
PHP/Java Bridge The PHP script engine for Java. --- Run PHP applications within any J2EE server or servlet engine and/or connect script engines like PHP with Java or .NET back ends efficiently.
929 weekly downloads -
MLton A whole-program optimizing Standard ML compiler
37 weekly downloads -
libtld Extract the TLD of any, world wide, URI.
3 weekly downloads -
xoris xoris grabs the RGB color value of any pixel on the screen and dumps the color's name to stdout.
3 weekly downloads -
Dwm-Hacked This is The DWM X window manager - hacked to add a few extra features and slightly modified to suit a still ultra-slim but not featureless need. A collection of a bunch of jacks from a bunch of different people.
1 weekly downloads -
GlutMaster Glutmaster is a set of platform-independent classes that wrap GLUT in a C++ object model.
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muhttpd muhttpd is a simple but complete web server written in portable ANSI C, supporting logging, CGI scripts, MIME type based handlers, and HTTPS. It has been tested on various Unix environments on 32-bit, 64-bit, little endian and big endian systems.
0 weekly downloads


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WASHINGTON (AP) - Officials say a fire broke out at a building near the Smithsonian's National Museum of Natural History in Washington, emitting a plume of black smoke and closing area streets.
Smithsonian spokeswoman Linda St. Thomas says a building detached from the museum that contains the facility's cooling tower caught fire early Monday. She says it appears the fire started while a contractor was working in the mechanical building.
No smoke entered the main building, where millions of artifacts and specimens are housed. The museum opened to visitors Monday shortly after its regular opening of 10 a.m.
D.C. Deputy Fire Chief Ken Crosswhite says the fire did not pose a risk to the museum. No injuries were reported.
Natural History Museum In DC Reopens After Fire
© 2011 The Associated Press. All Rights Reserved. This material may not be published, broadcast, rewritten, or redistributed.


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Topic: the body human
Thursday, January 23, 2014
From the letter press to cutting-edge 3-d bio printers, the story of printing evolution has come a long way! Currently scientists are using 3-d bio printing technology to create organs to help people in need. Pretty remarkable stuff!
Topics Covered: the body human, printing, science, technology, stem, science museum of virginia, Question Power, ink
Tuesday, January 14, 2014
Busted door knobs, broken heels, and cracked glasses are a few things that can be fixed using super glue. The quick bonding adhesive works on nearly everything, perhaps that's why this glue is considered to be super. As amazing as this glue is it still can't be used to help us...
Topics Covered: anatomy, biology, Doctor, genetics, health, leeches, medical, medical research, medicine, nutrition, ouch, physiology, question your world, science, science museum of virginia, stem, surgery, the body human, worm
Tuesday, January 7, 2014
Every event in the universe that we have been able to observe is deeply entangled with time. Time's forward impact has an influence on everything from the forming of distant galaxies to the wear and tear within our cells. The impact time has on us is called aging. This is a...
Topics Covered: age, biology, Body, cell wall, cells, communication, future, genetics, harvard, mitochondria, nucleus, Organs, question your world, science, science museum of virginia, stem, steve miller band, the body human, Time, aging, anatomy, medical ethics, medical research, physiology, sirtuins
Monday, January 6, 2014
For over a decade scientists around the world have been studying happiness and its impact on our physiology. Why would people spend so much time studying happiness? Maybe that makes them happy? So, what makes you happy?
Rod Stewart loves soccer, Jennifer...
Topics Covered: biology, Boost!, brain, Chemicals, happiness, health, hobby, passions, physiology, polar bears, psychology, question your world, research, RVA, science, science museum of virginia, stem, the body human
Friday, December 20, 2013
Understanding how your brain operates can lead you to maximizing its potential—whether it's improving the way you interact with people or maybe even age-proofing yourself.
Enhance your memory and focus with interactive games that increase in difficulty as you...
Topics Covered:
Exercise doesn't have to be about hitting the gym, but taking simple steps to improving your body – which will make you feel better and boost your brain too!
Test your strength, agility and balance through a series of activities that will keep you on your toes! Put...
Topics Covered:
Thursday, December 19, 2013
Right around the holiday season we start to see a lot of top 10 lists that go over all the major highlights of the year. Entertainment, politics, sports, and day-to-day living are all discussed in the yearly recap. So, what happened in science this year?
2013 was a very productive...
Topics Covered: Astronomy, biology, Boost!, brain, cells, discovery, genetics, health, Out of this World, question your world, richmond, RVA, science, science museum of virginia, solar system, space, stem, study, the body human, travel
Tuesday, December 10, 2013
Decisions, decisions, decisions! Our lives are basically a series of decisions, one after the other. The big and small decisions we make shape and guide everything in our lives. So, the big question right now is, how does the brain make decisions?
Topics Covered: biology, brain, choices, decisions, deep brain, depression, electrical, genetics, neurons, question your world, RVA, science, science museum of virginia, shock, stem, the body human, anatomy, brain function, research, thinking, neuroscience, nervous system
Monday, November 25, 2013
Everyone has had at least one cranky moment over being hungry, right? Those moments are where the temperament of the mind has been altered by a need of the body, but what about other times? Are there other occasions where brain function is impacted due to stomach related issues? Can...
Topics Covered: the body human, science museum of virginia, question your world, stem, bacteria, biology, brain, brain function, communication, gut, impact, mental, nerves, science, stomach, the body
Friday, November 22, 2013
Our collective knowledge is constantly evolving – from new discoveries on distant planets to inventions for the smallest cells in our bodies. Here at the Science Museum of Virginia, we have been busy questioning our world and keeping you up-to-date with the most current science stories...
Topics Covered: the body human, Creatures, Out of this World, Idea Factory, Question Power, science museum of virginia, stem, RVA


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Best New Ice Fishing Gear
This Sunday, January 13, at 7 pm ET/4 pm PT, WFN will be airing Ice Block, a five-hour programming marathon dedicated to ice fishing. Anglers from six different shows that air on WFN, including Canadian Sportfishing, Hooked on Utah, and John Gillespie's Water & Woods, will put their ice fishing tips and techniques to the test.
If you're interested in trying ice fishing for the first time, or if its one of your favorite pastimes, its always important to make sure that you have the best equipment possible. This past year saw some great new products hit the market, and WFN is pleased to present our list of the best new ice fishing gear.
Frabill Titanium Spring Bobber
Theres nothing worse than having a fish on the line but not realizing it thanks to an inferior spring bobber. Enter Frabills high-performance Titanium Spring Bobber. Its endlessly durable, has completely kink and bend elimination, virtual weightlessness, and will fit any combo that youd want to use.
MarCum VS385C/VS385 Underwater Cameras
Underwater cameras have become a stable for many anglers who enjoy ice fishing. The ability to see a fish bite your lure underwater adds an entirely new thrill to the sport. The MarCum VS385C/VS385 series of underwater cameras provide unparalleled views in color or black and white, respectively. Youll never miss another bite.
Sufix 832 Advanced Ice Braid
If youre planning on going ice fishing, having the right type of line is extremely important. You need a line that has the ability to shed water and ice, so that it doesnt freeze in your rod guides. This is what makes Sufix 832 Advanced Ice Braid stand out from the rest its the toughest, most sensitive line you can find, and any angler planning on going ice fishing wont want to be caught without it.
Frabill Ice Suit
Theres no doubt about it: ice fishing can be a cold and wet activity. In order to combat the elements, you need to have the proper apparel. Look no further than the Frabill Ice Suit. It offers complete protection in cold weather, and doesnt do so by sacrificing comfort. Its also 100% seam sealed for complete dryness gone are the days of being cold and uncomfortable in your ice hut.
Rapala Sherpa M2 Pop-Up Portable Shelter
Lets face it as handy as shelters can be when ice fishing, they can also be a pain in the you-know-what. Theyre heavy, awkward to transport, and take a lot of time to set up and take down. And this is what makes this new pop-up portable shelter from Rapala stand out from the rest of the pack. The two-man shelter weighs a mere 18 lbs, and is a breeze to set up and take down. Gord Pyzer recently reviewed this shelter for WFN, and he had nothing but good things to say about it.
Check out WFN's Gear section for more great ice fishing products.
Gear of the Week: Marcum 485C Underwater Viewing System
Learn More »Gear of the Week: Marcum 485C Underwater Viewing System
The MarCum 485C underwater viewing system proves that top-of-the-line performance doesn't have to come with a top-shelf price tag.
Everything You Need to Know to Go Ice Fishing
Learn More »Everything You Need to Know to Go Ice Fishing
This infographic contains everything anglers need to know before beginning their ice fishing adventure.
Gear of the Week: Eskimo Fatfish 6120 Ice Shelter
Learn More »Gear of the Week: Eskimo Fatfish 6120 Ice Shelter
The Fatfish 6120 is a wide-bottom, six-sided shelter that features the wide-bottom fishable area that the Fatfish line is known for.


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Unisan Cut-End Wet Mop Head, Cotton, #24 Size
Clean up quicker with a high-quality, ultra-absorbent mop head. Cut-end design minimizes snags. Heavy-duty headband ensures secure attachment. For use with clamp-style mop handles (sold separately).
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Unisan Cut-End Wet Mop Head, Cotton, #24 Size
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Chili Cumin Stuffed Chicken Breasts
"This is a Tex-Mex twist on stuffed chicken breasts. Chicken breasts are slow cooked with green and red peppers, tomato, cilantro, and cheese."
cheddar cheese, chicken, +chili powder, +cilantro, +cumin, +green pepper, +red pepper, +salt, +tomato, +toothpicks
allrecipes.com - Similiar recipes
Five Cheese Stuffed Chicken Breasts
Wonderful cheesy stuffed chicken breasts topped with a cheese sauce when served. This recipe makes four chicken breasts, but can easily be doubled if...
chicken, cheddar cheese, +black pepper, +chicken broth, +bread crumbs, +eggs, +half and half, +mozzarella cheese, +parmesan cheese, +ricotta cheese, +salt, +swiss cheese
www.recipezaar.com - Similiar recipes
Garlic N Cheddar Stuffed Chicken Breasts Recipe
These chicken breasts are stuffed with a garlicky cheddar mixture, lightly breaded and cooked in a skillet! Sooooo good! Great with a loaded baked potato...
www.grouprecipes.com - Similiar recipes
Grilled Stuffed Chicken Breasts
Wonderful dish that looks and tastes fancy, but is super easy to make!
chicken, cheddar cheese, +broccoli, +toothpicks
www.recipezaar.com - Similiar recipes
Chicken Breasts Stuffed With Apples & Cheddar
I have been meaning to give this elegant sounding chicken dish for years and have decided to share it here even though I haven't tried it yet. I originally...
chicken, cheddar cheese, +apple, +cornstarch, +white wine, +parsley, +black pepper, +salt, +butter, +water
www.recipezaar.com - Similiar recipes
Pineapple and old cheddar stuffed chicken breasts
chicken, cheddar cheese, +pineapple, +green onion, +butter, +lime juice, +olive oil, +salt, +toothpicks
www.bigoven.com - Similiar recipes
Chili And Cheese Stuffed Chicken Breasts
"This recipe is excellent as a leftover as well. Serve it with a guacamole salad or fruit salad. It's also great cold or on a picnic!"
cheddar cheese, chicken, +black pepper, +corn flakes, +cumin, +eggs, +green onion, +green chilies, +salt, +rice
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Find a copy in the library
Finding libraries that hold this item...
Genre/Form: | Biography |
Additional Physical Format: | Online version: Kirk, Clara Marburg, 1898- Mr. Pepys and Mr. Evelyn. Philadelphia, University of Pennsylvania Press; London, H. Milford, Oxford University Press, 1935 (OCoLC)587349955 |
Named Person: | Samuel Pepys; John Evelyn; John Evelyn; Samuel Pepys |
Document Type: | Book |
All Authors / Contributors: |
Clara Marburg Kirk |
OCLC Number: | 776896 |
Description: | xi, 156 pages illustrations 24 cm |
Contents: | Introducing Mr. Pepys and Mr. Evelyn. -- Publick employment. -- Private enjoyment. -- Notes (p. 75-80) -- Appendix. I. Manuscript letters: Pepys-Evelyn; Hewer-Evelyn; Jackson-Evelyn. -- II. Finding list of letters advertised in book catalogues. -- III. Finding list of printed letters. |
Responsibility: | by Clara Marburg. |
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This doctor matches your preferences for Specialty.


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In this section I give warnings on scams and general nasties that are out to trap the unwary.
Here is a useful page about Your E-Mail Responsibility written by Duane Alan Hahn. It covers how to deal with emailing groups of people, forwarding e-mails and dealing with chain e-mails. Good, sensible advice.
Here is a good site with useful, practical and trustworthy information on identity theft, Internet scams, credit card fraud, phishing, lottery scams and more, plus how to stop spam: Scambusters.org (it's an American site but the scammers are world wide!). There tend to be a few "announcements" (adverts) before the actual articles, but they have to pay the bills somehow!


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I was about to call B.o.B. the world's most popular rapper turned rocker/pop sensation, and then I remembered Lil Wayne's musical transformation (see also: How to Love). Considering both Bobby and Weezy have joined forces for a new single, is it unreasonable then to think that Strange Clouds will be the biggest hit in music history? Ok, yeah, that is a little unreasonable, but you get the point. This one's aimed at the charts, especially with proven hitmaker Dr. Luke cooking up an atmpospheric beat that's as dark as it is catchy, a formula that's worked for B.o.B. before (Airplanes). Vocally the esteemed Nothin on You creator walks both sides of the line nicely, one minute flipping off-kilter rhymes (first Top Chef reference in rap history?) and the next delivering party-ready vocals on the hook. For his part Weezy is, well, Weezy, alternately promising women some serious acrobatics in bed and proclaiming his gang ties. While we've yet to get either a title
(the album will also be entitled Strange Clouds) or release date for B.o.B.'s highly-anticipated sophomore album, Strange Clouds soaring up the charts will ensure both happen sooner rather than later. So how about it Booth Nation, does this one have #1 written all over it?
Written by Nathan S. on 09/25/11
Submit your Rating
Rebel Rock/Grand Hustle/Atlantic
First DJ Booth Appearance:
"Haterz Everywhere We Go (Remix)" (2007)
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09-21-2012, 11:42 AM | #31 (permalink) |
Crowned Member
Join Date: Nov 2010
Location: Wisconsin
Posts: 4,632
That's how the CGC test is...they don't have to hold her back. If you can tell your dog to stay, and hand the leash to someone else and walk away its perfectly fine. Just that they actually get a little more leeway and its not a full blown out of sight stay. The dog can switch positions...it can even stand up and walk around a bit, but the leash can't get super tight for too long I believe. So it can't look like the person is actually physically trying to prevent your dog from going to you.
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09-21-2012, 11:50 AM | #32 (permalink) |
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Join Date: Aug 2012
Posts: 2,158
If I hand the leash to someone and she feels physically restrained if I even take one step back she has a fit! lol
Yet I can do a down-stay, drop the leash and walk away with other people around in class and she's fine. I'm going to try the loose leash thing with the stay, maybe if she doesn't feel like they are taking her away, she'll be ok. She's so sweet and loves people, but holy hannah, when they try and hold her back it's like a personal tragedy for her! |
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Auto Accident Claims Life Of Football Student-Athlete, Three Others Injured
Sept. 22, 2013 CINCINNATI - University of Cincinnati football student-athlete Ben Flick (Hamilton, Ohio/Hamilton) died and Mark Barr (Fort Lauderdale, Fla./St. Thomas Aquinas) and Javon Harrison (Dayton, Ohio/Huber Hts. Wayne) were injured in a single-vehicle accident in Hanover Township Saturday night. Flick was pronounced dead at the scene. He was 19 years old. The crash occurred around 10:30 p.m. on Stahlheber Road near Morman Road in Butler County. Barr and Harrison were transported to UC Medical Center via helicopter along with the driver of the vehicle, whose name has not been released. Barr and the driver are in critical condition and Harrison is in stable condition. The three student-athletes, all true freshmen, had attended the Bearcats' 14-0 win over rival Miami (Ohio) in Yager Stadium earlier Saturday, but due to redshirting this season, did not dress or travel with the team. "I can't put into words how tragic this is," Head Coach Tommy Tuberville said. "As a father and a coach, it's something you hope you never have to go through. Ben was so proud to be a part of this team and University. He worked hard and had shown a great deal of improvement since the summer. His future was bright. Our thoughts and prayers are with the Flick family on their loss. We also hope and pray for Mark and Javon to recover from their injuries." UC Director of Athletics Whit Babcock offered support to the families and the Bearcats football team. "The Bearcats family has suffered a great tragedy," Babcock said. "All three young men are great representatives of the University and their team. Our hearts go out to all the families involved. We are doing all we can to help and support them along with the rest of our student-athletes."
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Tommy Tuberville Named 2015 AFCA President


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byMelissa Lewelling on
Sometimes technology vendors make strategic moves that create more questions than they answer. From Microsoft's foray into tablet hardware to Google and Asus teaming up on an Android tablet to Cisco's latest executive reshuffle, CRN looks at 10 recent technology stories and the questions that will still be simmering in the minds of the channel this month.
Live At XChange Solution Provider 2015
XChange Solution Provider 2015 is finally upon us and the timing couldn't be better. The premier channel event is happening March 1-3 in Dallas, bringing together 225 solution provider decision makers from across North America. CRN is at the event to provide news, analysis and a firsthand take from partners.
Here are 10 recent searches by CRN visitors.
Cloud 100


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valenciaS1 's Mom Answers Activity
How can I tell if i,m carrying twins besides an ultrasound?
Does this sound like a twin pregnancy??
Most recent answer
Mom determines twins or not, not dad. Sperm can't split or produce an egg. I say its possible you're having twins, I knew with both of my...
posted by
a BabyCenter Member


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Create a three-dimensional pumpkin or plaque, perfect for either the Halloween or Thanksgiving holiday. This piece will be an indoor or outdoor decoration. Students are encouraged to bring any of their own additions to add to their mosaic such as beads, vintage jewelry or buttons. A wide variety of fall shards will be available to cover the pumpkin which is approximately 8 inches in diameter. You will complete your project including grouting.
Instructor: Lisa Tolbert, mosaic artist
Notes: Please bring a lunch. Supplies included in registration fee. Limit 15.
Prerequisites: Beginners welcome--no art background is necessary.
Sunday, October 19, 10:00 a.m.-1:00 p.m.
Please note the location of the class has changed to:
Thornhill Education Center
Nonmembers: Fees include admission to the Arboretum.
IN PERSON: Stop by the Visitor Center during open hours.


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David Cross
- Birthday
- Apr 4, 1964
- Birthplace
- Atlanta, Georgia, USA
Irreverent comedian and social commentator David Cross has maintained a relatively low celebrity profile while at the same time working consistently in TV, film, and the live performance circuit, endearing himself to legions of fans. His smart and fearless comedy style is marked by a simultaneous honesty and cynicism that kind of goes beyond satire to… More
Irreverent comedian and social commentator David Cross has maintained a relatively low celebrity profile while at the same time working consistently in TV, film, and the live performance circuit, endearing himself to legions of fans. His smart and fearless comedy style is marked by a simultaneous honesty and cynicism that kind of goes beyond satire to somewhere else. His solo work tends to focus on topics of religion, politics, and a total refusal to skirt around any issue. Characterized by his small frame, bald head, and black glasses, his major career accomplishment has been as one-half of the HBO series Mr. Show with Bob and David. However, his memorable bit parts (Donnie, the guy who repeatedly says "Chicken Pot Pie" on NBC's Just Shoot Me) tend to stick in the imagination of the larger public.
Born in Atlanta, GA, he went to college in Boston and started doing stand-up comedy before moving out to Los Angeles. He met Bob Odenkirk while working as a writer for The Ben Stiller Show on HBO and the two joined forces to create the unique sketch comedy series Mr. Show in 1995. With Odenkirk and Cross as the original funders, writers, actors, and executive producers, the show was nominated for several Emmy awards and eventually ended in 1998. Cross made several notable TV guest appearances on The Drew Carey Show and News Radio, as well as movies like Men in Black, The Cable Guy, Ghost World, Eternal Sunshine of the Spotless Mind, and Waiting for Guffman.
As a voice actor, he worked on the Hercules animated TV series, the feature films Small Soldiers and Alvin and the Chipmunks 2: Chipwrecked. Cross also continued to appear live on-stage in various formats (often with indie pop-rockers Ultrababyfat), wrote columns for magazines, and did a Mr. Show tour with Odenkirk. In November 2002, Cross released a two-disc comedy album, Shut Up You Fucking Baby!, consisting of highly charged political rants and other solo material recorded live in concert. Cross had a particularly memorable part on the beloved comedy series Arrested Development, and would later return to the small screen, writing and starring in The Increasingly Poor Decisions of Todd Margaret.
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