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6 Indie Film Must-Sees From Sundance
2015 is shaping up to be a smorgasbord of indie cinema. Here are six films to keep an eye out for
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On the Menu at Sundance: Jonathan Gold Talks City of Gold
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Sundance 2014: The Final Tally
An Indonesian film offers a bit of the old ultra-violence, a documentary about rural Missouri wins hearts, and a British actor does a brilliant job playing a reformed L.A. gangster
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Sundance 2014: Aaron Paul's New Role, A Notorious South Korean Court Case & More Films from the First Weekend
From a slow-burn French thriller and a notorious South Korean court case to Aaron Paul's latest role and a 3D retelling of Madame Butterfly, here are six buzzworthy films from the 2014 Sundance Film Festival
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Sundance's Westward Gaze: 9 Festival Films With L.A. Links
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Beasts of the Southern Wild Now Back in Theaters
After earning four Oscar nominations, Benh Zeitlin's powerhouse indie drama Beasts of the Southern Wild will be storming its way back into theaters starting today.
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Sundance Film Festival 2013: Your L.A. Connection
Right now and for the next week, the capital of Utah is Park City. The 2013 Sundance Film Festival, which kicks off with a gala premiere tonight, takes over the rustic town and popular ski destination for the next 11 days.
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The Dead Zone Paintball Related Chat |
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11-20-2012, 08:58 PM | #41 (permalink) |
MCB Member Join Date: Apr 2006 Location: Saugus MA |
Why is this thing so large? Kingman's new pump is a fraction of this size, and in essence does the same thing, without the semi-auto feature. It looks too big, too difficult to deploy effectively and too expensive for a bolt action/mechanical gun. Practicality out the window.
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11-20-2012, 11:51 PM | #42 (permalink) |
Carmatech SAR-12 BTT #006 Join Date: Feb 2011 Location: Port Angeles, WA |
Could say the opposite about the others, Why are they so small. It is because it is.
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11-21-2012, 12:25 AM | #43 (permalink) | |
Banned Join Date: Oct 2006 | Quote:
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11-21-2012, 12:33 AM | #44 (permalink) |
Carmatech SAR-12 BTT #006 Join Date: Feb 2011 Location: Port Angeles, WA |
It's not for everyone. With Carmatech you get what you pay for hands down.
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11-21-2012, 03:04 AM | #45 (permalink) |
MCB Member Join Date: Oct 2008 Location: cleveland ohio |
Rifled barrels due spin the fs round. It's in a high speed video on YouTube. Heck paint One and push it through the barrel yourself. You'll see. It's big, it's awesome. You want small get a dam or mini.
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12-12-2012, 03:48 PM | #46 (permalink) |
firsttime 4 pb 2/4/2014 Join Date: Jan 2010 Location: The back woods of NJ |
This whole argument over barrels is pointless. I call brüno on it all.
__________________ My first paintball game was last year. I should know everything there is to know about paintball. The best marker is the one I use. I learned everything I need to know about how to fix and run a successful paintball venture from the Internet. |
02-15-2013, 01:30 PM | #47 (permalink) |
Active Member Join Date: Aug 2011 Location: Vancouver, WA |
Does any one know if the 20in HammerHead rifled barrel will be sold in A/C threads? I looked on hammerheads website and couldn't find it and i'm thinking it wont be available with out buying the SAR12. Reason im wondering is i might pick up a empire trracer and throw the 20in on it and just breach load. I'm thinking if i can engage targets accuratly at 75 yards I can spare the reload time.
02-15-2013, 01:33 PM | #48 (permalink) |
Tug Contest Winner Join Date: Aug 2012 Location: Calgary, Alberta |
You can buy the SAR-12 barrel seperately through Carmatech's new website, Products | Carmatech Engineering It is AC threaded, but be prepared - it's a bit spendy! |
02-17-2013, 06:46 PM | #49 (permalink) | |
all work Join Date: Jan 2011 | Quote:
I'd always figured you went with the long barrel on account of a low pressure high volume design. | |
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SanDisk unveils microSD card with a whopping 200GB capacity Moore's Law is an amazing thing, folks. Yesterday, SanDisk announced its latest high-capacity Ultra-branded microSDXC card, which crams 200GB of storage into a card... Type: News story Tags: Storage Memory Mobile computing |
38 |
Unreal Engine 4 now free for everyone Free-to-play games are all the rage these days, so it's only fitting that development tools appear to be headed in the same direction. Epic Type: News story Tags: Gaming Software |
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Tiny PowerVR G6020 GPU targets 720p phones, wearables Along with its new H.265 encoders, Imagination Tech also announced a new PowerVR GPU at the Mobile World Congress this morning. The PowerVR G6020... Type: News story Tags: Graphics Mobile computing Personal tech |
3 |
New PowerVR H.265 encoders promise big efficiency gains Imagination Technologies is unveiling new products at the Mobile World Congress this week. Among them: the PowerVR Series5 family of video encoders, which are designed... Type: News story Tags: Graphics Multimedia |
18 |
HTC announces Vive headset powered by Steam VR When we heard Valve was planning to make some virtual-reality-related announcements around this week's Game Developer's Conference, I didn't expect to see the first part... Type: News story Tags: Graphics Displays Gaming |
53 |
Deal of the week: Radeons, mechanical keyboards, IPS displays, and more The deal gods are smiling upon us today. We've got some nice bargains on a Radeon R9 290 graphics card, a mechanical keyboard, and an... Type: News story Tags: Graphics Storage Displays Input devices |
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Windows 10 to support USB 3.1 Type-C's new features USB 3.1 Type-C is coming, and Microsoft looks to be ready for it. As Neowin reports, the outline of a session from next month's... Type: News story Tags: Storage Input devices Windows |
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The TR Podcast 171 video is now available via YouTube Last night's live stream was a lot of fun once we got going. We talked about Nvidia being in hot water, the excellence of the... Type: News story Tags: CPUs Graphics Cases Podcast |
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Crucial's BX100 and MX200 solid-state drives reviewed Crucial makes some of the most popular SSDs around, so we were eager to get our hands on its latest creations. The MX200 features... Type: Feature article Tags: Storage |
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Nvidia CEO on GTX 970 controversy: 'We won't let this happen again' Jen-Hsun Huang, Nvidia's CEO, has spoken out on the recent controversy... Type: News story Tags: Graphics |
128 |
Nvidia faces class-action lawsuit over GTX 970 memory issue Lenovo isn't the only one facing a possible class-action suit. As PC World reports, Nvidia is also the subject of legal ire over... Type: News story Tags: Graphics |
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Lenovo posts Superfish removal tool; user files lawsuit The Superfish saga continues. In its latest statement about the vulnerability, Lenovo has provided a link to an "automated removal tool" that can rid users... Type: News story Tags: Systems Software |
39 |
The rest of the story: Komodia, Lenovo, and Superfish It's always a busy month in the field of security. This month has seen its share... Type: News story Tags: Software |
68 |
Samsung investigating 840 EVO slowdowns, prepping another fix Last month, we reported that some Samsung 840 EVO SSDs are still experiencing slow read speeds with old data. The issue was supposedly fixed... Type: News story Tags: Storage |
98 |
The TR Podcast 170.5: The Heimlich maneuver Last night's stream with Paul Heimlich was lots of fun. Thanks again to everybody who joined us live and participated via the chat. We talked about... Type: Feature article Tags: Displays Software The Tech Report Podcast |
9 |
Say hello to TR's new storage test rigs For years, we've been testing storage performance on a pair of P67 motherboards equipped with Sandy Bridge processors. The machines have served us well, but... Type: News story Tags: Storage |
29 |
Deal of the week: A Bay Trail netbook for only $150 Another week, another lame introductory sentence for our bulleted list of sweet PC hardware deals. Forget Chromebooks. Staples is selling Asus' 11.6" X205TA netbook for Type: News story Tags: Graphics Storage Memory Mobile computing |
42 |
Lenovo CTO laments 'mistake,' promises Superfish removal utility Following the furore over the Superfish snafu, Lenovo is now in full damage-control mode. Speaking to... Type: News story Tags: Systems Software |
64 |
Monitors with AMD's FreeSync tech now available in select regions | 52 |
And Samsung makes new phone with no sd slot lol whaw whaw whaw | +59 |


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Hey everyone. I have a few questions regarding infections, but first the backstory. I brewed a Saison a few months ago, which I had many complications with such a unreliable temperature control and stuck fermentation. Long story short, the Saison was sour, very sour. I didn't realize this until after I brewed an Oktoberfest, which I racked into the primary with the same racking cane (sanitized in Star-San as usual) I used for the Saison. The Oktoberfest took about 36 hours for fermentation to go crazy, but I pitched 200 billion cells for 5 gallons at 58F then it was brought down to 47F, so the slow start seemed normal. It has been 2 weeks exactly and the beer is at the intended FG and my reading indicate it is done fermenting. However, it doesn't really taste right. I think it kinda tastes sour and a bit watery. I don't know if I'm actually tastes tartness or not. I also do not have a LHBS to go get an opinion. So my questions are: 1. How long does an infection take to develop and produce enough flavors to detect? 2. Can an infection continue to produce flavors even if there are no more sugars left to eat? 3. There was definitely a watered down-ness to beer, where could this come from? P.S. The beer was in a brand new carboy as well. Thanks for the help.
You might be tasting a lot of things that can be perceived as sour. It could be tannins due to a ph issue or even suspended yeast. Lagers take a great deal of time to even out. I have had lagers that I thought about dumping only to later have them score very will at competition. The beer tasted like crap early. Just give it lots of time to cold condition. You may have an infection......however, an infection usually would in my opinion, give a more vinegary taste. Judging a lager young is tough to do.
BL, CL, Miller etc. is like makin love in a canoe..... its fkin close to water. Lagering/conditioning: German pils, Dortmunder Lagering:Kolsch, Dusseldorf alt American Amber, Red ale Double ipa, Rye ipa Fermenting: German pils Wheat 1,Wheat 2 All to be kegged and served by May 10
Some saison strains contain brettanomyces. This could be giving you the tartness. People who routinely make sour beers will have separate carboys and racking canes so that the brett does not cross contaminate. Since normal sanitization will not kill brett. Maybe this it? Not sure about the watered down issue though.
Thanks for the replies. Reinstone, what kind of ph issues could there be? I have not learned a lot about ph yet. two one seven, I used wyeast 3724 in the saison do you know if this strain has brett in it? I believe it is Duponts strain.
That one doesn't I believe. You could have picked up a wild one perhaps.
Yep Brett is a yeast so the acid based sanitizers don't touch it. There are ways to get rid of it but it involves different methods.
The high ph could definitely be the problem. I did a little research on ph during the mash and learned some good stuff. I didn't pay attention to ph at all in any of my brews, so I don't really have any way of knowing what went wrong. Next time for sure though, I will check the ph and adjust. Another thing I read was that it takes a long time to get rid of the sulfur smell in lagers. Could this "Sulfur" be tasted? Maybe thats also contributing to the weird flavor.
Up Next: Irish Red Ale Primary: Empty Secondary: Oktoberfest, Hippies an' Hillbillies Cal-tuckey Cream Lager Bottled: All out Kegged: Drained dry
It could be a lot of things. I'd give it more time.


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8 Nancy Ct, Wappingers Falls, NY 12590
Earth Angels Veterinary Hospital is a small animal Integrative facility where Dr. Alexandra Barrientos and her staff practice a blend of the finest in alternative and conventional veterinary medicine for our canine, feline, exotic and pocket-pet patients. Earth Angels Veterinary Hospital's
view deal230 Main Street, New Paltz, NY 12561
Welcome to New Paltz Animal Hospital, the premier provider of complete veterinary care for your pet. New Paltz Animal Hospital has been serving New Paltz and the surrounding communities since 1986. Our veterinarians have established a reputation for high quality medicine, compassionate care, and
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Veterinary Specialty and Emergency Care Expert Medicine & Surgery, More Options, More Hope The Veterinary Specialty Center of the Hudson Valley was created to provide an extension of your veterinarian's medical and surgical services. We offer advanced diagnostics and therapeutics with services
2485 Route 9G, Staatsburg, NY 12580
Countryside Animal Hospital provides professional veterinary care in the Staatsburg, NY area. It is our goal to do everything possible to assure that your animal companion lives a long, healthy, and happy life. Countryside Animal Hospital's Services Include: Annual examinations Vaccinations
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Dr. Tamara McArdle, and the entire Roosevelt Vet on the Husdon team knows how important your pets are to you. Your pet brings love, joy and affection into your life and as a full service veterinary hospital we're here to provide high quality care with the utmost compassion. We serve the Beacon
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Welcome to the home of Dr Michele Yasson and HolVet : Holistic Veterinary Services. I offer homeopathy, very species specific and individually customized diet, natural supplements, acupuncture, as well as Neoplasene for cancer cases. I can never guarantee results, but I generally achieve
view deal156 Old Little Britain Rd, Newburgh, NY 12550
Banfield is a convenient, affordable and wise choice for all of your Pet's healthcare needs. We take an innovative and caring approach to healthcare that enables us to consistently provide Pets with the same level of care we want for ourselves. In keeping with our commitment to quality, each


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People who take aspirin for many years - heart patients, for example - are more likely to develop a certain kind of blindness, revealed scientists at the University of Sydney, Australia. The results were published Jan. 21 in the journal JAMA Internal Medicine.
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Open AccessThis article is
MDPI and ACS Style
- freely available
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Int. J. Mol. Sci. 2011, 12(1), 78-113; doi:10.3390/ijms12010078
Cell Surface Markers in Colorectal Cancer Prognosis
Received: 30 November 2010 / Revised: 16 December 2010 / Accepted: 20 December 2010 / Published: 28 December 2010
(This article belongs to the Special Issue Biomarkers)
Abstract: The classification of colorectal cancers (CRC) is currently based largely on histologically determined tumour characteristics, such as differentiation status and tumour stage, i.e., depth of tumour invasion, involvement of regional lymph nodes and the occurrence of metastatic spread to other organs. These are the conventional prognostic factors for patient survival and often determine the requirement for adjuvant therapy after surgical resection of the primary tumour. However, patients with the same CRC stage can have very different disease-related outcomes. For some, surgical removal of early-stage tumours leads to full recovery, while for others, disease recurrence and metastasis may occur regardless of adjuvant therapy. It is therefore important to understand the molecular processes that lead to disease progression and metastasis and to find more reliable prognostic markers and novel targets for therapy. This review focuses on cell surface proteins that correlate with tumour progression, metastasis and patient outcome, and discusses some of the challenges in finding prognostic protein markers in CRC.
colorectal cancer; biomarkers; proteomics; prognostic
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Belov, L.; Zhou, J.; Christopherson, R.I. Cell Surface Markers in Colorectal Cancer Prognosis. Int. J. Mol. Sci. 2011, 12, 78-113.
AMA StyleBelov L, Zhou J, Christopherson RI. Cell Surface Markers in Colorectal Cancer Prognosis. International Journal of Molecular Sciences. 2011; 12(1):78-113.
Chicago/Turabian StyleBelov, Larissa; Zhou, Jerry; Christopherson, Richard I. 2011. "Cell Surface Markers in Colorectal Cancer Prognosis." Int. J. Mol. Sci. 12, no. 1: 78-113.
Int. J. Mol. Sci.
Published by MDPI AG, Basel, Switzerland
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US 20070200180 A1 Abstract An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or ōstripsö (or ōstripesö). This provides having two physically separated charge storage regions (nitride ōstripsö, or ōstripesö) in each memory cell.
Claims(21) 1. A method of making a non-volatile memory (NVM) cell comprising:
providing an ONO layer comprising a bottom layer of oxide (O), a layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate; processing the ONO layer to create a number (n) of individual ONO stacks; processing the ONO stacks so as to separate at least the nitride layers of the stacks into two distinct portions; and forming a given memory cell from a portion of one stack and a portion of an adjacent (neighboring) stack. 2. The method of
3. The method of
when separating the ONO stacks, leaving the bottom layer of oxide in place. 4. The method of
using a nitride mask having openings and an etch process to create the individual ONO stacks. 5. The method of
depositing a layer of oxide in the openings of the nitride mask, thereby reducing the size of the openings. 6. The method of
filling the openings with poly. 7. The method of
removing remnants of the nitride mask, leaving poly structures having their sidewalls covered by the oxide which was deposited in the openings of the nitride mask. 8. The method of
stripping the oxide from the sidewalls of the poly structures. 9. The method of
depositing and processing a poly liner to form poly sidewalls on the poly structures. 10. The method of
removing exposed portions of the ONO layer between adjacent poly structures. 11. The method of
implanting bitline diffusions. 12. The method of
prior to processing the ONO layer to create the individual ONO stacks, depositing at least one sacrificial layer atop the ONO layer. 13. The method of
a layer of poly. 14. The method of
a layer of sacrificial poly followed by a layer of sacrificial oxide. 15. The method of
in a subsequent processing step, removing substantially all of the layer of sacrificial oxide. 16. The method of
in a subsequent processing step, removing all but a portion of the layer of sacrificial poly. 17. A method of making a non-volatile memory (NVM) cell comprising:
providing an ONO layer comprising a bottom layer of oxide (O), an layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate; depositing sacrificial layers of material on the ONO layer; processing the ONO layer and sacrificial layers to create a number (n) of individual ONO stacks covered by sacrificial layers; processing the ONO stacks so as to separate each ONO stack into two portions; and forming a given memory cell from a portion of one ONO stack and a portion of an adjacent (neighboring) ONO stack. 18. The method of
19. Non-volatile memory (NVM) cell comprising:
an ONO layer disposed on a semiconductor substrate and comprising a plurality (n) of ONO stacks; and for a given memory cell, a gate formed atop a portion of a given ONO stack and an adjacent portion of another ONO stack. 20. The NVM cell of
vestiges of a sacrificial poly layer on outer edges of the ONO stacks. 21. The NVM cell of
the NVM cell is an NROM cell. Description This application is a continuation-in-part application claiming benefit from U.S. patent application Ser. No. 11/489,327, filed Jul. 18, 2006 which is hereby incorporated by reference. This application claims the benefit of U.S. Provisional Application No. 60/777,114, filed Feb. 28, 2006, the entire disclosure of which is incorporated herein by reference. The disclosure relates to techniques for fabricating semiconductor devices and, more particularly, to nitride read only memory (NROM) or other microelectronic cells or structures. The Field Effect Transistor The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain. Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a ōfield effectö in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain). The Floating Gate Transistor A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate. Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a ōconductorö). Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow. Generally, if a charge is stored on the floating gate, this represents a binary ō1ö. If no charge is stored on the floating gate, this represents a binary ō0ö. (These designations are arbitrary, and can be reversed so that the charged state represents binary ō0ö and the discharged state represents binary ō1ö.) That represents the programming ōhalfö of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gateŚin other words, to ōreadö the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow. Normally, the floating gate non-volatile memory (NVM) cell has only a single ōcharge-storing areaöŚnamely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary ō1ö or binary ō0ö). More recently, using a technology referred to as ōmulti-level cellö (MLC), two or more bits can be stored in and read from the floating gate cell. The NROM Memory Cell Another type of memory cell, called a ōnitride, read only memoryö (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being flee to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary ō1ö or binary ō0ö) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary ō1ö or binary ō0ö) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified. The ONO structure is a stack (or ōsandwichö) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316. In The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322. The memory cell 300 is generally capable of storing at least two bits of dataŚat least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two ōhalf cellsö, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term ōhalf cellö, as it may be used herein, is used herein only to refer to the ōleftö or ōrightö bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as ōcharge storage areasö, ōcharge trapping areasö, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left ōbitsö.) Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove ( Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary ō1ö, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary ō0ö. (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary ō0ö and the discharged state represents binary ō1ö,) That represents the programming ōhalfö of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping materialŚin other words, to ōreadö the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is. Generally, one feature of NROM cells is that rather than performing ōsymmetricalö programming and reading, NROM cells are beneficially programmed and read ōasymmetricallyö, which means that programming and reading occur in opposite directions. The arrows labeled in ōReadingö an NROM Cell Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing ōsymmetricalö programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read ōasymmetricallyö, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in Memory Array Architecture, Generally Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom). As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated ōsourceö) of a plurality of memory cells are connected to a first bit line which may be designated ōBL(n)ö, and second diffusions (usually designated ōdrainö) of the plurality of memory cells are connected to a second bit line which may be designated ōBL(n+1)ö. Typically, the gates of a plurality of memory cells are connected to common word lines (WL). The bitlines may be ōburied bitlineö diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells. Notice, for example that the gates of the memory cells ōeö and ōfö (to the right of ōeö) are both connected to the same word line WL(n). (The gate of the memory cell ōdö to the left of ōeö is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell ōeö is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell ōfö. In this example, the memory cells ōeö and ōfö have two of their three terminals connected together. The situation of neighboring memory cells sharing the same connectionŚthe gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cellŚis even more dramatically evident in what is called ōvirtual ground architectureö wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein. Secondary Injection, and Managing Far From Junction Injection Generally, NVM cells (both floating gate and ONO-based) are programmed by injecting electrons into the charge storage medium, such as the conductive floating gate of a floating gate memory cell, or the bit storage areas of the charge trapping layer (typically nitride) of an ONO-based memory cell. A common mechanism for injecting electrons is channel hot electron (CHE) injection. Generally, in order to implement CHE injection of electrons into the charge storage medium, the source may be grounded, the drain may be set to a positive voltage (which will ōattractö electrons from the source, laterally across the channel region), and the gate is also set to a positive voltage (which will ōattractö electrons vertically through the tunnel oxide or bottom oxide of the ONO, into the charge storage medium). As electrons flow through the channel from source to drain, some of the electrons will make their way through the tunnel oxide (of floating gate) or bottom oxide (of ONO) and become stored in the charge storage medium. This injection of electrons into the charge storage medium increases the threshold voltage of the memory cell. The threshold voltage (Vt) of the memory cell can later be measured, or ōreadö. The NROM cell can store charges in two separate (sometimes referred to as ōleftö and ōrightö) bit storage regions 321 and 323 of the charge-trapping layer 324. Depending on which bit (storage region) is desired to be programmed, the left and right diffusion regions 314 and 316 can act as source and drain, or as drain and source. The left and right bit storage areas are generally above and adjacent to the respective left and right diffusion regions (or ōjunctionsö). The gate always functions as the gate. It is important to manage the injection of electrons in an NROM cell, so that (for example) when programming the right bit, most of the electrons are injected into the right bit storage region (and conversely, when programming the left bit, most of the electrons are injected into the left bit storage region). Else, there can be effects resulting from ōfar from junctionö electrons, discussed hereinbelow. With CHE programming, the situation is generally well characterized (under control). A byproduct of CHE injection of electrons in NVM memory cells can be what is called ōsecondary injectionö, or ōsecondary electron injectionö, and may be abbreviated ōSEIö. Generally, the ōprimaryö channel electrons (e1), as they accelerate from source to drain, impact valence electrons in the channel, next to the drain, ionizing valence elections in the substrate, and resulting in the generation (creation) of electron/hole pairs (e2/h2). The generated electrons e2 may be collected by the drain. However, the generated holes h2 may accelerate towards the low substrate potential Vb of the substrate, back under the channel region. Within the substrate, another impact ionization may occur, this time between holes h2 and valence electrons, creating another electron/hole pair e3/h3. Holes h3 are pulled further into substrate, and are generally of no concern. However, electrons e3, called secondary electrons, may be accelerated towards the positive gate potential Vg of the gate and, if they have gained sufficient energy, they can be injected into the charge storage medium. The generation and injection of secondary electrons can be of great benefit to a floating gate memory cell, but generally causes problems for an NROM memory cell, because it has proven itself to be difficult to controlŚelectrons injected far from the junction cause problems with reading, and retention. The phenomenon of the generation of secondary electrons and problems associated with their injection into the charge storage areas (see 321, 323,
The '063 patent, for example, discloses techniques for decoupling injection of channel hot electrons into a charge trapping layer of an NROM cell from injection of non-channel (secondary) elections into the charge trapping layer, as well as for minimizing the generation of the non-channel (secondary) electrons. As disclosed therein, secondary injection reduces the performance of NROM cells because secondary electrons are injected far from the bit line junctions. These secondary electrons are not removable during erasure and thus, reduce the ability of the NROM cell to separate between the two charge storage areas. The '007 patent, for example, discloses methods and apparatus for managing and reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices, and also discloses methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer. The problem of far from junction injection can occur with both CHE injection and secondary injection of electons, and boils down to non-localization of charge in the ONO nitride layer (324). The solutions set forth in the '063 and '007 patents are exemplary of techniques for trying to control the injection point of secondary and hot electron injection. However, the charge location is difficult to control since the injection of hot and secondary electrons can have a wide distribution (ōwideö equates with ōfar from junctionö). Another, what one might deem ōobviousö solution, is to physically separate the nitride charge storage layer (324) into two pieces, strips, or stripes. Such a physical solution, of course, involves elaborate processing steps to accomplish and, if it takes up more space, may tend to be self-defeating (generally speaking, there would be limited benefit to making a memory cell perform better, if it needs to be larger). A technique for decreasing charge distribution and diffusion during and after CHE injection is discussed in Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate, Lee et al., (Samsung), Solid State Electronics 48 (2004), pp 1771-1775, incorporated by reference in its entirety herein. Generally, the nitride layer (the whole ONO stack) is formed in two distinct sections (may be referred to as ōstripsö, or ōstripesö), rather than as one single planar structure, under the gate. Although the ōbrute forceö approach discussed in the article may provide good 2 bit separation (for either CHE or SEI), it is a complicated process which may result in a non-uniform (thickness and characteristics) ONO stack. Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387. Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496. Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750. Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084. Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007. Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896. A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at ōNon Volatile Memory Technologyö, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety. Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks («). anisotropic literally, one directional. An example of an anisotropic process is sunbathing. Only surfaces of the body exposed to the sun become tanned. (see ōisotropicö). bit The word ōbitö is a shortening of the words ōbinary digit.ö A bit refers to a digit in the binary numeral system (base 2). A given bit is either a binary ō1ö or ō0ö. For example, the number 1001011 is 7 bits long. The unit is sometimes abbreviated to ōbö. Terms for large quantities of bits can be formed using the standard range of prefixes, such as kilobit (Kbit), megabit (Mbit) and gigabit (Gbit). A typical unit of 8 bits is called a Byte, and the basic unit for 128 Bytes to 16K Bytes is treated as a ōpageö. That is the ōmathematicalö definition of ōbitö. In some cases, the actual (physical) left and right charge storage areas of a NROM cell are conveniently referred to as the left ōbitö and the right ōbitö, even though they may store more than one binary bit (with MLC, each storage area can store at least two binary bits). The intended meaning of ōbitö (mathematical or physical) should be apparent from the context in which it is used. bit line or bitline (BL). A conductor connected to (or which may actually be) the drain (or source) of a memory cell transistor. byte A byte is commonly used as a unit of storage measurement in computers, regardless of the type of data being stored. It is also one of the basic integral data types in many programming languages. A byte is a contiguous sequence of a fixed number of binary bits. In recent years, the use of a byte to mean 8 bits is nearly ubiquitous. The unit is sometimes abbreviated to ōBö. Terms for large quantities of Bytes can be formed using the standard range of prefixes, e.g., kilobyte (KB), megabyte (MB) and gigabyte (GB). cap a term used to describe layers of a material disposed over another, dissimilar material, typically to protect the underlying material from damage during subsequent processing steps. A cap may be left in place, or removed, depending upon the situation. Cell Well (CW) the cell well is an area in the silicon substrate that is prepared for functioning as a transistor or memory cell device by doping with an electron acceptor material such as boron or indium (p, electron acceptors or holes) or with an electron donor material such as phosphorous or arsenic (n, electron donors). The depth of a cell well is defined by the depth of the dopant distribution. CHEI short for channel hot electron injection. sometimes abbreviated ōCHEö. CHISEL short for channel initiated secondary electron. CMOS short for complementary metal oxide semiconductor. CMOS consists of n-channel and p-channel MOS transistors. Due to very low power consumption and dissipation as well minimization of the current in ōoffö state CMOS is a very effective device configuration for implementation of digital functions. CMOS is a key device in state-of-the-art silicon microelectronics.
CMP short for chemical-mechanical polishing. CMP is a process, using both chemicals and abrasives, comparable to lapping, for removing material from a built up structure, resulting in a particularly planar resulting structure. Dopant element introduced into semiconductor to establish either p-type (acceptors) or n-type (donors) conductivity; common dopants in silicon: p-type, boron, B, Indium, In; n-type phosphorous, P, arsenic, As, antimony, Sb. EEPROM short for electrically erasable, programmable read only memory. EEPROMs have the advantage of being able to selectively erase any part of the chip without the need to erase the entire chip and without the need to remove the chip from the circuit. The minimum erase unit is 1 Byte and more typically a full Page. While an erase and rewrite of a location appears nearly instantaneous to the user, the write process is usually slightly slower than the read process; the chip can usually be read at full system speeds. EPROM short for erasable, programmable read only memory. EPROM is a memory cell in which information (data) can be erased and replaced with new information (data). Erase a method to erase data on a large set of bits in the array, by applying voltage scheme that inject holes or remove electrons in the bit set. This method causes all bits to reach a low Vt level. FET short for field effect transistor. The FET is a transistor that relies on an electric field to control the shape and hence the conductivity of a ōchannelö in a semiconductor material. FETs are sometimes used as voltage-controlled resistors. The terminals of FETs are called gate, drain and source. Flash memory Flash memory is a form of non-volatile memory (EEPROM) that can be electrically erased and reprogrammed. Flash memory architecture allows multiple memory locations to be erased or written in one programming operation. FN tunneling Field emissionŚalso called Fowler-Nordheim tunnelingŚis the process whereby electrons tunnel through a barrier in the presence of a high electric field. This quantum mechanical tunneling process is an important mechanism for thin barriers as those in metal-semiconductor junctions on highly-doped semiconductors. Using FN tunneling, electrons can be moved to the floating gate of a MOSFET memory cell. half cell this term is sometimes used to refer to the two distinct charge storage areas (left and right bits) of an NROM memory cell. HHI short for hot hole injection isotropic literally, identical in all directions. An example of an isotropic process is dissolving a tablet in water. All exposed surfaces of the tablet are uniformly acted upon. (see ōanisotropicö) mask a layer of material which is applied over an underlying layer of material, and patterned to have openings, so that the underlying layer can be processed where there are openings. After processing the underlying layer, the mask may be removed. Common masking materials are photoresist and nitride. Nitride is usually considered to be a ōhard maskö. MLC short for multi-level cell. In the context of a floating gate (FG) memory cell, MLC means that at least two bits of information can be stored in the memory cell. In the context of an NROM memory cell, MLC means that at least four bits of information can be stored in the memory cellŚat least two bits in each of the two charge storage areas. MOS short for metal oxide semiconductor. MOSFET short for metal oxide semiconductor field-effect transistor. MOSFET is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material, and is accordingly called an NMOSFET or a PMOSFET. (The æmetalÆ in the name is an anachronism from early chips where gates were metal; modern chips use polysilicon gates, but are still called MOSFETs). nitride commonly used to refer to silicon nitride (chemical formula Si3N4). A dielectric material commonly used in integrated circuit manufacturing. Forms an excellent mask (barrier) against oxidation of silicon (Si). Nitride is commonly used as a hard mask or, in the case of a NVM memory cell having an ONO layer as a charge-trapping material. n-type semiconductor in which concentration of electrons is higher than the concentration of ōholesö. See p-type. NROM short for nitride read only memory. NVM short for non-volatile memory. NVM is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy disk drives, and magnetic tape), optical disc drives, and early computer storage methods such as paper tape and punch cards. Non-volatile memory is typically used for the task of secondary storage, or long-term persistent storage. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. Unfortunately most forms of non-volatile memory have limitations which make it unsuitable for use as primary storage. Typically non-volatile memory either costs more or performs worse than volatile random access memory. (By analogy, the simplest form of a NVM memory cell is a simple light switch. Indeed, such a switch can be set to one of two (binary) positions, and ōmemorizeö that position.) ONO short for oxide-nitride-oxide. ONO is used as a charge storage insulator consisting of a sandwich of thermally insulating oxide, and charge-trapping nitride. oxide commonly used to refer to silicon dioxide (SiO2). Also known as silica. SiO2 is the most common insulator in semiconductor device technology, particularly in silicon MOS/CMOS where it is used as a gate dielectric (gate oxide); high quality films are obtained by thermal oxidation of silicon. Thermal SiO2 forms a smooth, low-defect interface with Si, and can be also readily deposited by CVD. Some particular applications of oxide are:
Poly short for polycrystalline silicon (Si). Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices; p-type semiconductor in which concentration of ōholesö is higher than the concentration of electrons. See n-type. Examples of p-type silicon include silicon doped (enhanced) with boron (B), Indium (In) and the like. Program a method to program a memory cells, or half cells, typically by applying a voltage scheme that injects electrons to increase the Vt of the cells or half cells being programmed. PROM short for programmable read-only memory. RAM short for random access memory. RAM refers to data storage formats and equipment that allow the stored data to be accessed in any orderŚthat is, at random, not just in sequence. In contrast, other types of memory devices (such as magnetic tapes, disks, and drums) can access data on the storage medium only in a predetermined order due to constraints in their mechanical design. Read a method to read the digital data stored in a memory cell. resist short for photoresist. also abbreviated ōPRö. Photoresist is often used as a masking material in photolithographic processes to reproduce either a positive or a negative image on a structure, prior to etching (removal of material which is not masked). PR is usually washed off after having served its purpose as a masking material. ROM short for read-only memory. SEI short for secondary electron injection (or simply ōsecondary injectionö). SEI occurs as a result of impact ionization by CHE electrons (e1) near the drain diffusion, generating an electron-hole pair (e2-h2), the hole (h2) of which continues into the substrate whereat another impact ionization results in another electron-hole pair (e3-h3), and the e3 electron becomes injected into the charge storage area(s) of the memory cell. Si Silicon, a semiconductor. SLC short for single level cell. In the context of a floating gate (FG) memory cell, SLC means that one bit of information can be stored in the memory cell. In the context of an NROM memory cell, SLC means that at least two bits of information can be stored in the memory cell. SONOS Si-Oxide-Nitride-Oxide-Si, another way to describe ONO with the Si underneath and the Poly gate on top. spacer a spacer, as the name implies, is a material (such as a layer of oxide) disposed on an element (such as a poly gate electrode). For example, sidewall spacers disposed on sides of a gate electrode cause subsequent implants to occur further away from the gate than otherwise (without the spacers in place). STI short for shallow trench isolation TEHH short for Tunnel Enhanced Hot Hole injection. TEHH is an ōinjection mechanismö. Units of Length Various units of length may be used herein, as follows:
Voltage abbreviated v, or V. A voltage can be positive or negative (or zero). Usually, a negative voltage is preceeded by a minus sign (−). Sometimes a positive voltage is preceeded by a plus sign (+), or no sign at all. A number of voltages are relevant with regard to operating a memory cell, and are typically designated by the capital letter ōVö, followed by another letter or letters. Some exemplary voltages of interest are are:
word line or wordline, (WL). A conductor normally connected to the gate of a memory cell transistor. The wordline may actually be the gate electrode of the memory cell. write a combined method of first erase a large set of bits, then program a new data into the bit set. In addition to the above, some abbreviations that may be used herein, or in a provisional application from which this non-provisional application claims priority, include:
According to the disclosure, generally, an NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or ōstripsö (or ōstripesö). According to the disclosure, a method of making a non-volatile memory (NVM) cell comprises: providing an ONO layer comprising a bottom layer of oxide (O), a layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate; processing the ONO layer to create a number (n) of individual ONO stacks; processing the ONO stacks so as to separate at least the nitride layers of the stacks into two distinct portions; and forming a given memory cell from a portion of one stack and a portion of an adjacent (neighboring) stack. The NVM cell may be an NROM cell. When separating the ONO stacks, the bottom layer of oxide may be left in place. A nitride mask having openings and an etch process may be used to create the individual ONO stacks. A layer of oxide may be deposited in the openings of the nitride mask, to reduce the size of the openings. And, the openings may be filled with poly. Removing remnants of the nitride mask may leave poly structures having their sidewalls covered by the oxide which was deposited in the openings of the nitride mask. The oxide may be stripped from the sidewalls of the poly structures. A poly liner may be deposited and processed to form poly sidewalls on the poly structures. According to the disclosure, a method of making a non-volatile memory (NVM) cell comprises: providing an ONO layer comprising a bottom layer of oxide (O), an layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate; depositing sacrificial layers of material on the ONO layer; processing the ONO layer and sacrificial layers to create a number (n) of individual ONO stacks covered by sacrificial layers; processing the ONO stacks so as to separate each ONO stack into two portions; and forming a given memory cell from a portion of one ONO stack and a portion of an adjacent (neighboring) ONO stack. According to the disclosure, a non-volatile memory (NVM) cell comprises: an ONO layer disposed on a semiconductor substrate and comprising a plurality (n) of ONO stacks; and for a given memory cell, a gate formed atop a portion of a given ONO stack and an adjacent portion of another ONO stack. Vestiges of a sacrificial poly layer may remain on outer edges of the ONO stacks. The NVM cell may be an NROM cell. Reference will be made in detail to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawing figures (FIGs). The figures are intended to be illustrative, not limiting. Although the disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the disclosure to these particular embodiments. Certain elements in selected ones of the figures may be illustrated not-to-scale, for illustrative clarity. The cross-sectional views, if any, presented herein may be in the form of ōslicesö, or ōnear-sightedö cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity. In some cases, hidden lines may be drawn as dashed lines (this is conventional), but in other cases they may be drawn as solid lines. If shading or cross-hatching is used, it is intended to be of use in distinguishing one element from another (such as a cross-hatched element from a neighboring un-shaded element. It should be understood that it is not intended to limit the disclosure due to shading or cross-hatching in the drawing figures. Elements of the figures may (or may not) be numbered as follows. The most significant digits (hundreds) of the reference number correspond to the figure number. For example, elements of Throughout the descriptions set forth in this disclosure, lowercase numbers or letters may be used, instead of subscripts. For example Vg could be written Vg. Generally, lowercase is preferred to maintain uniform font size.) Regarding the use of subscripts (in the drawings, as well as throughout the text of this document), sometimes a character (letter or numeral) is written as a subscriptŚsmaller, and lower than the character (typically a letter) preceding it, such as ōVsö (source voltage) or ōH2Oö (water). For consistency of font size, such acronyms may be written in regular font, without subscripting, using uppercase and lowercaseŚfor example ōVsö and ōH20ö. Conventional electronic components may be labeled with conventional schematic-style references comprising a letter (such as A, C, Q, R) indicating the type of electronic component (such as amplifier, capacitor, transistor, resistor, respectively) followed by a number indicating the iteration of that element (such as ō1ö meaning a first of typically several of a given type of electronic component). Components such as resistors and capacitors typically have two terminals, which may be referred to herein as ōendsö. In some instances, ōsignalsö are referred to, and reference numerals may point to lines that carry said signals. In the schematic diagrams, the various electronic components are connected to one another, as shown. Usually, lines in a schematic diagram which cross over one another and there is a dot at the intersection of the two lines are connected with one another, else (if there is no dot at the intersection) they are typically not connected with one another. As discussed hereinabove, with reference to Generally, the purpose of an ōinjection mechanismö is to cause electrons to be injected, into the charge storage areas of the NROM cell, and controlled so that when electrons are being injected into a given one of the charge storage areas, the electrons are injected into the charge storage area close to the diffusion, and as few as possible electrons are injected far from the junction. Channel hot electron (CHE) injection of electrons can be fairly well controlled to minimize far-from-junction injection. However, secondary injection of electrons (SIE) is known to be difficult to control, causing undesirable far-from-junction injection. See, for example, U.S. Pat. Nos. 6,429,063 and 6,583,007 for a more detailed discussion of secondary injection in NROM cells. In a very general sense, one solution to the problem of far-from-junction is to separate the nitride layer of the ONO stack into two strips, separated by (for example) oxide (an insulating material), so that there is no charge-trapping material ōfar from the junctionö, and in this manner, problems such as second bit effect and RAC can be minimized or avoided. (As used herein, ōfar from the junctionö means partway across the ONO stack to the other bit storage area. Of course, all the way on the other side of the cell is the other nitride strip.) See, for example, Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate, Lee et al., Solid State Electronics 48 (2004), pp 1771-1775, incorporated by reference herein in its entirety. Generally, the process of making an ONO-based NVM cell, such as NROM, starts by laying down the ONO layers, then etching away portions of the top oxide and nitride (often the bottom oxide is left in place, to protect underlying silicon), resulting in a plurality (N) of ONO stacks separated from one another (although the bottom oxide may be continuous across all of the ONO stacks). For example, the width of a given ONO stack may be 13 nm, and the space between adjacent ONO stacks may be 12 nm. Generally, in the approach suggested by the article (ōScalable 2-bit . . . ö) a damascene gate process method is used, which implies that after forming the ONO stacks, a middle portion of the stack is removed, leaving two nitride strips separated by a trench. Then, a modified gate structure is formed atop the two separated nitride strips. Generally, to achieve an effective result using the technique of According to this disclosure, a different, less difficult, more effective technique is used to create nitride strips. Generally, the broad purpose is the same as othersŚnamely, having two physically separated charge storage regions in each memory cell. Generally, according to the technique of this disclosure, after the ONO stacks (such as A, B, C) are formed, they are split into two separate strips. A gate (GATE D) is formed atop a right half (such as A-R) of one ONO stack (such as A), and the left half (such as B-L) of an adjacent ONO stack (such as B), thereby forming a cell D. A gate (GATE E) is formed atop a right half (such as B-R) of one ONO stack (such as B), and the left half (such as C-L) of an adjacent ONO stack (such as C), thereby forming a cell E. Notice that the half stacks A-L and C-R at the end of the ōrowö of cells are not useful for making a corresponding memory cell. In the illustration of There follows a detailed process flow for making NROM memory cells with nitride strips, elaborating greatly on the technique illustrated only very generally in Generally, all of the individual processing steps described herein use conventional semiconductor fabrication techniques of deposition, implanting, masking, etching, polishing, and the like, and are well known to those having ordinary skill in the art to which the present invention most nearly pertains. Generally, dimensions which awe presented herein are intended to be illustrative, not limiting, to provide a sense of proportion to the various elements. The CMOS logic portion 706 comprises N Wells and P Wells, separated by STI (shallow trench isolation) oxide, and covered by LV (low voltage) oxide and HV (high voltage) oxide. An STI oxide 708 separates (is at the intersection of) the periphery portion 706 and the array portion 704, and isolates the two portions from one another. A conventional ONO layer 720 is formed on the array portion, and may comprise:
The ONO layer 720 may be annealed, using a conventional thermal anneal process. In a step 602 (ōPoly/Oxide (PO) Cap on ONOö), a layer of poly 728 is disposed over the ONO layer, and a layer of oxide 730 is disposed over the poly layer 728. The oxide layer 730 acts as an etch stop for a subsequent poly etch and as a barrier to the subsequent hot phosphoric strip. Its thickness is adjusted accordingly. The poly layer 728 acts a barrier to a subsequent wet oxide liner strip. Its thickness is determined by the oxide undercut and barrier effectiveness. The poly layer 728 and the oxide layer 730 may be formed immediately after ONO anneal. The poly and oxide form a poly/oxide (PO) cap on the ONO layer. As will become evident from the process flow, a paramount concern was that in creating ONO strips, it is desired to maintain the integrity and characteristics of the original ONO stack. To this end, the use of sacrificial layers such as PO (Poly/Oxide), NO (Nitride/Oxide), etc. was considered and the integrity of the original ONO stack can be maintained. Inherent in the process is also the use of standard technologies (as opposed to developing new technologies) and the independent targeting of key technology parameters such as the width of the ONO strips, the channel doping and profile, the BL junction doping and profile, and so forth. Next, in a step 604 (ōPoly Depositionö), a layer of polysilicon (Poly-1) 732 is deposited, using a conventional poly deposition process, to a initial thickness of approximately 90 nm. See The Poly-1 layer 732 is planarized, using a conventional CMP process, resulting in a loss of approximately 5 nm of thickness (resulting poly thickness, ś85 nm). During subsequent poly liner etchback, the Poly-1 layer 732 will lose another approximately 14 nm of thickness (resulting poly thickness, ś71 nm). The loss of 14 nm of poly thickness comes from 10 nm (thin poly on ONO ??)+4 nm (10% overetch). During subsequent ONO and spacer etches, the Poly-1 layer 732 will lose another approximately 3 nm of thickness (resulting poly thickness, ś68 nm). During subsequent poly and BL Oxide CMP, the Poly-1 layer 732 will lose another approximately 10 nm of thickness (resulting poly thickness, ś58 nm). The resulting approximately 55 (ś58) nm of thickness for the Poly-1 layer 732 should be sufficient for attaining an ample BL oxide thickness so as to maintain good BL oxide integrity, but not so much as to jeopardize the integrity of the narrow poly lines, and may be in the range of 40-70 nm. Next, in a step 606 (ōPeriphery Protect Maskö), a periphery protect mask 734, such as of photoresist (PR), is applied atop the poly layer and is positioned so that in a subsequent etch step the Poly-1 layer 732 will be opened (removed from) atop the array area 704, as well as at the STI area 708 at the interface of the array area 704 and the CMOS area 706. The Poly-1 layer 732 is then etched, using a conventional plasma etching process, stopping on the top oxide 730 of the PO layer resulting in a structure as shown in The periphery mask 734 (of resist) is removed, using a conventional resist removal process, leaving the original approximately 90 nm of poly atop the periphery area 706. The entire array area 704 is exposed (no poly remaining), as well as the STI oxide structure 728 at the interface of the periphery area 706 and the array area 704. Next, in a step 608 (ōNitride Depositionö), a hard mask layer 736 such as of nitride, is deposited using a conventional nitride deposition process, to a thickness greater than approximately 120 nm (90+30), atop the entire substrate 702. The nitride layer 736 should be deposited to a thickness which is greater than the thickness (ś90 nm) of the Poly-1 layer 732. The resulting structure is shown in Next, in a step 610 (ōNitride CMö), the nitride hard mask layer 736 is planarized (now labeled 736′ (prime)) using a CMP process, leaving approximately 30 nm of nitride over the Poly-1 layer 732. The resulting structure is shown in The remaining (30 nm) nitride 736′ covering the periphery 706 need only be sufficient to act as an implant stop (for subsequent cell threshold and punch through implants). Next, in a step 612 (ōCELL Formation, OPON Etchö), the nitride hard mask layer 736′ is opened, in the array area 704, using a conventional plasma etch process. The oxide 730, poly 728, top oxide 726 and nitride 724 layers (OPON) are also etched, using a conventional plasma etch process, stopping on the bottom oxide 722 (O), leaving about 2 nm of bottom oxide 722 on the surface of the substrate 702. The resulting structure is shown in Openings 738 are shown extend to the bottom oxide 722, and have a width ōFö of approximately 50 nm. The opening of the nitride layer 736′ may be done with an inverse BL mask, which opens the cell area for channel formation. This creates a plurality of vertical structures 740 comprising ONO covered by PO, covered with nitride. The vertical structures 740 are spaced a distance ōFö (where F is the minimum lithography feature) of approximately 50 nm apart from one another. The openings 738 between the vertical structures 740 are for subsequent cell channel formation. The width (Ld) of a vertical structure 740 is approximately 90 nm. The center-to-center distance LD between vertical structures is approximately 90 nm. Next, in a step 614 (ōCell Gate Oxideö), the bottom oxide 722 remaining after the previous etch step is cleaned (removed) if necessary, and a new oxide 742 is deposited and densified, using conventional gate oxide process, to a thickness of approximately 10 nm. (This reduces the effective size of the openings in the nitride mask.) The resulting structure is shown in As illustrated, the oxide 742 covers everything, including the exposed surface of the substrate in the openings 738 between the vertical structures 740, the sidewalls of the vertical structures 740 and the surface of the nitride hard mask 736′ in the periphery area 706. Since the oxide covers the sidewalls of the openings 738 between the vertical structures 736′ are reduced from their original size (F) by 2ū the thickness of the oxide, so that the new size F′ for the opening 738′ (prime) is approximately 50 nm−2ū approximately 10 nm, or approximately 30 nm. Cell punch through (PT) and threshold adjust implants (not shown) can now be made, through the reduced-size openings, using conventional processes. Next, in a step 616 (ōPoly Deposition and Fillö), polysilicon (Poly-2) 744 is deposited, using a conventional poly deposition process. The resulting structure is shown in Sufficient poly 744 needs to be deposited so that the BL openings 738 are overfilled for subsequent CMP. Next, in a step 618 (ōPoly CMPö), the Poly-2 744 is planarized, using a conventional CMP process. The resulting structure is shown in This (2nd) CMP removes a top portion of the Poly-2 744, proceeds through a top portion of the new oxide 742, proceeds through the nitride 736′ overlying the Poly-1 732 in the periphery area 706, and stops on the Poly-1 732, resulting in removal of approximately 5 nm of Poly-1 732. Poly-1 732 now has a thickness of approximately 85 nm, and is labeled 732′ (prime). The further thinned nitride 736′ is labeled 736″ (double prime). The remaining oxide 742 is labeled 742′ (prime). The height of the Poly-2 744′ in the BL opening 738 is approximately 75 nm, and sits atop 10 nm of new oxide 742. Next, in a step 620 (ōWet Nitride Stripö), remaining nitride 736″ is removed, using a conventional Wet Nitride Strip process. The resulting structure is shown in At this stage of the process, the Poly-2 structures 744′ have a width of approximately 30 nm. They sit atop 10 nm of ōnewö oxide 742′ and their sidewalls are covered with 10 nm of oxide 742′ as described hereinabove (see step 614, At this stage of the process, the Poly-2 structures 744′ (including sidewall liner oxide 742′) are spaced approximately 90 nm apart from one another. (From sidewall liner oxide 742′ of one Poly-2 structure 744′ to the sidewall liner oxide 742′ of an adjacent Poly-2 structure 744′, is 90 nm.) Next, in a step 622 (ōSidewall Liner Oxide Stripö), the sidewall liner oxide 742′ is stripped from the Poly-2 structures 744′, using a conventional wet oxide etch process. The resulting structure is shown in During this process, the uppermost oxide 730 of the original ONOPO is removed (leaving ONOP). (Substantially all of the layer 730 of sacrificial oxide is removed.) The STI oxide 708 also loses approximately 10 nm during this oxide etch, but but typically these STI oxides are approximately 300 nm thick and so a 10 nm loss is relatively insignificant. Also, the sidewall liner oxide 742′ adjacent the poly layer 728 of ONOP is undercutŚin other words, etched down below the top of the poly 728, but not reaching the ONO 720, else it would etch the top layer (726) of the ONO 720. The resulting Poly-2 structures 744′, without sidewall liners, are very narrow (approximately 30 nm), and the integrity of these narrow 744′ poly lines has to be maintained during the wet oxide strip. These narrow poly lines 744′ are now relabeled 750, and are now referred to as ōpoly linesö. The poly lines will eventually serve as the gates for NROM cells. The spacing between adjacent poly lines 750 is approximately 110 nm. The width of the ONOP stack is approximately 90 nm. A given ONOP stack is located between two adjacent poly lines 750 spaced apart from each by 10 nm (the thickness of the original sidewall oxide). Attention is directed to the individual ONO stacks 720 shown in As described with respect to Next, in a step 624 (ōPoly Liner Depositionö), a third polysilicon (ōpoly linerö) 752 is deposited, using a conventional deposition process. The resulting structure is shown in The poly liner 752 is deposited to have a thickness of approximately 30 nm, based on an assumed 20 nm nitride strip requirement plus the width of the previous oxide liner 742 (742′). The thickness of the poly liner 752 should be sufficient that, when acting as a sidewall liner on the poly lines 750, it extends approximately ⅓ of the width across an ONO stack 720. This will define the size of nitride strips which will be formed from the ONO stack 720. Nominally, each nitride strip is a first fraction ōsö, such as ╝ the width ōwö of the stack 720, separated from each other by another fraction ōrö, such as Į of the width ōwö of the stack 720, as described hereinbelow. (2s+r=w). Note that s<r. As is evident, using the techniques disclosed herein, it is the dimension of the poly line 750 (750′) and the poly spacer 752 (752′) that determines the split (gap) between nitride strips in a given NROM cell. Note that there is poly liner 752 atop Poly-2 732′, on a side of Poly-2 732′, atop STI 708, atop the poly 728 atop the ONO 720, atop the poly lines 750, as well as on the sides of the poly lines 750. Next, in a step 626 (ōBL FormationŚPoly Liner Etchbackö), poly liner 752 is etched, using a conventional isotropic process such as plasma etch, removing poly from on top of other structures, while leaving it on the sides of other structures. The resulting structure is shown in In this etch step, any poly underlying poly liner 752 will be etched. The poly 728 is removed, stopping on oxide 726. First of all, the poly liner 752 is now labeled 752′ (prime). The underlying Poly-2 732′ had a thickness of approximately 85 nm, and now has a thickness of approximtely 71 nm, and is labeled 732″ (double prime). In the resulting structure, there is poly liner 752′ (prime) remaining on the sidewalls of Poly-2 732″. More importantly, there is poly liner 752′ remaining, as a sidewall spacer, on the sidewalls of the poly lines 750′ (prime). The space between poly lines 750′/752′ is ōFö (the minimum litho feature size), which is approximately 50 nm, which is the original 110 nm less two times the thickness (30 nm) of the poly liner deposition. During this process, the poly (P) 728 over ONO becomes removed. A central portion of the top oxide layer 726 of the ONO stack 720 is now exposed. The outer edges of the ONO stack are covered by remnants (vestiges) of the original poly 728 (now labeled 728′), and sidewall liner poly 752′. (All but a portion of the layer 728 of sacrificial poly is removed.) The original ONO stack 720 has a width of approximately 90 nm. Now, only approximately 50 nm (ōFö) of the ONO stack 720 is exposed, in the space between adjacent poly liners 752′. During this process, the poly-2 732 in periphery area 706 becomes thinned approximately 14 nm (it was approximately 85 nm, thick, and is now approximately 71 nm thick), and is labeled 732″ (double prime). The STI oxide 708 at the interface is partially covered (by poly 752′). What can be observed in Next, in a step 628 (ōBL FormationŚONO Etchö), the exposed central portion of the ONO stack 720 is etched, etching away top oxide 726 and the nitride 724, and stopping on the bottom oxide 722, using a conventional dry etch processes. The bottom oxide 722 is left in place to protect the underlying silicon The resulting structure is shown in During this step, the Poly-2 732″ may also become thinned, by about 2 nm (now shown as having a thickness of 69 nm rather than 71 nm), as a result of the previous oxide and nitride etches. In subsequent steps, buried bitlines (BB) will be formed under the bitline openings 754, by implanting through the remaining bottom oxide 722. The 754 opening size F is small (approximately 50 nm), reduced from its original size of 110 nm, as a result of 30 nm thick sidewall spacers 752′ on the poly lines 750′. Similar bitline construction techniques (using sidewall spacers to reduce ōFö) are disclosed in commonly-owned, copending U.S. Patent Publication No. 2006/0084219 (published Apr. 20, 2006) which discloses an NROM structure and method of fabrication (hereinafter referred to as the '219 patent). In addition to being an initial step in the formation of buried bitlines, this step 628 performs the important function of taking one continuous ONO layer and separating it into two strips (or stripes). As discussed hereinabove, a ONO strip from one stack and a ONO strip from an adjacent stack function as two physically separated (yet coplanar) charge storage areas in a given NROM cell, avoiding problems associated with far-from-junction injection. Next, in a step 630 (ōBL FormationŚSpacer Depositionö), a layer (liner) 760 of oxide, having a thickness of approximately 10 nm, is deposited, using a conventional oxide deposition process. The resulting structure is shown in Next, in a step 632 (ōBL FormationŚSpacer Etchö), the horizontal portions of the oxide liner 760 are etched, using a conventional plasma dry etching process. Remaining are the vertical portions of the oxide liner 760, forming sidewall spacers 762 on the poly elements 752′. The resulting structure is shown in During this step, the thin bottom oxide on the substrate in the BL opening 754 becomes removed, so it is re-created by re-oxidation, using a conventional oxidation process, and is now labeled 764. The purpose of this thin (2-5 nm) layer of oxide is primarily to prevent channeling of the implanted species. (The purpose of the original bottom oxide layer 722, when it is under nitride in an NROM cell, is to insulate the nitride from the FET channel in the underlying silicon.) The bitline opening 754′ (prime) is now approximately 30 nm (the original 50 nm less to 10 nm sidewall spacer thicknesses). Next, in a step 634 (ōBL FormationŚBL Implantö), the bitline (BL) diffusions 764 are implanted, through the bitline openings 754′, using a conventional implant process. The resulting structure is shown in The Arsenic (bit line) and Indium (pocket, if necessary) implants should be low KeV implants. A suitable material and dosage for BL implant is 2ū1015 cm2, 20 KeV, Arsenic. Note that there is no hard mask. Hence, a pocket implant (if necessary) should be low KeV Indium. Also, the BL implant needs to be at low energy so as not to penetrate through the reduced (ś68 nm) poly 732″. Else, the poly height could be increased to allow for an increase in KeV. The process parameters are targeted to achieve approximately a 5 nm overlap (OL) of BL under the edge of the ONO stack. Next, in a step 636 (ōOxide Fill and CMPö), oxide 766 is deposited to fill (overfill) the bitline openings 754′ using conventional oxide deposition process. Then, excess oxide is removed, using a conventional CMP process. The resulting structure is shown in As a result of CMP, another approximately 13 nm are removed from peripheral poly 732″ (68−13=55). Thus, the height of the poly lines 750′ is now also approximately 55 nm. Note, in the previous figure ( In a step 438 (ōWL Formationö), conventional steps are performed to form wordlines. In a step 440 (ōRemaining Flowö), conventional steps are performed to connect the cells in the array area 704 to control circuitry in the CMOS area 706, including fanout, as described hereinabove. While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced be interpreted to include all such modifications, permutations, additions and sub-combinations. Referenced by
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It's the weekend before Halloween, so let's get costumed up! Costumes are strongly encouraged; I will come up with silly rules to handicap those who don't come dressed. This game will run earlier in the day to accommodate people going to parties in the evenings. We will start at noon and finish by 3PM.
We'll be playing at the National AIDS Memorial Grove in Golden Gate Park. This location is in the middle of the park and not on Market street. Please refer to the map.
Awesome game today. Thanks for setting it up Roman. Undercover games looks fun!
October 29, 2011
great game today. did you know about this tomorrow?
October 29, 2011
I'm planning to come attired as Christopher Columbus, complete with Spanish flag to plant on my opponents' toes. To make it even more politically incorrect, let's play in the AIDS Grove.
October 11, 2011
I started the group because there wasn't any other type of group like this. I've met some great folks in the group who have become close friends and have also met some amazing business owners.
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Best Mexican Restaurants in Dallas
Whether you're craving a frozen margarita or fresh guacamole,...
Zagat calculates ratings on a 30-point scale based on periodic consumer surveys
Numerical cost estimates are for the price of dinner with one drink and tip.
A "longtime staple" in Fort Worth for "authentic Mexican food", this duo from the Joe T. Garcia–Lancarte family wows with "generous portions" of "delicious" fare (including one of the "best breakfasts" in town) and "wickedly strong" margaritas; both the Northside and Berkeley Place outposts are no-frills, but the "wonderful" on-site bakeries sweeten the setting. How we get this »
1601 Park Place Ave | Map
Fort Worth,
Today's hours:
6:00am - 9:00pm
Monday | 6:00am - 9:00pm |
Tuesday | 6:00am - 9:00pm |
Wednesday | 6:00am - 9:00pm |
Thursday | 6:00am - 9:00pm |
Friday | 6:00am - 10:00pm |
Saturday | 6:00am - 10:00pm |
Sunday | 6:00am - 5:00pm |
Esperanza's Mexican Bakery & Cafe
1601 Park Place Ave
Fort Worth, Texas 76110


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Over the last 6 years the University of Pittsburgh Nursing Students Association has created an incredible tradition and established themselves as consistent advocates for patients in need of bone... See more


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Town Square
Brentwood, Dublin lead in commission's report on quality roadways
Original post made on Feb 1, 2010
Read the full story here Web Link posted Monday, February 1, 2010, 6:59 AM
Comments (1)
a resident of Danville
on Feb 1, 2010 at 7:10 am
We'd have plenty of money to spend on our infrastructure, which is truly a matter of life and death, if California wasn't spending $20 billion a year on just two things- excessive teachers for small class sizes which are certainly not as important as safety, and of course illegal immigrants who, unlike legal immigrants are a net fiscal drain of $10 billion a year just to our state. There's also a million forms of welfare that go too far and when cut could save the state from structural collapse, but our politicians and the special interests spend like drunken sailors
thank you for doing a report on infrastructure
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Steve Glazer for State Senate
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05-30-2014, 09:11 AM | #1 (permalink) |
Join Date: Mar 2014
Posts: 86
Video of Lako eating Raw for the first time.
Today is the day of the big switch!
Lako got his last kibble meal yesterday, and here are the results of this morning's first raw feeding. https://www.youtube.com/watch?v=tDe2aX0Y-oA I think he likes it! |
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05-30-2014, 10:48 AM | #6 (permalink) |
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" ewhhh, don't bring it to me".....LOL
How nice of your pooch to give you the first piece of his wonderful meal. The " crunching " is good !!! Hopefully, you always hear him grinding it up.....he's a good chewer. If you should care....please let us know any changes you might notice once Lako has been on a raw diet for a while.. Good job taking the "leap" !! SuperG |
05-30-2014, 10:59 AM | #7 (permalink) |
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Congrats on going to raw. Lako is gorgeous. Where did you get him? I remember Jerry Lee's first meal of raw. He just looked at me with this face that said "what am I supposed to do with this". LOL he just licked his chicken but figured it out after a few minutes.
Belinda Rusti EAC, TN-N, TG-O, WV-N, NCC, NJC, CGC, GSD Diva Jerry Lee AXP, MJP, OAC, TN-N, WV-N, NCC, NJC, SPJ, UAG1 |
05-30-2014, 11:06 AM | #8 (permalink) | |
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Even now he looks 110 times better than when we first got him 2 months ago. He was left in a fenced back yard all day and night and stank to high heaven! And he was only being fed once a day, Ol' Roy kibble....complete garbage! We switched him to Fromm kibble, and started adding Omega 3 capsules every day. With just that switch, his fur became so soft and he stopped sheding in huge clumps. Here he is the first week we had him. It's not the best picture ever, but you can see all the matting and clumps of fur on him. Here are the before pics from last night. Taken in natural light, cloudy day, no flash. Current weight is 72lbs |
05-30-2014, 11:09 AM | #9 (permalink) | |
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05-30-2014, 11:41 AM | #10 (permalink) |
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He is SOOOOOOOO beautiful!! I love that he brought one over to eat right in front of you.. bahaha. Super cute video!!
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This is a discussion on teryx hop-up parts within the Engine and Drivetrain forums, part of the Kawsaki Teryx Forum Technical category; I don't know if this would be cost-effective, but has anyone considered using T4 parts as performance upgrade on a Teryx? Specifically thinking about the ...
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Last week, NOM introduced us to his mellow, out-the-box style via The Christening, a Booth-exclusive single which won an impressive 4.0-star rating on our pages. Lo and Behold, the Iowa native has returned to do it all over again with the follow-up—another world premiere. While Jharee replaces Weirdough behind the boards, his sampled production has a similarly drowsy, headphone-ready feel. Over the mesmerizing beat, NOM trades intricate, insightful verses with newcomer Caliiko. Singer Jade, another first-time featuree, contributes some soothing background vocals to the record's hook. Feeling it? This is just one of many low-key bangers to be found on DJBooth-hosted mixtape Lucid, scheduled for free digital release September 16.
Written by richard on 09/5/13
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First DJ Booth Appearance:
"The Christening" (2013)
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