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US 6854003 B2 Abstract A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.
Claims(13) 1. An integrated circuit using a memory, said integrated circuit comprising:
an interface circuit configured to control access to said memory, said interface circuit coupled to said memory;
an embedded processor configured to control said integrated circuit, said embedded processor receiving information from said interface circuit; and
an array processor for performing mathematical calculations on data received from said interface circuit and connected to said embedded processor via an internal bus, said array processor comprising:
a plurality of multiplier/accumulator circuits;
a plurality of shared operand circuits coupled to said plurality of multiplier/accumulator circuits for simultaneously providing a shared operand to at least two of said plurality of multiplier/accumulator circuits; and
a shared output and feedback interface coupled to receive outputs from the at least two of the plurality of multiplier/accumulator circuits and to provide them for further processing by the at least two of the multiplier/accumulator circuits,
wherein each of the plurality of shared operand circuits comprise:
a front end unit for determining a fixed point result by performing a fixed point addition or subtraction on a plurality of operands; and
a floating point conversion unit for converting said fixed point result to a first floating point result.
2. An integrated circuit comprising:
a first embedded processor;
a first array processor coupled to the first embedded processor;
a first memory interface circuit coupled to the first embedded processor and the first array processor;
a first communication port coupled to the first embedded processor;
a second communication port configured to communicate with the first communication port;
a second embedded processor coupled to the second communication port;
a second array processor coupled to the second embedded processor; and
a second memory interface circuit coupled to the second embedded processor and the second array processor,
wherein the first array processor comprises at least two arithmetic processing units, each of the at least two arithmetic processing units comprises:
a first MAC unit coupled to a first local memory;
a second MAC unit coupled to a second local memory;
a third MAC unit coupled to a third local memory;
a shared operand unit coupled to provide a shared operand to the first MAC unit, the second MAC unit, and the third MAC unit; and
a shared output and feedback interface coupled to receive a first output from the first MAC unit, a second output from the second MAC unit, and a third output from the third MAC unit, and further coupled to provide the first output to the first local memory, the second output to the second local memory, and the third output to the third local memory.
3. The integrated circuit of
4. The integrated circuit of
5. An integrated circuit comprising:
an interface circuit configured to receive data from an external memory;
a first embedded processor configured to control the interface circuit;
a first array processor configured to receive data from the interface and to perform arithmetic calculations;
a first communication port coupled to the first embedded processor and the first array processor for communicating with a second array processor and a second embedded processor,
the array processor comprising:
a first MAC unit configured to receive data from a first local memory;
a second MAC unit configured to receive data from a second local memory;
a third MAC unit configured to receive data from a third local memory;
a first shared output and feedback circuit configured to receive data from the first MAC unit, the second MAC unit, and third MAC unit, and further configured to provide data to the first local memory, the second local memory, and the third local memory;
a fourth MAC unit configured to receive data from a fourth local memory;
a fifth MAC unit configured to receive data from a fifth local memory; and
a second shared output and feedback circuit configured to receive data from the fourth MAC unit and the fifth MAC unit, and further configured to provide data to the fourth local memory and the fifth local memory.
6. The integrated circuit of
a first shared operand circuit configured to simultaneously provide a shared operand to the first MAC unit, the second MAC unit, and the third MAC unit.
7. The integrated circuit of
a second shared operand circuit configured to simultaneously provide a shared operand to the fourth MAC unit and the fifth MAC unit.
8. A frame rendering integrated circuit comprising:
an interface circuit coupled to an external memory;
an embedded processor coupled to the interface circuit and configured to control the integrated circuit; and
an array processor coupled to the interface circuit, wherein the array processor performs arithmetic calculations;
wherein the array processor comprises:
a first multiply/accumulator (MAC) unit coupled to a first local memory, the first local memory comprising a first plurality of operands;
a second MAC unit coupled to a second local memory, the second local memory comprising a second plurality of operands;
a third MAC unit coupled to a third local memory, the third local memory comprising a third plurality of operands;
a fourth MAC unit coupled to a fourth local memory, the fourth local memory comprising a fourth plurality of operands;
a fifth MAC unit coupled to a fifth local memory, the fifth local memory comprising a fifth plurality of operands;
a sixth MAC unit coupled to a sixth local memory, the sixth local memory comprising a sixth plurality of operands;
a first shared operand unit coupled to the first MAC unit, the second MAC unit, and the third MAC unit, and
a second shared operand unit coupled to the fourth MAC unit, the fifth MAC unit, and the sixth MAC unit.
9. The integrated circuit of
a first shared output and feedback interface coupled to the first MAC unit, the second MAC unit, and the third MAC unit, and further coupled to the first local memory, the second local memory, and the third local memory.
10. The integrated circuit of
11. The integrated circuit of
12. The integrated circuit of
13. The integrated circuit of
a second shared output and feedback interface coupled to the fourth MAC unit, the fifth MAC unit, and the sixth MAC unit, and further coupled to the fourth local memory, the fifth local memory, and the sixth local memory.
Description This patent application claims priority from U.S. Provisional Applications No. 60/033,476, filed Dec. 19, 1996, and No. 60/050,396, filed Jun. 20, 1997. The contents of these provisional applications are herein incorporated by reference in their entirety for all purposes. The present invention relates to circuits. More particularly, the present invention relates to high-performance integrated circuitry suited to the video frame generation task and digital signal processing (DSP) tasks. The central problem of the graphics industry is to generate frames. Each frame is a rectangular array of pixels, often involving over 1 million pixels. Animation and in particular, 3-D animation, usually requires many millions to many billions of calculations to generate one pixel. Similarly, graphics applications (such as medical imaging) require the generation of one or more frames, again, often in animation sequences. Consider the example of this need in the 1995 effort by Pixar generating the motion picture Toy Story. There are 110,000 frames in the motion picture. Pixar used 87 dual processor 100 MHz Sparc 20's and 30 quad processor 100 MHz Sparc 20's. This is a total of 294 CPU's. There was an average of 96 Megabytes of RAM per CPU and each processing node had a local 3-5 gigabyte local disk drive. The disk farms and their servers are not relevant to this patent, but were quite large. The entire motion picture took 46 days to compute with an average frame taking between 1 to 3 hours of Sparc CPU processor time. See reference [1]. While Toy Story was not photo-realistic it did represent a breakthrough. It was the first full length, feature motion picture entirely generated by 3D computer animation technology. Photo-realism for such a film requires at least a factor of 10 more computing complexity. Assume the photo-realistic frames compute in 30 hours. There are many different programs used in frame generation. See references [19]-[23]. These programs are both complex and need high performance. They are created with high level procedural and object-oriented computer programming languages such as C, C++, and FORTRAN. Only the most performance critical portions of these programs might be directly written in assembly/machine language targeting the underlying rendering engine hardware because of the prohibitive expense and difficulty of programming in assembly/machine language. Floating point arithmetic is popular in these programs because of its wide dynamic range and programming ease. The need for performance improvements is large. Optimal video editing requires 1 frame every second. Real-time virtual reality needs up to 30 frames generated per second. The performance improvements needed to satisfy these two industrial applications are speedups of 108,000� for video editing (=30 hrs./frame�3600 seconds/hr) and 3,240,000� for virtual reality (=30*Video Editing). A similar situation exists in high performance Digital Signal Processing. The typical requirement includes processing images, often collected from 2-D and 3-D sensor arrays over time to construct images of the interior of materials including the human body and machine tools. These multidimensional signal processing applications construct images from banks of ultra-sound or magnetic imaging sensors. This has similar performance requirements to frame generation. These applications have the goal of resolving features in a reconstruction/simulation of a 3-D or 4-D environment. (Note: 4-D here means a 3-D domain observed/simulated over time.) Feature resolution is a function of input sensor resolution, depth of FFT analysis which can be computationally afforded within a given period of time, control of round-off errors and the accumulation of those rounding errors through the processing of the data frames. Fine feature resolution in minimum time lead to performing millions and often billions of arithmetic operations per generated pixel or output data point. The use of floating point arithmetic to provide dynamic range control and flexible rounding error control is quite common. Algorithmic flexibility is a priority, due to the continuing software evolution and the availability of many different applications. These differing applications often require very different software. The application software development requirements are very consistent. In particular, most applications need numerous programs, mostly written in the procedural computer programming languages, C, C++ and FORTRAN (see references [11]-[18]); and the use of machine level programming is restricted to the most performance critical portions of the programs. The target algorithms display the following common features: a need for large amounts of memory per processing element, often in the range of 100 MB; a need for very large numbers of arithmetic calculations per output value (pixel, data point, etc.); a need for very large numbers of calculations based upon most if not all input values (pixel, data point, etc.); and relatively little required communication overhead compared to computational capacity. Support for high resolution graphics has developed over the last 30 years. Preliminary efforts in the 1960's and early 1970's such as seen in reference [40] created graphics computer systems with a minimum of specialized hardware. There was little or no thought at that time to VLSI (Very Large Scale Integration) integrated circuits (ICs). The support of the graphics industry by semiconductor devices has focused on the following issues:
These efforts have fundamental limitations, as is described below. A. Display device controllers are limited in that each frame is generated by a fixed execution structure machine within a specific amount of time. Thus, the variation of frame algorithms is necessarily limited. B. High speed micro-processors and DSPs possess great intrinsic algorithmic flexibility and are therefore used in high performance dedicated frame rendering configurations such as the SUN network that generated Toy Story. See reference [1]. The advent of the Intel Pentium� processors brought the incorporation of all the performance tricks of the RISC (Reduced Instruction Set Computing) community. �Appendix D: An Alternative to RISC: The INTEL 80x86� in reference [30] and �Appendix: A Superscalar 386� in reference [31] provide good references on this. �Appendix C: Survey of RISC Architectures� in reference [30] provides a good overview. However, commercial micro-processor and DSP systems are severely limited by their massive overhead circuitry. In modern super-scalar computers, this overhead circuitry may actually be larger than the arithmetic units. See references [30] and [31] for a discussion of architectural performance/cost tradeoffs. C. High performance memory is necessary but not sufficient to guarantee fast frame generation because it does not generate the data�it simply stores it. D. There have been several special purpose components proposed which incorporate data processing elements tightly coupled on one integrated circuit with high performance memory, often DRAM. However these efforts have all suffered limitations. The circuits discussed in [32] use fixed point arithmetic engines of very limited precision. The circuits discussed in [32] are performance constrained in floating point execution, and in the handling of programs larger than a single processor's local memory. The proposed special purpose components are optimized to perform several categories of algorithms. These components include:
What is needed is a computational engine that avoids the above-described limitations with regard to computation for video frame rendering and DSP tasks. A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance. Wire A wire is a mechanism for sharing the state between multiple nodes of a circuit. The state is a finite alphabet based upon certain physical conditions including but not limited to: electrical voltage, current, phase, spectral decomposition, photonic amplitude. Symbols are the individual elements of an alphabet. Measured value ranges of the relevant physical conditions typically encode symbols. The most commonly used alphabet is the set {0,1}, the binary symbol set. Binary systems using all of the above schemes exist. Other commonly used alphabets include 3 symbol alphabets, e.g., {0,1,2}, multiple binary alphabets, e.g., {00,01,10,11}, etc. There are other alphabets in use. A wire may be embodied, for example, as a strip of metal (e.g., in an integrated circuit or on a circuit board), an optical fiber, or a microwave channel (sometimes referred to as a microchannel). Wire Bundle A wire bundle is a collection of one or more wires. Bus A bus is a wire bundle possessing a bus protocol. The bus protocol defines communication between circuits connected by the wire bundle. A bus will typically be composed of component wire bundles wherein one or more of the component wire bundles will determine which connected components are receiving and which are transmitting upon one or more of the other component wire bundles. Floating Point Floating point notation includes a collection of states representing a numeric entity. The collection includes sub-collections of states defining the sign, mantissa and exponent of the represented number. Such notations non-exclusively include binary systems including but not limited to IEEE standard floating point and special purpose floating point notations including but not limited to those discussed in the references of this document. A floating point notation non-exclusively includes extensions whereby there are two sub-collections each containing the sign, mantissa and exponent of a number as above. The numeric representation is of an interval wherein the number resides. A floating point notation additionally includes non-binary systems, wherein the mantissa and exponent refer to powers of a number other than 2. Programmable Finite State Machine A programmable finite state machine is a machine which includes a state register, possibly one or more additional registers wherein state conditions, quantities, etc. reside, and a mechanism by which the state register, additional registers, external inputs generate the next value for the state register and possible additional registers. SIMD A Single Instruction Multiple Datapath architecture executes the same instruction on more than one datapath during the same instruction execution cycle. A typical extension to this basic concept is the incorporation of �status flag bits� associated with each datapath. These flags enable and disable the specific datapath from executing some or all of the globally shared instructions. SIMD architectures are optimal in situations requiring identical processing of multiple data streams. The inherent synchronization of these data streams produce advantages by frequently simplifying communications control problems. SIMD architectures become inefficient whenever the data processing becomes dissimilar between the datapaths. SIMD architectures require a relatively small amount of instruction processing overhead cost because there is only one instruction processing mechanism, shared by the datapaths. The instruction processing mechanism has an instruction fetching mechanism. The datapath collection typically needs only one instruction memory. MIMD A Multiple Instruction Multiple Datapath architecture executes distinct instructions on different datapath units. The fundamental advantage of this approach is flexibility. Any data processing unit can execute its own instruction, independently of the other data processing units. However, this flexibility has added costs. In particular, each data processing unit must possess its own instruction fetching, decoding, and sequencing mechanisms. The instruction fetching mechanism frequently possesses at least a small memory local to the data processor. This local memory is often a cache. (Very) Long Instruction Word Processors (VLIW and LIW, Respectively) A (Very) Long Instruction Word Processor is a class of architectures whereby there is a single instruction processing mechanism which contains a program counter capable of common operations, such as branches on condition codes, and multiple instruction fields that independently control datapath units. In these architectures, the datapath units often are not identical in structure or function. Array Processor An Array Processor is defined as an LIW or VLIW instruction-processing architecture having multiple datapath units arranged into one or more collections. In embodiments of the present invention, as will be described, the datapath collections receive and may act upon a common operand received via a common operand bus having a transmitting unit; each datapath receives one or more additional operands from a memory; each datapath collection contains an instruction memory possessing instruction fields that control the operation of the program controlled elements within; each datapath unit contains one or more multiplier/accumulators (MACs); and each MAC possesses a multiplicity of accumulating registers. Multiplier-Accumulator A Multiplier-Accumulator is an arithmetic circuit simultaneously performing multiplication of two operands and addition (and possibly subtraction) of at least one other operand. Fast Fourier Transform (FFT) The fast fourier transform is a highly optimized algorithm for generating the spectrum of a signal. See the relevant chapters of references [11], [12], and [15] for thorough discussions of the various involved topics. Vector Processor A vector processor is an architecture designed to operate exclusively on vectors. Typically, a vector processor is deeply pipelined. There is a large literature devoted to vector processing. See references [46]-[53]. Appendix B, �Vector Processors� in reference [30] provides an overview on the subject. The present invention provides a cost-effective basic circuit which encapsulates memory, logic, arithmetic, and specialized circuitry and controls particularly suited to supporting a broad class of algorithms, especially those used for video frame rendering. Replicating the basic circuit increases the computing capacity, creating the capability to support very high performance requirements. The distinction between high performance, often multi-dimensional, signal processing and high performance frame rendering graphics is slight. For the duration of this document, the discussion will focus on frame rendering from a graphics perspective, with commentary added where necessary to delineate the differences in application of the invention. The GEBI 7 provides an interface to the external environment. This external bus may be a standard computer bus such as the well-known Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), Universal Serial Bus (USB), IEEE 1394 (formerly, FireWire), or Fiber Channel; or a special purpose bus designed to support communications between external controller-host(s) and a multiplicity of instances of this invention. The embedded micro-processor sub-system 8 controls operation of the basic circuit 1 and performs computations not targeting the DSP (array processor) 9 or the special-purpose circuitry 11. The micro-processor sub-system 8 is discussed in more detail below. The DSP (array processor) 9 performs floating point computations. In one embodiment of the present invention, the DSP (array processor) 9 is as shown and discussed in U.S. Patent application Ser. No. 60/050,396, filed Jun. 20, 1997, incorporated by reference. The DSP (array processor) 9 is discussed in more detail below. The neighboring circuit communication port(s) 10 provide communication between the basic circuit 1 and other instances of the basic circuit 1 in a system. In system applications wherein only one instance of the basic circuit 1 is used, these port(s) 10 are not needed. An exception to the previous sentence exists in a specific embodiment in which some of these port(s) 10 provide communication with other components (not shown) which are not instances of the basic circuit 1 but which nevertheless benefit from highly concurrent transactions with or via the instance of the basic circuit 1. Applications having multiple instances of the basic circuit 1 often need high speed, concurrent communications between the instances of the basic circuit 1. By providing the communication port(s) 10, the basic circuit 1 reduces a potential bottleneck in the GEBI 7. In a specific embodiment, the communication port(s) 10 provide dedicated communication between exactly two instances; therefore, the protocols used on each port may be much simpler than, e.g., the bus protocol used in the external bus interface 7. In general, standard methods are used for inter-instance communication. For example, various communication schemes based on messaging protocols, which are well documented in the art, may be used. Similarly, any of several �semaphore� systems, or handshaking systems, may be used to provide the ability to synchronize and control Concurrent Sequential Processes (CSP) operating upon instances which are not proximate. Special purpose circuitry 11 exist in various embodiments to provide performance enhancement for otherwise extremely complex or time consuming operations essential to an application. Examples of such circuitry include, but are not limited to: a frame generator for accelerating Z-buffer operations, triangular fills, �BitBlts� and surface texturing; a content addressable memory (CAM) for accelerating pattern matching for fractal compression or transforming a compressed token into a standard handle pointing into a hash table, for instance; and a bit code parser for decoding the command and data headers for highly compressed communications schemes such as MPEG (Moving Pictures Experts Group) and languages such as Java�, which is a trademark of Sun Microsystems. Internal memory bank(s) 4 contain one or more banks of random access memory (RAM) arrays. These memories are economical dynamic random access memory (DRAM) in embodiments of the invention, but other types of memories may also be used. In a preferred embodiment, one to 32 megabytes (MBs) of total memory, organized in a wide configuration, are provided. Widths of up to 1024 bits (1K bits) are contemplated. Widths above 64 bits are considered to be �wide.� Preferred configurations for these memories include but are not limited to:
Note that configurations providing access to data lengths other than powers of 2, such as 72, can have advantages. Such configurations support error detection and correction schemes implemented with added, standard logic incorporated in the MMIC 6. The MMIC 6 (master memory interface and control) is a digital logic circuit which supports a number of functions. If the internal memory banks 4 are DRAM, or require refreshing as does DRAM, then the MMIC 6 automatically refreshes the internal RAM banks 4. The MMIC 6 allows and controls access to the internal RAM banks 4 for reading and writing by the GEBI 7, the embedded microprocessor 8, the DSP (array processor) 9, and, potentially, by instances of the neighboring circuit communications ports 10 and by the special purpose circuitry 11. The MMIC 6 also allows and controls access to the external local memory interface(s) 2 by the GEBI 7, the embedded microprocessor 8, the DSP (array processor) 9, and potentially by instances of the neighboring circuit communications ports 10 and by the special purpose circuitry 11. In preferred embodiments of the invention, the MMIC 6 includes an Finite State Machine (FSM) to control the data and instruction flow by accepting requests from the modules 7, 8, 9, 10, and 11 for data and/or instructions in the external local memory. The MMIC 6 satisfies them based on a decision algorithm encoded in the FSM. FSMs for data/instruction flow control are well known. In a preferred embodiment of the invention, separate instruction and data streams are maintained for each of the embedded microprocessor 8, the DSP (array processor) 9, and the special-purpose circuitry 11. These instruction and data streams would typically reside on the external local memory, after having been loaded therein, during program initialization and operation, from the GEBI 7. These instruction and data streams would typically be produced by one or more compilers according to known compiler technology, and may incorporate some amount of handshaking for coordination according to known methods. In addition to the MMIC 6, the embedded microprocessor 8 and the GEBI 7 provide direction for controlling data/instruction flow in a manner known in the art. For example, the microprocessor 8 can preemptively seize control of the FSM for, e.g., error control, initialization, and capture of bus error transactions on the GEBI 7. The controller 2 for the external local memory interface(s), or ELMI(s) 2, provide support for external timing and interface conventions to access one or more kinds of external IC memories. For example, the ELMI(s) 2 provide read and write access to RAM and read access to non-volatile memories. If some or all external memory is DRAM-related (see Chapters 6 and 7 in reference [54], then the ELMI(S) 2 support automatic memory refresh. Optimally, the ELMI(s) 2 provide queuing of access requests during refresh. The ELMI(s) 2 optionally also provide queuing of access requests during write, erase and other potentially slow operations. In embodiments in which at least some of the external memory is programmable and non-volatile (see Chapters 10, 11 and 12 in reference [54]), the ELMI(s) 2 provide writing of specific words and, as appropriate, erasing of blocks of words. Optionally, the ELMI(s) 2 provide additional functions known in the art, such as erase-suspend for non-volatile memory operations, in order to provide advantages in certain applications. Although not specifically shown in Additional secondary support circuitry in alternate embodiments include, but are not limited to, internal clock multipliers, Phase Locked Loops (PLLs), clock distribution networks, built in self test (BIST) circuitry, boundary scan path(s), etc., which are known in the relevant art. The basic circuit 1 has a design which is optimized in many ways to provide a high performance computation engine for frame rendering and similar tasks. Significantly, the embedded microprocessor 8, the DSP (array processor) 9, and special-purpose circuitry 11 are provided with the circuit resources to process their individual instructions and data concurrently and with a minimum of stalling for lack of data or instructions. This efficiency arises for example from the overall design and from the design of the individual modules, as described above and below. For example, the wire bundle 13 reduces the bandwidth overhead on the main bus interface (MMIC 6, and wire bundles 12, 14, 15, 16, 17) by providing a dedicated path for interactions, e.g., control, between the global external bus 7 and the embedded microprocessor 8 that is independent of the primary flow transactions on the main bus interface. In this way, the bandwidth of the main bus interface is conserved. In a preferred embodiment, the basic circuit 1 is implemented as an integrated circuit (IC). Importantly, the basic circuit 1 can be implemented using relatively low amounts of IC surface area due to its design. Also, the architecture is simple and flexible enough to permit compilers to efficiently target its computation units, especially the microprocessor and the array processor. The calculations include, for example, calculations requiring several relatively short vectors. For example, in calculating complex valued functions such as X=(az+b)/(cz+d), wherein a, b, c, d, and z are all complex floating point numbers. As is well-known, these calculations and similar calculations are common in frame rendering. To calculate the function, a0, b0, c0, d0, z0 and X0 are defined as the real components and correspondingly, a1, b1, c1, d1, z1 and X1 are defined as the imaginary components. The calculation prior to entry into a floating point division circuit proceeds in two multiply-accumulate passes. In the first pass, the following are calculated:
According to the embodiment of Within the APU 970, an internal floating point notation is used. This internal notation may or may not be the same as the floating point notation(s) used externally. In general, the APU 970 is adapted to expect at least a standard external notation, e.g., standard IEEE floating point notation. In a preferred embodiment, the floating point notation used is a simplified notation that does not include the exceptional cases of, e.g., standard IEEE floating point notation. Using the simplified notation enables greater internal efficiency, e.g., with regard to circuit size, by avoiding the complexity of the exceptional cases. Using the simplified notation is practical because the exceptional cases are typically not of great relevance in frame rendering and DSP applications. The APU 970 includes a shared operand circuit (SOC) 910 which acts as a multiplier input circuit. Optionally, the SOC 910 includes a RAM circuit having address controls that determine whether the RAM may be used as an operand cache or a first-in-first-out (FIFO) queue. A first sub-circuit (not shown in the figure) within the SOC 910 includes a multiplicity of input registers for accepting input and capturing the state of the wire bundle 902. The SOC 910 contains a second sub-circuit (not shown) coupled to the registers within the first sub-circuit. The second sub-circuit includes an integer Arithmetic Logic Unit (ALU) (not shown). The second sub-circuit performs fixed point add/subtracts (in the ALU) on selected fields of the state of the wire bundle 902 from the registers. The second sub-circuit also converts the fixed point result of the add/subtract operation or of the selected fields of the input registers into an internal floating point notation according to known conversion algorithms. Therefore, the second sub-circuit is said to contain a floating point conversion unit (not shown). The APU 970 also includes two or more Multiplier/ACcumulators (MACs) 900 as the datapath processing units 900. MACs are well-known in the relevant art. Each MAC 900 is coupled to wire bundle 906 for receiving a shared operand from the SOC 910. Each MAC 900 is also coupled to a corresponding Local Data Store 920. In general, there are as many local data memory circuits 920 as MACs 900. During operation, each MAC 900 receives 3 numbers X, Y and Z in some numeric format, wherein X is the shared operand received via wire bundle 906, and Y and Z are received from the local data store 920 via wire bundle 909. Each MAC 900 possesses two or more registers, preferably at least four. Each MAC 900 can perform a multiplication and an add/subtract in each clock cycle to thereby generate XY+Z or XY−Z from values of X, Y and Z received in the (possibly) current or predecessor clock cycles. Each MAC 900 conditionally stores the generated result in one of its registers. The APU 970 further includes a Shared Output and Feedback Interface (SOFI) 940. The SOFI 940 contains a floating point conversion unit (not shown) that is adapted using standard techniques to convert the internal numeric format of a wire bundle (907) to the requisite floating point (e.g., IEEE floating point) or fixed point notation needed externally. Of course, in embodiments in which the internal floating point representation is identical to the external representation, then that particular conversion need not be performed. The SOFI 940 controls the transmission of the results of such conversions upon a wide bus 901 to the APIC 965. In a particular embodiment, the SOFI 940 also temporarily stores such results as necessary prior to transmission. The data memory 920 has a corresponding address generator (in, e.g., module 950, discussed below) for providing addresses for access. The addresses used to fetch the Y and Z operands may or may not be identical. By supporting generation of distinct addresses, an advantage is provided for many applications requirements, such as FFTs. The APU 970 includes an overall Control, Synchronization circuitry and Instruction Store unit (CSIS) 950. The CSIS 950 performs control and synchronization of the various modules of the APU 970 and includes storage for instructions. Given the architecture of the APU 970 as shown in FIG. 2 and discussed herein, the CSIS 950 has an appropriate structure for carrying out its tasks. In particular, the CSIS 951 includes (not shown in The status register optionally preserves at least a multiplicity of wire states. These wire states include at least state condition bits of the loop counters, a zero detect signal from the integer ALU of each SOC 910, and condition bits of the floating point conversion unit of the SOFI 940 of each APU 970. The CSIS is adapted to request instructions (via the MMIC 6 and the APIC 965) and to buffer these instructions in its instruction store. The wire bundle 903 provides inputs to the local data stores 920. The wire bundle 903 contains at least: the addresses for the component memories of each local data memory 920, and the read/write controls and page interleaving control signals of each local data memory 920. Each APU 970 operates on two vectors, as in �vector added to vector� operations, or on one vector and a scalar, as in �scalar multiplying the elements of a vector� operations. The APU 970 is extremely versatile because an input operand is shared amongst a multiplicity of MACs and because a local memory circuit (920) or the state of another MAC's register provides the other two operands. The array processor 9 according to the present invention enables types of computations to be performed which could not be efficiently performed using, e.g., vector processors. For example, in the calculation of several Discrete Wavelet Transform Filters (DWTFs) it is frequently necessary to share several different scalars across several sub-components of a vector. Vector processors typically required as many cycles to perform this task as the number of scalars to be shared. In these DWTFs, every even input affects all the filter outputs, and the odd inputs affect only half the filter outputs. Processing four inputs in this manner forces the limitation that the odd entries cannot be concurrently processed using the vector processor approach. In the array processor 9, however, these problems are minimized, for example because it can send two (or more) odd-entry scalar elements to different components of a vector. Radix 2 FFTs present both the sum and difference to differing components of a vector. The present invention, by presenting these in parallel to the respective components of the vector achieves the result in one cycle, rather than two cycles per pair of elements required by vector processors. The array processor 9 according to The embedded micro-processor sub-system 8 also includes an optional local cache 810, preferably 2-4 way interleaved with at least 64 pages and a total memory of at least 1K words of memory. Typically, the cache memory 810 is organized as, e.g., 32 bit words. The cache memory 810 may contain two component caches, one for instructions and one for data. The embedded microprocessor subsystem 8 also includes additional optional local storage, such as a RAM 820 or a ROM 830, as is known in the relevant art. The ROM 830 may contain, e.g., initialization information for the microprocessor subsystem 8 and/or for the basic circuit 1. In a preferred embodiment, the microprocessor(s) 800 provides a two version instruction set: one version being 16 bits in length, which contains the most common instructions used by code generated with compiler technology; and the other version being 32 bits in length. Such microprocessors are known in the relevant art. The advantage of such microprocessors is that most of the generated program code will be in the 16 bit format. In each microprocessor 800, each instruction fetch of 32 bits or more can provide the next 1 to 3 instructions without recourse to further instruction memory accesses. The basic circuit 1 and array processor 9, as discussed herein, reveal an architecture, or class, of circuitry which has a number of notable advantages. One such advantage is that the circuit 1 possesses very high levels of efficiency in executing specific computationally intensive algorithms in an environment compared to the performance of such algorithms on comparable sized printed circuit boards using microprocessors or conventional DSPs. In general, the basic circuit 1 has a lower requirement for circuit size compared to other mechanisms available to achieve the same results. Therefore, the basic circuit 1 is cheaper than other mechanisms for achieving the same results. One factor in the array processor 9's low circuit size requirement is that it does not directly implement the division operation, which is actually not very common in a great number of frame rendering and DSP algorithms of interest. In embodiments of the array processor 9 in which the MACs are configured to support only single-precision arithmetic, as is typically sufficient for a large class of frame rendering and DSP applications, the array processor 9's circuit size requirement is substantially further reduced. The architecture of the array processor 9 provides a �front end� of fixed point addition/subtraction followed by floating point conversion (in, e.g., SOC 910), then multiplication and accumulation (in MACs 900). This �front end� can perform preliminary operations involved with symmetric, anti-symmetric FIRs, and some low radix FFT calculations. These operations are extremely useful in practical DSP applications wherein the data is often received in a fixed point version from sampling circuitry which typically generate between 8 and 16 bits of fixed point precision. Another advantage of the array processor 9 relates to the general phenomenon of accumulating rounding errors. It is very important that DSP algorithms maintain the precision of arithmetic results. For efficiency, many prior DSP processors use algorithms that perform fixed-point arithmetic. Such fixed-point arithmetic requires a great deal of care in managing rounding errors to maintain precision. In contrast, the array processor 9 is able to efficiently perform floating point computations. Floating point computations have the advantage of providing much better dynamic range, while being considerably easier to program for the same precision of results. It is interesting to examine the capabilities of a specific, example embodiment of the array processor 9. In the example embodiment, the array processor 9 (according to In the example embodiment, the array processor subsystem 9 has an internal clock rate of 200 megahertz (MHz). The following operations can be performed in every clock cycle: four single precision floating point multiplies and 4 single precision floating point additions; an integer/fixed point add/subtract operation, integer/fixed point to floating point scaled conversion; and floating point to fixed point scaled conversion. In the example embodiment, the local data stores 920 are two-way interleaved to support concurrent loading from data received from accesses via the MMIC 6 while fetching the Y and Z operands for the corresponding MAC 900. In the example embodiment, a communications scheme is embodied in the implementation of the GEBI 7, the MMIC 6, the embedded micro-processor sub-system 8, the ELMI(s) 2, and the array processor 9's APIC 965, using standard techniques, to permit the array processor 9 to stay fully active on the order of 75% of the time for the types of frame rendering and DSP applications envisioned. This performance assumption is reasonable based upon the locality of the data to the basic circuit 1 and to its internal array processor 9. The resulting performance of the example embodiment, given the above assumptions would be one to three gigaflops (billion floating point operations per second) for many DSP and specific frame rendering algorithms. Assuming that the basic circuit 1 is implemented in a standard IC package such as 176-pin TQFP (Thin Quad Flat Pack), then each IC would take up roughly one square inch of printed circuit board space. Thus, an embodiment of the present invention can be implemented as a PCI bus card capable of holding up to 32 of these ICs, thereby delivering roughly 16 times the performance of a Silicon Graphics Workstation (see Toy Story, reference [1]) at a fraction of the cost. The present invention is particularly suited for use in applications involving Java (see references [64]-[65]) and interactive audio-video languages such as MPEG-4 (see references [57] to [63]). The MPEG-4 standards activity is developing an environment where a wide variety of algorithms can run on customer targeted hardware. Java is essentially machine independent in its definition and possesses the semantic capability to create and invoke very complex and computationally expensive algorithms. The present invention provides high performance support of network appliances. Some embodiments of the present invention might be supplementally described in a stylized, outline form as an integrated circuit including:
In an embodiment, the bus B0 additionally includes component wire bundles D0A and D0C wherein:
In an alternative embodiment, the bus B0 additionally includes a component wire bundle D0F wherein:
In an embodiment, at least one of the communications interfaces to external circuitry provides a communications interface to a bus in which the claimed circuit acts as a bus master. In an embodiment, at least one of the communications interfaces to external circuitry provides a communications interface to a bus in which the claimed circuit acts as a bus slave. 1. Ubois, Jeff, �Sun goes Hollywood: 117 SPARCstations render �Toy Story�, the first feature-length computer-animated film�, SunWorld Online, November 1995, a world wide web electronic magazine to be found at http://www.sun.com/sunworldonline/swol-11-1995/swol-11-pixar.h tml 2. Fuchs, Henry, U.S. Pat. No. 4,590,465, �Graphics Display System Using Logic-Enhanced Pixel Memory Cells�, Filed Feb. 18, 1982, granted May 20, 1986. 3. Andrews, David H., et. al. U.S. Pat. No. 4,646,075, �System and Method for a Data Processing Pipeline�, Filed Nov. 3, 1983, granted Feb. 24, 1987. 4. Littlefield, Richard, U.S. Pat. No. 4,949,280, �Parallel Processor-based Raster Graphics System Architecture�, Filed May 10, 1988, granted Aug. 14, 1990. 5. Hedley, David, et. al., U.S. Pat. No. 4,953,107, �Video Signal Processing�, Filed Aug. 28, 1989, granted Aug. 28, 1990. 6. Westberg, Thomas, et. al., U.S. Pat. No. 5,101,365, �Apparatus for Extending Windows Using Z Buffer Memory�, Filed Nov. 7, 1990, granted Mar. 31, 1992. 7. Cawley, Robin, U.S. Pat. No. 5,103,217, �Electronic Image Processing�, Filed Nov. 29, 1988, granted Apr. 7, 1992 8. Liang, Bob, et. al., U.S. Pat. No. 5,182,797, �Multi-Processor Graphics Display System for Displaying Hierarchical Data Structures�, Filed May 27, 1992, granted Jan. 26, 1993. 9. Sokai, Toshio, et. al. U.S. Pat. No. 5,594,844, �Three Dimensional View Using Ray Tracing Through Voxels Subdivided Numerically Using Object Based Parameters�, Filed Jan. 25, 1994, granted Jan. 14, 1997. 10. Uhlin, Keith, U.S. Pat. No. 5,630,043, �Animated Texture Map Apparatus and Method for 3-D Image Displays�, Filed May 11, 1995, granted May 13, 1997. 11. Oppenheim, Alan & Schafer, Ronald, Digital Signal Processing, � 1975, Prentice Hall, Englewood Cliffs, N.J., 12. Oppenheim, Alan & Schafer, Ronald, Discrete-Time Signal Processing, � 1989, Prentice Hall, ISBN 0-13-216292-X 13. Barnsley, Michael & Hurd, Lyman, Fractal Image Compression, � 1993, AK Peters, Ltd., Wellsley, Mass. 02181, ISBN 1-56881-000-8 14. Daubechies, Ingrid, Ten Lectures on Wavelets, � 1992, Society of Industrial and Applied Mathematics, ISBN 0-89871-274-2 15. Kaiser, Gerald, A friendly guide to wavelets, � 1994, Birkhauser, Boston, ISBN 0-8176-3711-7 16. Fisher, Yuval (ed.), Fractal Image Compression, � 1995 Springer-Verlag, New York, ISBN 0-387-94211-4 17. McGregor, D. R., et. al. �Faster Fractal Compression�, Dr. Dobb's Journal, January, 1996, pp 34, etc. 18. Lim, Jae, Two-Dimensional Signal and Image Processing, � 1990, Prentice Hall, ISBN 0-13-935322-4 19. Glassner, Andrew, Principles of Digital Image Synthesis, vol. 1 & 2, � 1995 Morgan Kauffman Publishers, Inc., ISBN 1-55860-276-3 20. Foley, James, et. al., Computer graphics: principles and practice�2nd ed. In C, � 1996, 1990, Addison-Wesley Publishing Company, ISBN 0-201-84840-6 21. Watt, Alan, 3D Computer Graphics, 2nd ed., � 1993, Addison-Wesley Publishers, Ltd., ISBN 0-201-63186-5 22. Watt, Alan & Watt, Mark, Advanced animation and rendering techniques, � 1992, ACM Press, ISBN 0-201-54412-1 23. Prusinkiewicz, Przemyslaw & Lindenayer, Aristid, et. al., The Algorithmic Beauty of Plants, � 1990, Springer-Verlag New York, Inc., ISBN 0-387-97297-8 24. Iwata, Eiji, et. al., �A 2.2GOPS Video DSP th 2-RISC MIMD, 6-PE SIMD Architecture for Real-Time MPEG2 Video Coding/Decoding�, 1997 IEEE International Solid-State Circuits Conference, � 1997 IEEE, ISBN 0-7803-3721-2, pages 258-259. 25. Silverbrook, Kia, U.S. Pat. No. 5,590,252, �Video processor system and audio processor system�, Filed Apr. 28, 1993, granted Dec. 31, 1996. 26. Uhlin, Keith, U.S. Pat. No. 5,630,043, �Animated Texture map Apparatus and method for 3-D image displays�, Filed May 11, 1995, granted May 13, 1997 27. Sakai, Toshio, et. al., U.S. Pat. No. 5,594,844, �Three Dimensional View Using Ray Tracing Through Voxels Subdivided Numerically using object based parameters�, Filed Jan. 25, 1994, granted Jan. 14, 1997 28. Greene, Edward, et. al., U.S. Pat. No. 5,579,455, �Rendering of 3D Scenes on a display Using Hierarchical Z-Buffer Visibility�, Filed Jul. 30, 1993, granted Nov. 26, 1996 29. Poulton, John, et. al., U.S. Pat. No. 5,481,669, �Architecture and Apparatus for Image Generation Utilizing Enhanced Memory Devices�, Filed Feb. 6, 1995, granted Jan. 2, 1996 30. Patterson, David & Hennessey, John, Computer Architecture: A Quantitative Approach (2nd ed.), � 1990,1996, Morgan Kauffman Publishers, Inc., ISBN 1-55860-329-8. 31. Johnson, Mike, Superscalar Microprocessor Design, � 1991, P T R Prentice-Hall, Inc., Englewood Cliffs, N.J., ISBN 0-13-875634-1. 32. Murakami, Kazuaki, et. al., �Parallel Processing RAM Chip with 256 Mb DRAM and Quad Processors�, 1997 IEEE International Solid-State Circuits Conference, pages 228-229, ISBN 0-7803-3721-2. 33. Aimoto, Yoshiharu, et. al., �A 7.68 GIPs 3.84 GB/s 1W Parallel Image-Processing RAM Integrating a 16 Mb DRAM and 128 Processors�, 1996 IEEE International Solid-State Circuits Conference, pages 372-373, ISBN 0-7803-3136-2. 34. Yao, Yong, �Chromatic's Mpact 2 Boosts 3D: Mpact/3000 Becomes First Media Processor to Ship in Volume�, pages 1, 6-10, Microprocessor Report, Vol. 10, No. 15, Nov. 18, 1996, � 1996, Microdesign Resources 35. Shimizu, Tonu, et. al., �A Multimedia 32b RISC Microprocessor with 16 Mb DRAM�, 1996 IEEE International Solid-State Circuits Conference, pages 216-217, ISBN 0-7803-3136-2. 36. Glaskowsky, Peter, �Fujitsu Aims Media Processor at DVD: MMA Combines Long-Instruction-Word Core, Integrated Peripherals�, pages 11-13, Microprocessor Report, Vol. 10, No. 15, Nov. 18, 1996, � 1996, Microdesign Resources 37. �Samsung announces Multimedia Signal Processor�, The John Peddie Associates PC Graphics Report, Aug. 20, 1996, � 1996, John Peddie Associates, Tiburon, Calif. 94920, pages 1153-1156. 38. Yao, Yong, �Samsung Launches Media Processor: MSP is Designed for Microsoft's New 3D-Software Architecture�, pages 1, 6-9, Microprocessor Report, Vol. 10, No. 11, Aug. 26, 1996, � 1996, Microdesign Resources 39. �Chromatic rolls out Mpact�, The John Peddie Associates PC Graphics Report, Aug. 27, 1996, � 1996, John Peddie Associates, Tiburon, Calif. 94920, pages 1182-1183 40. Romney, Gordon, et. al. U.S. Pat. No. 3,621,214, �Electronically Generated Perspective�, Filed Nov. 13, 1968, granted Nov. 16, 1971. 41. Gove, Robert, U.S. Pat. No. 5,410,649, �Imaging Computer System and Network�, Filed Jun. 29, 1992, granted Apr. 25, 1995. 42. Gove, Robert, et. al., U.S. Pat. No. 5,522,083, �Reconfigurable Multi-Processor Operating in SIMD Mode with one processor fetching instructions for use by remaining processors�, Filed Jun. 22, 1994, granted May 28, 1996. 43. �TMX320C6201 Digital Signal Processor: Product Preview�, SPRS051.pdf�January, 1997, � 1997 Texas Instruments, available from the Texas Instruments Web-site http://www.ti.com 44. Weinreb, Daniel and Moon, David, Flavors: Message Passing in the Lisp Machine, AI Memo 602, November, 1980, M.I.T. Artificial Intelligence Lab. 45. Dally, William, et. al., Message-Driven Processor Architecture, Version 11, AI memo 1069, August 1988, M.I.T. Artificial Intelligence Lab. 46. Cray, Seymour, U.S. Pat. No. 4,128,880, Filed Jun. 30, 1976, granted Dec. 5, 1978 47. Beard, Douglas, et. al., U.S. Pat. No. 5,544,337, �Vector Processor having Registers for Control by Vector Registers�, Filed Jun. 7, 1995, granted Aug. 6, 1996 48. Yoshinaga, Toru and Shinjo, Naoki, U.S. Pat. No. 5,598,574, �Vector Processing Device�, Filed Mar. 18, 1996, granted Jan. 28, 1997 49. Cray, Seymour, U.S. Pat. No. 3,833,889, �Multi-mode Data Processing System�, Filed Mar. 8, 1973, granted Sep. 3, 1974 50. Porter, John, et. al., U.S. Pat. No. 4,589,067, �Full Floating Point Vector Processor with Dynamically Configurable Multifunction Pipelined ALU�, filed May 27, 1983, granted May 13, 1986 51. Ellis, James, et. al., U.S. Pat. No. 5,418,973, �Digital Computer System with Cache Controller Coordinating both Vector and Scalar Operations�, filed Jan. 22, 1992, granted May 23, 1995 52. Omoda, Koichiro, et. al. U.S. Pat. No. 4,651,274, �Vector Data Processor�, Filed Mar. 28, 1984, granted Mar. 17, 1987 53. Gallup, Michael, et. al., U.S. Pat. No. 5,600,846, �Data processing system and method thereof�, Filed Feb. 17, 1995, granted Feb. 4, 1997 54. Prince, Betty, Semiconductor Memories: A Hanbook of Design, Manufacture and Application, 2nd ed., � 1983, 1991 John Wiley & Sons, Ltd., ISBN 0-471-94295-2. 55. Product Description: The MIPS16 Application Specific Extension, v1.1, found through the Silicon Graphics Incorporated website on Jul. 24, 1997, http://www.sgi.com/MIPS/mips16.pdf 56. An Introduction to Thumb� v.2.0, Issued March, 1995, � Advanced RISC Machines Ltd. (ARM) 1995. 57. �Volume 1 Editorial�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er0.htm 58. Koenen, Rob, Pereira, F., and Chiariglione, L. �MPEG4: Context and Objectives�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er1.htm 59. Contin, L, et. al. �Tests on MPEG-4 Audio Codec Proposals�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er3.htm 60. Osterman, J�rn, �Methodologies Used for Evaluation of Video Tools and Algorithms in MPEG-4�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er4.htm 61. Ebrahimi, Touradj, �MPEG-4 Video Verification Model: A video encoding/decoding algorithm based on content representation�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er5.htm 62. Avaro, O. et. al. �The MPEG-4 Systems and Description Languages: A way ahead in Audio Visual Information Representation�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er6.htm 63. Doenges, P. et. al. �MPEG-4: Audio/Video & Synthetic Graphics/Audio for Mixed Media�, Image Communication Journal: Special Issue on MPEG-4, downloaded the week of Jul. 17, 1997, from http://drogo/cselt.stet.it/ufv/leonardo/icjfiles/mepg-4_si/pap er7.htm 64. Gosling, James, Joy, Bill and Steele, Guy, The Java� Language Specification, � 1996 Sun Microsystems, Inc. published by Addison-Wesley, ISBN 0-201-63451-1 65. Arnold, Ken and Gosling, James, The Java� Programming Language, � 1996 Sun Microsystems Inc. published by Addison-Wesley, ISBN 0-201-63455-4 66. Intel, Accelerated Graphics Port Interface Specification, rev. 1.0, Intel Corporation, Jul. 31, 1996 67. Universal Serial Bus Specification, rev. 1.0, by Compag, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, NEC, Northern Telecom, Jan. 15, 1996 68. Solari, Edward and Willse, George, PCI Hardware and Software, 3rd Edition, � 1994, 1995, 1996, Published by Annabooks, San Diego, Calif., ISBN 0-92392-32-9, Fifth printing, January, 1996 69. Shanley, Tom, Anderson, Don, PCI System Architecture, 3rd Edition, � 1995Mindshare, Inc., ISBN 0-201-40993-3, First Printing, February 1995 70. Papaichalis, Panos and So, John, �Implementation of Fast Fourier Transform Algorithms with the TMS32020�, pages 84-85, Digital Signal Processing Applications with te TMS320 Family, � 1986 Texas Instruments, Incorporated. Patent Citations
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Summary: Reading Popular Culture is an economical Penguin Academics#xA0;thematic reader exploring a full range of topics in the field of contemporary popular culture from a variety of theoretical perspectives. #xA0; This book takes up the most important general questions that arise from our immersion in the culture of everyday life: why do the artifacts of popular culture, such as certain movies or websites, app ...show moreeal to us, and what effect does our engagement with each of these phenomena have on us?#xA0; Chosen for both their theoretical and rhetorical approaches, the selections inReading Popular Culturewill challenge and engage instructors and students alike. ...show less
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I have such a curiosity about words and exploring the depths of their meanings. In the English language, some words have up to forty or more meanings. That kind of verbal complexity absolutely fires me up!
Part of the reasons writing, reading, and words fuel me is they are the ingredients of story. Story, in every form, carries so much power. Stories have the power to inspire, to teach, to emote, to entertain, to awaken, to guide, and so much more. Stories have the power to release something into the world that wasn't there before!
Every person we encounter is in the process of living a story. Some of us are conscious to it and some of us are not. Some of us step through life with intention and focus and others of us meander and wander. Either way a story is being woven every day.
If I'm being perfectly honest, sharing my story is not always the easiest thing. The world is not always a tender place of reception for the most vulnerable parts of us. My story has been received before with many reactions and not all of them have been pleasant.
But, if it's true that stories have the power to release something new in the world, it gets me curious about the idea of release. The word has several meanings, actually. One of them is "to free something from it's restraints."
Telling our stories has the power to free something in us that has been restrained.
Part of my story has been restrained inside of me for years. I have only let it out in little pockets of safe community or to trusted friends. Today is a day of release for that part of me that has been restrained.
I'm so excited (and terrified at the same time) to release my first book, Reflections of the Twelve Steps : A Companion to Freedom, on Amazon today. That part of my story receives it's freedom today from the restraints that have held it captive for so many years. My deepest prayer is that many who find themselves restrained by addictions, compulsions, and pain will find their way towards freedom.
I wonder what part of your story is being restrained inside of you. What would it look like for you to tell your story? What inside you needs to be freed from it's restraints? I would LOVE to hear your story today!


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Mon, Sep 30, 13 at 10:57
Here is a picture of my son's clematis flowering for the second time this year. It's about 3 ft. high and 5 ft. across. |
Follow-Up Postings:
Why do you think this is Clematis montana? Does it have the same foliage? |
- Posted by plantknitter 8 (My Page) on Tue, Oct 1, 13 at 1:46
Is this blooming now or is the picture from last spring? |
- Posted by dottyinduncan z8b coastal BC (My Page) on Tue, Oct 1, 13 at 11:54
This is what they told me they bought last year but they can't find the tag. This picture was taken last week and the flowers have opened up even more now. I have to tell you that they are not conscientious gardeners so I'm sure this plant has had to look after itself most of the time. |
Probably C. terniflora or similar. |
- Posted by gardengal48 PNW zone 8 (My Page) on Tue, Oct 1, 13 at 14:06
Yes, I seriously doubt it is a montana.........first, I have never encountered a 'dwarf' montana - they get to be massive vines. Second, while they can throw a few flowers in late summer or fall, they would never have a second bloom period as intense as that shown in photo. And white montanas are not at all that common and tend to be somewhat hard to find - most cultivars are in various shades of pink. Could be C. terniflora - an appropriate bloom time for that species as well as similar appearance. But a second bloom cycle?? Very unlikely. And if SAC, it too is no dwarf - it can get as large - if not larger - than any of the montanas. 25-30 feet is pretty standard. |
One my girlfriend had for years on Camano Island never got very big, maybe 10' or so at one point. |
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South Australian iron ore explorer IronClad trials offshore loading system in seas off Adelaide
- From: The Advertiser
- February 13, 2013
WILCHERRY Hill iron ore explorer IronClad Mining has successfully trialled a new offshore bulk commodity loading system in seas off Adelaide, in what is believed to be a world first.
IronClad yesterday said the loading system had the potential to significantly cut iron ore transport and shipment costs from its planned mine, near Kimba on the Eyre Peninsula.
"The world-first style of offshore transhipment operation has been designed, developed and fine-tuned exclusively in South Australia," chief executive Robert Mencel said.
"We are not aware of anywhere else in the world where this same system is in operation, and believe it has the potential to revolutionise the loading of some bulk commodities onto offshore anchored vessels."
IronClad Mining plans to transport direct shipping ore from Wilcherry Hill to vessels anchored seven nautical miles off Lucky Bay in the Spencer Gulf.
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stunnel and zookeeper and timeouts
I am running a 3 cluster setup where the zookeeper connections (both client
- server and server - server ) run through stunnel. Stunnel has an idle timeout setting, where if it sees a connection that is idle (default 12 hours) it tries to close it. I see that for the server to server, there are two ports/connections configured in zookeeper. One for followers to be connected to the leader and a separate one for leader election. My question is, after the cluster is bought up, and leader election is done, is there any activity (keep-alive etc) on the leader election connections, if things are operating normally? If not, i am worried stunnel will try to close this port as there is no activity. Thanks, -Prakash +
Patrick Hunt 2012-12-17, 08:25
Matt Wise 2012-12-22, 05:56


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Being a traveling writer is an exciting occupation. You get to do what you love the most and travel at the same time; visiting different cities, experiencing different cultures, and eating different foods. People can only dream about the places that you travel and would love to follow you on Instagram to live their dream of travelling through you. You can also benefit from Instagram because the more people follow you and your travels, the more popular your work gets, and you may receive more business prospects. Below we will show you some create ways to gain followers for your Instagram page.
Visit more than the typical sites
Everyone knows the Eiffel Tower, the Leaning Tower of Pisa, and other iconic sites; but what about the sites and places that they don't know that could be just as exciting. Ask the locals about other grand sites or just go exploring, and document everything that you found pleasurable. Discover old taverns that no one knows about, a grand theatre that has been standing for hundreds of years but is not well known, or a hidden cave. Try to find a unique discovery everywhere you go your followers will really appreciate it. When people find or learn something new from your post they will tell their, thus gaining you more followers
Make a game out of it
If Carmen Sandiego was your favorite character as a kid and you always wanted to be her, now here is your chance. People love to test their knowledge and will be excited when trying to figure out where you are or where you are going next. Take a picture of anything you want and provide clues on where you might be. Give a brief history and ask people to guess. People who are really into traveling and history will love to follow you.
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When the Grammy nominations were announced last night, there were numerous notable events and a slew of live performances, but if you ask Beliebers, the biggest moment was Psy earning a Grammy nom over Justin Bieber. Never mind that Psy didn't receive a single nomination; this was a tragic oversight that can only be corrected by angry, hyperbolic tweets.
According to the Bieber Army, Psy is irrelevant and can "sit on a cactus," the Grammys lost "millions of views" and an army of Beliebers are now insisting that this is a sick joke, finding Jesus, loading up on guns or giving up on humanity. And the kicker for many: "Gangham Style" isn't even in English!
Imagine what would have happened if Psy was actually nominated.
You were saying, Beliebers...


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When members of a high-school class reunited this summer to celebrate their long-ago graduation, they asked one of their classmates to get their senior-year annual online.
Lounge member t8ntlikly is the designated producer. Although he found most of his efforts went well, he ran into perplexity reproducing captions and photos that spanned spreads.
What programs other than Photoshop would help him accomplish that? See what fellow Loungers recommend.
The following links are this week's most interesting Lounge threads, including several new questions to which you may be able to respond:
starred posts: particularly usefulIf you're not already a Lounge member, use the quick registration form to sign up for free. The ability to post comments and take advantage of other Lounge features is available only to registered members.
If you're already registered, you can jump right in to today's discussions in the Lounge.
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Cook this easy spaghetti pie for a quick and budget-friendly weeknight dinner.
All You AUGUST 2005
Bring a pot of salted water to a boil, add spaghetti and cook according to package directions, stirring often, until al dente. Drain pasta and rinse well with cold water.
Preheat oven to 400°F. Grease an ovenproof 9- or 10-inch skillet with about 1/2 Tbsp. butter.
In a bowl, whisk together eggs, milk, bacon, scallion, pepper and 3 Tbsp. Parmesan. Add spaghetti; mix well. Transfer mixture to skillet, spreading evenly. Dot with remaining butter and sprinkle remaining 1 Tbsp. Parmesan on top. Bake for 25 to 30 minutes, until center is set and top is golden. Let cool for 10 minutes before serving.
Go to Full Version of


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New Delhi-based designer Manish Gupta on his festive line for Chennai
Ever since Manish Gupta launched his eponymous line in 2007, he's been quite a style-setter in the New Delhi fashion circuit. Having embraced the energy and edge of urban styling from top designers, including Rohit Bal, before he made it on his own, the young designer's USP has evolved.
Ahead of the launch of his new line in Chennai, at Collage, Gupta speaks about his unspoken bond with work-intensive crafts. "Textures and needle work have fascinated me. I try to incorporate them subtly in all my work. Since most of the work is tonal, I pick my fabrics and create textures in such a way the work stands out."
Manish's collection for Chennai comprises both ethnic and Western clothes. "I'm doing a festive line for the first time. It's called 'Interpreting the Festive'. Celebration is the essence of the line as the festival season is around the corner. It's about colour and 'essential' bling. Moss, ruby and mustard are some of the colours. I've used silk, silk-cotton and brocade to create ensembles. I've veered away from traditional cuts and given them a fresh spin."
As for his regular Western line of dresses, Gupta tempers bold new looks with clean lines. Well structured with panels, the dresses are seemingly simple. But Gupta's artistic flourishes give the garments a distinct look. "I've used satin tape and feel-good floral jali work in wispy fabrics such as silks and georgettes. It involves painstaking work."
For the upcoming Wills Lifestyle India Fashion Week (October 2009), Gupta is working on special weaves and textures. "Such experiments can make a big difference to modern silhouettes."
Having worked with design aces Abhishek Gupta, Nandita Basu and Rohit Bal, he says, each has contributed immensely to his evolving aesthetic. "I learnt finesse and finish from Abhishek and Nandita. At Bal's studio, I learnt the importance of creative freedom as a designer. With freedom comes creativity. Because, ultimately good design is about autonomy."
Conjuring up a new line every season isn't a big deal for Gupta because he draws inspiration from everything around him. "It can be anything — architecture or flora and fauna. Simple ideas can spur refreshing lines."
Keywords: Manish Gupta, ethnic, Western wears, fashion, clothing


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Record of Agarest War Zero
this wiki
Record of Agarest War Zero, known as Agarest Senki Zero (アガレスト戦記 ZERO, Agaresuto Senki Zero) in Japan, is a tactical role-playing game developed by Compile Heart and Red Entertainment. It was published in Japan by Idea Factory on June 25, 2009 for the PlayStation 3 and published by Aksys Games in North America on June 14, 2011 for the Playstation 3 and Xbox 360. It is the prequel to the 2007 game Record of Agarest War.
As of July 2010, Agarest Senki Zero: Dawn of War has been released for Xbox 360. The Xbox 360 version was released with extra content not found in the PS3 version of the game, such as costumes, CGs and more. There is also an extra mode where you can return to the maps from the previous game, and unlock characters via PlayStation Store. This mode is available in both the PlayStation 3 and Xbox 360 versions.
Agarest: Generations of War Zero for PC (Steam) has been released on April 17, 2014.
Long before Summerill and the gods of darkness were defeated in Record of Agarest War, another battle was fought across generations to save the world from evil. Record of Agarest War Zero takes you back to that ancient time…
The war between the forces of darkness and the forces of light, a conflict already many years old, has been fought to a stalemate. In the nation of Kraltarla, the forces of light hold back the evil hordes of darkness spilling from Findeste at the Scarred Mountains, but only just. In a desperate attempt to gain an advantage that could change the course of the war, the generals of the armies of light dispatch their loyal servant Sieghart, whom fate has seen fit to grant a strange and awesome power. Sieghart's mission takes him across Kraltarla to gather the components for a magical tool that can free the imprisoned blacksmith of the gods, so that he might forge magical artifacts of great and terrible power for the forces of light.
The Battles are the same as the first game, the maps, and the Soul Breed System. Two new systems were introduced, The Feel Link System and the Free Intention. There is also an Extra Mode.
Differences / ImprovementEdit
There are some differences from the original Agarest games.
- First of all there are only 2 generations in this games. The first gen save the world and the second tries to protect it.
- There are only 15 members, 9 in the first gen and 6 in the second. This is a lot less than the first game with the first having 34 characters.
- Featured in the game, Trinity Universe, Agarest will now use AAA (Active Animation Adventure), known in this game AAS (Action Animation System). As such characters mouth will move while talking, eyes will blink, and clothes and hair will rustle in the wind.
- There is a new fairy-like race. In the previous game fairy-like creatures were only opponents (e.g. Titania [1]).
- The towns and city menu are more interactive.
- Players now have more control over the battle style of the main character, as well as his skills, by way of a card system. By picking the appropriate cards, Sieghart can be customized to reflect the type of fighter one wishes to play.
Feel LinkEdit
A new system is introduced called the Feel Link System. The Feel Link System is where the heroine's costume, and dialog depend on their relationship level.
Free IntentionEdit
Another new system, players can build relationship with the heroines. This may result in new costumes,CGs, and items. This is accessed by the City Menu. These costumes have been confirmed - Maid, Shinto Priestess (Miko), a Nurse and School Uniform. This is not limited to the Love Interests.
Extra ModeEdit
If the players have a Clear Data from the first game, it's possible to load it and unlock the Door to the Future after some progress. Through the Door, players can access the maps from the first game and unlock items and characters from the first game. Leonhardt, his descendants, the heroines, Ellis and Dyshana are unlocked free. However, other playable characters must be downloaded from the Playstation Store. It is currently unknown if this will be a feature in the English versions or if it have to be downloaded from the Playstation Network/Xbox Live Marketplace.(Players can unlock this mode once beating the game then replaying it on Hard.)
On November 5, 2010, Aksys Games announced that it will bring both the PlayStation 3 and Xbox 360 versions of Agarest Senki Zero to North America as Record of Agarest War Zero. It was released on June 14, 2011.
- The Limited Edition will include:
- 48 page Character Data Guide
- The Soundtrack
- Special Card Set Including one deck of Playing Card (with characters printed on them) and a deck of collectible skill card with a specil box.
Ghostlight, on the other hand, is bringing the game to SCEE territories as a PlayStation 3-exclusive.
- The Collector Edition will include
- Black T-shirt (bespoke design to Ghostlight ) *GL pre-order item only*
- Blu-ray PS3 game (of course)
- A3 double sided poster showing on one side the concept drawing of the image used on the inlay and on the other the finished coloured artwork
- Agarest: GoWZ OST
- 3 x 3D lenticular art cards
- All of this will be packaged neatly in to a Collector's Edition box.


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Noby Noby Boy
Easy Trophy total: All 12 trophies
Time necessary: Four hours
This $5 oddity from the creator of Katamari is a great, creative PSN exclusive based around the very odd idea of stretching a caterpillarish thing as much as possible. It's full of the endearingly weird stuff the game's creator is known for, and while it perhaps wasn't the best game last year, it's without a doubt one of the most original.
Above: Just eat the title in the manual for a very easy gold Trophy
Thanks to the game's wacky style and lack of clear goals, it's got some of the easiest trophies around. Most involve just stretching Boy a certain amount or eating a set number of people. And the gold Trophy requires you to eat the title in the in-game manual. Since it's a PSN game, there's no platinum, but that's certainly one of the simplest golds we've seen.
Eat Lead: The Return of Matt Hazard
Easy Achievement total: 925 points
Time necessary: Eight hours
Having the dubious honor of our Anti-Award for worst game with best story, Eat Lead wasn't an atrocious game, even if at least one boss battle is so bad it could count as a war crime. But this lackluster third-person shooter had such a great premise, and so much genuine humor going on, that it made us pretty sad that few could bring themselves to suffer through the gameplay for the laughs.
Above: You can earn your first hundred in less than five minutes
So maybe it will encourage you to give this game a try if you know it's filled with very gettable Achievements/Trophies. In our first standard play-through on 360, we got nearly 800 points in the eight hours it took to beat the campaign, and another 100 shortly after that. Not only do you get tons of points for unmissable campaign moments, but many rewards are jokes: starting the game, trying to play nonexistent multiplayer or pressing pause, with some witty descriptions for good measure. It almost makes the game fun to play… almost.
Terminator: Salvation
Easy Achievement total: 1000 points
Time necessary: Eight hours
Remember that hilarious viral sound-bite of Christian Bale yelling at some guy? It was probably the funniest thing to happen all year. Well, few may know this, but during that tirade, they were filming an underwhelming movie called Terminator: Salvation. And as companies are fond of doing, a tie-in game was made for this little-seen release, and boy did it suck. Christian Bale's likeness was not included, it had THREE enemy-types outside of its horrible driving sections, and it was just an ugly, boring Gears of War rip-off.
Above: Yup, they couldn't get the rights to Christian Bale
But here's an end-of-the-year countdown where this lackluster game can shine. That's because it had some of the most straightforward goals of 2009. The game was so bereft of imagination that all its Achievements/Trophies are campaign related. Just finish the game on normal and you'll have gained 820 points or all but one gold Trophy in the game with just a few hours' work. Now the final award involves beating the game on hard, and we didn't feel it was worth it, as the game can get insanely cheap on that setting. But if you must have all 1,000 or the platinum Trophy, then have at it, you nut.
Band Hero
Easy Achievement total: 900 points
Time necessary: Seven hours
Boy, last year publishers created a giant carbon footprint, thanks to the ungodly amount of plastic crap that was clogging store shelves. Contributing to the detritus was Band Hero, made as a more casual and kid-friendly alternative for those afraid of some T-rated Guitar Hero rocking. It's not a bad idea – no worse than most Guitar Hero spin-offs, anyway – and we accept it wasn't really made for us. But that doesn't mean we can't mine it for points!
Above: One step closer to the 490 point behemoth
As any Achievement/Trophy enthusiast/whore will tell you, kiddie games are a goldmine. The bar is set very low, because the intended audience is supposedly not that good at games. That's the case with Band Hero, as most are pretty easy, and it has one of the biggest single Achievements of the year, valued at 490 points. How do you get it? Just find all the secret notes in the game, which is pretty simple with a guide. But the real cheaters out there can play mic-only on Beginner difficulty, and put the mic next to a fan or something else that makes constant noise for every song. You can't fail and will five-star every song (but keep the means of your victory to yourself, for your pride's sake).


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The original deal pioneer keeps on pinching pennies and cracking wise. No, that price isn't a typo.
Go to Woot
Candlepower and puppet shows are so passé. Get the newest TVs, speakers, home theater gear, and more.
Go to Electronics.Woot
The robots are coming! And so are the laptops, the tablets, the chargers, and all sorts of other gadgets!
Go to Computers.Woot
High living at low prices with name-brand deals for your pad, crib, nest, or castle - inside and out.
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Make it, build it, improve it. But whatever home project you've got in mind, start by saving money on it.
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Sports, fitness, and outdoors deals, because saving money is only one of your passions.
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You don't have to spend a lot to look like you do. Werk it and twerk it with amazing deals on designer watches, handbags and more.
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Our exclusive graphic tees will make you laugh, will make you cry, will make you look totally hot.
Go to Shirt.Woot
Direct from the winery to your thirsty lips: wine deals worth doing a spit-take over.
Go to Wine.Woot
Last chance deals for hardcore cheapskates. Catch 'em before they - you guessed it - sell out.
Go to Sellout.Woot
447,999 deals (and counting) from around the web, shared and ranked by a community of deal fiends like you. Go to Deals.Woot.
cute. but ill pass.
Open Letter to Woot Staff Dear Woof Staff, I love woot. Sincerely, Woot X
Note: This post contains pricing information for future reference because it is generally not available elsewhere once the next Woot has been offered. The Must-See Comedy Shirt of the Summer $10.00 + $0.00 shipping + or $5 to get it by Thursday condition: Unauthorized product(s): 1 Navy Woot Tee (3627) Size: WS, WM, WL, S, M, L, XL, 2X
shirtly, you can't be serious
3xl please
aww, this one is just plain bad!
does these shirts have back prints?
yay ... unauthorized ...
I get it. Funny stuff. Really.
worst. shirt.ever.
err do not want this
Another blue shirt makes me blue : - ( Hopefully tomorrow will be more witty
lets do better guys
LOL not bad Woot.
normalbrains wrote:Please clarify a few things for us. You are offering t-shirts under the assumption of exclusivity and limited edition, but this is not actually the case. The first two shirts "sold out", but then reappeared for $5 more.
Where are they promising exclusivity?
Not a great joke, woot - not even a good one. Yesterday's shirt was far better in comparison.
so this also goes off at 12 midnight like reg old woot?
H+ now YOUR TALKIN "shake this "at all you shirtwoot Unlovers...I know I know that was me too...... This one a can get behind.
NO! Not again. To spend $10/day on a woot-fetish, it's gotta be good!
mmkay.. I liked the past shirts, but this one lame.. I still love shirt.woot and its potential with a passion.
gagz135 wrote:Woot. I hate you. THis is ridiculous. I'm already done with shirt.woot.
dont go whos gonna buy all the good stuff coming soon
Those of us with a Comic Book Guy physique will not be satisfied with a tight-fitting 2X.
wear your shirt, insult yourself. nope. and I thought this one would be SO CLOSE. I'm weeping with joy!!
I agree with the shirt's sentiments exactly. pass.
So far, I'm not really all that impressed with these shirts. The first two designs were too busy and this one...it's like someone just phoned it in.
This is terrible. Even if I liked The Simpsons I wouldn't buy this. At least the last two shirts I wouldn't feel embarrassed by wearing.
normalbrains wrote:Open Letter to Woot Staff Dear Woof Staff, Please clarify a few things for us. You are offering t-shirts under the assumption of exclusivity and limited edition, but this is not actually the case. The first two shirts "sold out", but then reappeared for $5 more. examples: Sore Thumbs: http://shirt.woot.com/Friends.aspx?k=3622 Shirt.Woot Launch: http://shirt.woot.com/Friends.aspx?k=3618 Ive got no problem with capitalism and you guys making fat loot, ive just got a problem with purchasing "exclusive" tees under a false pretense. for example, by looking at the "sore thumbs" product stats, it would appear that the sore thumbs t-shirt had a total print run of 500 pieces. Since many people have purchased this tee after it "sold out", this is obviously not true. So, here are my questions: 1.) Will you publicly disclose the exact amount of every print run? 2.) Will every "sold out" tee be available for $5 more after it "sells out"? We the wooters would prefer a more transparent and forthcoming shirt.woot.com experience. Thanks for your time and good job, Woot X
OMG I AM PISSED NOW! I just bought a launch shirt off ebay for $25, and here they show up again for $15 shipped! Not cool, woot, not cool AT ALL.
but then again, imagine this one over a GREAT RACK ...
Yet they don't even have a shirt to fit someone half the size of Comic Book Guy.
Awwww why are people buying this? Don't encourage these shirts!!! Just not good at all woot. I thought maybe the first couple shirts were flukes. But I mean...are you trying? I'm done with shirt.woot until there comes a day, if there comes a day, where i miss out on something I'd want. As of now, i doubt that will happen.
jbzcar wrote:OMG I AM PISSED NOW! I just bought a launch shirt off ebay for $25, and here they show up again for $15 shipped! Not cool, woot, not cool AT ALL.
Its not woots fault your a sucker.
oister wrote:shirtly, you can't be serious
Now, THAT'S a woot shirt I would buy - good form, old man!
best. unliscenced. merchandise. ever
this is fairly amusing as a concept, but i wouldn't wear it... it's only really funny if you wear it to the movie in question opening weekend... if i'm buying a funny shirt i want it to be funny every time i wear it. keep up the good work woot, just get back on track a bit tomorrow, k?
please add my vote for 3x because AA is small as hell
3X! HEY... WOOT! You should start another new woot.. cigar.woot.com I LOVE cigars! Would be a cool item to woot on!
I'm in! Woot!
Why the shirts don't fit. You want fries with that?
Anim8ir wrote:worst. shirt.ever.
I'm blinded by your originality. Best.Joke.Ever.
View All →


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Follow Us: Twitter | Facebook | Google+ | Pinterest | Quick Links: Join Blogger Programs | Featured Moms | More Featured Moms
Hello ladies! Are you looking for new followers? Do you need some feedback on your blog? Look no further! Let's get to know one another by following each others blogs and providing positive feedback. I have noticed that there are lot's of discussions that say they will follow back and don't. Let's not be like that. Let's help to build each others following.
I can't wait to connect with all of you!!
I just followed your blog and your FB page. Please following me back at:
Thanks much,
Hi Ana! I just followed you and I LOVE your blog!!! Thanks
hello mommies , check my blog and follow i'll follow back ..
Website : http://www.mywealthyjourney.com/
hey im debra heres my info
i hope to make new friends on here and ill follow back
following your blog - http://mometimes.wordpress.com/
Does this you follow me and I follow you thing works?
mine is http://fonmee.com and http://glad2bhere.com
I'm following you! :)
Hello my fellow mommy blogger! I am following everyone that left a blog link. Please follow me back.
Love this! I will follow all that follow me just leave me a comment with your links
Mine are
Every Topic Under the Sun Blog
Hello ,
welcome to bloggers , just wondering if we could exchange follows? you got nice blog.. please follow
www.mywealthyjourney.com . i followed.
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Brittany is a director of the Toxic Free Foundation and created the first ever Toxic Free Certification Program. Weekly, Brittany publishes the Toxic Free Blog and provides coaching to over 10,000 families in the United States alone. She is the author of a Toxic Free educational series and co-author of several Toxic Free learning programs. Brittany is also an award winning author.
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rideau 500 1957, excellent condition, collector car. Apparently only a few build. Runs Great engine 312 po cu 2bbl Car belonged to my dad took... More
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