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714 - Error detection/correction and fault detection/recovery
714799000 - Error/fault detection technique
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|Class / Patent application number
|Number of patent applications / Date published
|Modulo-n residue check character
|Determining a message residue - In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
|RESIDUE GENERATION - In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
|REDUCING A DEGREE OF A POLYNOMIAL IN A POLYNOMIAL DIVISION CALCULATION - An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.
|METHOD AND APPARATUS FOR PROCESSING A DOWNLINK SHARED CHANNEL - A method and apparatus is disclosed wherein a user equipment (UE) receives control information on a first channel and uses the control information to process a second channel.
|DATA TRANSMITTING APPARATUS AND DATA RECEIVING APPARATUS - To provide a data transmitting apparatus and the like capable of enhancing error detection accuracy without increasing a bandwidth unnecessarily used for the error detection performed on encrypted data and minimizing deterioration in sound quality of the data by effectively reducing noises in the transmission of the data through networks for cars and the like even though the data transmitting apparatus has been simply structured. The present invention makes it possible to perform error detection on audio data according to the sizes of encrypted blocks or packets using simple error check codes embedded in the audio data, or to perform error detection using a variation sequence of attribute information to be transmitted together with the audio data. In this case, output of the sound resulting from the audio data having an error is stopped.
|SYSTEM AND METHOD PROVIDING FAULT DETECTION CAPABILITY - A system and method for providing fault detection capability is provided which comprises a first node (
|APPARATUS AND METHOD FOR DECODING IN MOBILE COMMUNICATION SYSTEM - Provided are an apparatus and a method for improving the performance of a decoder by improving a decoding speed when correcting an error of a control signal in Long Term Evolution (LTE). The apparatus includes an error determination unit for performing a traceback operation on a received signal, and simultaneously determining if an error has been generated to the received signal.
|METHOD OF ERROR DETECTION FOR WIRELESS TRANSMISSION - A transmitter generates an encrypted data by processing a specific data according to a specific transmission mode, generates a verification code according to the specific transmission mode, and provides a protocol data unit according to the encrypted data and the verification code. After transmission, a receiver decodes the protocol data unit and determines whether the decrypted data of the protocol data unit matches the verification code, thereby providing error detection for wireless transmission.
|APPARATUS AND METHOD FOR PERFORMING CYCLIC REDUNDANCY CHECK (CRC) ON PARTIAL PROTOCOL DATA UNITS (PDUS) - The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.
|TERMINAL APPARATUS AND RESPONSE SIGNAL TRANSMITTING METHOD - A terminal apparatus and a response signal transmitting method wherein the system transmission efficiency can be improved by devising a bundling rule. In a terminal (
|CHECKSUM CALCULATION, PREDICTION AND VALIDATION - A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.
|64b/66b Coding Apparatus and Method - A system and method for transmitting digital data over a transmission medium includes receiving digital values representing a plurality of N-bit characters to be output over the transmission medium, each N-bit character being either a data character or a control character. A determination is made as to which of the plurality of N-bit characters are control characters. The digital values represented by the plurality of N-bit characters are encoded to provide an encoded codeword, the encoded codeword being {Mx(N−1)+P} bits having M fields of N−1 bits, each of the M fields corresponding to one of the N-bit characters being encoded. The encoding further includes: designating, for each data character, the respective field of the M fields as a data field, designating, for each control character, the respective field of the M fields as a control field, and ordering the M fields to position any control fields at predetermined positions with respect to each other in the encoded codeword and to position any data fields at other remaining positions within the encoded codeword. The encoded codeword is then transmitted over the transmission medium. A system and method that receives such an encoded codeword over a transmission medium is also contemplated.
|System and Method for Pre-calculating Checksums - In a packet transmission system that uses checksums, partial checksum calculations may be performed during periods of processor underutilization while the data is awaiting final output processing for transport. A system wide checksum service process may coordinate checksum calculations across multiple network protocol layers. The checksum calculations for the buffered data may be performed according to a priority assigned to the buffered data. For example, buffered data whose transmission is imminent may have a higher priority than buffered data that will be transmitted at a later time. Applications that generate data for transmission may register those portions with the service for checksum calculation. To simplify the process, a metadata structure may be created for the data portion, and used to manage the checksum calculations.
|PARITY ERROR CHECKING AND COMPARE USING SHARED LOGIC CIRCUITRY IN A TERNARY CONTENT ADDRESSABLE MEMORY - Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.
|Data transfering apparatus - An information processing apparatus includes a data transmitting apparatus that transmits data of an N-bit width; a data receiving apparatus that receives the data of the N-bit width from the data transmitting apparatus; and a data bus of the N-bit width connecting the data transmitting apparatus and the data receiving apparatus. The data transmitting apparatus includes a first error-detection-code-attached data generation circuit, a second error-detection-code-attached data generation circuit, a first degeneration correspondence register, and a transmission-side selection circuit. The data receiving apparatus includes a first error checking circuit, a second error checking circuit, and a second degeneration correspondence register.
|INFORMATION PROCESSING APPARATUS, COMMUNICATION CONTROL METHOD, AND COMMUNICATION CONTROL SYSTEM - According to an embodiment, an information processing apparatus includes: a receiving unit that receives a fragment packet; an extracting unit that extracts checksum information of which packet has not been subjected to the fragmentation process, and causes the checksum information to be stored in a checksum storage unit; a calculating unit that performs a checksum calculation on each of the plurality of received fragment packets, integrates a calculation result of each fragment packet, and causes an integrated calculation result to be stored in a calculation result storage unit; and a determining unit that determines whether or not there is an error in a packet obtained as a result of combining based on the integrated calculation result stored and the checksum information stored.
|Method and Apparatus for Determining a Cyclic Redundancy Check (CRC) for a Data Message - A CRC (Cyclic Redundancy Check) code for a data message is created by placing an initial portion of the data message on a bus of width W bits consisting of an integral number N of segments of width S such that the initial portion of the message fills n complete segments, where n≦N. A known bit pattern is placed on any segments preceding a start of the message as determined by a start indicator. A first intermediate CRC code is computed for the n segments of the initial portion by applying the W bits of the bus forming an input word to a CRC full processing circuit using a compensating constant to compensate for any known bit pattern preceding the initial portion of the message. Subsequent portions of the message width W are placed on the bus during subsequent bus cycles, and in each case a new first intermediate CRC code is computed on the W bits of the bus as input words using the current first intermediate CRC code as a seed input. A final portion of the message as determined by an end indicator is placed on the bus. The final portion has a width w bits, where w≦W, and at least completely occupies s segments, where s
|SERIAL INTERFACE DEVICES, SYSTEMS AND METHODS - A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values.
|CODE ERROR DETECTOR AND ERROR DETECTING CODE GENERATOR - A code error detector includes an input data generator and a code calculator. The input data generator divides received data into a plurality of data blocks, each including the same number of code bits as a predetermined number of parallel processes. The code calculator receives, as a parallel input, the code bits of each of the data blocks and applies a parallel calculation based on a predetermined generator polynomial on the data blocks to perform an error detection process. When a bit is missing from any of the data blocks, the input data generator inserts a dummy bit into a bit position of the missing bit.
|OPTIMIZATION OF PACKET BUFFER MEMORY UTILIZATION - A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.
|METHODS AND APPARATUS TO COMPUTE CRC FOR MULTIPLE CODE BLOCKS - A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.
|Communication apparatus and method therefor - Provided are a communication apparatus and a method therefor that are capable of executing a checksum attachment processing without increase of a circuit scale. A data generating unit (for example, a CPU) that forms a communication apparatus generates data, and stores the data in a memory. A checksum processor calculates a checksum for the data read from the memory, and writes the checksum into a predetermined position in the data stored in the memory. A data sending unit (for example, a transmission processor, a MAC processing circuit, and a PHY processing circuit) reads the data having the written checksum from the memory, and sends the data to a network.
|OPTIMIZED DECODING IN A RECEIVER - A receiver includes a decoder configured to decode at least a portion of a data stream comprising a data frame. The data frame includes a code block having a data block and a parity block. The receiver also includes a controller. The controller is configured to determine whether to disable at least a portion of the receiver during transmission of the parity block to the receiver when the data block contains at least one erasure.
|ERROR DETECTING DEVICE AND MEMORY SYSTEM - According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.
|SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD - A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
|Method and System for Interlocking Data Integrity for Network Adapters - Certain aspects of a method and system for interlocking data integrity for network adapters are disclosed. Aspects of one method may include executing a plurality of interlocking checks within a network adapter. Each interlocking check may comprise receiving a plurality of input check values associated with a plurality of input data packets corresponding to a first protocol. A plurality of check values may be generated which are associated with the plurality of input data packets and a plurality of output data packets corresponding to a second protocol. The data integrity of the plurality of input data packets and the plurality of output data packets may be validated based on one or more comparisons between one or more of the generated plurality of check values and one or more of the received plurality of input check values.
|METHOD AND APPARATUS FOR ENCODING AND DECODING HIGH SPEED SHARED CONTROL CHANNEL - A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding, cyclic redundancy check (CRC) bits are generated based on part 1 data and part 2 data. The number of CRC bits is less than the WTRU ID. The CRC bits and/or the part 2 data are masked with a mask. The mask may be a WTRU ID or a punctured WTRU ID of length equal to the CRC bits. The mask may be generated using the WTRU ID and a generator matrix with a maximum minimum Hamming distance. The masking may be performed after encoding or rate matching.
|NETWORK MANAGEMENT APPARATUS FOR SETTING COMMUNICATION METHOD OF NETWORK APPARATUS - A network management apparatus includes: a receiving unit for receiving from a first network apparatus a notification of a communication method setting incompatibility with a second network apparatus connected to a first port of the first network apparatus; and a setting unit for setting on the second network apparatus a communication method of the second port of the second network apparatus connected to the first network apparatus such that the communication method of the second port matches a communication method of the first port of the first network apparatus.
|METHOD AND APPARATUS FOR ENCODING AND DECODING - A method of encoding a bit sequence over a Physical Downlink Control Channel (PDCCH) having Downlink Control Information (DCI) including: determining DCI bits to provide a DCI bit sequence; performing a CRC calculation on the DCI bit sequence to provide a CRC parity bit sequence; scrambling the CRC parity bit sequence to provide a scrambled CRC bit sequence; if the DCI format is LTE-A, further scrambling the DCI together with the attached scrambled CRC bit sequence to provide a LTE-A scrambled bit sequence; channel coding either the DCI attached scrambled CRC bit sequence or LTE-A scrambled bit sequence to provide a channel coded bit sequence; modulating the channel coded bit sequence to provide a modulated symbol sequence; layer mapping the modulated symbol sequence to one or more antennas associated with a transmitter to provide one or more layers having a symbol sequence; and precoding the layered symbol sequences.
|Translation Between A First Communication Protocol And A Second Communication Protocol - Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.
|INTERFACE DEVICE, DECODED DATA VALIDITY DETERMINATION METHOD AND RECORDING DEVICE - According to one embodiment, an interface device including a decoding module configured to decode received data, a storage module configured to store data obtained after the decoding module performs decoding, a CRC module configured to detect a CRC error included in the data obtained after the decoding module performs the decoding, an error detection module configured to detect a decoding error included in the data obtained after the decoding module performs the decoding, and a data processing module configured to process, as valid data, the data that is obtained after the decoding module performs the decoding and stored in the storage module when the decoding error detected by the error detection module is non-user data and the CRC module does not detect any CRC error.
|Configurable Parallel Computation of Cyclic Redundancy Check (CRC) Codes - An apparatus (
|FIRMWARE VERIFICATION USING SYSTEM MEMORY ERROR CHECK LOGIC - Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.
|STORAGE CONTROL DEVICE, AND CONTROL METHOD FOR STORAGE CONTROL DEVICE - The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device, and the size of physical blocks, which are provided within the storage device, are different from one another. A write object range generation unit reads out both of the extended logical blocks which are adjacent to the write data, and creates a write object range by linking them to the write data. An assurance code checking unit checks a corresponding assurance code for each of these extended logical blocks. And a block size adjustment unit deletes superfluous data from the adjacent blocks, and adjusts the size of the write object range, so that it becomes an integral multiple of the size of the physical blocks.
|Device, System and Method of Modification of PCI Express Packet Digest - Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.
|METHOD AND APPARATUS FOR PERFORMING A CRC CHECK - A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments and a plurality of first CRC check units, wherein each of the first CRC units is configured to perform a CRC check of a respective one of the plurality of segments of data, and wherein the plurality of CRC checks are performed concurrently.
|DATA TRANSFER METHOD CAPABLE OF SAVING MEMORY FOR STORING PACKET IN USB PROTOCOL AND APPARATUS THEREOF - A data transfer method is utilized for saving memory for storing packet in USB protocol. When a transmitter is to send a payload, the protocol layer of the transmitter writes the payload into a shared payload memory. The protocol layer generates a corresponding header according to the payload, and writes the corresponding header into a shared header memory. The data-link layer of the transmitter generates a packet by means of directly combining the payload saving in the shared payload memory and the header saving in the shared header memory, and sends the packet. Hence, when the transmitter is to send the payload, the transmitter only requires a memory of which the size is equal to a packet. In this way, the memory can be saved, reducing the cost.
|DATA INTEGRITY VALIDATION IN A COMPUTING ENVIRONMENT - A method for validating data in a data storage system comprising associating a first data chunk with first check data and storing the first data chunk and the first check data on a first storage device. Additional associated data chunks of the first data and associated additional check data are stored on at least one of the first storage device or one or more additional storage devices. At least a portion of the first check data and at least a portion of the additional check data are stored to a second storage device, which is distinct from the first storage device and the additional storage devices. I/O access to the second storage device is minimized by retaining at least a portion of the first check data and at least a portion of the additional check data in a readily accessible storage medium, during servicing of a first I/O request.
|SYSTEMS AND METHODS FOR ROUTING DATA IN A NETWORK DEVICE - A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.
|Apparatus and method for frame transmission - An apparatus for frame transmission includes a dummy data inserting unit that inserts dummy data, at timing of an interval in which a received frame input intermittently is not detected, in a sequence of processing processes of scrambling processing of user data cut out from the received frame, reading-out of the data after the scrambling processing with a parity appended thereto from a memory and parity checking thereof, and descrambling processing of the data after the parity checking, and an error determining unit that determines whether an error is occurring in the sequence of the processing processes, based on the dummy data obtained by the descrambling processing of the dummy data inserted in the sequence of the processing processes by the dummy data inserting unit.
|Error Detecting and Correcting Mechanism for a Register File - A data processing system includes a register file (
|TECHNIQUES FOR CYCLIC REDUNDANCY CHECK ENCODING IN COMMUNICATION SYSTEM - A method and apparatus for generating a Cyclic Redundancy Check (CRC) encoded message in a communication system are provided. The method includes generating the message, generating a first CRC for the message, generating a second CRC for the message, scrambling the first CRC by a first bit sequence of the message, and scrambling the second CRC by a second bit sequence of the message. The apparatus includes a message generator, a first CRC encoder, and a second CRC encoder. The message generator generates a message. The first CRC encoder generates a first CRC for the message, and scrambles the first CRC by a first bit sequence of the message. The second CRC encoder generates a second CRC for the message, and scrambles the second CRC by a second bit sequence of the message.
|INTELLIGENT ERROR CHECKING METHOD AND MECHANISM - An intelligent streaming media error check detection method and apparatus. The claimed invention discloses an apparatus and method where all streaming media are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The parameter W is not constant and conceptually represents a state of the error check method. The destructive value of a first predefined constant is added to the parameter W each time the acceptability of a data set cannot be verified. The constructive value of a second predefined constant is subtracted from the parameter W each time the acceptability of a data set is successfully verified. If the value of the parameter W equals or exceeds a predefined threshold, the remainder of the streaming media is decoded and played without error check protection.
|Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
|APPARATUS AND METHOD FOR FAULT TOLERANT FOTA UPDATE - An apparatus and method for fault tolerant Firmware-Over-The-Air (FOTA) update are provided. The method includes computing a checksum for each sector of a partially updated firmware, for each sector of the partially updated firmware, determining a last instruction in an update package that was applied to that sector, based on checksums included in the update package and the computed checksums of the sectors of the partially updated firmware, determining a last instruction of the update package that was applied to the partially updated firmware prior to the interruption based on the last instruction applied to each sector, and resuming the update procedure starting from an instruction immediately following the last applied instruction.
|APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING CONTROL INFORMATION IN MULTIPLE INPUT MULTIPLE OUTPUT SYSTEM - An apparatus and a method for transmitting and receiving control information in a Multiple Input Multiple Output (MIMO) system are provided. A method of a base station for transmitting control information to a terminal in the MIMO system includes transmitting first control information for every transmission mode except for a Multiple-User (MU)-MIMO mode, to the terminal over a control channel of a subframe, and transmitting second control information for the MU-MIMO mode to the terminal over a data channel of the subframe.
|CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK - A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
|Methods, Systems, and Computer Program Products for Class Verification - A method, system, and computer program product for class verification are provided. The method includes initiating loading of a class, and searching for the class in verification caches. A record from the verification caches, including a checksum, is returned upon locating the class. The method further includes comparing the checksum in the record to a checksum of the class being loaded, and completing the loading of the class when the checksums match. The method additionally includes performing bytecode verification of the class upon one of: a checksum comparison mismatch, and a failure to locate the class in the verification caches. The method also includes calculating a new checksum of the class upon a successful bytecode verification, and storing the new checksum in the verification caches.
|SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.
|METHODS AND ARRANGEMENTS FOR PARTIAL WORD STORES IN NETWORKING ADAPTERS - Typically, in designs for networking adapters, challenges are encountered where a partial word (e.g., 16 bit of IP checksum) has to be inserted into packets in buffers that are typically aligned to bus widths (e.g., 64 bit as in the case of 8× PCI Express interface). In fact, this is frequently required in hardware logic that implements a "checksum offload" feature. In many conventional designs, the hardware logic is required to insert the partial word into any given offset into the packet; this insert position in the buffers could be odd or even. Broadly contemplated herein, in accordance with at least one presently preferred embodiment of the present invention, is the implementation of a simple algorithm to store the 2 B IP checksum into any unaligned position within an 8 B word. This avoids the use of a logic-intensive implementation that employs 16 1:8 demultiplexers, or a latency-increasing approach of "read-modify-write".
|Circuit Arrangement and Method for Error Detection and Arrangement for Monitoring of a Digital Circuit - A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E
|Method and Device of Rewriting a Primary Sector of a Sector Erasable Semiconductor Memory Means - In a method of rewriting a primary sector of a sector erasable semiconductor memory device, a bootloader code is copied from the primary sector to a second sector, all content of the first sector is subsequently erased, and the bootloader code is recopied from the second to the primary sector. Subsequently, an application code is written to a remaining unused part of the primary sector.
|FAST AND RELIABLE WIRELESS COMMUNICATION - A communication system that provides fast and reliable communications. The system is suitable for use in connection with wireless computing devices in which transmission errors may occur because of channel conditions, such as interference. Channel conditions causing transmission errors may be bursty and transient such that the errors temporarily overwhelm an error control code. By combining data received for multiple transmission attempts of a packet that fail error checking or that pass error checking with low reliability, a reliable representation of the packet may be quickly constructed. Though, combining may be omitted when a transmission attempt is received that passes error checking with high reliability.
|METHOD AND SYSTEM FOR UPDATING TOPOLOGY CHANGES OF A COMPUTER NETWORK - A method for detecting topology changes of a computer network, includes the following steps of acquisition of the raw data from the configuration tables of the network elements during successive primary pollings, the following steps being carried out between two successive primary pollings: calculation and storage of a checksum value for each network element having raw data which are considered to be sensitive, at least one secondary polling, allowing the sensitive data to be retrieved again from each corresponding element, comparison of the previously-stored checksum value, at each secondary polling and for each element termed sensitive, with a new checksum value calculated with the new sensitive data, for each sensitive element, when the two checksum values differ, updating in a topology database only the topology data relative to the corresponding element.
|Two Dimensional Data Randomization for a Memory - In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address.
|Method and Computer Unit for Error Detection and Logging in a Memory - In a method for detecting errors in computer data in a memory, a check sum is calculated in runtime and compared to a stored check sum. In this method, the computer data is being subdivided into at least two logical blocks and a check sum is calculated for each logical block. Also provided is a computer unit having a processor and a memory which has a ROM in which firmware is stored, and/or which has a RAM, the memory having at least two logging functions for logging established memory errors, e.g., errors in the ROM and/or the RAM.
|MULTI-LAYER CYCLIC REDUNDANCY CHECK CODE IN WIRELESS COMMUNICATION SYSTEM - A communication device is disclosed. The device is configured to generate a first block of first cyclic redundancy check (CRC) parity bits on a transport block wherein the first block of CRC parity bits is based on a first generator polynomial, to attach the first block of CRC parity bits to the transport block and to segment the transport block into multiple code blocks. The processor is also configured to generate a second block of CRC parity bits on each code block wherein each of the second blocks of CRC parity bits is based on a second generator polynomial that is different than the first generator polynomial. The first and second generator polynomials have a common degree. A second block of CRC parity bits is attached to each code block, and the code blocks are concatenated after channel encoding.
|END-TO-END CYCLIC REDUNDANCY CHECK PROTECTION FOR HIGH INTEGRITY FIBER TRANSFERS - A method, transceiver, and computer program storage product transfer data over fiber between a first transceiver and a second transceiver. The second transceiver is determined to support a high integrity cyclic redundancy check associated with substantially an entire data set in a Fibre Channel Protocol exchange between the first transceiver and the second transceiver. A last data frame in a plurality of data frames is formatted for communication to the second transceiver during the Fibre Channel Protocol exchange. The last data frame includes a plurality of data and at least one cyclic redundancy check field associated with the plurality data and at least one additional cyclic redundancy check field associated with the plurality of data frames.
|Performing A Cyclic Redundancy Checksum Operation Responsive To A User-Level Instruction - In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
|Semiconductor device and method for operating the same - Semiconductor device includes a pad for outputting a cyclic redundancy check (CRC) data for error detection and a signal outputting unit for outputting the CRC data or a data strobe signal, which is output together with data of being output in response to a read command, through the pad according to operation modes. Method for operating a semiconductor device provided a step of outputting a CRC data for error detection through a CRC data pad and a step of outputting a data strobe signal, which is output together with data output in response to a read command, through the CRC data pad according to an operation mode.
|Digital File Marked By a Series of Marks the Concatenation of Which Forms a Message and Method for Extracting a Mark from Such a Digital File - The marked digital file (
|Data Protection Method for Variable Length Records by Utilizing High Performance Block Storage Metadata - An enhanced mechanism for providing data protection for variable length records utilizes high performance block storage metadata. In an embodiment, an emulated record that emulates a variable length record, such as a Count-Key-Data (CKD) record or an Extended-Count-Key-Data (ECKD) record, is generated by a Host Bus Adapter (HBA) of a mainframe system. The emulated record comprises a sequence of extended fixed-length blocks, each of which includes a data block and a footer. A confluence of the footers defines a high performance block storage metadata unit associated with the emulated record and includes a checksum that covers all data blocks and all footers of the entire emulated record. In one embodiment, the checksum is checked during transit of the emulated record between a HBA and a storage subsystem (e.g., by the HBA when the emulated record is received from the storage subsystem, and/or by a switch in the data transfer path), during a hardening step when writing the emulated record to a disk, and/or during a verification step when reading the emulated record from the disk.
|PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS - A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.
|Method of detecting data transmission errors in a CAN controller, and a CAN controller for carrying out the method - A method of detecting data transmission errors in a CAN controller includes generating at least one check bit that is verifiable for ensuring the consistency of the transmitted data. A CAN controller that ensures continuous error monitoring during data transmission includes an interface unit for exchanging data with a CAN bus, a memory unit for storing received data and data to be transmitted, and an electronic unit for controlling data transmission between the memory unit and the interface unit. The interface unit of the CAN controller has an arrangement for generating check bits for received data and for verifying check bits for data to be transmitted.
|Broadcast Equipment Communication Protocol - A method for transmitting data between components of a digital broadcasting system includes: receiving payload data, adding a content layer header to the payload data to form a content layer data frame, adding a transmission and authentication layer header and a cyclic redundancy check field to the content layer data frame to form a transmission and authentication layer data frame, adding an application framing layer header to the transmission and authentication layer data frame to form an application framing layer data frame, and transmitting the application framing layer data frame to a destination component.
|SIGNAL PROCESSING METHOD IN MIMO SYSTEM AND APPARATUS THEREOF - Disclosed is a signal processing method and apparatus in MIMO system. In a mobile communication system having a plurality of transmitting antennas, the present invention includes the steps of receiving a feedback signal including status information of at least one channel, segmenting one of the first data blocks to segment into at least one or more of the second data blocks, attaching a CRC to each of the at least one or more of the second data blocks, allocating the at least one or more second data blocks to a plurality of the transmitting antennas, respectively, and transmitting the at least one or more of the second data blocks. In a mobile communication system having a plurality of receiving antennas, the present invention includes the steps of receiving at least one data block including a CRC or dummy bits, acquiring channel status information using the CRC or dummy bits, and transmitting the channel status information.
|Method and apparatus for error detection in a communication system - A method processes a data packet in a first sequence of disjoint original segments of the same length. The method includes modifying a first of the original segments of the first sequence by modifying one or more symbols therein. A start of the data packet is located in the first of the original segments and is positioned after a first digital data symbol therein. The method also includes modifying a last of the original segments of the first sequence by modifying one or more digital data symbols therein. An end of the data packet is located in the last of the original segments and is located before the last digital data symbol therein. The method also includes determining a remainder sequence by effectively performing a polynomial division on a second sequence of disjoint segments that are derived from the first sequence. Each segment of the second sequence corresponds to and is derived from one of the original segments of the first sequence. The segments of the second sequence have the length of the original segments of the first sequence. A first of the derived segments of the second sequence is the modified first of the original segments. A last of the derived segments of the second sequence is derived from the modified last of the original segments.
|EXTRACTION OF VALUES FROM PARTIALLY-CORRUPTED DATA PACKETS - In one embodiment, a method for processing data packets having a payload and a checksum, wherein the payload has a first portion of interest. If a received data packet fails a CRC check, then it is determined whether the first portion has a valid relationship with one or more previous first portions of one or more corresponding previous payloads of one or more corresponding previous data packets. If the relationship is valid, then the first portion is output. The method enables recovery of first portions of interest from corrupted data packets having transmission errors in other parts of the data packets, thereby potentially decreasing retransmissions and increasing throughput.
|CONTROL CHANNEL DETECTION FOR MULTIPLE IMPLICIT IDENTIFIERS - A method for identifying matched mobile stations includes receiving by a first mobile station signals from a plurality of mobile stations located within a threshold distance of the first mobile station, identifying a first group of mobile stations of the plurality of mobile stations, and receiving uni-cast control information from a network entity. For each mobile station of a first group, the method includes identifying a matched mobile station based upon first data of a mobile station of the first group effectively matching second data of a mobile station of a second group. One operation includes generating a descrambled information element for each matched mobile station of the first group by using the first scrambling sequence that is associated with the matched mobile station to descramble the scrambled information element of the mobile terminal of the second group that is matched to the mobile terminal of the first group.
|Method for the Operation of a Microcontroller and an Execution Unit and Microcontroller and an Execution Unit - A microcontroller which can be coupled to an execution unit. For the operation of the microcontroller, a program in the microcontroller generates a message as a function of input data and transmits said message to the execution unit. For the operation of the microcontroller, accompanying the message, a check code is generated as a function of the execution of the program and is transmitted to the execution unit. For the operation of the execution unit, a test determines whether the check code is logically predefined and/or received within a predetermined time interval, wherein in the case of a positive test result, the message is designated as valid, and in the case of a negative result, the message is designated as invalid.
|MULTI-LAYER CYCLIC REDUNDANCY CHECK CODE IN WIRELESS COMMUNICATION SYSTEM - A wireless communication device includes a transmitter configured to transmit a transport block with a sequence of bits wherein A is the number of bits, a first CRC coder configured to generate a first block of CRC parity bits on a transport block and to associates the first block of CRC parity bits with the transport block, wherein a number of CRC parity bits in the first block is L, a segmenting entity configured to segment the transport block into multiple code blocks after associating when A+L is larger than 6144, a second CRC coder configured to generate a second block of CRC parity bits on each code block and to associate a second block of CRC parity bits with each code block, and a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits if A+L>6144.
|Enhanced Error Detection in Multilink Serdes Channels - A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.
|INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - An information processing device, comprising: a first encoder configured to encode data having an error detecting code in a first encoding format to generate first data; a second encoder configured to encode the first data in a second encoding format corresponding to decoding of the first encoding format to generate second data; and an error detector configured to perform error detection on the second data based on the error detecting code added to the data.
|UPDATING SEQUENTIAL DATA - Disclosed is a storage apparatus comprising a data store; a data input; and a data processor arranged to: receive from the data input a block of data to be stored at an append point after sequential data comprising one or more stored blocks of data; retrieve an integrity measure, of one or more stored integrity measures that are associated with one or more respective points in the sequential data, said retrieved integrity measure being associated with a point at or preceding the append point; calculate a new integrity measure using the received block of data and the retrieved integrity measure; and store the received block of data and the new integrity measure in the data store, in addition to at least one stored integrity measure that is associated with a point in the data at or preceding the append point.
|ITERATIVE DECODING OF BLOCKS WITH CYCLIC REDUNDANCY CHECKS - The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a predetermined number of consecutive iterations. In another example embodiment, a decoding iteration is performed on a particular sub-block of multiple sub-blocks of a transport block, which includes a single CRC over an entirety of the transport block. The CRC is checked using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from previous decoding iterations on other sub-blocks of the multiple sub-blocks. The decoding iteration is then performed on a different sub-block if the CRC does not check. Also, the decoding iterations for the sub-blocks may be terminated if the CRC checks.
|Methods and apparatus to generate multiple CRCs - Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a selected cyclic redundancy check generator polynomial, at least one cyclic redundancy check is calculated based upon a first subset of the plurality of bits with a certain bit ordering, and at least another cyclic redundancy check is calculated based upon a second subset of the plurality of bits with a different bit ordering. The second subset of bits may overlap with the first subset of bits. In another aspect, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a plurality of different cyclic redundancy check generator polynomials. A first cyclic redundancy check generator polynomial is used for calculating a first cyclic redundancy check based upon a first plurality of bits, and a second cyclic redundancy check generator polynomial is used for calculating a second cyclic redundancy check based upon a second plurality of bits.
|TRANSMISSION SYSTEM - A frame format used to send a command in which high-reliability transmission is demanded includes an SFD area, an inverted header area, a normal data area, a normal check area, an inverted header area, an inverted data area, and an inverted check area. Command data and data obtained by inverting the command data are stored in the normal and inverted data areas, respectively. Similarly, pieces of response data (normal/inverted) are stored in each data area. Check codes used to check the header area and the data area is stored in the normal and inverted check areas, respectively. A receiving device performs a check by the normal and inverted check codes, compares the normal header area with the inverted header area, and compares the normal data area with the inverted data area. The receiving device normally performs reception when all the comparison results are correct.
|METHOD AND APPARATUS FOR MITIGATING MEMORY REQUIREMENTS OF ERASURE DECODING PROCESSING - A system and method corrects erroneous sections received in a memory by pre-filling at least a portion of memory with a pre-defined value. If a received data packet is valid, the valid received data packet is stored over the pre-defined values in the memory location associated with the valid data packet. Values associated with a data segment and an adjacent data segment in the memory are compared to the pre-defined value. When the values of each data segment match the pre-defined values, then each data segment is an erroneous data segment.
|Storage sub-system and method for controlling the same - The present invention provides means for effectively reducing the amount of data by means of de-duplication in a disk array apparatus having a data guarantee code.
|TURBO DECODER WITH STAKE HERITAGE FOR DATA BLOCK REDUNDANT VERSION DECODING - An iterative decoding device (ITD) for a communication receiver comprises: i) a means (SISO
|Wireless communications method - A Wireless communications protocol/method comprises: a. Sensors data size and structure are constant, and consist of several fields; b. The sensors message include one or more of the following: 1) a 8 to 16 bits long preamble of a start sequence, for example a binary 1010 . . . binary sequence 2) a sync sequence of for example 8 bits of a 11001100 sequence 3) a sensor's unique ID number of for example 8 to 16 bits 4) several bits of sensor's internal clock counter 5) several bits indicating the message type 6) data, for example 16 bits of data, and/or 7) CRC (for Cyclic Redundancy Check purposes), for example 8 to 16 bits. A method for detecting leakage from a pipe uses multiple channels/inputs, wherein a low frequency range input measures seismic noises, and a high frequency range input measures cavitation noises.
|METHOD AND APPARATUS FOR CALCULATING FRAME CHECK SEQUENCE - One embodiment provides a system for calculating a checksum for a packet. During operation, the system receives a packet, pads the received packet with a number of bits having predetermined values, and calculates an initial checksum value for the padded packet. Subsequently, the system calculates a final checksum for the original packet by reversing the initial checksum value using the padded bits with predetermined values
|METHOD AND APPARATUS FOR PROVIDING ADAPTIVE CYCLIC REDUNDANCY CHECK COMPUTATION - A method and apparatus for providing adaptive cyclic redundancy check (CRC) computation is disclosed. A transport block size is determined. Transport block (TB) CRC bits are computed with a first CRC generator when the TB size is less than or equal to a predetermined threshold. TB CRC bits are computed with a second CRC generator when the transport block size is greater than the predetermined threshold. When the TB is greater than the predetermined threshold, the TB is segmented into code blocks (CBs) and CB CRC bits are computed with the first CRC generator. A method and apparatus for handling adaptively cyclic redundancy check (CRC) encoded transport blocks (TBs) is also disclosed. A TB is received. The TB is CRC checked based on a first CRC generator when the TB size is less than or equal to a predetermined threshold. Code blocks of the TB are CRC checked based on the first CRC generator when the TB size is greater than the predetermined threshold. When the TB size is greater than the predetermined threshold, the code blocks are concatenated, and the TB is CRC checked based on a second CRC generator.
|Configuration device for configuring FPGA - An FPGA configuration device comprises: a read operation control unit which performs control to read configuration data from a configured FPGA; and a configuration data transfer unit which transfers the configuration data read out of the FPGA to a memory.
|SYSTEMS AND METHODS FOR DATA ALIGNMENT - A data alignment system suitable for use in manipulating the positioning of a designated portion of a data stream transmitted by a high speed communications system, so as to facilitate further processing of the data carried by the data stream. The data alignment system includes a detector and an alignment component in communication with each other. In operation, the detector locates and identifies, in accordance with suitable instructions, the designated portion of the data stream. The alignment component then repositions, in accordance with suitable instructions, the designated portion of the data stream at a predetermined location within the data stream.
|METHOD FOR TRANSMITTING SAMPLED DATA AND CONTROL INFORMATION BETWEEN A DSP AND AN RF/ANALOG FRONT-END - A method for delivering control information together with sampled data between a DSP and an RF/analog front-end in a high speed communication modem, which embeds sampled data and control information in frames to be transferred over one interface. A frame may comprise various fields, each may consist of one or more bytes or octets. The frame may have a data field for carrying the sampled data, and at least one control field for transferring the control information to update RF/analog front-end registers. The control field may include an octet containing a control address, an octet containing a control command, and an octet containing control data. The frame may also provide means of synchronization, e.g., by using a sync field to identify the frame boundary.
|BUFFER TRANSFER CHECK ON VARIABLE LENGTH DATA - The disclosure is related to systems and methods for checking the integrity of a data transfer to or from a buffer or other data storage medium. Check values can be added to a data object in a data object based file system. From the check values, a device receiving the data object may determine an integrity or validity of the received data object based on the check values. In a particular embodiment, a hash value may be determined based on the check values. The hash value may be stored in the metadata of the transferred data object. The receiving device may re-calculate the hash value from the check values and compare it to the stored hash value to determine an integrity of the received data object.
|TECHNIQUES FOR SEGMENTED CRC DESIGN IN HIGH SPEED NETWORKS - Embodiments of the present invention provide techniques for efficient generation of CRC values in a network environment. Specific embodiments of the present invention enable CRC processing circuits that can generate CRC values at high data throughput rates (e.g., 100 Gbps or greater), while being capable of being implemented on currently available FPGAs. Accordingly, embodiments of the present invention may be used in network devices such as routers, switches, hubs, host network interfaces and the like to support high speed data transmission standards such as 100G Ethernet and beyond.
|MULTI-LAYER CYCLIC REDUCNDANCY CHECK CODE IN WIRELESS COMMUNICATION SYSTEM - A wireless communication device includes a receiver configured to receive a transport block with a sequence of bits wherein A is the number of bits, a first cyclic redundancy check (CRC) coder configured to generate a first block of CRC parity bits on a transport block and to associates the first block of CRC parity bits with the transport block, wherein a number of CRC parity bits in the first block is L, a segmenting entity configured to segment the transport block into multiple code blocks after associating when A+L is larger than 6144, a second CRC coder configured to generate a second block of CRC parity bits on each code block and to associate a second block of CRC parity bits with each code block, and a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits if A+L>6144.
|PHASE SHIFT ADJUSTING METHOD AND CIRCUIT - Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
|CHECK CODE GENERATING APPARATUS, METHOD OF GENERATING CHECK CODE, AND COMMUNICATION APPARATUS - A check code generating apparatus generates a first check code that is a check code concerning exclusive OR of first data and second data obtained by rewriting a part of the first data and calculates exclusive OR of the first check code and a second check code that is a check code attached to the first data.
|SYSTEMS, METHODS, AND APPARATUSES TO TRANSFER DATA AND DATA MASK BITS IN A COMMON FRAME WITH A SHARED ERROR BIT CODE - Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame.
|HIGH EFFICIENCY, HIGH PERFORMANCE SYSTEM FOR WRITING DATA FROM APPLICATIONS TO A SAFE FILE SYSTEM - Systems and methods for increasing the efficiency of data storage processes for high performance, high core number computing systems. In one embodiment, the systems of the present invention perform sequential I/O whenever possible. To achieve a high degree of sequentiality, the block allocation scheme is determined by the next available block on the next available disk. This simple, non-deterministic data placement method is extremely effective for providing sequential data streams to the spindle by minimizing costly seeks. The sequentiality of the allocation scheme is not affected by the number of clients, the degree of randomization within the incoming data streams, the logical byte addresses of incoming request's file extents, or the RAID attributes (i.e., parity position) of the block.
|SYSTEM AND METHOD FOR IDENTIFYING UPPER LAYER PROTOCOL MESSAGE BOUNDARIES - Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries is provided. The method may include one or more of the following steps: attaching a framing header of a frame to a data payload to form a packet, the framing header being placed immediately after the byte stream transport protocol header, the framing header comprising a length field comprising a length of a framing protocol data unit (PDU); and inserting a marker in the packet, the marker pointing backwards to the framing header and being inserted at a preset interval.
|DISPLAY CONTROL APPARATUS - To enable an instrument panel to appropriately check whether or not data display is normal.
|APPARATUS AND METHOD FOR STORING DATA USING NON-VOLATILE BUFFER - An apparatus and method for storing data using a non-volatile buffer. A first data is stored in a first non-volatile buffer according to a first input/output request. The first data stored in the first non-volatile buffer is written into a memory cell while a second data is being stored in a second non-volatile buffer according to a second input/output request.
|Concatenated decoder and concatenated decoding method - A concatenated decoder and concatenated decoding method are provided. The concatenated decoder, including: an inner decoder to receive an input bit stream, inner-decode the received input bit stream, and generate a first bit stream; and an outer decoder to generate error information about the received first bit stream, according to the generated error information, transmit an iterative decoding continuation request to the inner decoder or outer-decode the first bit stream to generate a second bit stream.
|CALCULATION PROCESSING DEVICE FOR PERFORMING HIGH-SPEED CALCULATION - In a calculation processing device for calculating inputted data to output the result of the calculation, a number-of-calculation generator generates the numbers of parallel and serial calculations based on the data length of the received data. When a calculation enable generator applies a parallel enabling signal or a serial enabling signal to an input controller in order to control the numbers of these calculations, the received data is inputted to a calculation processor in parallel during an input period of the parallel enabling signal, and is inputted to the calculation processor in serial during an input period of the serial enabling signal. The calculation processor performs parallel and serial processes for the inputted data to output the results of the processes on an output.
|DATA PARALLELIZING RECEIVER - Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.
|SYSTEM AND METHOD FOR MULTICAST ERROR RECOVERY USING SAMPLED FEEDBACK - A method is provided in one example and includes receiving a data stream that includes an error code probability; detecting an error in the data stream; and determining whether to generate an error signal for the error in the data stream based on the error code probability being compared to a threshold value. In more particular embodiments, the error code probability may be based on a total number of network elements that receive the data stream. In addition, more specific methodologies may include generating a number to be used as a basis for the threshold value; and generating the error signal if the error code probability is below the threshold value.
|Method for Verifying Correct Encryption Key Utilization - A method for sending encrypted data in response to a request for an I/O operation. The method includes the steps of requesting a data encryption key, the request including one or more identifiers unique to the I/O operation; receiving a data encryption key attached with a first key use fingerprint, independently generating a second key use fingerprint in response to the one or more identifiers; comparing the first and the second key use fingerprints; and if the first key use fingerprint matches the second key use fingerprint, using the data encryption key to encrypt the data to be sent. In one embodiment, the one or more identifiers include at least one of a target identifier, a LUN identifier, and a LBA range identifier.
|Multi-User Packing Techniques for Wireless Network - Various example embodiments are disclosed herein. According to an example embodiment, a method may include transmitting a Media Access Control Protocol Data Unit (MAC PDU) via a wireless link to one or more mobile stations, the MAC PDU including a plurality of MAC management messages as a pay load, at least some of the MAC management messages directed to different mobile stations, the KIAC PDU including a MAC header having a connection ID field identifying a connection for all (or at least one, or a plurality) of the MAC management messages included in the MAC PDU.
|METHODS AND APPARATUS TO IMPROVE PERFORMANCE AND ENABLE FAST DECODING OF TRANSMISSIONS WITH MULTIPLE CODE BLOCKS - A method includes separating resource elements from multiple code blocks into different groups, and decoding the code bits of the resource elements within each group without waiting for a completed reception of a transport block to start decoding.
|CHECKING METHOD AND ELETRONIC CIRCUIT FOR THE SECURE SERIAL TRANSMISSION OF DATA - A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.
|METHOD, APPARATUS, AND USER EQUIPMENT FOR CHECKING FALSE ALARM - In the field of mobile telecommunications, a method for checking a false alarm is provided. In the method, after a user in a Long Term Evolution (LTE) system receives control signaling for scheduling physical resources, Cyclic Redundancy Check (CRC) is performed on the control signaling; and if the CRC is passed, false alarm check is performed on the control signaling according to false alarm check bit(s) and padding bit(s) in the control signaling. An apparatus and a user equipment (UE) for checking a false alarm are also provided. According to the method, the apparatus, and the UE for checking a false alarm, the number of bits participating in the false alarm check is increased, thereby reducing the probability of false alarm occurrence, and improving receiving performance of the control signaling.
|ERROR CHECKING WITH DATA PRESENCE DETECTION - The present invention relates to an apparatus and a method for detecting presence of data, wherein input data is decoded using a decoder metric to obtain decoded data, and an error check is performed for the decoded data. Furthermore, a threshold value is determined based on an obtained maximum value that the de coder metric can assume for the input data, and the threshold value is compared with an actual value of the decoder metric. Presence of the input data is then decided based on results of the error check and the comparison.
|APPARATUS AND METHOD FOR PROTECTING RFID DATA - An apparatus and method for protecting radio frequency identification (RFID) data in a communication between a RFID tag and a RFID reader are provided. In the apparatus and method for protecting RFID data, message header information transmitted while communicating the RFID tag and the RFID reader is used to perform an encryption operation for important data, thereby protecting the important data included in the RFID tag. In the present invention, information of the RFID tag can be protected from an illegitimate eavesdropper and an ill-intentioned and unusual message can be detected, thereby ensuring the security of a RFID system.
|METHOD OF CERTIFYING MULTIPLE VERSIONS OF AN APPLICATION - A first check code is computed by applying an algorithm to a proper subset of a first body of data. A second check code is computed by applying the algorithm to an equivalent proper subset of a second equivalent body of data. The two check codes are compared. The extent of the proper subset of the first body of data is determined by a semantic analysis of the first body of data. Multiple versions of an application, when the semantic changes between the applications are inconsequential, may then be certified by ignoring the non-significant modifications and ensuring the integrity of the remainder of the content.
|False Detection Reduction in Communication Systems - A decoding-reliability metric from a received-signal decoder is compared with a threshold to decrease significantly the probability of false detection in a receiver and thus increase communication reliability and performance. In a wideband code division multiple access communication system, for example, significant decrease of the probability of false grant-message detection and significant increases of enhanced uplink performance and reliability can be obtained.
|DETECTION OF POTENTIAL NEED TO USE A LARGER DATA FORMAT IN PERFORMING FLOATING POINT OPERATIONS - Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
|METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING CONTROL INFORMATION IN A WIRELESS COMMUNICATION SYSTEM - A method and apparatus for transmitting and receiving control information in a wireless communication system are disclosed. The control information transmission method includes masking a Cyclic Redundancy Check (CRC) by a CRC mask including a bit stream of a predetermined length and an indicator indicating the bit stream, and transmitting control information including the masked CRC to at least one Mobile Station (MS). The indicator indicates whether the bit stream included in the CRC mask includes a Random Access IDentifier (RAID).
|APPARATUS FOR BLIND CHECKSUM AND CORRECTION FOR NETWORK TRANSMISSIONS - Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
|Mechanism for Interleaved Parallel Cyclic Redundancy Check Calculation for Memory Devices - In one embodiment, a mechanism for interleaved parallel cyclic redundancy check calculation for memory devices is disclosed. In one embodiment, a method includes generating an index value as part of a cyclic redundancy check (CRC) operation, the index value being a result of a first exclusive-or operation applied to both of input data directly as-is from a data bus and to data in a 64-bit accumulator utilized to store results of the CRC operation. The method also includes indexing an interleaved parallel CRC table with the index value to retrieve a 64-bit polynomial entry from the CRC table, performing a second exclusive-or operation on the retrieved polynomial entry and data in the 64-bit accumulator, storing the results of the second exclusive-or operation in the 64-bit accumulator, and transmitting contents of the 64-bit accumulator directly as-is to the data bus.
|INFORMATION PROCESSING TERMINAL, DATA SELECTION PROCESSING METHOD, AND PROGRAM - There is provided an information processing terminal that has a plurality of data communication portions that receive data from a read/write unit by a non-contact method. The information processing terminal includes a data processing portion that selects and processes one of the data received by a first data communication portion that is one of the plurality of data communication portions and the data received by a second data communication portion that is one of the plurality of data communication portions. The information processing terminal also includes a load modulation portion that performs a load modulation with respect to a response to the read/write unit according to the data processing in the data processing portion.
|EFFICIENT IN-BAND RELIABILITY WITH SEPARATE CYCLIC REDUNDANCY CODE FRAMES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for efficient in-band reliability with separate cyclic redundancy code (CRC) frames. In some embodiments, a memory system uses data frames to transfer data between a host and a memory device. The system also uses a separate frame (e.g., a CRC frame) to transfer a CRC checksum that covers the data frames.
|SYSTEM AND METHOD FOR DETECTING AND IGNORING AN INVALID CHANNEL MAP FEATURE - There is provided a system and method for detecting an ignoring an invalid channel map feature. More specifically, in one embodiment, there is provided a method, comprising receiving an initial channel map feature, determining a cyclic redundancy check value for the initial channel map feature, receiving a subsequent channel map feature, determining a cyclic redundancy check value for the subsequent channel map feature, and processing the initial or the subsequent channel map feature if the cyclic redundancy check values for each of the initial and subsequent cyclic redundancy check values match.
|METHOD AND SYSTEM FOR CALCULATING AND VERIFYING THE INTEGRITY OF DATA IN A DATA TRANSMISSION SYSTEM - A method is described of calculating and verifying the integrity of data in a data communication system. The system comprises a base station and one or more remote stations, such as in an RFID system. The method includes transmitting a select instruction from the base station to the one or more remote stations, the select instruction containing a data field which matches a portion of an identity or other data field in one or more of the remote stations; transmitting from a selected remote station or stations a truncated reply containing identity data or other data of the remote station but omitting the portion transmitted by the base station; calculating in the base station a check sum or CRC from the data field originally sent and the truncated reply data received and comparing the calculated check sum or CRC with the check sum or CRC sent by the remote station.
|SYSTEM, METHOD AND APPARATUS FOR EARLY TERMINATION BASED ON TRANSPORT BLOCK FAIL FOR ACKNOWLEDGMENT BUNDLING IN TIME DIVISION DUPLEX - Methods, apparatus and articles of manufacture are disclosed that provide for early termination based on transport block fail for acknowledgement bundling in time division duplex. In one embodiment, a method for operating a communication device is provided. In this embodiment, the communication device decodes a downlink subframe that is part of a bundle of subframes. If it detects a CRC failure in the subframe, it inhibits decoding of at least one other subframe in the bundle if present and reports the failure to the sending node. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the disclosed subject matter. Therefore, it is to be understood that it should not be used to interpret or limit the scope or the meaning of the claims.
|METHOD FOR DETECTING CONTROL INFORMATION IN WIRELESS COMMUNICATION SYSTEM - A method for detecting control information in a wireless communication system is provided. The method includes checking a cyclic redundancy check (CRC) error by monitoring control channels, determining whether a value of an error check field is equal to a specific value, and, if the value of the error check field is equal to the specific value, detecting the control information on the control channel.
|PROCESSING OF BLOCK AND TRANSACTION SIGNATURES - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
|COMMUNICATION ERROR MONITORING SYSTEM OF POWER DEVICE BASED ON ETHERNET AND METHOD THEREOF - Disclosed is communication error monitoring system and method thereof. In the present disclosure, a master lower-level device, at least one or more slave lower-level devices, and an upper-level monitoring unit are inter-connected via Ethernet, wherein the upper-level monitoring unit receives information of lower-level devices determined as with communication error from the master lower-level device to request and collect necessary data with the slave lower-level devices except for the lower-level devices with the communication error through Ethernet. And thus, a communication delay unnecessary of an entire power system is eliminated and a real time response and stability of a system is enhanced.
|LOW COMPLEXITY DECODING OF LOW DENSITY PARITY CHECK CODES - An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a "best guess" as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.
|AVIONIC DATA VALIDATION SYSTEM - An example method of verifying avionic data includes establishing a first cyclical redundancy check value associated with a data file. The first cyclical redundancy value is established on an aircraft. The method transmits the data file from the aircraft to a ground system. The method receives a second cyclical redundancy check value associated with the data file. The second cyclical redundancy check value is established by the ground system. The method determines the transmitted data file integrity by comparing the first cyclical redundancy check value to the second cyclical redundancy check value. An example aircraft avionic data verification arrangement includes a collector device that assembles avionic data into a data file that is transmittable to a ground system. A controller is programmed to provide a first cyclical redundancy check value associated with the data file and to identify errors in the data file received by the ground system based on a comparison between the first cyclical redundancy check value and a second cyclical redundancy check value established by the ground system.
|Communication Method and Echo - Communication method in a communication system comprising a first communication unit (A) and a second communication unit (B) which are connected to one another via at least one first communication path, wherein the first communication unit (a) transmits at least one first message or a first command to the second communication unit (B), which message or command comprises at least one item of address information (ADDR) according to which the second communication unit (B) transmits a first response message to the first communication unit in response to the first message or the first command, wherein this first response message comprises at least one item of data information (DAT) and additionally the address information relating to the first command itself (ADDR) or an item of information (CRC) derived from this address information.
|WIRELESS APPARATUS AND METHOD FOR DE-MASKING A PACKET - A wireless apparatus and a method thereof are provided. The wireless apparatus comprises a receiving unit and a processing unit. The receiving unit is configured for receiving a packet which comprises a data portion and a cyclic redundancy check portion from the base station. The processing unit connected to the receiving unit which is configured for generating a de-masked packet by de-masking the cyclic redundancy check portion and at least one selected bit of the data portion by a plurality of predetermined bits, determining that the de-masked packet pass a cyclic redundancy check, and accepting the packet after the determination.
|ALARM REPORT METHOD, SYSTEM AND DEVICE FOR CASCADED EQUIPMENT - The disclosure discloses an alarm report method for cascaded equipments, comprises: after receiving link alarm information, a radio equipment determines the source of the link alarm information; the radio equipment selects one link alarm information report mode from multiple predetermined link alarm information report modes according to the result of determining the source; the radio equipment reports the link alarm information to a Radio Equipment Controller (REC) according to the selected link alarm information report mode. The disclosure further discloses an alarm report system and device for cascaded equipments. The disclosure can effectively lower the alarm information processing complexity of an REC and the correlation of alarms.
|SYSTEM, METHOD, AND APPARATUS FOR A SCALABLE PROCESSOR ARCHITECTURE FOR A VARIETY OF STRING PROCESSING APPLICATIONS - Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.
|ERROR DETECTION CODE GENERATING METHOD AND ERROR DETECTION CODE GENERATOR - In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver.
|METHOD AND APPARATUS FOR COMPRESSION AND NETWORK TRANSPORT OF DATA IN SUPPORT OF CONTINUOUS AVAILABILITY OF APPLICATIONS - Methods and apparatus for compressing data for network transport in support of continuous availability of applications are described. One computer-implemented method of compressing data includes receiving a current instance of data in an input buffer. A candidate chunk of data is selected from the input buffer. A signature hash is computed from a signature length range of data within the candidate chunk. A matching dictionary entry having a matching signature hash from a multi-tiered dictionary is identified. The matching dictionary entry prospectively identifies a location of a prior occurrence of a selected range of consecutive symbols including the signature length range of data within at least one of the current instance of data and a prior instance of data in the input buffer. A dedupe processed representation of the instance of data is formed wherein a dedupe item is substituted for the selected range of consecutive symbols if the selected range is verified as recurring. The dedupe item identifies the location of the prior occurrence of the selected range in accordance with the matching dictionary entry.
|CYCLIC REDUNDANCY CHECK CIRCUIT AND COMMUNICATION SYSTEM HAVING THE SAME FOR MULTI-CHANNEL COMMUNICATION - A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, creating a generation expression with respect to points in time that are sequentially delayed as much as the number of multi-channels from the first point in time by applying each point in time to the generation expression, and embodying a circuit corresponding to the generation expression with respect to the most delayed point in time among the created generation expressions. The CRC circuit corresponding to the generation expression will have more modulo-2 adders (e.g., XOR gates) than the number of non-zero coefficients in the selected CRC polynomial.
|METHOD OF GENERATING AND PROCESSING RANGING RESPONSE MESSAGE IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to ranging response message generating and processing methods that can reduce overhead in a wireless portable Internet system. A method of generating a ranging response message according to an exemplary embodiment of the present invention includes: adding to the ranging response message a first field indicating the number of responses for CDMA codes included in the ranging response message and received from terminals; adding to the ranging response message second fields indicating ranging code attributes as the responses for the CDMA codes by a value of the first field; and adding to the ranging response message a plurality of third fields indicating transmission parameter adjustment values corresponding to the individual second fields.
|METHOD AND DEVICE FOR DETECTING POSSIBLE CORRUPTION OF SECTOR PROTECTION INFORMATION OF A NON-VOLATILE MEMORY STORED IN AN ON BOARD VOLATILE MEMORY ARRAY AT POWER-ON - A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.
|METHOD FOR DETERMINING TRANSPORT BLOCK SIZE AND SIGNAL TRANSMISSION METHOD USING THE SAME - A device and method for attaching a CRC code to a transport block and turbo encoding the CRC attached transport block, where the transport block has a predetermined size.
|METHOD OF CONDUCTING SAFETY-CRITICAL COMMUNICATIONS - An exemplary method of communicating with a safety device includes obtaining a key from the safety device that is useable for only a single communication session with the safety device. A plurality of messages are sent to the safety device during the single communication session. Each of the plurality of messages includes the obtained key, an identifier of the source of the message, an identifier of the safety device, a sequence number indicating how many of the plurality of messages preceded the message during the communication session, a command for the safety device, and at least one cyclic redundancy code (CRC) based on content of the message. A next one of the plurality of messages is sent only after confirming that the safety device has accepted a most recently sent one of the plurality of messages.
|STORAGE DEVICE, STORAGE SYSTEM, AND METHOD FOR CONTROLLING STORAGE DEVICE - A storage device disclosed in the present application includes a device-error-codes table, first-information indicating a process-setting that can be changed by a device-state, and second-information indicating a process-setting that is a previously determined by a device-error-type, are associated with each other; a management-unit that adds information indicating a change in the second-information to the second-information stored in the table; a determining-unit that determines the device-error-type; an acquiring unit that acquires, from the table, the first-information; an information-converter that determines whether or not information indicating a change in the second-information, and changes the first-information by the acquiring unit; a transmitter that transmits the first-information by the acquiring unit or changed by the information-converter to a storage-device-controller; and an information-transmitter that receives, from the controller, a request to transmit the second-information and transmits, to the controller, the second-information that corresponds to the request.
|Speed-optimized computation of cyclic redundancy check codes - Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.
|ENFORCING NETWORK BANDWIDTH PARTITIONING FOR VIRTUAL EXECUTION ENVIRONMENTS WITH DIRECT ACCESS TO NETWORK HARDWARE - A method for enforcing network bandwidth partitioning. The method includes verifying that a guest driver in a guest operating system (OS) is configured to enforce a resource usage policy, wherein the guest OS resides on a host, mapping a hardware receive ring (HRR) residing on a physical network interface card (NIC) operatively connected to the host to the guest OS, wherein after the mapping the guest OS is configured to receive packets directly from the HRR, determining, using monitoring information, that the guest OS should not receive packets directly from the HRR, and in response to the determination, creating a data path from the HRR to a host OS executing on the host, receiving packets for the guest OS from the HRR by the host OS over the data path, and forwarding the packets from the host OS to the guest OS.
|System to Improve Error Code Decoding Using Historical Information and Associated Methods - A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
|Method for transmitting a data transfer block and method and system for transferring a data transfer block - A method for transmitting a data transfer block, the data transfer block comprising at least one data segment having a predetermined number of one or more data units, to be identified using validity information, and a header segment, the method including the following steps: a) writing a data unit into a first area of an output register predetermined for the data segment, from which the buffered data transfer block is transmitted via a bus system at a predetermined transmission instant with the aid of a time multiplexing method; b) writing a validity datum, implemented as a toggle bit or as an N-bit counter, into a second area of the output register predetermined for the header segment, the particular validity datum specifying the validity of the corresponding written data unit; c) enabling the data transfer block buffered in the output register for transmission, after the particular data unit and the corresponding validity datum are written into the output register; d) repeating steps (a) through (c) until the predetermined number of the data units and the corresponding validity data are written or the predetermined transmission instant is reached; and e) transmitting the enabled data transfer block buffered in the output register at the transmission instant.
|Method and Apparatus for Establishing a Streamed Media Session - A method and an arrangement for enabling a communication session for streamed media between a client terminal and a server. A request-to-establish message is sent (
|CRC PROTECTION OF DATA STORED IN XOR BUFFER - An XOR unit is provided in a hard disk controller for calculating an XOR of two operands stored in a buffer memory. The XOR unit includes an XOR calculator for calculating the XOR of the operands and a CRC of the XOR resulting from the calculation. An XOR buffer is also included in the XOR unit for storing the XOR result and the CRC of the XOR result, and a CRC calculator for calculating a CRC of the XOR result stored in the XOR buffer. The CRC calculated by the CRC calculator is compared with the CRC of the XOR result stored in the CRC buffer to determine whether the XOR result has been corrupted in the XOR buffer. The XOR result stored in the XOR buffer is determined to be corrupted if the CRC calculated by the CRC calculator and the CRC stored in the XOR buffer do not match.
|CIRCUIT FOR REDUCING THE READ DISTURBANCE IN MEMORY - A memory includes an internal data block and a temporary storing unit. The internal data block stores internal data of the memory. The temporary storing unit temporarily stores the internal data of the memory after the memory is powered on.
|Apparatus, System, and Method for Specifying Intermediate CRC Locations in a Data Stream - An apparatus, system, and method are disclosed for determining the location of intermediate CRC in a data stream sent from a channel subsystem to a control unit of an I/O processing system. A CRC locating module determines the location of at least one intermediate CRC in a transport data information unit. A CRC offset module determines a CRC offset of the at least one intermediate CRC. The CRC offset is a value identifying the difference between the location of the at least one intermediate CRC and the location of the first byte of user data in the transport data information unit. An offset block creation module creates a CRC offset block which includes a CRC offset value for each of the at least one intermediate CRC within the transport data information unit and a transmission module transmits the COB to a control unit in the I/O processing system.
|SYSTEM AND METHOD TO SERIALLY TRANSMIT VITAL DATA FROM TWO PROCESSORS - A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.
|DATA RECEIVING APPARATUS, DATA RECEIVING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A data receiving apparatus includes: a header analyzing unit that analyzes a header of a frame and outputs header information; a checksum judging unit that calculates and judges a checksum of the frame; a buffer unit that stores a data portion of the frame; a reading unit that reads connection information corresponding to the header information from a second storage unit; an identifying unit that identifies a write location for the data portion based on the connection information; a data writing unit that reads data from the buffer unit and starts writing the data to the identified write location in a first storage unit before the checksum is judged; and a writing unit that, if the judgment result is "pass," writes the connection information updated based on the header information to the second storage unit while the data writing unit is writing.
|METHOD AND APPARATUS FOR CYCLIC REDUNDANCY CHECK IN COMMUNICATION SYSTEM - A method for performing a Cyclic Redundancy Check (CRC) in a communication system is provided. An input message is divided into a predetermined number of segments. The CRC is performed on each segment to generate a CRC code of each segment. Polynomial addition is performed on CRC codes of respective segments to obtain a CRC code of the input message.
|CRC COUNTER NORMALIZATION - The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.
|System and Method for Fault Tolerant Computing Using Generic Hardware - A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function. The first application instance calls the synchronization function provided by the multitasking real-time operating system before invoking a set events function provided by a multitasking real-time operating system.
|System and Method for Fault Tolerant Computing Using Generic Hardware - A dual redundant process controller is provided. The controller comprises a first processor, memory, and instance of a process control application stored in the first memory. The controller further comprises a second processor, memory, and instance of the process control application stored in the second memory. When executed by the first processor, the first application instance writes a first synchronization information to the second memory, reads a second synchronization information from the first memory, and, when the second synchronization information disagrees with the first synchronization information after passage of a predetermined time-out interval, performs a resynchronization function; and wherein, when executed by the second processor, the second application instance writes the second synchronization information to the first memory, reads the first synchronization information from the second memory, and, when the first synchronization information disagrees with the second synchronization information after passage of the predetermined time-out interval, performs the resynchronization function.
|RELAY APPARATUS AND WIRELESS COMMUNICATION SYSTEM - A relay station and a wireless communication system wherein novel retransmission control is achieved in cases when a TTI-bundling technique and a relay technique are used in communication between a terminal and a base station. A relay station (
|MEMORY SYSTEM AND METHOD FOR GENERATING AND TRANSFERRING PARITY INFORMATION - A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.
|SILENT ERROR DETECTION IN SRAM-BASED FPGA DEVICES - Methods and systems for detecting errors in a field programmable gate array are disclosed. One method includes applying a cyclic redundancy check value to a transaction, the transaction including an address and data associated with the address. The method also includes applying a cyclic redundancy check value prior to routing the transaction through a field programmable gate array, and checking the cyclic redundancy check value after routing the transaction through the field programmable gate array to detect errors in the field programmable gate array.
|Method of detecting error in a semiconductor memory device - A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.
|Content Integrity Management System - A method and system are provided for efficiently verifying the integrity of file-based video audio and other essence in a content production system. The method involves creating a sequence of hash codes for the editable units of the essence, which are stored as metadata apart from the content (either in a separate file or in a separate portion of the same file), and are correlated to the content by a time label (which may be an offset or a timecode number). Upon retrieval from storage, the hash codes are generated for the retrieved essence and compared to the stored hash codes to verify that the content has not been modified.
|DATA INTEGRITY UNITS IN NONVOLATILE MEMORY - An integrity unit can be calculated from a first data unit, and a first storage device can be requested to store the first data unit. A second storage device, which can be separate from and/or a different type of device from the first storage device, can be requested to store metadata, which includes the integrity unit, in nonvolatile memory. Also, a second data unit can be received from the first storage device in response to a request for the first data unit. The integrity unit can be received from the second storage device, and the second data unit and the integrity unit can be analyzed to determine whether the second data unit matches the first data unit. Alternatively, a first integrity unit can be stored in a metadata region of a nonvolatile memory block, where the block also stores the data from which the first integrity unit was calculated.
|Systems and Methods for Authenticating and Protecting the Integrity of Data Streams and Other Data - Systems and methods are disclosed for enabling a recipient of a cryptographically-signed electronic communication to verify the authenticity of the communication on-the-fly using a signed chain of check values, the chain being constructed from the original content of the communication, and each check value in the chain being at least partially dependent on the signed root of the chain and a portion of the communication. Fault tolerance can be provided by including error-check values in the communication that enable a decoding device to maintain the chain's security in the face of communication errors. In one embodiment, systems and methods are provided for enabling secure quasi-random access to a content file by constructing a hierarchy of hash values from the file, the hierarchy deriving its security in a manner similar to that used by the above-described chain. The hierarchy culminates with a signed hash that can be used to verify the integrity of other hash values in the hierarchy, and these other hash values can, in turn, be used to efficiently verify the authenticity of arbitrary portions of the content file.
|METHOD OF TRANSMITTING AND RECEIVING DATA IN A WIRELESS COMMUNICATION SYSTEM - A method for transmitting data from a network to a user equipment in a wireless communication system is provided. The network adds an error detection code, generated using a first identifier allocated to the user equipment, to scheduling information for data to be transmitted to the user equipment and transmits the scheduling information to which the error detection code has been added to the user equipment. The network also adds an error detection code, generated using a second identifier allocated to the user equipment, to the data to be transmitted to the user equipment and transmits the data to which the error detection code has been added to the user equipment.
|Verification of Configuration Parameters - In a battery management system, error detection data is generated for various configuration parameters used by the battery management system. The error detection data is compared against corresponding error detection data previously generated during production or development of a battery pack or battery pack application. Based on the comparison, an appropriate action can be taken.
|METHOD AND APPARATUS FOR DATA CHECK PROCESSING - The invention discloses a method and an apparatus for data check processing, the method comprises: acquiring data to be checked; acquiring a first polynomial matrix F according to a generator polynomial; acquiring a second generator polynomial matrix F
|OFDM SYMBOL DIVERSITY COMBINER FOR BURST INTERFERENCE MITIGATION - The invention disclosed in this application describes a diversity combiner that operates as a maximal ratio combiner (MRC) when no interference is detected and as a selection combiner when OFDM symbol errors are detected with high probability.
|CYCLIC REDUNDANCY CHECK CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE CYCLIC REDUNDANCY CHECK CIRCUIT - An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.
|RUNNING CYCLIC REDUNDANCY CHECK OVER CODING SEGMENTS - In order to allow early stopping of codeblock decoding iterations, a cyclic redundancy check (CRC) is attached to each codeblock segment that pertains to the same transport block carrying information bits. The CRC for segment k is calculated for all bits within segments
|Solid State Disk Device and Program Fail Processing Method Thereof - A solid state disk device includes at least one nonvolatile memory and a controller reporting an error code to a host for requesting a previously received data and a command corresponding to the data when a program fail occurs in the nonvolatile memory. The error code is one of a plurality of error codes defined in an interface supported by the controller or a data transmission protocol supported by the nonvolatile memory.
|AUDIO ERROR DETECTION AND PROCESSING - A method of processing a DAB audio stream, the method comprising: receiving a compressed and modulated DAB audio stream comprising a plurality of audio frames encoded with scale factors and a DAB-CRC error detection code for indicating errors in the scale factors; demodulating the DAB stream; and processing the demodulated and still compressed DAB stream responsive to the DAB-CRC of at least one audio frame of the plurality of audio frames; by determining a trend in values of scale factors and repairing or concealing the error in the scale factor responsive to the trend.
|SERIAL DATA COMMUNICATION - CAN MEMORY ERROR DETECTION METHODS - A method is provided for formatting a message, with a first plurality of bits forming a data component, and a second plurality of bits forming a reserved component, for transmission in a vehicle. The method comprises the steps of calculating an initial checksum from the data component, calculating a revised checksum at least from the initial checksum, and storing the revised checksum in the reserved component. The number of bits in the reserved component is less than the number of bits in the data component.
|SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD - The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
|Error correcting viterbi decoder - Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
|CRC Counter Normalization - The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.
|CHECKSUM VERIFICATION ACCELERATOR - Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum.
|SEMICONDUCTOR APPARATUS AND DATA PROCESSING METHOD - A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals.
|System and Method for Device Identification in a Communications System - A method of transmitting an information sequence in a message includes embedding a first information sequence into an original payload of the message to produce an augmented payload and generating an original error check code using the augmented payload, the original error check code derived from the first information sequence. The method also includes transmitting the message, the message including the original payload and the original error check code.
|Reliable Data Transmission with Reduced Bit Error Rate - A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.
|Compression of Stream Data Using a Hierarchically-Indexed Database - The present invention, in particular embodiments, is directed to methods, apparatuses and systems that provide an efficient compression technique for data streams transmitted to storage devices or over networks to remote hosts. Local storage as well as network transmission of streams is made more efficient by awareness and utilization of repeated sequences of data blocks. Such data blocks can be placed in a dictionary on persistent storage and shared across all streams. The dictionary is hierarchically indexed (two or more levels of indexing) to combine high efficiency search with efficient access to the stored data blocks. Additionally, data blocks, in particular implementations, are stored sequentially in order to improve overall performance.
|APPARATUS AND METHOD FOR GENERATING ERROR DETECTION CODES - An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.
|Packet transmission device and packet transmission method - Aiming to shorten the transmission operation, the present invention provides an apparatus including a memory, a checksum calculation circuit, and a transmission device. The memory stores data of a packet to be transmitted. The checksum calculation section reads data sets corresponding to all the packet fragments except for that having a checksum storage area, sequentially and cumulatively adds the data sets to obtain a checksum value, thereafter reads a data set corresponding to the fragment having the checksum storage area therein from the memory, and adds the read data to the checksum value to obtain a final checksum value. The transmission section sequentially transmits the fragments once the individual fragments are used for the checksum calculation in the checksum calculation section, and, thereafter, transmits the fragment which is read from the memory and has the checksum storage area including the final checksum value therein.
|Method for Visually Confirming a Relationship Between an Edited Packet and Serial Data - A user may easily confirm a relationship between an edited packet and the output serial data derived from the edited packet. The user may edit a packet with known method (step
|CRC MANAGEMENT METHOD PERFORMED IN SATA INTERFACE AND DATA STORAGE DEVICE USING CRC MANAGEMENT METHOD - A cyclic redundancy check (CRC) management method performed in a serial advanced technology attachment (SATA) interface and a data storage device using the CRC management method. A host interface connected to the SATA interface performs CRC computation on transmitted data to generate a first CRC code, determines whether a host interface block error or a data integrity error occurs, or the status of a data storage device needs to be reported to the host interface, generates a second CRC code, which is different from the first CRC code, according to the determination result. If a frame including the transmitted data and the second CRC code is transmitted to a host, the host performs CRC computation on a data FIS in the transmitted data to expect the first CRC code. Since the CRC code in the transmitted data is the second CRC code, the host recognizes that the transmitted data is wrong and provides an error notification to the data storage device. Accordingly, the host can be informed of the host interface block error, the data integrity error, or the status error of the data storage device, not a protocol error in the SATA interface.
|METHOD FOR PARALLEL DATA INTEGRITY CHECKING OF PCI EXPRESS DEVICES - An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer (
|SECURITY COMMUNICATION METHOD BETWEEN DEVICES - There is provided a security communication method between devices to tighten the security of data by changing CRC polynomials and scramble codes in the communication between the devices.
|Performing A Cyclic Redundancy Checksum Operation Responsive To A User-Level Instruction - In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
|METHODS AND APPARATUS TO COMPUTE CRC FOR MULTIPLE CODE BLOCKS - A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.
|POWERLINE COMMUNICATION FRAMES HAVING CRC WITHIN HEADER - A method of powerline communications including a first node and at least a second node on a powerline communications (PLC) channel in a PLC network. The first node sends a physical layer (PHY) data frame on the PLC channel including a preamble, a PHY header, a MAC header and a MAC payload. The MAC header includes a Cyclic Redundancy Check (CRC) field (MH-CRC field). The second node receives the data frame, parses the MAC header to reach the MH-CRC field, and performs CRC verification using the MH-CRC field to verify the MAC header. If the CRC verification is successful, (i) the second node parses another portion of the MAC header to identify a destination address of the data frame and (ii) to determine whether the data frame is intended for the second node from the destination address.
|CO-HOSTED CYCLICAL REDUNDANCY CHECK CALCULATION - A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result.
|CODING APPARATUS, CODING METHOD, DATA COMMUNICATION APPARATUS, AND DATA COMMUNICATION METHOD - A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive "0" data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a "0" data value and maximum one bit of tail end two bits is permitted to have a "0" data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive "0" data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.
|HIGH THROUGHPUT FRAME CHECK SEQUENCE MODULE ARCHITECTURE - Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
|Method and System For Cyclic Redundancy Check - The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.
|DATA DEDUPLICATION USING CRC-SEED DIFFERENTIATION BETWEEN DATA AND STUBS - Various embodiments for differentiating between data and stubs pointing to a parent copy of deduplicated data are provided. Undeduplicated data is stored with a first cyclic redundancy check (CRC) seed. A stub pointing to the parent copy of the deduplicated data is stored with a second CRC seed. Subsequent to reading the deduplicated data, the first CRC seed is associated with the undeduplicated data, and the second CRC seed is associated with the stub. A CRC check is performed using one of the first and second CRC seeds. If the CRC check is positive, an I/O operation is allowed to proceed. If the CRC check is negative, an additional CRC check is performed using another one of the first and second CRC seeds.
|Method and Apparatus for Performing a CRC Check - A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments. The apparatus further includes a plurality of first CRC check units, wherein each of the first CRC check units is configured to perform a first CRC check of a respective one of the plurality of data segments, the plurality of first CRC checks being performed concurrently, and wherein each of the first CRC check units is configured to perform a second CRC check based on an output of the respective first CRC check unit.
|Detection Of Duplicate Packets - A packet is received from a network. The packet includes a field. The content of the field is compared to each element of a list. If the content of the field fails to match any element in the list, the packet is accepted and the content of the field is added to the list as an additional element of the list.
|Management Method And System For Implementation, Execution, Data Collection, and Data Analysis Of A Structured Collection Procedure Which Runs On A Collection Device - A collection device for performing a structured collection procedure may include a processor that executes program instructions communicably coupled to at least one memory. The processor can initiate a schedule of events of the structured collection procedure upon one or more entry criterions being met and segregate the at least one memory into a primary data store and a secondary data store. The processor can write structured patient data collected in accordance to the schedule of events to the secondary data store. The processor can transform a relevant portion of the structured patient data into an evaluated data object. The processor can generate a data abstraction based in part upon the evaluated data object. The processor can link the primary data store and the secondary data store with the data abstraction.
|Information processing apparatus and error detection method - An information processing apparatus includes multiple bus slaves, a bus master that outputs address data having a base address value for specifying arbitrary bus slave among the multiple bus slaves, and an offset address value for specifying access position in the bus slave, a selection unit that outputs a selection signal for selecting the arbitrary bus slave to the multiple bus slaves according to the base address value output from the bus master, an error detecting code generation unit that outputs an error detecting code from the address data output from the bus master, and an error detection unit that detects an error in the address data according to the error detecting code, which is generated from the offset address value output from the bus master and the base address value for specifying the selected bus slave, and the error detecting code output from the error detecting code generation unit.
|Method and Device for Fast Cyclic Redundancy Check Coding - The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2
|METHOD AND SYSTEM FOR PERFORMING DATA INTEGRITY VERIFICATION OF A TRANSPORT STREAM - A method, system, and computer-readable medium for facilitating integrity verification of a transport stream is provided. Integrity verification is performed without increasing the bit rate of the transport stream by generating a checksum corresponding to a portion of the transport stream and inserting the checksum into a null packet within the transport stream. Utilizing a null packet to carry the checksum allows the checksum to be transmitted without increasing the bit rate of the transport stream. In addition, by creating a checksum corresponding to a portion of the transport stream, integrity verification may be performed on a streaming data file.
|ERROR CODE PATTERN GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.
|METHOD FOR DETERMINING TRANSPORT BLOCK SIZE AND SIGNAL TRANSMISSION METHOD USING THE SAME - A method and device for segmenting, CRC encoding and turbo encoding a CRC attached transport block.
|WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION APPARATUS, AND WIRELESS COMMUNICATION METHODAANM HARATA; MasakazuAACI KawasakiAACO JPAAGP HARATA; Masakazu Kawasaki JPAANM SHIRASAWA; HidetoshiAACI KawasakiAACO JPAAGP SHIRASAWA; Hidetoshi Kawasaki JP - A wireless communication system includes: a dividing unit to divide data into a plurality of first code blocks; a generation unit to generate first error detection information for each of the plurality of code blocks; a transmission unit to wirelessly transmit at least one of the plurality of first code blocks using a first channel and the first error detection information using a second channel; a reception unit to receive a plurality of second code blocks and second error detection information transmitted wirelessly; and a detection unit to execute error detection on each of the plurality of second code blocks using the second error detection information and to control a continuation of the error detection for the code blocks based on a result of the error detection.
|HIERARCHICAL MODULATION AND DEMODULATION APPARATUS AND METHOD - An apparatus and method for hierarchical modulation and demodulation in a wireless communication network are provided. A hierarchical modulation apparatus may map information bits to a plurality of levels based on a predetermined level map, may generate an error verification code for each of the levels based on the information bits mapped to the levels, may generate coded information bits for each of the levels, and may map bits in a predetermined position among the coded information bits, to Pulse-Position Modulation (PPM) symbols in a sequence of the levels.
|Data relay apparatus, data relay method and data relay integrated circuit - According to an aspect of an embodiment, a data relay apparatus for transferring writing data and an associated check code sequentially sent from a host into a memory device, said writing data containing a plurality of fields classified by the kind of information in said writing data, comprising: a memory for storing said writing data and said check code for checking an error of said writing data; a calculating module for calculating said check code to determine whether the writing data sent from the host contains an error; a transfer module for transferring the writing data into the memory, the transferring of the writing data into the memory being initiated before determination by the calculating module.
|MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.
|Bit Error Rate Impact Reduction - In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and the burst control word and a second error check that protects only the burst control word. The first error check and the second error check are examined. Only the one logical communication channel is errored out if the first error check is bad and the second error check is good; all open logical communication channels are errored out if the first error check is bad and the second error check is bad.
|SECURE ERROR DETECTION AND SYNCHRONOUS DATA TAGGING FOR HIGH-SPEED DATA TRANSFER - Embodiments of the present invention provide a system for secure error detection and synchronous data tagging for high-speed data transfer (e.g., utilizing a set of SSD memory disk units). Specifically, in a typical embodiment, the system comprises a SSD memory disk unit in communication with a device driver. A first encoded communication stream will be generated with the device driver and sent via PCI-based channel (e.g., full duplex) to the SSD memory disk unit. The stream is received, synchronized, and decoded on the SSD memory disk unit. In turn, the SSD memory disk unit can generate and send a second encoded communication steam to the device driver.
|ADDRESS TRANSLATION CHECKING DEVICE, CENTRAL PROCESSING UNIT, AND ADDRESS TRANSLATION CHECKING METHOD - An information processing apparatus includes an MMU that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses that are addresses in physical memory and virtual addresses that are addresses in virtual memory. Stored in a RAM are page table information indicating a page table, as well as error detection information attached to the page table information for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU. A CPU detects the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU on the basis of the error detection information.
|Systems and Methods for Post Processing Gain Correction - Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a filter circuit, a gain error generation circuit, and a multiplier circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The filter circuit is operable to filter the detected output to yield a filtered output. The gain error generation circuit is operable to calculate an error value based upon a combination of an instance of the data set and a corresponding instance of the filtered output. The multiplier circuit operable to multiply the instance of the data set by a gain feedback value to yield a gain corrected output. The gain feedback value is derived from the error value.
|INCREMENTAL MODIFICATION OF AN ERROR DETECTION CODE BACKGROUND OF THE INVENTION - Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.
|Method For Transferring A Number Of Medical Image Data Records And System For Managing Image Data Records - A method is disclosed for transferring a number of medical image data records from a first computation facility to a second computation facility, with the second computation facility sending a transmission confirmation to the first computation facility after transmission is completed. In at least one embodiment, before the image data records are transmitted, a first checksum is determined for all the image data records and sent with the image data records; the first checksum is extracted at the second computation facility and is compared with a second checksum determined from the transmitted image data records in the same manner as the first checksum; and the transmission confirmation indicates a failure if the checksums do not correspond.
|Method for Error Correction Coding Comprising Local Error Detection Codes, Corresponding Decoding Method, Transmitting, Receiving and Storage Device and Program - The disclosure relates to a coding method for associating redundant and source data and for carrying out a plurality of local codes associating at least one input status word and at least one output status word according to at least one label word and permutations applicable on at least certain of said words. The local codes are embodied in the form of detection codes and not error correction codes on a predetermined coding alphabet. The local codes are interconnected by the status words in such a way that at least one coding matrix is formed, each of which defining a base code.
|Detecting Data Error - A method includes segmenting a first portion of a data block into a plurality of segments that includes a first segment. The data block includes a second portion, different from the first portion, which stores cyclic redundancy check data calculated from data stored in the first portion of the data block. The method also includes calculating cyclic redundancy check data from the first segment, and, translating the calculated cyclic redundancy check data to a location associated with the data block. The method also includes combining the cyclic redundancy check data associated with the first segment and cyclic redundancy check data associated with at least one other segment included in the plurality of segments. The method also includes using the combined cyclic redundancy check data for error detection.
|MONITORING DEVICE OF INTEGRATED CIRCUIT - A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.
|METHOD AND APPARATUS FOR ENCODING AND DECODING HIGH SPEED SHARED CONTROL CHANNEL - A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding, cyclic redundancy check (CRC) bits are generated based on part 1 data and part 2 data. The number of CRC bits is less than the WTRU ID. The CRC bits and/or the part 2 data are masked with a mask. The mask may be a WTRU ID or a punctured WTRU ID of length equal to the CRC bits. The mask may be generated using the WTRU ID and a generator matrix with a maximum minimum Hamming distance. The masking may be performed after encoding or rate matching.
|METHOD AND DEVICE FOR IMPLEMENTING CYCLIC REDUNDANCY CHECK CODES - The present invention relates to an error control technology in the communication system and discloses a method and an apparatus for implementing Cyclic Redundancy Check (CRC) codes to improve the operation performance of the system significantly and satisfy operation requirements when processing high-rate CRC data. The method includes: performing at least one XOR operation for information bits input in parallel to obtain a first result, where at least one pipeline is added during the XOR operation; performing an XOR operation for a previously obtained CRC code to obtain a second result; and performing an XOR operation for the second result and the first result to obtain a current CRC code. The present invention is applicable to any field that needs to implement CRC codes by means of hardware.
|METHOD AND APPARATUS FOR MAP TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM - An operating method of a base station for transmitting MAP information in a wireless communication system includes determining a seed value for randomizing MAP information bits, generating a Media Access Control (MAC) control message including the seed value and a Station IDentifier (STID), and transmitting the MAC control message to a mobile station. Hence, the assignment A-MAP IE can be transmitted more safely.
|DISTRIBUTED CHECKSUM COMPUTATION - Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.
|Apparatus for Generating a Checksum - An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.
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