text: Speaking of the Calontiri.... I thought we had some sort of mutual aid and defense treaty with them, didn't we? Or shouldn't we? We keep the hurricaines down here andd they keep the ice up there.... Just a thought, Colin mikea <mikea at mikea.ath.cx> wrote: On Wed, Jan 17, 2007 at 12:31:57PM -0500, DonnelShaw at aol.com wrote: > > > > I am sitting here thinking the same thing. > Donnel > (I don't do cold well) > > In a message dated 1/17/2007 11:00:31 A.M. Central Standard Time, > vmarsh at twmarsh.net writes: > > Well.... Burke correctly predicted the weather last weekend (and some people > didn't listen to him!). > > Is there a contingency plan in place for Round Table this coming weekend? It > doesn't look like it will be safe enough to travel throughout the Kingdom > until sometime Sunday or Monday. Maybe. > > Xene The weather-guessers here are saying that Oklahoma is about to get yet another dose of what we had the past weekend, only this one is aimed a bit more carefully at Namron and Wiesenfeuer. Still, the effects as shown in the prognostications are a bit widespread, and it really, really doesn't look good from somewhere south of Steppes to the north border of the Kingdom. Pah! Ship it to the Calontiri; they're used to it. -- Mike Andrews / Michael Fenwick Barony of Namron, Ansteorra mikea at mikea.ath.cx / Amateur Extra radio operator W5EGO Tired old music Laurel; Chirurgeon; SCAdian since AS XI _______________________________________________ Ansteorra mailing list Ansteorra at lists.ansteorra.org http://lists.ansteorra.org/listinfo.cgi/ansteorra-ansteorra.org Do, or do not. There is no try. -- Yoda


text:
White RIver Museum Celebrates Lighting Project
- When: Saturday, September 8, 2012, 3:30 p.m. to 5 p.m.
- Where: White River Museum , Meeker
- Cost: Not available
- Age limit: Not available
- Categories: Tours, Photography, Community, Social
Rio Blanco County Historical Society and WHite River Museum Lighting Project Open House and Celebration.
The completion of the first phase of the Lighting Project. Open house Saturday, September 8, between 3:30 & 5:00 p.m.
White RIver Museum located at 565 Park St. Meeker Co.
Ellene Meece, RBCHS President Welcomes the Meeker Community and Meeker Sheep Dog Classic guests to join in the celebration and tour the Museum to appreciate the exceptional effort of new state-of-the-art Museum lighting technology.
Refreshments will be served.
Use the comment form below to begin a discussion about this content.
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subset: commoncrawl


text:
Category Archives: Sprints and Hurdles
Sprint Acceleration Training Video
Usain Bolt's coach Glen Mills believes in sprint training drills, "Athletes tend to reverse to their old habits when put under pressure or when running at maximum velocity. Like helping an actor learning a part, coaches have to continuously react and replay and redo the drills, getting the athlete to run over and over in order to break habits, both psychologically and physically, and get into the right running technique."
"We set about doing drills then we took videos of his workouts and broke them down on the screen in slow motion to show him exactly what he was doing. I would draw diagrams and show him the position that we are working to achieve."
Sprint training drills are important for warm up and teaching proper sprint mechanics, the acceleration a-run drill is one example of the drills sprinters can use to improve technical skills and increase sprint speed.
Sprint Training Videos with Digital Membership
Hurdle Technique and Training Progression
Hurdle Training Progressions
Beginner Hurdle Step Patterns
3 Step Hurdling
8.00m or less between hurdles
1.90m – 2.00m at takeoff before the hurdle
.80m – .90m at touchdown after the hurdle
1.90m average stride between hurdles (less stride length than sprinting)
Set the hurdle distances to accomplish 3 step pattern
Hurdle Height Recommedations
Start low and build up
6 – 18″ for beginners
24 – 30″ as beginners improve
4 step hurdle rhythm can help develop leading with the both legs
Girls/Women Hurdle Teaching Progression
5 Hurdles Novice Progression
- 6″ hurdles at 7.00m apart
- 12″ hurdles at 7.00m apart
- 12″ hurdles at 7.30m apart
- 18″ hurdles at 7.60m apart
Up to 12 Hurdles Advanced Progression
- 24″ hurdles at 7.50m apart
- 24″ hurdles at 8.00m apart
- 30″ hurdles at 8.00m apart
- 30″ hurdles at 8.30m apart
Build up to 12 30 inch hurdles at 8.30m apart with proper rhythm
100m Hurdle Race Simulation
100m Hurdles
30″ 12m to first hurdle and 7.00m (add 20cm between each hurdle)
30″ 12.5m to first hurdle and 8.00m between hurdles x 5 hurdles
30″ 13m to the first hurdle and 8.00m between hurdles x 3 hurdles
Boys/Men Hurdle Teaching Progression
5 Hurdles Novice Progression
- 6″ hurdles at 7.50m apart
- 12″ hurdles at 7.50m apart
- 12″ hurdles at 8.00m apart
- 18″ hurdles at 8.00m apart
Up to 12 Hurdles Advanced Progression
- 24″ hurdles at 7.50m apart
- 24″ hurdles at 8.20m apart
- 30″ hurdles at 8.00m apart
- 30″ hurdles at 8.20m apart
110m Hurdle Race Simulation Boys 39″ hurdles
110m Hurdles High School 39″ hurdles
33″ 12m to first hurdle and 7.50m (add 20cm between each hurdle) x 5 hurdles
36″ 12.5m to first hurdle and 8.00m between hurdles x 5 hurdles
36″ 13m the first hurdle and 8.20m between hurdles x 3 hurdles
110m Hurdles Race Simulation College 42″ hurdles
33″ 12m to first hurdle and 7.50m (add 20cm between each hurdle) x 5 hurdles
36″ 12.5m to first hurdle and 8.00m between hurdles x 5 hurdles
39″ 13m to the first hurdle and 8.20m between hurdles x 3 hurdles
Adjust hurdle heights based on competition height: youth, international and high school heights can vary based on association rules for the hurdles.
All Access Members Hurdle Rhythm Drills Video
Learn more about hurdle training here
10 Hurdle Training Tips For Coaches
10 Hurdle Training Tips
Coaching Hurdles Tip #1
- Do not jump hurdles
Coaching Hurdle Tip #2
- Develop quick trail leg
-long high path for trail leg knee
Coaching Hurdles Tip #3
- Teach takeoff close to hurdle
-teaches vertical aspect of hurdling
Coaching Hurdles Tip #4
- Takeoff leg coaching
– knee and thigh lead
Learn more from Coach Gary Winkler on Hurdle Biomechanics (PDF link)
Coaching Hurdles Tip #5
- Reduce spacing and height of hurdles
Coaching Hurdles Tip #6
- Use coaching marks for takeoff
-time takeoff to touchdown
Coaching Hurdles Tip #7
- 100m/110m Hurdles
Train high hurdle technique 25-50%
Train sprinting 50-75%
Train high hurdles like hurdlers and 100m sprinters
High hurdlers can run 4x100m and 200m
Coaching Hurdles Tip #8
- 300-400m Hurdles
Train hurdles 25-40%
Train sprinting 60-75%
Train 300-400m hurdles like 200m sprinters
300-400m hurdlers can run 4x400m and 800m
Coaching Hurdles Tip #9
- Train 3-6 hurdles for acceleration
- Train long flights of hurdles for rhythm and confidence
Coaching Hurdles Tip #10
- Hurdle Contrast Training
50% training with lower hurdlesContrast Options
- Height of the hurdles
- Spacing between hurdles
- Number of hurdles
- Steps between hurdles
- Group start vs. individual start
- Start variations (jog into, 3 point, blocks)
Download Hurdle Training Videos from Digital Track and Field
Track and Field Warm Up Video Backward Skip with Coach
Warm Up Phases
Designing the start of a practice session for athletes includes warm up drills to prepare for the activities of the training session. The warm up is broken up into three phases.
Phase One- Low Intensity Exercises and Flexibility (4-6 minutes)
The start of the warm up is active with low intensity activities, such as arm circles, easy skipping or walking toe touches. The initial exercises are controlled, focusing on raising the body temperature slowly and developing a full range of motion from head to toe. The exercises are stationary or up to 30 meters in length. The recovery between exercises is about 10-20 seconds and the first phase of the warm up is about 3-5 minutes.
Phase Two- High Intensity Exercises (3-5 minutes)
Then the general activities will increase intensity and speed. Athletes will advance from the initial low intensity active exercises to more dynamic movements, such as A- skip, high knee running, bounding or medicine ball throws. The exercises during the second phase of the warm up range from 20-40 meters, with a walk back recovery.
Phase Three- Event Specific Exercises (5-10 minutes)
The final phase of the warm up is event specific preparation activities. Coaches can add specific elements to the final phase of the warm up to develop speed, strength, or technique.
Link to complete article: Warm Up Exercises


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On the way to the event Christopher asked his Dad if we could stop by the store and get some snacks for the day. Chris responded, "Well we have sausages." Fortunately we stopped by the store and picked up a few things to break up the all day only sausage diet.
I am still a bit uncomfortable with KC small hoodie fashion trend, but the kids seem to love it. I guess it is better than saggy pants.
Prepping the sausage fatties for the smoker.
After you do this for awhile you can sleep anywhere.
KCBS Officials checking the coolers for the competition. Everything checked out.
Time to go on a walkabout. The area of the competition was under the freeway. There's an eerie feeling late at night with the sound of cars, and lingering clouds of smoke.
After we got back from our walk I powered up on some cold milk.
The sausage logs are well on their way to being finished. We temped them just to be safe.
It was going to be a meat only day again. However our buddy Mike Smoots pulled through with some biscuits and all was right with the world again.
After a glutinous breakfast of giant sausage slabs and smoked biscuits we started prepping the meats. The brisket was first on the list. Shelton breathed deep as he realized the gravity of the moment. This is the turn in brisket for the Three Little Pigs team, gulp!
Jaccarding the brisket. Mike Smoots had to show Shelton the "mad man technique" when it came to Jaccarding the briskets. This involved hitting the meat so hard the table bounced.(that is a bbq statement, please do not take it out of context.)
Wrapped and seasoned briskets ready for the ice chest.
Our neighbor took an early morning rip of Kentucky go juice.
Smoots and Mike worked together to get all the butts injected.
Smoots and Mike applied the rub to the butts.
Once again Christopher demonstrated his amazing ability to sleep virtually anywhere.
The smoked spatchcock chicken made for a great mid afternoon snack. Yep, you got it. More meat. Just meat. That is all you eat. meat, meat, meat, meat.
After the fueling up, we went for for another wander. I took a peek at the judges meeting. It was interesting to see who was going to judging our food.


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Weather Averages for Lisbon in May
Averages for Lisbon in May
May brings very pleasant warm temperatures to Lisbon.
The average temperature reaches up to around 22°C (that's about 72°F), and dips now lower than 13°C (about 55°F) in the evenings.
The average monthly rain is only around 39mm and there is about 9 hours of average daily sunshine.
The average sea temperature is about 17°C (about 62°F), so you can head to the nearby beaches to top up your or try your hand at surfing.
The Parque das Naçoes, also known as Lisbon Nations Park, is situated around the River Tagus and houses the Oceanário de Lisboa.
This Oceanarium contains a huge range of sea life as well as a lifesize exhibit of extinct sea creatures.
There are also backstage tours explaining about the conservation work and care of sea animals.
The Planetarium features regular sky shows projected on to the massive domed roof. There are also diagrams and models of the entire solar system.
Tennis enthusiasts can head to the Estoril Open to cheer on some of the world's most famous players as they compete.
The Book Fair (Feira do Livro) is held in Eduardo VII Park and features discussions, readings and presentations, as well as book sales and the chance to meet some prominent authors.
May events in Lisbon
Lisboa International Triathlon
2nd May 2015
Lisboa International Triathlon is held in late April every year. Running, swimming, cycling and other tough sporting events are the main attactions that ends in last week of April.
FIMFA - International Festival of Puppets and Animated Forms
7th May 2015 to 25th May 2015
FIMFA, an International Puppets and Animated Forms festival, takes place from 7th May and continues until 25th May. Many different styles of puppetry of artists and performers from all around the world gather together in the best theatres in Lisbon.
Alkantara Festival
13th May 2015 to 8th June 2015
Alkantara Festival is full of innovative and adventurous events that link Lisbon to the world. Artists from many different parts of the world present their performances in multiple venues all over the city of Lisbon.
Rock in Rio - Lisboa
8th May 2015 to 16th May 2015
This rock festival in Lisbon, Rock in Rio, is the biggest five-day musical entertainment filled with the world's top entertainers.


text:
Body found in cabin may be Christopher Dormer
- Written by Roz Edward, National Content Director
- Published in RTM News Reel
Near Big Bear Lake, California (CNN)-- It may take days before authorities can officially determine whether Christopher Jordan Dorner's body was found in the ashes of a torched cabin near Big Bear Lake, California.
But several signs early Wednesday seemed to suggest that the ex-Los Angeles police officer's vendetta against his brothers in blue ended in that wooden cabin with a shootout that left one deputy dead and another wounded.
The frenzied manhunt, road blocks and helicopter flights, which had brought the mountain town to a standstill for six days, died down Tuesday night.
And late in the evening, authorities announced that they found human remains in the cabin and would need forensic experts to identify them.
But even as the question of Dorner's fate seemed close to being answered, other details eluded explanation.
The carjacking
The deputy's death in the shootout Tuesday brought to four the number of people Dorner is accused of killing.
Dorner, a man who vowed to kill police officers to avenge what he called an unfair termination, was first named a suspect in two shooting deaths on February 3: that of the daughter of his police union representative and of her fiance.
Police also say he killed one officer in Riverside, California, and wounded two others Thursday.
Authorities offered a $1 million dollar reward in the case after Dorner's burned truck was found on a forestry road near Big Bear Lake on February 7, about 100 miles east of Los Angeles.
Officers converged on the remote area but the trail went cold for days. On Sunday, the San Bernadino authorities said they had scaled back the search.
That all changed Tuesday, where arguably the most wanted man in America was finally spotted.
The question of where Dorner was between February 7 and Tuesday was unclear.
Wardens of the California Fish and Wildlife said they spotted Dorner driving a purple Nissan down the icy roads Tuesday. Dorner was driving very close to some school buses as if using them as cover, said Lt. Patrick Foy.
The wardens, driving in two different vehicles, chased Dorner and a gun battle ensued.
A warden's car was hit.
Dorner crashed his car, ran and then quickly carjacked a pick up truck.
Rick Heltebrake, a camp ranger, said he was driving in the area when he saw the crashed purple car -- and then something terrifying.
"Here comes this guy with a big gun and I knew who it was right away," Heltebrake told CNN affiliate KTLA. "He just came out of the snow at me with his gun at my head. He said, 'I don't want to hurt you. Just get out of the car and start walking.'"
Heltebrake said he was allowed to get his dog out of the truck before he walked away with his hands up.
"Not more than 10 seconds later, I heard a loud round of gunfire," Heltebrake said. "Ten to 20 rounds maybe. I found out later what that was all about."
The fire
Dorner fled to a nearby cabin and got into another shootout with San Bernadino County deputies, killing one and wounding another.
San Bernardino County Sheriff John McMahon told reporters Tuesday the other deputy was in surgery "but he should be fine,"
The cabin caught fire after police tossed smoke devices inside, a law enforcement source told CNN.
The intense fire burned for hours as authorities waited at a distance.
Despite the enormity of the blaze, authorities were hesitant to officially say they had stopped Dorner.
"No body has been pulled out," LAPD Cmdr. Andrew Smith said at a news conference Tuesday night. "No reports of a body being ID'd are true."
Cindy Bachman, a spokeswoman for the lead agency in the case -- the San Bernardino Sheriff's Department -- echoed the words, saying at a separate news conference that authorities believe whoever was in the cabin never left.
"They believe that there is a body in there, but it is not safe to go inside," she told reporters.
Finally, late Tuesday night, sheriff's investigators said they found charred human remains within the ashes of the torched cabin.
The department said it will work to identify the remains -- but it could take a while.
The security
Clues to the targets of the violence were mentioned in Dorner's fiery manifesto that was posted online. Authorities say Dorner began making good on his threats on February 3 when he allegedly killed Monica Quan and Keith Lawrence in an Irvine parking lot, south of Los Angeles.
According to the manifesto, Randal Quan, Monica Quan's father, bungled Dorner's LAPD termination appeal.
Randal Quan represented Dorner during the disciplinary hearing that resulted in his firing. The officer was among dozens named in the manifesto.
On February 7, Dorner allegedly opened fire on two LAPD police officers, wounding one, in the suburban city of Corona.
Roughly 20 minutes later, Dorner allegedly fired on two officers in the nearby city of Riverside, killing Officer Michael Crain and wounding another.
Since then, the LAPD has provided security and surveillance details for more than 50 police officers and their families -- many of whom were named in the manifesto.
Police said Tuesday night they would continue to protect the people Dorner said he would target until it was confirmed that he died in the cabin.
In the manifesto Dorner wrote about death multiple times. Not just the death of his targets but of his own.
"Self Preservation is no longer important to me," the manifesto said at one point. "I do not fear death as I died long ago."
CNN's Miguel Marquez reported from near Big Bear Lake and Lateef Mungin wrote from Atlanta. CNN's Paul Vercammen, Stan Wilson, Casey Wian, Kathleen Johnston, Alan Duke, Matt Smith, Chelsea J. Carter, Michael Martinez and Holly Yan also contributed to this report.
I also worked for an evil agency that was relentless in preventing me from doing my job and made threats when I'd try to report my superiors when I'd witness their abuses. There are bullies with badges but I feel that if Chris worked anywhere else he may have had a beautiful long life without these incidents proceeding and lives lost when he snappped from the stress.


text:
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text:
November 23, 2014
COLUMBUS, Ohio (AP) - Rick Nash and the Columbus Blue Jackets have reached agreement on an eight-year contract extension through
the 2017-18 season.
Blue Jackets general manager Scott Howson confirmed the signing to The Associated Press on Friday night. The Canadian Press first reported the signing, saying the deal is worth $62.4 million. Nash will make $7 million in 2009-10.
Nash, who would have been an unrestricted free agent after next
season, set career and team highs last season with his 79 points
(40 goals, 39 assists) in 78 games in leading Columbus to its first trip to the playoffs in the franchise's eighth season.
The 25-year-old left wing from Brampton, Ontario, tied for the NHL lead in goals with 41 in the 2003-04 season.
Copyright 2014 Associated Press. All rights reserved. This material may not be published, broadcast, rewritten, or redistributed.
Click Here to access the online Public Inspection File
Viewers with disabilities can get assistance accessing this station's FCC Public Inspection File by contacting the station with the information listed below. Questions or concerns relating to the accessibility of the FCC's online public file system should be directed to the FCC at 888-225-5322, 888-835-5322 (TTY), or email@example.com.


text:
Hit The Brakes Lyrics - Saint Etienne
Transcribed by Jamie Fletcher and Jason Flynn
She's waking up,
the mirror says
that her hairs
getting far too long.
A coffee cup,
to start the day,
better make sure
it's good and strong.
To get her through.
Got things to do.
And now that the clock says eight,
can't be late,
so hit the brakes.
Lost all your friends
they'd had enough,
couldn't watch
while you killed yourself.
And you pretend
you gave them up,
for a lifetime of cars and wealth
Don't feel so good.
Another the clock says eight,
can't be late
so hit the brakes.
I said hit the brakes.
Click here to submit the Corrections of Hit The Brakes Lyrics
Please Click Here to Print Hit The Brakes Lyrics
The following area is only for review, if you want to submit the lyrics or the corrections of the lyrics, please click the link at the end of Hit The Brakes Lyrics.


text:
Hello Kitty received a Audition Tape Award!.
Tunerfish is free to join, and helps you share great things worth watching with your friends.
It all started when I was five...
Hello Kitty has watched 5 shows in the Reality Show genre.
Hello Kitty received the Audition Tape award.3 years agoSign in to comment to this.
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text:
Yes In My Backyard is a semiweekly column showcasing MP3s from new and emerging local talent. Marielle SolanTaut New York five-piece MiniBoone are an enchanting mesh of old-school energy and new-school melody. The band mixes the dervish energy of '78-era post-punk with the super-hooks of mod ... More >>
Film and winemaker Francis Ford Coppola is taking Vinicor to court for ruining 55,000 cases of wine by supplying faulty bottles and leaky screw caps. [Bloomberg] Celebrate the season with beer. Try one of these festive brews: Sam Adams Winter Lager, Jewbelation Bar Mitzvah, or St. Bernardus ... More >>
The feds say this Albanian tough guy swings for John Gotti's old team


text:
"This card is very beautiful and tasteful. Quality is fantastic. I've been ordering from Tiny Prints for years now and wont go anywhere else. Thank you, Tiny Prints!"
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text:
Score Breakdown based on
1 Reviews
4.8 on December 24, 2010
I had a wonderful stay with Sara and Leigh at La Siroque. The room was superior. Everything was clean. They made me feel like I was home. It was especially nice to get to take Max, the family dog, for walks. I hope some day I can return and stay longer. Thank you.


text:
Senior reporter Frank Esposito returns from the Brasilplast trade show with news of several Brazilian and U.S. firms expanding their presence in the growing South American economy. Also in this edition of Plastics News' Material Insights, PolyOne opens a new design center and Selenis Canada opens a PET plant near Montreal.
Material Insights: Evonik attempts to replace microbeadsNovember 24, 2014 11:48 am ET


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Inventors list
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Fusible link or intentional destruct circuit
Subclass of:
327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Patent class list (only not empty are listed)
Deeper subclasses:
|Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.
|Trim fuse circuit capable of disposing trim conducting pads on scribe lines of wafer - A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected.
|ELECTRICAL FUSES WITH REDUNDANCY - The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for providing redundancy to at least one fuse of the first set, wherein if one of the first set of electrical fuses is defective, at least one of the second set of the electrical fuses can be programmed to provide a redundancy function of the defective fuse.
|SEMICONDUCTOR INTEGRATED CIRCUIT HAVING FUSE CIRCUIT AND DRIVING METHOD OF FUSE CIRCUIT - A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.
|Antifuse Circuit Having Protection Circuit - An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.
|SEMICONDUCTOR DEVICE AND METHOD OF MONITORING BLOWING OF FUSE IN SEMICONDUCTOR DEVICE - In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion.
|FUSE CIRCUIT - A fuse circuit includes a first power supply line, a second power supply line, a first current source connected between the first power supply line and an output terminal, a second current source connected between the second power supply line and the output terminal, the second current source having higher current supply capacity or current draw-out capacity than the first current source, and a fuse connected in series with the second current source between the second power supply line and the output terminal
|Method to Bridge a Distance Between eFuse Banks That Contain Encoded Data - An eFuse system that includes a mechanism that bridges banks of eFuses and allows the banks of eFuses to be placed any distance from each other. The bridging of the eFuse banks is transparent to compression and encode programming algorithm and hardware decode mechanisms. Thus, by using the mechanism for bridging gaps between eFuse banks, an eFuse subsystem with several banks distributed on an integrated circuit chip appears to be a single large eFuse bank to the encode/decode mechanisms of the integrated circuit. Additionally, with this mechanism, eFuse banks can be easily added or deleted.
|SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
|ANTI-FUSE CIRCUIT AND FUSE REPTURE METHOD THEREOF - An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds.
|PROGRAMMABLE SEMICONDUCTOR DEVICE - A programmable device includes a substrate (
|METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
|ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT IDENTIFICATION, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT INCORPORATING THE SAME - An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller.
|FUSE CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.
|TRIMMING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND TRIMMING METHOD THEREOF - A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage.
|SEMICONDUCTOR DEVICE WITH TRANSISTOR-BASED FUSES AND RELATED PROGRAMMING METHOD - A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.
|Trimmer circuit and method - A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one.
|SEMICONDUCTOR DEVICE AND METHOD OF CUTTING ELECTRICAL FUSE - A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
|EFUSE DEVICE - An exemplary embodiment of an efuse device is provided, operating in a write mode and a read mode and comprising a source line, a cell, a blow device, and a sensing circuit. The cell has a first terminal coupled to the source line and a second terminal. The blow device is coupled between the second terminal of the cell and a ground terminal. The blow device is turned on in the read mode. The sensing circuit is coupled to the first terminal of the cell and the ground terminal, and is arranged to determine a state of the cell.
|FUSE CELL AND METHOD FOR PROGRAMMING THE SAME - The fuse cell architecture
|FUSE-FETCHING CIRCUIT AND METHOD FOR USING THE SAME - A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.
|ELECTRONIC TRIMMING CIRCUIT WITH REDUCED NUMBER OF DEDICATED TRIMMING PINS - An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof.
|Fuse Circuit - A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not.
|FUSE SET AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THE SAME - A fuse set includes a first row constituted by a plurality of fuses which are arranged with a first spacing; a second row including a plurality of fuses which are disposed to correspond to the fuses of the first row on the same plane, and separated from the fuses of the first row with a second spacing; and a connection part disposed between the first row and the second row and electrically connected with the plurality of fuses of the first row and the plurality of fuses of the second row, wherein the connection part and the pluralities of fuses of the first and second rows are disposed on different planes.
|Skew signal generator and semiconductor memory device - A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.
|Voltage Divider, Constant Voltage Circuit Using Same, And Trimming Method In The Voltage Divider Circuit - A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant.
|FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA - A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively.
|STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE - A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
|INTEGRATED CIRCUT, AND APPARATUS AND METHOD FOR PRODUCTION THEREOF - An integrated circuit includes a trimming signal creating section, disposed downstream of a trimming circuit in which a number of fuses are arranged in alignment, creating a trimming signal corresponding to the trimming value on the basis of a signal output from said trimming circuit and arranges blown object fuses such that every two of the blown object fuses are interposed at least one un-blown fuses in the trimming circuit. An efficient arrangement of blowing points in addition to the above arrangement of blown object fuses can reduce the area occupied by the trimming circuit.
|Programmable electronics - An electronic device with polarity reversal protected connections and irreversibly interruptible programming connections, wherein the interruption is performed through safety elements provided in the programming paths, behind which safety elements diodes are disposed which block towards ground in normal operation, so that an overload current can be passed through the safety elements and through the diodes to ground through intentional polarity reversal of the respective connections, whereby the safety elements are destroyed and the programming conductors are irreversibly interrupted.
|SEMICONDUCTOR DEVICE AND OFFSET VOLTAGE ADJUSTING METHOD - A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage.
|Method and Circuit for Implementing Efuse Resistance Screening - A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse.
|Automatic Bias Circuit for Sense Amplifier - The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.
|Multi-level anti-fuse and methods of operating and fabricating the same - Provided may be a multi-level anti-fuse and methods of fabricating and operating the same. The multi-level anti-fuse may include at least three anti-fuses having a plurality of anti-fuses connected in parallel constituting a parallel connection structure and at least one anti-fuse connected to the parallel connection structure in series, wherein the parallel connection structure may have a smaller resistance than the resistance of the anti-fuse connected in series, the plurality of anti-fuses connected in parallel may include dielectric layers having different thicknesses from one another, and the breakdown voltages of each dielectric layer may be different from one another.
|MASTER FUSE MODULE - A master fuse module includes a base housing configured to be disposed on a battery, a fuse assembly connected to the base housing, and a cover disposed on the base housing. The fuse assembly includes a first generally planar portion including a first terminal, a second generally planar portion disposed generally perpendicular to the first generally planar portion, a plurality of second terminals, and a plurality of fuses. Each fuse includes a first portion in electrical communication with the first terminal and a second portion in electrical communication with one of the plurality of second terminals. A fuse element is in electrical communication between the first and second portions and provides overcurrent protection by melting when subjected to a predetermined current. A plurality of connectors connects the fuse assembly to the base housing.
|Antifuse and methods of operating and manufacturing the same - Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.
|SEMICONDUCTOR DEVICE HAVING PLURAL OPTICAL FUSES AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.
|SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, REDUNDANCY SYSTEM, AND REDUNDANCY METHOD THEREOF - A semiconductor integrated circuit device including a fuse latch circuit including a fuse and a latch circuit for latching fuse data held in the fuse, a fuse counter circuit for counting the number of transfers of the fuse data, and a control circuit including a transmitter circuit for transmitting the fuse data to the outside, and a detour data path circuit which when the fuse data is not transferred, does not transfer the fuse data to the outside, and forms a detour data path for detouring the fuse data in the circuit itself.
|Electrical fuse, semiconductor device and method of disconnecting electrical fuse - An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.
|FUSE CIRCUIT AND OPERATION METHOD THEREOF - A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not.
|FUSE CIRCUIT WITH ENSURED FUSE CUT STATUS - A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.
|FUSE FOR USE IN HIGH-INTEGRATED SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.
|FUSE CIRCUIT - A fuse circuit includes a fuse, a control pulse generation unit, and an equipotential element. The fuse is coupled between a power supply voltage terminal and a first node. The control pulse generation unit is configured to generate a control pulse including a pulse generated in a period in which a power-up period is ended. The equipotential element is configured to make the first node have the same potential as a power supply voltage in response to the control pulse.
|FUSE CIRCUIT AND LAYOUT DESIGNING METHOD THEREOF - A fuse circuit for sensing a fuse connected state and layout designing method thereof are disclosed. Embodiments include a fuse program control unit providing a fuse open voltage in response to a program signal, a fuse cell unit configured to use a contact resistor connecting a node supplied with the fuse open voltage and a node supplied with a fuse connection voltage as a fuse, the fuse cell unit outputting a state information of the contact resistor in response to the fuse open voltage, and a fuse sensing unit outputting a fuse data signal corresponding to the state information of the contact resistor in response to a read signal. Accordingly, embodiments reduce a layout size of the fuse circuit.
|Programmable fuse and anti-fuse elements and methods of changing conduction states of same - A programmable anti-fuse element includes a substrate (
|SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
|Fuse devices and methods of operating the same - A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.
|IMPLEMENTING eFUSE CIRCUIT WITH ENHANCED eFUSE BLOW OPERATION - A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.
|CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE (E-FUSE) - Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
|ELECTRONIC FUSE SYSTEM - An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used of receiving a reference voltage. The electronic fuse circuit is used of changing a voltage level when a current signal passes. The first switch circuit coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit, for transferring the switch control signal according a control signal and a lock signal. Wherein, when the lock signal is enabled, the control signal is unable to control the control circuit to turn on the first switch circuit.
|Fuse option circuit - A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.
|SEMICONDUCTOR DEVICE - A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
|SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND SYSTEM - A semiconductor device (
|FUSE CIRCUIT OF SEMICONDUCTOR DEVICE AND METHOD FOR MONITORING FUSE STATE THEREOF - A fuse circuit of a semiconductor device includes a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode.
|Fuse Device - Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.
|Semiconductor device and trimming method therefor - Provided is a semiconductor device including a divisional resistor having a fuse, and a divisional resistor for measuring relative accuracy which is obtained by eliminating the fuse from the divisional resistor having the fuse. Characteristic values of the divisional resistor for measuring relative accuracy are measured so as to obtain trimming data, and then the divisional resistor having the fuse is trimmed, to thereby obtain a semiconductor device with highly precise characteristics.
|SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.
|INTEGRATED CIRCUIT - An integrated circuit, wherein a voltage-adjustable power supply circuit (
|APPARATUS AND METHOD FOR TAMPER PROTECTION OF A MICROPROCESSOR FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.
|MICROPROCESSOR APPARATUS AND METHOD FOR SECURING A PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations.
|TAMPER RESISTANT FUSE DESIGN - A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
|PASSIVE RESISTIVE-HEATER ADDRESSING NETWORK - There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.
|PROGRAMMABLE EFUSE AND SENSE CIRCUIT - A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.
|ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS - The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
|STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
|FUSE LINK SYSTEM FOR DISPOSABLE COMPONENT - A fuse system for use with a disposable component of a device may include a disposable component having at least a first lockout circuit and a second lockout circuit. The first lockout circuit may include a first fuse link, and the second lockout circuit may include a second fuse link. The fuse system may include a computing device in communication with the first lockout circuit and the second lockout circuit, and a computer-readable storage medium in communication with the computing device. The computer-readable storage medium may include one or more programming instructions for deactivating the first fuse link at a first time, and deactivating the second fuse link at a second time.
|Capacitive Discharge Fuse Programming Apparatus and Method - An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.
|APPARATUS AND METHOD FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE - An apparatus for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
|Trim Circuit for Power Supply Controller - A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection.
|ELECTRIC FUSE CUTOFF CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit.
|SEMICONDUCTOR DEVICE - A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
|ZERO PIN SERIAL INTERFACE - A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode. The circuit is set to permanently provide the output performance when the output performance is within a desired tolerance of the desired performance characteristic.
|Electrical fuse devices and methods of operating the same - Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse, and a driving element connected to the fuse and including a resistance change layer having a resistance that changes according to an applied voltage. The resistance change layer may have a metal-insulator transition (MIT) characteristic. As the driving element is turned on, a programming current may be applied to the fuse connected to the driving element.
|SEMICONDUCTOR DEVICE - A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
|Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Fuses - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias ('TSVs'), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias ('PTVs'), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
|ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a first fuse unit including a first anti-fuse which is determined to be short-circuited if the first anti-fuse in a programmed state and determined not to be short-circuited if the first anti-fuse in a non-programmed state, and configured to generate an output signal according to a state of the anti-fuse and a restoration signal; and a second fuse unit including a second anti-fuse, and configured to activate the restoration signal when the second anti-fuse is in the programmed state in case where the first anti-fuse is in the programmed state.
|SEMICONDUCTOR SYSTEM - A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
|ELECTRONIC TRIMMING CIRCUIT - The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.
|SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal.
|BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.
|Circuit for Adjusting Reference Voltage Using Fuse Trimming - A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected. The output terminal is located at the nodes of the third resistor set and the first loading resistor so that the trimming steps provided by the third resistor set and the fourth resistor set are opposite to that of the first resistor set and the second resistor set.
|METHOD FOR AUTOMATICALLY ADJUSTING ELECTRICAL FUSE PROGRAMMING VOLTAGE - The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming.
|Electric fuse determination circuit and determination method - An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.
|APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE - Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.
|ANTI-FUSE CONTROL CIRCUIT - An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated.
|DEVICE PROVIDING TRIM VALUES - Devices comprising trimmable electric units and methods for providing trim values to electric units are presented herein. One such device comprises a trimmable electric unit, at least one fuse to provide at least one first trim value, and a trim value provision unit to provide at least one second trim value, and a register. The register, which is connected to the electric unit, the at least one fuse, and the trim value provision unit, selectively stores the first and/or the second trim values and provides them to the electric unit. Optionally, a third trim value may be used. In the case of integrated circuits, provision of the trim values allows for on-chip debugging without waiting for creation of a test program used by automatic testing equipment at the wafer probe stage.
|CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER - A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor ("fuse/anti-fuse transistor"). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication.
|FUSE CIRCUIT - A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.
|FUSE CIRCUITS - A fuse circuit includes a fuse having an intact state and a blown state. The fuse can be switched to the blown state by enabling a blowing current to flow through the fuse. The fuse is coupled between a first transistor and a second transistor in series. The first transistor and the second transistor are complementary transistors and operable for reducing an electrostatic discharge current flowing through the fuse. The first transistor and the second transistor are turned on to enable the blowing current to flow through the fuse.
|Fuse circuit and semiconductor device including the same - A fuse circuit may include a fuse section which generates a fuse control signal at an output terminal of the fuse circuit in response to a power-up signal according to a status of a fuse in the fuse section; and a current path break section which detects the status of the fuse in the fuse section prior to a trip period of the power-up signal and breaks an inrush current path created in the fuse section during the trip period based on the detected status.
|FUSE CIRCUIT FOR SEMICONDUCTOR DEVICE - A fuse circuit of a semiconductor device includes a transfer unit configured to selectively transfer a corresponding address signal in response to a first test mode signal, a fuse control unit configured to drive an output end with a first voltage in response to an output signal of the transfer unit, a fuse unit including a MOS transistor having a gate coupled to the output end, and a fuse enable unit configured to selectively supply a second voltage to a source/drain of the MOS transistor of the fuse unit in response to the first test mode signal, wherein the fuse circuit is programmed by causing a breakdown of the MOS transistor in response to a voltage difference between the first voltage and the second voltage that are applied to the gate and the source/drain of the MOS transistor of the fuse unit.
|ELECTRIC FUSE CIRCUIT AND METHOD OF OPERATING THE SAME - A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
|TAMPER RESISTANT ELECTRONIC SYSTEM UTILIZING ACCEPTABLE TAMPER THRESHOLD COUNT - A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.
|TRIMMER CIRCUIT AND METHOD - A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one.
|Method and apparatus for protection of an anti-fuse element in a high-voltage integrated circuit - A soft clamp semiconductor device for preventing inadvertent programming of an unselected anti-fuse (AF) element comprises a MOSFET which includes a first well region disposed in a substrate. Source and drain regions are disposed in the first well region, the drain region being electrically coupled to the first capacitive plate of the AF element and the source region being electrically coupled to a second capacitive plate of the AF element. An insulated gate is disposed over a channel area of the first well region that separates the drain and source regions. A gate capacitance of the MOSFET is substantially less than a capacitance of the unselected AF element such that when a programming voltage is applied to the first capacitive plate, a current flows through the MOSFET that charges the second capacitive plate, thereby reducing a voltage build-up across the unselected AF element.
|TRIMMING CIRCUIT AND METHOD FOR DRIVING TRIMMING CIRCUIT - A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.
|FUSE DETECTING APPARATUS - A fuse detecting apparatus including a detector, a calibrator and a logical operating unit is disclosed. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to a first and a second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and the second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal.
Patent applications in class Fusible link or intentional destruct circuit


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Personalized plates primer
The special-plates program turned 40 this year
QUESTION: I just bought my husband a new motorcycle and I want to personalize its license plate. Because he served in Iraq, I want to get the "memorial" special interest plate. How do I go about requesting a personalized plate and do the proceeds go to a special cause?
ANSWER: Did you know the Personalized License Plate Program just turned 40 this year? Additional fees are required for acquiring these types of plates, a portion of which goes toward whichever program the selected plate commemorates, such as Arts, Kids, Coastal, Lake Tahoe, and, of course, supporting veteran's organizations. A portion of the fee also goes toward fighting pollution caused by motor vehicles. To date, the California specialty plate program has generated approximately $630 million for these specialty groups.
To purchase your personalized plates go to this DMV site: http://www.dmv.ca.gov/ipp2/welcome.do. You'll be able to browse the DMV's selection of personalized and special interest license plates. In a separate window, you will also have the ability to see what your specialized configuration will look like or if it already exists.
What are the rules for bicyclists? I'm from New York and just moved to California for college, and plan on using a bicycle as a primary mode of transportation.
Welcome to the Golden State! First off, be sure to protect yourself with a helmet. It is not mandatory for those over 18 years of age, but is highly encouraged.
Here are some safety tips:
• You must obey traffic signs and signals
• Ride in the same direction as traffic so you are more visible to drivers
• Stay in the right lane unless the right lane is too narrow then take the center traffic lane
• To make left turns you may use the crosswalk and cross as pedestrians cross or you can change lanes when safe to do so
• Beware of parked cars- stay far enough away to avoid being hit by an opening door
• Communicate your intentions
For more information about bicycle laws and safety, go here: http://www.dmv.ca.gov/pubs/brochures/fast_facts/ffdl37.htm
While I'm driving, I see more and more motorcycles "lane splitting" between cars, as if they (the motorcyclists) are making an individual lane to travel in. The motorcyclists even use the bike lane as a passing lane. Why are they allowed to maneuver in and out of traffic like that?
California does not have a law prohibiting this maneuver. Motorcyclists believe that lane sharing is safe and provides them an added "safety net" when confronted with a possible collision, by weaving between two vehicles. Motorcyclists can be cited for traffic violations for making unsafe maneuvers when lane sharing such as improper lane change, unsafe speed, or passing in a bike lane. Motorcyclists should use caution and maintain safe riding practices when lane sharing.
QUESTION; I'm a teen driver who recently acquired a learner's permit after passing the written test. My driving instructor told me that my permit had been "activated" after I took a two-hour lesson with him, and that now, I can drive if my parents are in the vehicle with me. My question is: can anyone else accompany me?


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Shree Karpaga Vinayakar TextileErode, Tamil Nadu
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Shree Karpaga Vinayakar Textile Incepted in the year 2002, engaged in manufacturing, supplying and exporting all kind of cotton, Linen, Lycra, Organic cotton fabric, Bamboo fabric, fashion garments, yarn dyed fabric, printed fabric, double cloth fabric and polyesters fabrics of optimum quality. We started as manufacturer of yarn dyed fabric but today we are touching the sky in the field of fabrics. We are well equipped with our own dyeing factory, weaving center and ...
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Contact UsShree Karpaga Vinayakar Textile Thanmozhi Yuvarajan+91-9894325522
No. 37, Marappa, 1st Street, Surampatti, Erode - 638009, Tamil Nadu, India
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