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Winter Storm Pounds Minnesota Again
(AP) A powerful late winter storm has closed schools for a second day in Duluth. Superintendent Bill Gronseth says some city roads remain in poor condition due to blizzard-like conditions that socked the area on Leap Day. The storm caused widespread closures on Wednesday. Thousands of customers lost power when high winds snapped power lines. Firefighters were called to West Duluth to help get people out of a stalled elevator because of a power outage. Wind gusts measured up to 65 mph on the Blatnik Bridge in Duluth. A gale warning was posted at Lake Superior where huge waves pummeled the Duluth shoreline.
Police Chief Arrested
(AP) The Ho-Chunk Nation's police chief has resigned following his arrest on possible obstruction charges. Dan Libke was placed on administrative leave following a Feb. 24 arrest at his home. Officials have not disclosed the reason for possible obstruction and no charges have been filed. Libke was sworn in as the band's first police chief in September 2010. The Jackson County district attorney is reviewing the case.
Redistricting Problems Even Worse This Year in Wisconsin Says Group
The legislative redistricting process in Wisconsin was bound to get a little contentious. Democrats were locked out of the process of redrawing political boundaries in the state completely during this last go 'round. The republican-controlled approach led to a federal court battle. There's a better way, says Jay Heck from Wisconsin Common Cause. Like in Iowa, where political districts are drawn up every ten years by a nonpartisan board
The groups who filed lawsuits regarding new redistricting maps claim they were done in such a way as to especially limit voting influence of blacks and latinos in the state.
Second Big Drug Bust in Stretch of Four Days for La Crosse Police
The second big drug bust for La Crosse cops in a matter of days. On Friday it was a married couple selling pot out of their southside trailer. Yesterday it was a couple guys selling crack and marijuana on the streets of La Crosse. Police used a sting operation to nab Jamario McKnight, who admitted to coming to La Crosse from Chicago to sell drugs because he'd heard there's good money to be made in La Crosse. Apparently so; they found a couple thousand dollars on him. Shane Tucker was also arrested in the bust. He's currently out on bond for dealing drugs. Meanwhile Jeremy and Jennifer Jenkins could face hard time for dealing pot after the Friday bust. A crimestoppers tip led to that arrest.
City Panel Agrees to Second Delay in Garbage Rules
Last June, when the La Crosse public works board started work on refining the city's garbage rules, they hoped to have the new rules in place by the time college students evacuated the city this May. Now the board has put that deadline in doubt by agreeing to a second month-long delay on the rules as critics complain about the scope of the new regulations.
Public works director, Dale Hexom. Among the biggest complaints from landlords on the new rules are ones that involve limiting big item pick-up and increasing the requirements for using dumpsters at rentals.


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Made To Worship
Chris Tomlin
Join the FISH LISTENER CLUB to stay up to date on concerts, contests, events, discounts, and music news!!
Enjoy special offers from businesses you can trust!
Free concert featuring Wayne Watson and Susan Ashton on November 22!
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subset: commoncrawl


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Recent Stories »
OAK RIDGE, Tenn. — Rhea County jumped way ahead and held off Oak Ridge, 35-21, in a quarterfinal battle of Class 5A unbeatens Friday night.
OAK RIDGE, Tenn. — With Oak Ridge High School's offense stalled, its defense rose to the occasion Friday night against Cleveland.
A Blountville, Tenn., man previously convicted of sexual battery faces new charges in southwest Virginia, where he allegedly penetrated a dog with a mixer attachment — inflicting injuries that required surgery — and left behind DNA evidence.
KNOXVILLE — A Maryville man was charged with rape over the weekend when the victim realized after a drunken sexual encounter that the man was not her husband, authorities said.
The Appalachian Trail Conservancy has a new plan for managing the Appalachian Trail over the next five years.
OAK RIDGE, Tenn. — The final score belied the magnitude of the struggle Friday night on Blankenship Field.
KNOXVILLE — Federal authorities on Wednesday unsealed a plea agreement with a Knox County Sheriff's Office deputy who confessed he and at least five other local law enforcement officers were providing protection for an illegal gambling ring.
Tennesseans apparently ratified all four amendments to the state constitution Tuesday, including the controversial Amendment 1 giving the state Legislature power to restrict abortion and, if Roe v. Wade is ever overturned at the national level, to ban abortions in the state.
A North Carolina traveling salesman was arrested early Monday morning in Alcoa and charged with impersonating a doctor after he allegedly tried to examine a woman who was interviewing to be his personal assistant, authorities said.
A Winter Storm Watch is in effect for portions of the region for Friday night into Saturday with up to 14 inches of snow possible at the highest elevations of East Tennessee's mountains.


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Simon Gagne still gets an occasional shift on the top line, but he's mostly fit in as a fourth liner on the Bruins.
There's no telling how long his audition might be, but it appears as if Simon Gagne will start Saturday's Boston Bruins - Buffalo Sabres game on the David Krejci - Milan Lucic line.
Simon Gagne made his regular season debut in a Boston uniform Wednesday night and it just happened to be the 800th game of his career.
Simon Gagne is expected to serve on the Bruins' fourth line for now.
Simon Gagne has inked a one-year, $600,000 contract with the Boston Bruins.
After Saturday's loss to Washington, Bruins coach Claude Julien hinted that their could be some changes coming to Boston's lineup.
Simon Gagne will stick with the Boston Bruins despite being unsigned.
Simon Gagne hasn't been released from his professional tryout with the Bruins yet.
It's looking more and more likely that Simon Gagne will be signed by the Bruins.
It doesn't sound like training camp tryout Simon Gagne will be sticking with the Bruins, but a final decision hasn't been made yet.
Simon Gagne said he felt much better in his second preseason game.
Boston coach Claude Julien feels that training camp tryouts Simon Gagne and Ville Leino have legitimate shots at roster spots.
According to Renaud Lavoie of TVA Sports and Journal de Montreal, Simon Gagne will attend Boston's training camp on a tryout basis.
Simon Gagne is still looking to play in the NHL.


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Town Square
Dr. Noize Live, Electronic Music & More! at CSMA - Sunday, Oct. 18
Original post made by CSMA, another community, on Sep 9, 2009
Two shows, at 2 & 4 pm. Part of CSMA's Family Concert series, supported by Target.
Limited, open seating (approx. 200) available on a first-come, first-served basis. Limited on-site and street parking. Arrive early!
Community School of Music and Arts at Finn Center is located at 230 San Antonio Circle, Mountain View, CA 94040.
650-917-6800 | firstname.lastname@example.com | www.arts4all.org/attend
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XVintage: 2011
Bottle $56.94
12 bottle $56.44
Rated 89-91 - Here too there is a mild application of wood on the otherwise very fresh and cool red pinot fruit and soft earth suffused nose. There is an attractive sense of energy to the nicely detailed...
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Rated 89-91 - This is riper and more deeply pitched with notes of black cherry, raspberry and earth. There is a generous aspect to the supple, rich and very round medium-bodied flavors that display a touch...
Bottle $115.94
12 bottle $115.44
Rated 90-92 - This is notably more refined aromatically than the Beaux Bruns with a pure and relatively high-toned nose composed primarily of various red berries with hints of plum and violets. There is...
Bottle $91.64
12 bottle $91.04
Rated 88-91 - A background application of wood surrounds the aromas of white peach, pear and resin. There is also enough oak to notice on the rich, powerful and well-concentrated medium weight plus flavors...
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Rated 90-93 - Good bright, deep red. Cherry, rose petal, mocha and game on the nose, plus a hint of metallic minerality. Dense, sappy and youthfully tight; less expansive today than the Echezeaux and...
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Rated 92-94 - Good full medium red. High-pitched aromas of raspberry, crushed stone, white pepper, blood orange and flowers. Tight today and folded in on itself, with some excess CO2 currently suppressing...
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Rated 91 - Bright medium red. Pungent, high-pitched scents of raspberry, blood orange and menthol, plus a touch of new oak. Subtly intense red berry flavors are accented by pepper and herbs. Round in...
Bottle $81.64
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Rated 89-91 - With the first three Nuits 1ers (Vignerondes, Chaignots and Les Damodes) we were on the Vosne side but now with Pruliers we're in the heart of the appellation and it shows because while there...
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Rated 89-91 - A generously wooded nose fights with the ripe mélange of red and black cherry aromas that precede the supple, round and almost easy flavors yet there is good energy on the much more tightly...
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Rated 93 - A beauty, offering sweet raspberry, strawberry and floral aromas and flavors allied to a medium-bodied frame. Light-footed and detailed, with a lingering finish of mineral-lined fruit. Drink...
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Thanksgiving Sunday is
November 23rd
St. Simons United Methodist will host the Community Service at 4:00pm, with a Reception after in the Thorpe Building. Please join us!
*If you would like to help with a donation of an appetizer or dessert, please contact the church office today!
You're Invited!
You are invited to share Thanksgiving Dinner with
Rev. Marcia Cochran on Thursday, November 27 in the Thorpe Building. Turkey and dressing will be provided, just bring a covered dish (salad, vegetable or dessert) to share. Dinner will be served at 12:00 noon. Please RSVP to the church office to let us know you are coming, 638-3317 or click on the link below.
Click here to sign up to attend Thanksgiving Dinner at church
St Simons United Methodist
The Coming of the Messiah
upcoming church events
Wednesday, December 3, 2014
Outdoor "Chrismon" Tree Lighting
5:30pm-Look for the tree adjacent to the playground!
Refreshments will be served after the lighting.
Come join us as we light this resplendent display!
Wednesday, December 10th
6:00pm in the Sanctuary
The Children's Choir presents
A reception will follow in the Thorpe Building.
Bring a side to share, RSVP to the church office if you would like to join us!
Volunteer opportunity on the first Thursday of each month. Please contact Joey Baldwin or the church office if you can help!
Next serving opportunity:
December 4th


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Fun! Baby Name Polls
Hone your baby naming skills and help others. Which baby names are best?
Show polls from: today | last seven days | last four weeks | all
Sort by: most recent | most comments | most votes
Which one of these names would best for a girl?
Allison Joy if my baby is a girl...Yes or No?
I'm looking for any suggestions on a baby girl name that would go with the middle name Ashley.
Any middle name ideas? Thank you, Karen.
Which name do you like? Any other suggestions to go with Angela?
Which boys name do you like best? Comments welcome!
Well, it looks like Camilla wasn't very popular, and Camille Joy doesn't flow as well, so I am still stuck for a name if my baby is a girl. The baby is due any day now and we want a delivery surprise. Owen Michael is the boy name we have and the girl name must have Joy, Leigh, or Lynne as the middle name. Any suggestions? Thanks!
Looking for first name ideas to go with the middle name Matthew. One idea we are tossing around is Tyler........
Spelling suggestions on this name set....... any first name spelling could be paired with any middle name spelling....or any other ideas
Ashton. Love it. For a girl. It's unisex, right? I've seen it as a boy name, and so I was wondering if it's EVER a girl name. I like it best as a middle name though. Like: Sydnee Ashton.... -------- ~thanks
What do you think of the name Blair for a girl?
we can't decide, we have 3 daughters Kimberly Ann 12, Rachel Madison 9, and Alexandra May 5
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Having trouble choosing between two or three baby names? Maybe its time for an outside opinion.
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Its super easy and fun!


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Online dating brings singles together who may never otherwise meet. It's a big world and the SeniorPeopleMeet.com community wants to help you connect with singles in your area. Whether you are seeking just a date, a pen pal, a casual or a serious relationship, you can meet singles in Kissimmee today! Florida is known as "Sunshine State" and SeniorPeopleMeet.com is here to bring their Senior Singles together.Search Single Senior Men in Kissimmee | Search Single Senior Women in Kissimmee
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The issues and attitudes that the immigration and racial conflicts have in common certainly make for odd timing.
In Oakland, leaders of this left-of-center, one-party town are dabbling with the capitalistic concept of "supply and demand."
Knowing the complicated truths of our racial history would help to eliminate race-baiting. If people see it doesn't work, they'll stop.
Beware Ebola solons who act without doubt. Isn't the more admirable person one who makes respect for fellow citizens the top priority?
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A 16-year-old runner has died after she completed a half-marathon in Virginia Beach.
Virginia Emergency Medical Services chief Ed Brazle tells media outlets that the 16-year-old girl was from the Richmond area.
Brazle says the teenager went to a first aid tent after finishing the Shamrock Half-Marathon on Sunday. She fell unconscious and was taken to a hospital, where she died.
Her name hasn't been released. No other details were immediately available.
Teen dies after completing half-marathon in Virginia
A 16-year-old runner has died after she completed a half-marathon in Virginia Beach.
Copyright © 2014 by WCYB. The Associated Press contributed to this report. All rights reserved. This material may not be published, broadcast, rewritten or redistributed.
Around The Watercooler
- Man stung more than 100 times by swarm of bees
- Strangers lift car to save woman's life
- Tenn. man hit with $3,000 Comcast bill
- Cops: Drunk N.J. man stole bulldozer for ride home
- Americans accused of trying to ship baby parts ID'd
- TV host wore same outfit for a year; no one noticed
- Marijuana-themed sandwich shop opens
- Maine teen charged with naked break-ins
- Declared dead, woman wakes up in funeral home


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417 Third Avenue Albany, Georgia 31701(229) 312-1000
2000 Palmyra Rd. Albany, Georgia 31701(229) 434-2000
126 Hwy. 280 West Americus, Georgia 31719(229) 924-6011
807 S. Isabella St. Sylvester, Georgia 31791(229) 776-6961
361 Randolph St. Cuthbert, Georgia 39840(229) 732-2181
Most sports injuries are the result of inadequate training in certain sports, structural defects in the body, and weaknesses in the body. Many people who start exercising after being sedentary sustain a sports injury. However, with the proper precautions, sports injuries can often be prevented.
The following are some basic steps to prevent a sports injury:
Warm up properly before any physical activity.
Alternate exercising different muscle groups and exercise every other day.
Cool down properly after exercise or sports.
Stretching exercises can improve the ability of muscles to contract and perform, reducing the risk for injury.
Shoe support may correct certain foot problems that can lead to injury.
If you do sustain a sports injury, make sure you participate in adequate rehabilitation before resuming strenuous activity.
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Properties in Worcester, Worcestershire between £30,000 and £2,000,000
Properties in Worcester, Worcestershire
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£36,000 Sold STC 2 Bedrooms Randwick Drive, Worcester
RESIDENTIAL SALES - DISCLAIMER NOTICE: Appliances such as radiators, heaters, boilers, fixtures or utilities (gas, water, electricity) which may have been mentioned in these details have not been tested and no guarantee can
The Property Centre - Worcester
£40,000 1 Bedroom Lot 1 20a Middle Street
WELL MAINTAINED SECOND FLOOR PROPERTY JUST OFF CITY CENTRE, WALKING DISTANCE OF LOCAL AMENITIES, PLEASANT CITY VIEWS, WITH PARKING TO THE REAR. Fitted Kitchen/Diner, Bedroom/Sitting Room, Bathroom, Double Glazing, Electric Heating, Rental Potential
Griffiths & Charles
£50,000 1 Bedroom Middle Street, Arboretum, Worcester
For Sale by Auction on Wednesday, 10th December 2014 at the Whitehouse Hotel, Foregate Street, Worcester WR1 1EA. Starting at 6.00pm. A Buyer's Premium is payable of £2,000 plus VAT (£2,400). To be paid on a sale before, during or after the Auction. EP
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cyclophosphamideSyllabification: cy·clo·phos·pha·mide
Pronunciation: /ˌsīklōˈfäsfəmīd /
Definition of cyclophosphamide in English:
A synthetic cytotoxic drug used in treating leukemia and lymphoma and as an immunosuppressive agent.
Example sentences
- A combination of two immunosuppressive drugs, cyclophosphamide and fludarabine, was given with the intent to knock out the patient's immune system to allow the foreign donor immune cells to take hold.
- The patient was treated with cyclophosphamide, doxorubicin, vincristine, and prednisone chemotherapy starting in August 1998.
- Adjuvant therapy, multidrug chemotherapy was carried out with methotrexate, cyclophosphamide, doxorubicin, vincristine, and prednisone.
Definition of cyclophosphamide in:
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Word of the day Sprachgefühl
Pronunciation: ˈʃprɑːxɡəˌfuːl
intuitive understanding of a language's natural idiom…


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If you're not paying attention at Royal Purple Raceway, you might miss the race. That's because the venue features a quarter-mile drag strip where racers accelerate from 0 to 300 mph in four seconds. Built in 1988, the straightaway now attracts national NHRA drag races and shares the spotlight with a newer quarter-mile dirt track. Although the raceway attracts national events, including the annual Super Chevy auto show, its owners and operators, the Angel family, hail from Texas and instinctively support and preserve the local culture.
A nationally renowned tutoring program, Sylvan Learning utilizes a personalized tutoring approach to develop students of all ages and abilities into perceptive pupils. During the initial visit, children will partake in a Sylvan Skills Assessment that reveals areas a child may need help in and serves as a base line for future progress. An erudite educator then leads four one-hour tutoring sessions tailored to young minds' particular needs, covering subjects that include math, reading, writing, and the ethics of alligator wrestling. Polymaths looking to increase their potential can use their customized tutoring sessions to prepare for future algebra tests or fine-tune study skills to get a head start on memorizing next year's phone book. Sylvan Learning gifts proud progenitors with regular progress reports granting comprehensive summaries of their offspring's progress. All six Sylvan Learning Centers are open Monday–Saturday, with hours in the morning and afternoon to accommodate busy estival schedules.
At each of its 31 area locations, the YMCA of Greater Houston pursues a mission to bring health, wellness, and personal growth to communities. Kids leap into activities ranging from swim lessons and youth sports to a teen Youth & Government program that stirs up confidence and leadership abilities in students, preparing them for mudslinging student-council campaigns.
Zumba, ballroom dance, and Les Mills group exercise classes shake up adult workout routines, as complimentary childcare frees up parents to pursue fitness goals. Meanwhile, adult sport leagues such as basketball and racquetball result in friendly competition and hyper-literate team names inspired by obscure philosophers.
A driver curls his fingers around the steering wheel, takes a deep breath, and places his foot onto the peddle, bringing a mechanical beast to life. The screech of burning rubber, roar of an 500-horsepower engine, and the silent rush of adrenaline block out the rest of the world, allowing the driver to focus entirely on the run. As he battles the g-force, the realization hits that he has just achieved a lifelong dream: He is a drag racer.
Doug Foley first noticed the lack of a comprehensive drag-racing training center in 1997, and he took it upon himself to fill the void. Along with a team of instructors, Foley lets novices ride shotgun or drive themselves to taste drag racing for the first time. Once the new racers are hooked, a lineup of beginner to advanced classes licenses students for everything from junior dragsters, to door cars and A-fueled dragsters. Through these efforts, Foley and his team ready drivers to compete in professional races and fulfill a dream.
Studio Fit grooves clients toward fitness goals with Zumba, an invigorating, Latin-inspired dance workout. Led by certified fitness professional Marcy Jo Taylor, Studio Fit's Zumba burns calories while pleasing the dance-inexperienced with simple, easy-to-follow moves. Zumba borrows strengthening and body-leaning moves from the likes of salsa, meringue, samba, tango, and other dance styles, targeting every major muscle group for a peerless cardio workout.
Welcome to Snap Fitness! Your local fitness center where we show each member personalized attention in meeting their fitness goals no matter what your fitness level. We're open 24 hours, 7 days a week, so you can work out when it's convenient for you. Did you know that when you join Snap Fitness, you belong to all the Snap


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Town Square
Voices Around Town
Original post made on Nov 19, 2011
Read the full story here Web Link posted Friday, November 18, 2011, 12:00 AM
Comments (1)
a resident of Sylvan Park
on Nov 19, 2011 at 7:00 pm
The road in and out of down town are designed terrible. You have a big circle at an intersection that make new drivers to the area confused. It also blinds the drivers from seeing people and cars cause there is a planter in the middle of the road. The cal train side is like a race into Castrol. Light turns green and you need to beat the other drivers or get stuck at another light cycle. Heavens forbid a train comes by, it's another 5 min cause the north trains activate it twice! Crosswalks in the middle of the road?, nice idea but the parked cars and trees make people appear as if they jumped out from between the cars. Let not excuse the people either, yapping on phones or emailing as they walk into the street.
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Grab a Bowl of Heaven soon in Mountain View
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Quick Check List for UC Applications
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A free dance training camp for children, men and women is being organized by Shailashree Manjunath Fine Arts and Education Society, Hubballi. Folk, film, Western and other dance styles will be taught. Call 7259990404/ 7795556883.
Shivashakti Kala Kendra will organize Odissi dance performance by Urmila Patra and bharatnatyam by Ratnamanjari Patra on November 16 at Kannada Bhavan. Guru Sanman will be offered to Sujata Rajgopal, Rohini Imarati, Pramoda Upadhyay, Sahana Bhat, Hema Wagmode, Vanita Mahale, Prerana Shindhe, Seema Upadhyay and Laxmi Okade on the occasion. Union leader and social worker Dr K S Sharma and president of Gangubai Hangal Music Foundation Manoj Hangal will be present.
Additional Chief Secretary Upma Chaudhary said that Kathak Kendra Repertory and Dipti Omchery Bhalla will perform on October 16 while Bindu Juneja and Preeti Patel will perform on October 17. Lakshmi Parthasarathy Athreya and Kiran Sehgal will perform on October 18 while Dr Sonal Maan Singh will perform on the last day of the festival on October 19.
All arrangements have been made for four day dance festival being organized by Sangeet Natak Academy, New Delhi in collaboration with Art, Culture and Language Department, Himachal Pradesh at Gaiety Theatre Shimla from October 16 to 19.
The next edition of the popular series of discussion and dialogue on dance, Dance DISCourse, will be held on September 29, 2014 at 6:30 pm at Alliance Française de Bangalore at Vasanthnagar. The focus of the event will be on the classical dance, Odissi. Dancers from Bengaluru's leading dance schools, Sanjali, Nrityantar and ARPAN, will bring alive the elegance & splendour of Odissi dance in a delightful visual treat.
This is the sixth consecutive year of this dance extravaganza. Parikramaa is a dance festival which brings together the veteran dancers and musicians of today and tomorrow.
Parikramaa, a mega fest of classical dance is being organized by Kalavardhini Charitable Trust in the city between September 19 and and 21, said a statement released by the trust.
The Lourd Vijay's Dance studio (LVDS) Junior Team from Bangalore grabbed four silver medals at the recently concluded Dance World Cup held in Portugal. The team had participated in four out of the 6 categories in which the competition was held. The LVDS junior team also won the silver and the bronze at the Dance World Cup in Brighton, England last year.
Yoganjali Natyalayam will celebrate its 21st anniversary and Ananda Ashram will celebrate the 46th anniversary will celebrate its 46th founding day by holding a festival of yoga, dance and music at 2pm on July 20 at Sri Subalakshmi Thirumananilayam.
A member of High Court Bar Association Indore Vishal Sanothiya complaint with inspector general of police about a reported striptease and nude dance organised by a popular tyre country at upmarket hotel of the city for its dealers.
Nrityantar which organises Bengaluru's very own and hugely popular annual dance festival Naman is in its 5th year now, exclusively dedicated to Odissi dance, will have its new initiative, Abhivadan highlighting the beauty and richness of various classical dance forms of India, with performances by established and talented upcoming exponents in the field will hold the first edition June 22 , at Seva Sadan Auditorium, Malleswaram at 5:30pm .
A day-long dance festival to celebrate World Dance Day will be held at Alliance Française, Vasanthnagar here, in association with Bangalore School of Music and Funky Guru. It is biggest ever day-long dance gathering in Bengaluru of dancers, gurus, teachers, connoisseurs, aspirants and art lovers scheduled on on Sunday, April 27.
The 114th dance festival of Sri Parthasarathy Swami Sabha will be concluded on Monday at Narada Gana Sabha Hall. The music programme is being conducted by P Vijayakumar Reddy and Preetha Reddy in memory of P Obul Reddy and P Gnanamba. Dr Nalli Kuppuswami Chetti, Meenakshi Chitharanjan will be present in the event.
Madras high court says no for village and mofussil temples'' pleas for cultural programmes such as dance. Justice V Ramsubramanian dismissed a big batch of petitons saying there is no devotion or devotees behind such vulgar shows.
Madras high court refuses to permit a Chennai hotel to have dance shows under the garb of ''cultural dance programme''. Justice V Ramasubramanian says police have curative as well as preventive duties.


text: In Pictures: 20 infamous hacker security vendor break-ins Here are 20 of the most notorious known break-ins over the past decade. Ellen Messmer (Network World) 0 - - - - print email prev next Loading... Back in 2004, a hacker managed to break into Microsoft's corporate network and stole the source code for Windows 2000, about 600 million bytes of data, posting it online. The hacker was never caught. Prev Next 2/18 Comments on this image There are currently no comments for this image. Comments are now closed. Close In Pictures: 20 infamous hacker security vendor break-ins 18 images


text: POPSUGAR Moms Kidmazing Video: Dancing Brazilian Baby Kidmazing: Brazilian Baby Knows How to Shake, Shake It! by Moms 6/17/10 4 Reactions 86 Shares Print 0 86 0 0 0 Your tot may dance, but this Brazilian baby can almost shake, shake, shake his diaper off! The babe takes his amazing moves onto the table top with hips swirls that could make Shakira dizzy. The wee one gets quite the workout and for obvious reasons, the video has become very viral! 0 86 0 0 0 Read More KidmazingBabiesDancingVideos Stay sane and savvy with our daily newsletter Enjoy expert advice, time-saving tricks, kid-friendly food and fun in your inbox. Sign up with sham28 4 years :) J/K sham28 4 years :) J/K sham28 4 years It's cute, definitely--these clips always freak me out a little bit, kids that young aren't supposed to have the control of motor skills that he does.... devil baby skigurl 4 years This is hilarious. It looked photoshopped at first. That's one big kid. Link Love How to be a grateful mom this Thanksgiving — BabyCenter Blog Drew Barrymore gets sentimental on Instagram — Celebrity Baby Scoop The latest (and cheapest) alternative to IVF — FitPregnancy Eva Mendes opens up about being a new mom — People Moms & Babies This baby and sloth make the most precious pair — The Bump Quick and easy holiday chores for children — Real Simple What happens when children do their mom's makeup — HuffPost Parents


text:
Sam Mendes
Jake Gyllenhaal
Peter Sarsgaard
Jamie Foxx
Printer-Friendly version
JARHEAD is a truthful, thought-provoking film (I wouldn�t expect anything less from Sam Mendes)�but if you�ve seen other war movies, you�ve pretty much seen this one too, as it does its fair share of cinematic borrowing. The plot of restless soldiers during Desert Storm was addressed in THREE KINGS (although the tone and plot couldn�t be more different); the arduous mental effects of war�THE DEER HUNTER; the boot camp instructor�FULL METAL JACKET; heck, the soldiers even watch APOCALYPSE NOW and sing along to "The Ride of the Valkyries". While the references could be viewed as tongue in cheek, the film really doesn�t do much to set itself apart from any other flicks in the genre�war is hell, both on and off the field of combat. We know this.
Jake Gyllenhaal is in just about every frame of JARHEAD and he gives a fantastic performance that drives home the emotional center of the movie. There�s also an impressive supporting cast, whose characters really deserved more face time. I almost forgot Peter Sarsgaard was even in the film until halfway through, which sucks because his character is pretty important. Likewise, Jamie Foxx starts out strong as Gyllenhaal�s CO, but isn�t given much to do afterwards. Chris Cooper and Dennis �I Own You� Haysbert are also in the movie for about 30 seconds apiece.
So, as a whole I enjoyed JARHEAD and appreciated its realistic portrayal of modern warfare�soldiers losing their mind while waiting around for something to happen�but that doesn�t necessarily make for the most �ber-exciting movie.
Commentary by director Sam Mendes: �I�m now going to bore you stupid with observations about this movie�� Maybe it�s his British accent or his humorous honesty about the film�s production, but I certainly wasn�t bored with this commentary. (Apparently there was a lot of improvisation due to the actor�s being deep in character, which led to some conflict on set.) I have a lot of respect for Mendes�even if this isn�t his best movie; he still has a fresh, inventive eye as a filmmaker and his comments here confirm that.
Commentary by writer William Broyles and author Anthony Swofford: A lot has been made about Swofford�s original autobiographical novel and the accuracy of his story. While he does talk some about the writing process (a lot of the book is based on stories he heard from other marines and some of the characters are composites of different people), he spends most of his time speaking about the marine life and the realities of combat, which I found really fascinating. If you�re at all interested in the military, you�d probably enjoy this track.
Deleted Scenes (19:08): Eleven cut and extended scenes. Most were just more of the same and rightfully excised, although there is a terrific alternate opening with a hilarious cameo by Sam Rockwell that 100% should�ve been left in. Each scene is available with director and editor commentary.
Swoff�s Fantasies (6:10): A few deleted extracts that show Gyllenhaal�s character daydreaming about doing crazy things to his superiors. The movie does run a bit long, but I don�t see the problem with leaving these in, as there�s actually only a few seconds of extra footage. They�re pretty funny (especially the boot camp instructor in a dress) and they further show Swofford�s mental deterioration.
News Interviews in Full (16:37): The complete uncut compilation of interview footage. While it�s nice to see it here, and it shows each actor�s committal to their character, the quicker montage that�s in the movie is a lot more effective.
Here is where I would usually point out the lesser extras like trailers and galleries, but this disc surprisingly had none (which blows because JARHEAD had an awesome trailer). So you can just ignore these last two sentences.
And a quick shout out to someone over there in the suck right now�LCPL Marc St. Pierre, the only dude man-enough to wield a .50 caliber machine gun, get wasted, and go rock out to an episode of Full House, all without missing a beat. Oohrah, bro!


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text:
A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.
1. A method comprising:
retrieving a packed floating-point operand for a register file entry;
copying significand, exponent and sign bits from each operand of the packed floating point operands to the register file entry;
testing exponent bits of each of the floating-point operands; and
for each operand, setting a bit associated with the register file entry responsive to a state of the exponent bits of the operand.
2. The method of claim 1, wherein testing exponent bits of each floating point operand includes determining from the exponent bits whether the floating point operand is denormal or zero.
3. The method of claim 2, wherein testing the exponent bits of the floating point operand comprises
determining whether each of the exponent bits is zero.
4. The method of claim 1, wherein the register entry is an 82 bit register entry that accommodates two 32 bit floating point operands and each of the bits is set to a first state if the exponent bits indicate the associated operand is denormal.
5. A method for loading a packed operand into a floating-point register file entry, the method comprising:
copying significand bits and exponent bits for each component operand of the packed operand to corresponding fields in the register file entry;
determining if each component operand is normalized; and
setting to a first logic state a bit associated with each component operand that is normalized.
6. The method of claim 5, wherein determining if each component operand is normalized comprises testing the exponent bits of the component operand.
7. The method of claim 6, wherein testing the exponent bits comprises:
determining whether any of the exponent bits are non-zero; and
identifying the component operand as normalized when it includes at least one non-zero exponent bit.
8. The method of claim 7, further comprising setting to a second logic state the bit associated with each component operand that is not normalized.
9. A processor comprising:
a data cache;
a floating point register file including a plurality of entries, each entry having one or more associated bits to indicate if an operand stored in the entry is normalized; and
a load converter to copy significand and exponent bits for each of a plurality of operands in a packed floating-point operand from the data cache to one of the register file entries, to test the exponent bits of each of operand of the packed floating point operand and to set a corresponding bit to a first or second logic state according to a result of the test.
10. The processor of claim 9, wherein the load converter includes an OR gate having a number of inputs equal to the number of exponent bits to test the exponent bits of each operand.
11. The processor of claim 9, wherein the load converter includes test logic for each component operand.
This patent application is related to U.S. patent application Ser. No. 09/169,865, entitled �Scalar Hardware for Performing SIMD Operations�, filed on Oct. 12, 1998, and assigned to the same assignee.
1. Technical Field
The present invention relates to systems for processing data and, in particular, to systems for processing data through single-instruction multiple data (SIMD) operations.
2. Background Art
Processor designers are always looking for ways to enhance the performance of microprocessors. Processing multiple operands in parallel provides one avenue for gaining additional performance from today's highly optimized processors. In certain common mathematical calculations and graphics operations, the same operation(s) is performed repeatedly on each of a large number of operands. For example, in matrix multiplication, the row elements of a first matrix are multiplied by corresponding column elements of a second matrix and the resulting products are summed (multiply-accumulate). By providing appropriate scheduling and execution resources, multiply-accumulate operations may be implemented concurrently on multiple sets of row-column operands. This approach is known as vector processing or single instruction, multiple data stream (SIMD) processing to distinguish it from scalar or single instruction, single data stream (SISD) processing.
In order to implement SIMD operations efficiently, data is typically provided to the execution resources in a �packed� data format For example, a 64-bit processor may operate on a packed data block, which includes two 32-bit operands. In this example, a vector multiply-accumulate instruction, V-FMA (f1, f2, f3), multiplies each of a pair of 32-bit operands stored in register f1 with a corresponding pair of 32-bit entries stored in register f2 and adds the resulting products to a pair of running sums stored in register f3. In other words, data is stored in the registers f1, f2, and f3 in a packed format that provides two operands from each register entry. If the processor has sufficient resources, it may process two or more packed data blocks, e.g. four or more 32-bit operands, concurrently. The 32 bit operands are routed to different execution units for processing in parallel and subsequently repacked, if necessary.
Even in graphics-intensive and scientific programming, not all operations are SIMD operations. Much of the software executed by general-purpose processors comprises instructions that perform scalar operations. That is, each source register specified by an instruction stores one operand, and each target register specified by the instruction receives one operand. In the above example, a scalar floating-point multiply-accumulate instruction, S-FMA (f1, f2, f3), may multiply a single 64-bit operand stored in register f1 with corresponding 64-bit operand stored in register f2 and add the product to a running sum stored in register f3. Each operand processed by the S-FMA instruction is provided to the FMAC unit in an unpacked format.
The register file that provides source operands to and receive results from the execution units consume significant amounts of a processor's die area. Available die area is a scarce resource on most processor chips. For this reason, processors typically include one register file for each major data type. For example, a processor typically has one floating-point register file that stores both packed and unpacked floating-point operands. Consequently, packed and unpacked operands are designed to fit in the same sized register entries, despite the fact that a packed operand includes two or more component operands.
Providing execution resources for packed and unpacked operands creates performance/cost challenges. One way to provide high performance scalar and vector processing is to include separate scalar and vector execution units. An advantage of this approach is that the vector and scalar execution units can each be optimized to process data in its corresponding format, i.e. packed and unpacked, respectively. The problem with this approach is that the additional execution units consume silicon die area, which is a relatively precious commodity.
In addition to providing appropriate execution resources, high performance processors must include mechanisms for transferring both packed and unpacked operand data efficiently. These mechanisms include those that transfer operand data to the register file from the processor's memory hierarchy, e.g. caches, and those that transfer operand data from the register file to the execution resources.
The present invention addresses these and other problems with currently available SIMD systems.
A system is provided that supports efficient processing of a floating point operand by setting an implicit bit for the operand �on-the-fly�, i.e. as the operand is loaded into a register file entry.
In accordance with the present invention, a floating-point operand is retrieved for loading into a register file entry. Selected bits of the floating-point operand are tested, and an implicit bit associated with the register file entry is set when the selected bits are in a first state.
For one embodiment of the invention, the floating-point operand is a packed operand that includes two or more component operands, and the register file entry includes an implicit bit for each component operand. The implicit bit for a component operand is set when the selected bits indicate that the component operand is normalized.
The present invention thus allows the normal/denormal status of an operand to be determined when the operand is loaded into the register file and tracked through an implicit bit associated with the corresponding register file entry. This eliminates the need for status-determining logic in the operand delivery module, which transfers the operand from the register file to the execution unit. Since the operand delivery module is on a critical (bypass) path for the execution unit, processor performance may be significantly improved.
The present invention may be understood with reference to the following drawings in which like elements are indicated by like numbers. These drawings are provided to illustrate selected embodiments of the present invention and are not intended to limit the scope of the invention.
FIG. 1 is a block diagram of a floating-point execution system in accordance with the present invention.
FIGS. 2A and 2B represent the bit fields for unpacked and packed operands, respectively, in an entry of the register file shown in FIG. 1.
FIG. 3 is a block diagram representing the operation of operand delivery module on a packed operand.
FIG. 4 is a circuit diagram of one embodiment of the operand delivery system shown in FIG. 1.
FIG. 5 is a circuit diagram of one embodiment of the output conversion module shown in FIG. 1.
The following discussion sets forth numerous specific details to provide a thorough understanding of the invention. However, those of ordinary skill in the art, having the benefit of this disclosure, will appreciate that the invention may be practiced without these specific details. In addition, various well-known methods, procedures, components, and circuits have not been described in detail in order to focus attention on the features of the present invention.
Processor architectures typically specify a format for storing data in on-chip resources, such as register files. This register file format is selected to accommodate the various data types handled by the processor's execution resources, as well as any ancillary information used to process the data. The data types to be accommodated may be, for example, those specified by IEEE 754-1985, the IEEE standard for binary floating-point arithmetic. A register file format supports efficient processing by storing operand data in a format that is readily accessed and processed by the execution resources.
For scalar processing, each operand is stored as an unpacked operand in the register file format. Here, �unpacked� refers to a data format that allows no more than one operand to be represented by data in a register file entry. For example, a processor may accommodate one single precision unpacked operand, one double precision unpacked operand, or one double extended precision unpacked operand per register file entry in the processor's register file format. For vector processing, multiple component operands are provided in a packed operand that fits in a single register file entry. Accommodating packed and unpacked operands in one size register entry means that the operands are mapped to the register entry differently. The different mappings may be reflected in the resources that transfer operands from, e.g., a cache to the register file and those that transfer operands from the register file to the execution resources.
The different operand formats for vector and scalar operations may also be reflected in the execution resources themselves. For example, a packed operand having two 32-bit component operands may be processed using two 32-bit execution units. An unpacked operand in the same system may be processed as a single 64-bit operand by a 64-bit execution unit. In this example, three different execution units, two 32-bit vector execution units and one 64-bit scalar execution unit, are provided for each execution pipeline, but only two operands are ever processed in parallel by the pipeline. The additional execution unit consumes precious silicon die area and power.
An alternative to providing two vector execution units is to modify the scalar execution unit to process both scalar and vector operands. This approach eliminates the need for one of the vector execution units. However, modifying the scalar unit in this way can degrade its performance on unpacked operands.
The present invention provides a system that processes data provided in packed and unpacked formats efficiently, without significantly increasing the silicon die area of the processor or degrading the processor's performance on unpacked data. A load conversion module determines implicit bits for the component operands of a packed operand �on-the-fly�, e.g. as the packed operand is loaded into an entry of the register file from a memory location, such as a cache. The implicit bits are associated with the register file entry, and they indicate the corresponding component operands are normal, denormal, or zero (normalized status). Implicit bits may also be determined for unpacked operands, although they are not used for subsequent processing of these operands.
When an instruction refers to the register file entry, an operand delivery mechanism converts a component operand from a packed operand into a format suitable for processing by a scalar execution unit. The operand delivery system may implement operand conversion by bit-steering to avoid loading the system with additional logic gates. This significantly reduces the impact of operand conversion on the system's performance, while preserving the scalar execution unit's performance on unpacked data.
For one embodiment of the present invention, the scalar execution unit operates in conjunction with a vector execution unit to process packed operands. The converted operand and an unconverted component operand are provided to the scalar and vector execution units, respectively, for processing. For one embodiment of the invention, the operand delivery mechanism includes bit-steering traces and inverters that convert one of the component operands into a scalar format without significantly loading the execution resources. This in turn preserves processor performance on scalar operations.
The scalar execution unit may be a floating-point multiply-accumulate module (FMAC) optimized to process an unpacked operand in a register file format (RFF). The vector execution unit may be an FMAC unit that is optimized to process a component operand provided by a packed operand in a packed data format (PDF). The operand delivery module may include a MUX having an additional leg to deliver bit resteered traces to the scalar execution unit, and an inverter to modify selected bits of the component operand for processing as an unpacked operand.
FIG. 1 is a block diagram of a floating-point system 100 that is suitable for implementing the present invention. System 100 includes a floating-point register file 110, an operand delivery module 120, a primary FMAC 130, a secondary FMAC 140, an output conversion module 150, and a load conversion module 160. Also shown is a cache 170 to provide operand data to register file 110 through load conversion module 160. Cache 170 represents a structure in a hierarchical memory system that stores data for processing by floating point system 100 and other processor resources (not shown). Data is typically stored in the memory system in the data formats prescribed by the IEEE floating point standard discussed above.
For the disclosed embodiment of system 100, primary FMAC 130 processes unpacked operands in a register file (�unpacked�) format. Secondary FMAC 140 processes component operands of a packed operand. Operand delivery module 120 couples data from register file 110 to FMACs 130 and 140 in the appropriate formats.
In the disclosed embodiment of system 100, register file 110 includes multiple register entries 112. For one embodiment, each entry 112 has an associated implicit bit 114 which may be set to indicate whether data stored in associated register entry 112 is normalized. Implicit bits are defined, for example, in the IEEE std. 754. An implicit bit may be combined with a component operand from a packed operand to characterize the operand for processing. For example, an implicit bit may be set to indicate that data is in normal form.
For scalar operations, operand delivery module 120 provides an unpacked floating-point operand from register file 110 to primary FMAC 130. The unpacked operand is stored in register file 110 in a register file format. For vector operations, operand delivery module 120 retrieves a packed operand from register file 110, converts one component operand to an unpacked operand, and provides it to primary FMAC 130. The second component operand is provided to secondary FMAC 140. Primary FMAC 130 is thus shared between vector and scalar operations, while secondary FMAC 140 provides the additional execution resource for vector operations.
Results generated by FMACs 130 and 140 are coupled to output conversion module 150 for recombination into a packed data format. For one embodiment of the invention, a bypass 160 couples output data from primary FMAC 130 to operand delivery module 120 prior to repacking. The bypassed data may undergo additional processing by primary FMAC 130 without first being repacked by conversion module 150 and subsequently unpacked by operand delivery module 120. This bypass loop eliminates the input conversion (packed to unpacked data) from the bypass path.
System 100 is shown having a single floating-point pipeline, but the present invention is not limited to single pipeline systems. It may be replicated in one or more additional pipelines to provide superscalar floating-point SIMD operations. That is, two or more vector instructions may be processed in parallel. More generally, persons skilled in the art will recognize that the present invention may be implemented in floating point systems configured differently than system 100.
FIG. 2A shows one embodiment of an unpacked operand 200 in a register file format (�RFF operand) that is suitable for use with the present invention. RFF operand 200 includes a significand field 210, an exponent field 220, and a sign field 230. For one embodiment of the invention, significand field 210 is 64-bits, exponent field 220 is 17 bits, and sign field 230 is one bit.
FIG. 2B shows one embodiment of a packed operand 250 in a packed data format (�PDF operand�) that is suitable for use with the present invention. The disclosed embodiment of PDF operand 250 includes first and second component operands 260(a) and 260(b), respectively. In the following discussion, the index is dropped unless required to distinguish a particular component operand 260. A block of unused bits 270 is also shown in PDF operand 250. Unused bits 270 are added to component operands 260 to fill the register file entry. Each component operand 260 includes a mantissa field 262, an exponent field 264, and a sign field 266. For one embodiment, mantissa field 262 is 23 bits wide, exponent field 264 is 8 bits wide, and sign field 266 is 1 bit wide. In the disclosed embodiment, each component operand is in a single precision floating-point format as specified, for example, in IEEE standard 754-1985.
Also shown in FIGS. 2A and 2B are implicit bit(s) 114, which are associated with each register file entry 112 (FIG. 1). Implicit bit(s) 114 may be used to indicate whether a component operand is zero or denormal. For one embodiment of FP register file 110, implicit bits may be determined as data is written to register entry 112 of register file 110, i.e. �on-the-fly�. This eliminates the need for additional logic in operand delivery module 120 to determine the normal/denormal status of an operand, which would only slow processing of vector operands. For example, evaluating the normal/denormal status of a component operand on delivery to FMAC 140 would require an OR gate in a critical path of operand delivery system 120.
For register file entries 112 storing unpacked and packed operands as in FIGS. 2A and 2B, respectively, implicit bits 114, e.g. bits 82 and 83 are set as follows when the data is written to register file 110:
IF (data [62:55]='0::8), THEN data [83]='0, ELSE '1
IF (data [30:23]='0::8), THEN data [82]='0, ELSE '1.
Here, '1 and '0 indicate binary one and binary zero, respectively.
For one embodiment of system 100 (FIG. 1), load conversion module 160 may implement the above operations using a pair of 8-input OR gates. For example, one embodiment of load conversion module 160 includes traces that transfer exponent, significand, and sign bits from an entry of cache 170 to their corresponding bit fields in a target entry 112 (FIG. 2B) of register file 110. The inputs of each OR gate is coupled to one of the exponent bit traces of one of the component operands, and the output of the OR gate is coupled to the implicit associated with the component operand. For this embodiment, the implicit bit is set to one if any of the exponent bits of the component operand is non-zero.
Implicit bits are available to operand delivery module 120 to provide component operands 260 in a format suitable for processing. For example, component operand 260 has a mantissa field 262 that accommodates 23 bits. A 24 bit significand may be formed by appending the associated implicit bit to the 23 bit mantissa as the most significant bit. In the disclosed embodiment, this conversion is not required for RFF data 200. However, the logic is simplified by determining implicit bits 114 for each operand written to register file 110, and ignoring them when a RFF data 200 is being processed.
For one embodiment of the invention, one of component operands 260 is converted to an RFF operand for processing by primary FMAC 130, and the other component operand is provided to secondary FMAC 140 for processing.
FIG. 3 is a schematic representation of the operations implemented by operand delivery module 120 to provide properly formatted data to FMACs 130 and 140. In the disclosed embodiment, an implicit bit 114 is combined with data from component operand 260(a), which is converted to an RFF operand for processing by primary FMAC 130. One feature of the present invention is that this conversion process may be implemented without loading primary FMAC 130 and, consequently, degrading its performance on scalar operations. Component operand 260(b) is provided to secondary FMAC 140 for processing, which may be optimized to process operands in that component format. While FMAC 130 is shown processing the upper component operand (260(a)) of the packed operand, this is not necessary. More generally, any of the component operands of the packed operand may be selected for routing to FMAC 130.
For one embodiment of the invention, operand delivery module 120 accomplishes data conversion by bit steering packed operand 250 into an unpacked operand 200. For example, data from mantissa field 262(a) and implicit bit 114 (I1) may be converted to RFF significand data (significand field 210). Similarly, data from exponent field 264(a) may be converted to RFF exponent data (exponent field 220). Data from sign field 266(a) may be mapped to an RFF sign bit (sign field 240). The various conversion steps are considered in greater detail below, using the exemplary data formats provided in conjunction with FIGS. 2A and 2B.
Significand Conversion
The exemplary embodiment of component operand 260(a) includes a 23 bit mantissa field 262(a). For one embodiment of the invention, data from mantissa field 262(a) is converted to an RFF significand by: (1) prepending an associated implicit bit 114 to the MSB position of a 23 bit mantissa from component mantissa field 262; and (2) appending binary zeroes to the least significant bit of the mantissa to form a 64-bit RFF significand. Bit-steering for the mantissa is summarized in Table 1, which indicates the bit(s) input to primary (10) FMAC 130 from register entry 112, the function of the bit(s), the source of the bit(s) for scalar instructions, and the source of the bit(s) for vector instructions.
As noted above, while these operands share the same footprint in register file 110, i.e. register entry 112, their operands are mapped to different bits of register entry 112.
In the disclosed embodiments of RFF operand 200 and PDF operand 250, the implicit bit is specified by bit 63 and bit 83, respectively. In order to accommodate both data formats, operand delivery module 110 may employ a 2:1 multiplexer (MUX) to select the appropriate source bit for input to FMAC 130. Introducing an additional 2:1 MUX into the logic chain between register file 110 and FMAC 130 loads operand delivery module 120 and slows the delivery of data to FMAC 130. The loading reduces performance for both scalar and vector operations. For one embodiment of the invention, bit steering is accomplished by providing an additional leg to an existing 3:1 MUX (FIG. 4) in operand delivery module 110 for bypassing data (late bypass 4:1 MUX). This eliminates the need to add an additional MUX to the data path between register file 110 and FMAC 130.
Exponent Conversion
For the disclosed embodiment, RFF and PDF exponents are expressed relative to different biases. The difference between the biases may be taken into account when converting the PDF exponent (field 264) to an RFF exponent (field 220). For one embodiment, the RFF bias value is FFFFh and the PDF bias value is 7Fh, i.e. the exponent bias for single precision real numbers in the IEEE standard. The difference between these values is FF80h.
One approach to exponent conversion adds FF80h to an 8-bit exponent value in PDF exponent field 264 to obtain the RFF exponent. A problem with this approach is that it employs an adder in the data path between register file 110 and primary FMAC 130. The additional gate delay in operand delivery module 120 degrades the performance of system 100 for both vector and scalar operations. An alternative approach to adjusting exponent biases eliminates the need for an adder.
Table 2 summarizes the bias adjustment process performed to convert a PDF exponent to an RFF exponent for the case where the bias difference is FF80h. Here, E0 through E7 are the 8 bits in PDF exponent field 264(a) and 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 is FF80h expressed in binary. As indicated in Table 2, exponent conversion can be achieved by inverting the 8th exponent bit (E7→) in PDF exponent field 264(a), replicating it in the next 9 bit positions of the RFF exponent (field 220), and copying the uninverted 8th bit (E7) to the most significant bit position of the RFF exponent. These operations may be accomplished with an inverter and appropriately routed traces. No adder is needed, and the performance impact of the inverter on operand delivery module 120 and primary FMAC 130 is not significant.
The approach summarized in Table 2 does not work for single precision denormal numbers. Denormal numbers may be identified by the value of the associated implicit bit 114, and conversion may be implemented using a software handler. The exponent bit steering discussed above is summarized in Table 3.
Here, �#� indicates that the bit is inverted. The exponent bits are numbered for primary FMAC 130 beginning with the first bit of the exponent field.
FIG. 4 represents one embodiment of operand delivery module 120 that is suitable for use in a processor having first and second floating-point pipelines, pipe0 and pipe1, respectively. The present invention is not limited to the particular number of pipelines employed in the processor. The disclosed embodiment of operand delivery module 120 includes a 4:1 early bypass MUX (EBPM) 410, a 6:1 middle bypass MUX (MBPM) 420, and a 4:1 late bypass MUX (LBPM) 430. For the exemplary data formats described above, operand delivery module 120 converts a 32-bit component operand 260(a) from a packed or PDF operand 250 into an 82 bit unpacked or RFF operand 200.
EBPM 410 receives cached data for pipe0 and pipe1 at inputs A and B. Write-back data from the backend of pipe0 and pipe1 may be coupled into operand deliver module 120 through inputs C and D. A control input of EBPM 410 selects data from one of inputs A, B, C, or D to be provided to MBPM 420. MBPM 420 receives data from EBPM 410 at input E. Bypass data from one stage of pipe0 and pipe1 is received at inputs F and G, respectively. Data from a load converter (not shown) for pipe0 and pipe1 is received at inputs H and I, respectively, and data from register file 110 is received at input J. A control input of MBPM 420 selects data from one of inputs E, F, G, H, I, or J to be provided to LBPM 430.
LBPM 430 receives bypass data from another stage of pipe0 and pipe1 at inputs M and N, respectively. Input K of LBPM 430 receives data from MBPM 420 through bit steering block 440, which implements the conversions described above for vector operations. In the above-example, bit-steering block 440 includes an inverter and bit-steering traces to reformat data from upper component operand 269(a) to REF data. For example, bit-steering block includes logic and traces to convert a 23-bit PDF mantissa to a 64-bit RFF significand and to convert an 8-bit PDF exponent to a 17-bit RFF exponent with a readjusted bias. For scalar operations, input L of LBPM 430 receives data from MBPM 420 without intervening bit-steering or inversion. Data from one of inputs K or L is provided to primary FMAC 130 according to whether packed or unpacked data, respectively, is being processed.
In the embodiment of FIG. 4, converted (bit-steered) and unconverted data is provided to primary EMAC 130 by selecting the appropriate input K or L, respectively. This allows data from register file 110 or any of the relatively early bypass stages to be converted at LBPM 430. In the disclosed embodiment, late bypass data at inputs M and N may be converted by replicating each input with a corresponding bit-steering block 440. However, if bypassed data at inputs M and N is not packed prior to the late bypass, there is no need to unpack it. Use of additional legs and bit steering blocks 440 on LBPM 430 may be avoided.
For one embodiment of operand delivery module 120, late bypass data may be provided to LBPM 430 via bypass 160 (FIG. 1). Bypass 160 captures the outputs of primary and secondary FMACs 130 and 140, respectively, before they are repacked into, e.g., PDF format 250. In this embodiment, no additional expansion of LBPM 430 or its inputs is required for bypassed data.
FIG. 5 shows one embodiment of output conversion module 150. The disclosed embodiment of output conversion module includes a primary output MUX 510 and bit-steering lock 520. Primary output MUX 510 includes inputs to receive results from primary FMAC 130 and various FPU resources (FMISC) 154, as well as special result encodings. For the exemplary data formats, FMAC 130 provides a result as an unpacked (RFF) operand 200 (82-bit) for both scalar and vector operations. In the latter case, bit steering block 520 combines the unpacked operand from primary FMAC 130 with a component operand from secondary FMAC 140 to form a packed operand.
The special encodings provided to primary output MUX 510 indicate special results, such as zero, infinity, or a maximum real (largest representable floating-point value) in the register file format. For the disclosed embodiments, these encodings may be converted for vector operations, as necessary, using the bit steering operations described above. If more elaborate conversions are required for zero, infinity, and Max Real results, they may be implemented in earlier stages of operand delivery module 120, since the necessary information is available relatively early in the floating-point execution pipeline. No additional delay is introduced into the critical path.
For vector operations, the results of primary FMAC 130 and secondary FMAC 140 are repacked to provide the result as a PDF operand. In the disclosed embodiment, the lower 32 bits of the 82-bit entry receive the component operand result from secondary FMAC 140. The next most significant 32-bits are provided, through bit-steering, by the unpacked operand result from primary FMAC 130. The upper 18-bits receive implementation-dependent constants, e.g. in the disclosed embodiment, these are '1 & 1003Eh.
The unpacked (RFF) exponent provided by primary FMAC 130 has an excess bias of FF80h relative to the IEEE single precision format employed for component operands 260 in packed operand 250. The excess bias is subtracted from the unpacked operand result when it is converted to a component operand result for packing. In the exemplary embodiment, this may be accomplished by adding the 2's complement of FF80h to the 17 bit RFF exponent and using the lower 8-bits of the result as the exponent for the component operand. As before, the conversion may be accomplished without loading the floating-point pipeline with an additional adder, using the bit-steering operation represented in Table 4.
As indicated in Table 4, exponent bits for the component operand may be derived from the unpacked operand provided by primary FMAC 130 without addition. In the above example, they are provided by the lower 8 exponent bits of the unpacked operand result, with the 8th bit inverted. The upper 8 bits, which are ignored in the conversion operation, are not shown in Table 2.
Table 5 summarizes the bit-steering operation that packs an unpacked operand result from primary FMAC 130 with a component operand result from secondary FMAC 140 to provide a packed operand result for vector operations.
Here, �CO� refers to component operand, �Result bits from 10 FMAC� refers to the packed operand result generated by primary FMAC 130, and �Result bits from 20 FMAC� refers to the component operand result generated by the secondary FMAC 130.
For certain instructions executed by the FMAC, additional control signals are provided to the FMAC to modify operation of the unit. For example, the FMAC may be used to convert floating-point operands to integer operands. The conversion may be applied to both vector and scalar operands. The bit shifting required for the vector and scalar cases is different, and a separate control signal is provided to adjust FMAC operation accordingly. The multiply accumulate operations discussed above, e.g. those involved in matrix multiplication and coordinate transformations, are processed without any such internal modifications of the FMAC units.
There has thus been provided a system for processing SIMD or vector operations using a combination of scalar and vector execution units. The amount of additional execution hardware that must be added to the system is reduced, while the performance of the scalar execution hardware is preserved. The system employs a register file having an implicit bit for each component operand of a packed operand. A load conversion unit includes logic to test each component operand for denormal/zero status during the load operation and to set the associated implicit bit accordingly. A scalar and a vector execution unit are provided for each pipeline in the system. An operand delivery module provides data from a register file to the scalar and vector execution units. For SIMD operations, the operand delivery module retrieves a packed operand from the register file, converts a component operand to an unpacked operand via bit steering, and provides the unpacked operand to the scalar execution unit for processing. A second component operand is provided to the vector execution unit. Bit steering logic includes trace routings and inverter, which has a minimal impact on the performance of the system for both scalar and vector operations.
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Google Phone Gallery Presents A Comparison Engine For Android Handsets
It's the return of the Nexus One online store. In fact the old URL for the Nexus One site is now occupied by a mini shopping comparison site for Android handsets called the "Google Phone Gallery." Note that it's called Google Phone Gallery and not "Android Phone Gallery." Indeed, it's meant to showcase "Android-powered devices that deliver the best Google experience today."
Android devices are multiplying like rabbits and consumers are going to be confused by all the handset choices. Verizon in the US, for example, has six Android handsets to choose from.
It's therefore helpful to be able to compare "Google Phones" across carriers, by manufacturer and by country:
This represents the best single place to compare features and capabilities of most Android handsets online. The glaring omission, which I'm sure Google will rectify, is handset reviews.
Each handset profile provides a link to a carrier store to buy the desired phone:
The Google Phone Gallery is in the same direct-to-consumer conceptual spirit of the Nexus One store while being far less alienating to Google's carrier partners. It also has a quality of "necessity" now with the dozens and dozens of Android devices on the market.
See also: Blame Bing: Why The Google Phone Gallery Doesn't List Verizon's Best Android Phone.
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Coverage: CBS
6:30 PM ET, January 20, 2013
Gillette Stadium, Foxboro, MA
Photo 198 of 232
FOXBORO, MA - JANUARY 20: Head coach John Harbaugh of the Baltimore Ravens hugs head coach Bill Belichick of the New England Patriots after winning the 2013 AFC Championship game at Gillette Stadium on January 20, 2013 in Foxboro, Massachusetts. The Baltimore Ravens defeated the New England Patriots 28-13. (Photo by Jim Rogash/Getty Images)
Photo 198 of 232


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Klarque Garrison of "Survive 365"
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Mr. 365, D. Klarque Garrison, host of the blog, Survive 365, and the blog talk radio show, Survive 365: The Conversation of Survive 365 discusses his book, How to Survive the Next 365 | Your Lifeline to a Better Life.
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Dave Payton: A life of sin can place us on a dangerous path. Many people do not recognize their destructive behavioral patterns, but for others this is a life-style. Sin has no boundaries, and it is capable of destroying the lives of very good people. This book will engage the reader and will expose those things which may have a negative influence in a person's life. It is important to recognize that all sins are forgiven when we place our trust in God. This book contains specific topics designed to promote journalism. While some of these topics are very sensitive, they will also open the door for healing as God will use this time to touch your heart. I hope you enjoy this intimate time with God. ???Dave Payton was born in Portsmouth, Ohio, 1957, and moved to Arizona at the age of five. He was raised in South Phoenix. He grew up in a predominately Hispanic neighborhood. It was in the streets that his lessons were learned. He acquired a different perspective on life as God showed him how to accept others for who they really are. Through much adversity and help along the way, he was able to fight his way to a better life. His tough life gave him compassion for those who suffered. His passion for the less fortunate will always be a soft spot in his heart as he can only thank God for saving him.
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On this episode of the Yanks Go Yard Series Preview Show, host and senior staff writer Ricky Keeler gives a brief recap of the series with the Red Sox and looks ahead to the Cubs' visit to Yankee Stadium on Tuesday for a 2-game series.
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Home » News » Education
Exeter charter school's goal is to make everyone a grad
EXETER - Seven years ago, the Great Bay Charter School was founded to address the growing need to provide alternatives for students who were not succeeding in a traditional high school setting.
Since then, the school has grown to accommodate five grade levels and about 150 students on a daily basis at the Tuck Learning Campus.
Now the charter school is offering a program to help high school students reach "the finish line." The free program is targeted at students in danger of not finishing high school.
Executive Director Cheryl York McDonough said it may also be a viable choice for students who would benefit from a late-day start or an alternative schedule.
"The Finish Line" program will begin in January and will typically be in session from 2:30 to 5:30 p.m. daily.
McDonough said students will work with certified teachers who will function as a coach, instructor and/or mentor to students as they create individualized learning plans and customized academic schedules.
As a charter school, McDonough said Great Bay is able to be more flexible and creative, and combine academic programs with internships, externships and career/technical opportunities.
With state law requiring students to stay in school until they graduate or turn 18, it is the job of educators to find options for every student, she said.
"There is no such thing as a one-size-fits-all education," McDonough said.
She said "The Finish Line" program is open to any New Hampshire student. The late schedule could work for students who have to work during the day to help support their families, those who want to do externships, or students who might need to make up a class, she said.
"It could be a high school dropout, it could be someone in a traditional school who knows they need another way out because they aren't going to make it," McDonough said.
For information, call 775-8638.
- - - - - - - -
Gretyl Macalaster may be reached at email@example.com.
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On Saturday, I went to Palm Springs for a friend's book launch party. My friend's name is Steve Vaught, and he just wrote this pretty impressive book:
But first, some background about Steve and about the book.
I met Steve around 1997-98. He and my friend Dee were heading a rights-research project at MGM. I had just split up from Husband No. 1, and needed a job. Dee brought me in. This was before law school, and in fact, was the impetus for law school. There I met not just Steve, but also our other friends Taylor, Lisa, Darren and Marie Anne.
Steve's passion has always been the history of buildings, and what role the buildings have played in the local history. He's an expert on all things Hollywood and Los Angeles and, now that he's in Palm Springs, he has become as expert on all things Palm Springs. When I was there in April for the Palm Springs Photography Festival, he gave us a private tour of the O'Donnell house - O'Donnell was one of the founders of the city.
This is his first published book. More will follow. But this is the first. It is a history the Committee of Twenty-Five, a gentlemen's club founded in 1948. The club's purpose, as Steve tells us, is and has always been to "'encourage the development and civic betterment of Palms Springs and the desert area.'"
The book's launch was the Committee of 25 club, where a reception was held, and Steve signed books till his hand fell off.
The club has a rich history, enough to fill a book. The book has lots of old timey photos, if words are not to your liking. But Steve! Steve is a fantastic writer, so if you have even the remotest interest, let me know, or contact the club in Palm Springs, they no doubt would be thrilled to sell you a copy.
Steve has put together a brilliant first book, and we are all very proud of our friend. Here are some pics of the "we."
This is Steve, the man of the hour. Here he is listening to speeches by important folks about the club and about the book and the effort it took to get it done, and people are being thanked for their invaluable contributions.
Steve briefly talked about getting the book done. It was probably the most understated speech about what it took to get a book done in the history of speeches about what it took to get a book done.
Friends Marie Anne and Dee.
Lorraine, Dee, Taylor, Ramy.
Friends and family came from far and wide to honor Steve's achievement. Steve is a wonderful, good person, and a great friend. And he also happens to be the funniest human being on the planet. There was eating, drinking, rejoycing, laughing, and catching up.
Can you think of anything better?