text:
Electronics Packaging Manufacturing, IEEE Transactions on
IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.
This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.
Latest Published Articles
Time–Frequency and Autoregressive Techniques for Prognostication of Shock-Impact Reliability of Implantable Biological Electronic SystemsNov-22 2010
Simulation Methods for Predicting Fusing Current and Time for Encapsulated Wire BondsNov-22 2010
Board-Level Vibration Failure Criteria for Printed Circuit Assemblies: An Experimental ApproachNov-22 2010
Reducing Solder Paste Inspection in Surface-Mount Assembly Through Mahalanobis–Taguchi AnalysisNov-22 2010
Scalability of Roll-to-Roll Gravure-Printed Electrodes on Plastic FoilsJinsoo Noh ; Dongsun Yeom ; Chaemin Lim ; Hwajin Cha ; Jukyung Han ; Junseok Kim ; Yongsu Park ; Subramanian, Vivek ; Gyoujin ChoNov-22 2010
Popular Articles
The changing automotive environment: high-temperature electronicsFeb-14 2005
Rough set theory: a data mining tool for semiconductor manufacturingAug-07 2002
Electron beam lithography in nanoscale fabrication: recent developmentOct-14 2003
Printed circuit board recycling: a state-of-the-art surveySep-03 2004
Scalability of Roll-to-Roll Gravure-Printed Electrodes on Plastic FoilsJinsoo Noh ; Dongsun Yeom ; Chaemin Lim ; Hwajin Cha ; Jukyung Han ; Junseok Kim ; Yongsu Park ; Subramanian, Vivek ; Gyoujin ChoNov-22 2010
Publish in this Journal
Meet Our Editors
R. Wayne Johnson
Auburn University
Popular Articles (October 2014)Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
1. The changing automotive environment: high-temperature electronics| | Quick Abstract | PDF (1560 KB) | | HTML
The underhood automotive environment is harsh and current trends in the automotive electronics industry will be pushing the temperature envelope for electronic components. The desire to place engine control units on the engine and transmission control units either on or in the transmission will push the ambient temperature above 125°C. However, extreme cost pressures, increasing reliability demands (10 year/241 350 km) and the cost of field failures (recalls, liability, customer loyalty) will make the shift to higher temperatures occur incrementally. The coolest spots on engine and in the transmission will be used. These large bodies do provide considerable heat sinking to reduce temperature rise due to power dissipation in the control unit. The majority of near term applications will be at 150°C or less and these will be worst case temperatures, not nominal. The transition to X-by-wire technology, replacing mechanical and hydraulic systems with electromechanical systems will require more power electronics. Integration of power transistors and smart power devices into the electromechanical actuator will require power devices to operate at 175°C to 200°C. Hybrid electric vehicles and fuel cell vehicles will also drive the demand for higher temperature power electronics. In the case of hybrid electric and fuel cell vehicles, the high temperature will be due to power dissipation. The alternates to high-temperature devices are thermal management systems which add weight and cost. Finally, the number of sensors in vehicles is increasing as more electrically controlled systems are added. Many of these sensors must work in high-temperature environments. The harshest applications are exhaust gas sensors and cylinder pressure or combustion sensors. High-temperature electronics use in automotive systems will continue to grow, but it will be gradual as cost and reliability issues are addressed. This work examines the motivation for higher temperature operation, the packaging limitations even at 125°C with newer package styles and concludes with a review of challenges at both the semiconductor device and packaging level as temperatures push beyond 125°C. View full abstract»
2. Rough set theory: a data mining tool for semiconductor manufacturing| | Quick Abstract | PDF (136 KB) | | HTML
The growing volume of information poses interesting challenges and calls for tools that discover properties of data. Data mining has emerged as a discipline that contributes tools for data analysis, discovery of new knowledge, and autonomous decisionmaking. In this paper, the basic concepts of rough set theory and other aspects of data mining are introduced. The rough set theory offers a viable approach for extraction of decision rules from data sets. The extracted rules can be used for making predictions in the semiconductor industry and other applications. This contrasts other approaches such as regression analysis and neural networks where a single model is built. One of the goals of data mining is to extract meaningful knowledge. The power, generality, accuracy, and longevity of decision rules can be increased by the application of concepts from systems engineering and evolutionary computation introduced in this paper. A new rule-structuring algorithm is proposed. The concepts presented in the paper are illustrated with examples View full abstract»
3. Electron beam lithography in nanoscale fabrication: recent development| | Quick Abstract | PDF (1611 KB) | | HTML
Miniaturization is the central theme in modern fabrication technology. Many of the components used in modern products are getting smaller and smaller. In this paper, the recent development of the electron beam lithography technique is reviewed with an emphasis on fabricating devices at the nanometer scale. Because of its very short wavelength and reasonable energy density characteristics, e-beam lithography has the ability to fabricate patterns having nanometer feature sizes. As a result, many nanoscale devices have been successfully fabricated by this technique. Following an introduction of this technique, recent developments in processing, tooling, resist, and pattern controlling are separately examined and discussed. Examples of nanodevices made by several different e-beam lithographic schemes are given, to illustrate the versatility and advancement of the e-beam lithography technique. Finally, future trends in this technique are discussed. View full abstract»
4. Printed circuit board recycling: a state-of-the-art survey| | Quick Abstract | PDF (352 KB) | | HTML
This survey is done with an intention of providing a clear and comprehensive review of current practices and recent developments in the area of printed circuit board (PCB) recycling. The aim of this paper is to be a reference for research and implementation for the PCB recycling process. Original information is collected from the companies engaged in the PCB recycling industry and articles published after 1990. The paper gives an overview of the PCB structure, material composition and different recycling processes. View full abstract»
5. Scalability of Roll-to-Roll Gravure-Printed Electrodes on Plastic FoilsJinsoo Noh ; Dongsun Yeom ; Chaemin Lim ; Hwajin Cha ; Jukyung Han ; Junseok Kim ; Yongsu Park ; Subramanian, Vivek ; Gyoujin ChoPage(s): 275 - 283| | Quick Abstract | PDF (3454 KB) | | HTML
Roll-to-roll (R2R) gravure printing is considered to be a leading technology for the production of flexible and low-cost printed electronics in the near future. To enable the use of R2R gravure in printed electronics, the limits of overlay printing registration accuracy (OPRA) and the scalability of printed features with respect to the physical parameters of the gravure system, including given plastic substrates and inks, should be characterized. Important parameters of printed lines include surface roughness, thickness, line widening, and line-edge roughness. To date, there are no comprehensive reports regarding the limits of OPRA and the scalability of printed electrodes, including the control of surface roughness, thickness, line widening, and line-edge roughness using R2R gravure printing. In this paper, we examine ways of evaluating the OPRA limit of our gravure system. We find that OPRA is limited in the web moving direction to 40 μm and in the perpendicular direction to 16 μm, showing the importance of web handling on registration. Furthermore, we demonstrate the scalability of printed electrodes formed using a R2R gravure system to linewidths of 317 μm, with 440 nm thickness, 30 nm of surface roughness and edge waviness of 4 μm on PET foils, and describe optimization strategies to realize improved surface roughness, thickness, line widening, and line-edge roughness for future printed electronics applications. View full abstract»
6. Feature transformation methods in data mining| | Quick Abstract | PDF (192 KB) | | HTML
The quality of knowledge extracted from a data set can be enhanced by its transformation. Discretization and filling missing data are the most common forms of data transformation. A new transformation method named feature bundling is introduced. A feature bundle involves a set of features in its pure or transformed form. The computational results reported in this paper show that the classification accuracy of decision rules generated from data sets with feature bundles is enhanced. The proposed concept of feature bundling is applied to a data set from the semiconductor industry View full abstract»
7. Formulation and processing of novel conductive solution inks in continuous inkjet printing of 3-D electric circuits| | Quick Abstract | PDF (3968 KB) | | HTML
One of the greatest challenges for the inkjet printing electrical circuits is formulation and processing of conductive inks. In the present investigation, two different formulations of particle-free conductive solutions are introduced that are low in cost, easy to deposit, and possess good electrical properties. A novel aqueous solution consisting of silver nitrate and additives is initially described. This solution demonstrates excellent adherence to glass and polymers and has an electrical resistivity only 2.9 times that of bulk silver after curing. A metallo-organic decomposition (MOD) ink is subsequently introduced. This ink produces a close-packed silver crystal microstructure after low-temperature thermolysis and subsequent high-temperature annealing. The electrical conductance of the final consolidated trace produced with the MOD ink is very close to bulk silver. In addition, the traces produced with the MOD material exhibit excellent wear and fracture resistance. When utilized in a specialized continuous inkjet (CIJ) printing technology system, both particle-free solution inks are able to produce conductive traces in three dimensions. The importance of three-dimensional (3-D) printing of conductive traces is finally discussed in relation to the broad range of applications in the freeform fabrication industry. View full abstract»
8. Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device| | Quick Abstract | PDF (1952 KB) | | HTML
In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft HFSSTM 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around 1.9 times 10-9 atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the ldquoY-shapedrdquo through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint. View full abstract»
9. Pressure-assisted low-temperature sintering of silver paste as an alternative die-attach solution to solder reflow| | Quick Abstract | PDF (934 KB) | | HTML
Pressure-assisted low-temperature sintering of silver paste is shown to be a viable alternative to solder reflow as a die-attachment solution. A quasihydrostatic pressure is used to lower the sintering temperature. The effect of parameters such as temperature and pressure are investigated. Characterization of the silver-attached samples shows a significant improvement in electrical conductivity, thermal conductivity and mechanical strength of the joint. Given that silver deforms with little accumulation of inelastic strains, and given the absence of large voids in the attachment layer, it is also expected that the joint to be more resistant to fatigue failure than a solder attached junction. Due to the high melting temperature of silver, this alternative process is also suitable for high temperature packages. View full abstract»
10. Constitutive and Aging Behavior of Sn3.0Ag0.5Cu Solder Alloy| | Quick Abstract | PDF (1316 KB) | | HTML
We describe double-lap shear experiments on Sn3.0Ag0.5Cu solder alloy, from which fits to Anand's viscoplastic constitutive model, power-law creep model, and to time-hardening primary-secondary creep model are derived. Results of monotonic tests for strain rates ranging from 4.02E-6 to 2.40E-3 s-1, and creep response at stress levels ranging from 19.5 to 45.6 MPa are reported. Both types of tests were conducted at temperatures of 25degC, 75degC , and 125degC. Following an earlier study where Anand model and time hardening creep parameters for Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys were reported, here we report power law model parameters so as to enable a comparison between all three alloys. Primary creep in Sn3.0Ag0.5Cu solder alloy is shown to be significant and are considered in addition to secondary creep and monotonic behavior. Aging influence on behavior is also shown to be significant. On the basis of experimental data, the following four aspects are discussed: 1) difference between testing on bulk versus joint specimen; 2) consistency between the creep and monotonic behaviors; 3) comparison against behaviors of Sn1.0Ag0.5Cu and Sn3.8Ag0.7Cu alloys as well as aganist Sn40Pb, 62Sn36Pb2Ag and 96.5Sn3.5Ag alloys; and 4) comparison of Sn3.0Ag0.5Cu and Sn3.8Ag0.7Cu relative to their aging response. View full abstract»
11. Acid Decapsulation of Epoxy Molded IC Packages With Copper Wire Bonds| | Quick Abstract | PDF (478 KB) | | HTML
Epoxy molded IC packages with copper wire bonds are decapsulated using mixtures of concentrated sulfuric acid (20%) and fuming nitric acid in an automatic decapping unit and, observed with minimal corrosion of copper wires (0.8-6 mil sizes) and bond interfaces. To attain maximum cross-linking of the molded epoxies, the post mold cured packages (175 degC for 4 h) were further, aged at high temperature of 150 degC for 1000 h. These packages are decapsulated using mixtures of higher ratio of concentrated sulfuric acid (40%) along with fuming nitric acid. The shear strength of copper wire bonds with 1 mil (25 mum) diameter of the decapsulated unit is higher than 5.5 gf/mil2. The present study shows copper stitch bonds to Au, Cu, Pd, and Sn alloy plated surfaces are less affected on decapping, with a few grams of breaking load on stitch pull test, while stitch bonds on silver plated surfaces reveal lifting of wire bonds on decapping View full abstract»
12. 300-mm Low-ZhiJie Wang ; Wang, J.H. ; Lee, S. ; Suying Yao ; Han, R. ; Su, Y.Q.Page(s): 313 - 319| | Quick Abstract | PDF (1297 KB) | | HTML
With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored. View full abstract»
13. Statistical methods for the estimation of process variation effects on circuit operation| | Quick Abstract | PDF (1264 KB) | | HTML
In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits. View full abstract»
14. Theory of Tin Whisker Growth: "The End Game"| | Quick Abstract | PDF (3723 KB) | | HTML
Previous theories of the tin whisker growth proposing various dislocation mechanisms have been largely disproved. This paper presents a new and different theory for the mechanism of tin whisker growth. The theory addresses the fundamental requirements for Sn to diffuse to the base of the whisker grain and proposes a mechanism for whisker initiation and growth. Part of this is a theoretical proposal as to what makes the whisker grain different. The role of oxidation in whisker growth is also briefly addressed. Using this theory, attempts are made to illustrate how different whisker shapes are created. Finally, a proposed potential solution to tin whisker growth is presented, assuming that this theory is correct View full abstract»
15. Critical variables of solder paste stencil printing for micro-BGA and fine-pitch QFP| | Quick Abstract | PDF (672 KB) | | HTML
Stencil printing continues to be the dominant method of solder deposition in high-volume surface-mount assembly. Control of the amount of solder paste deposited is critical in the case of fine-pitch and ultrafine-pitch surface-mount assembly. The process is still not well understood as indicated by the fact that industry reports 52-71% surface-mount technology (SMT) defects are related to the solder paste stencil printing process. The purpose of this paper is to identify the critical variables that influence the volume, area, and height of solder paste deposited. An experiment was conducted to investigate the effects of relevant process parameters on the amount of solder paste deposited for ball grid arrays (BGAs) and quad flat packages (QFPs) of five different pitches ranging from 0.76 mm (30 mil) to 0.3 mm (12 mil). The effects of aperture size, aperture shape, board finish, stencil thickness, solder type, and print speed were examined. The deposited solder paste was measured by an inline fully automatic laser-based three-dimensional (3-D) triangulation solder paste inspection system. Analysis of variance (ANOVA) shows that aperture size and stencil thickness are the two most critical variables. A linear relationship between transfer ratio (defined as the ratio of the deposited paste volume to the stencil aperture volume) and area ratio (defined as the ratio of the area of the aperture opening to the area of the aperture wall) is proposed. The analysis indicates that the selection of a proper stencil thickness is the key to controlling the amount of solder paste deposited, and that the selection of maximum stencil thickness should be based on the area ratio. The experimental results are shown to be consistent with a theoretical model, which are also described. View full abstract»
16. Modeling of time-pressure fluid dispensing processes| | Quick Abstract | PDF (104 KB)
The process of time-pressure fluid dispensing has been widely employed in the semiconductor industry, where the fluid is applied to boards or substrates. In such a process, the flow rate of fluid dispensed and the shape of fluid formed on the board are the two most critical performance indexes, yet extremely difficult to represent because of their complex behavior. This paper presents the development of a model for the time-pressure fluid dispensing process, by which the flow rate and shape can be established. Experiments have been performed to validate the model developed View full abstract»
17. Effect of Ag particle size on electrical conductivity of isotropically conductive adhesives| | Quick Abstract | PDF (348 KB)
The present work is to introduce nanoparticles in micro-sized metal particles to study particle distribution in polymer matrix. Previous examinations of the silver-filled particles reveal that the micro-sized particle fillers appear as full density silver flakes, while nanoparticle fillers appear as highly porous agglomerates, similar to open-cell foams. Actually little work has been carried out to study the cross-sectional area of a particle-particle-contact in isotropically conductive adhesives (ICA). In this study, transmission electron microscope is chosen as a main measure to analyze the distribution of different-sized particles. The percentage of the nanoparticles varies from 20 wt% and 50 wt% to full percentage within micro-sized particles, and the total metal content in epoxy resin is 70 wt%. So the change of contact area and contact behavior with various volume ratio of nano-sized and micro-sized particles was investigated. At the same time, the electrical resistivity was measured, which is compared with the different level of the filler loading View full abstract»
18. Flexible Electronics: Thin Silicon Die on Flexible SubstratesTan Zhang ; Zhenwei Hou ; Johnson, R.W. ; Del Castillo, L. ; Moussessian, A. ; Greenwell, R. ; Blalock, B.J.Page(s): 291 - 300| | Quick Abstract | PDF (2020 KB) | | HTML
Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill. View full abstract»
19. Cost analysis: solder bumped flip chip versus wire bonding| | Quick Abstract | PDF (208 KB)
The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided View full abstract»
20. Surface Insulation Resistance of Conformally Coated Printed Circuit Boards Processed With No-Clean Flux| | Quick Abstract | PDF (747 KB) | | HTML
Printed circuit board (PCB) specimens containing three different IPC-B-25 test structures were exposed to temperature/humidity/bias conditions in order to evaluate the effects of conformal coating, conductor spacing, voltage bias, flux chemistry, and test environment on surface insulation resistance (SIR). Results indicate that conformal coatings improve reliability, provided that sources of contamination on the PCB and within the coating are minimized. The presence of fibrous contaminants within the coating represented a preferential medium for moisture adsorption and ion transport, leading to accelerated reduction of SIR. In the absence of contamination, PCBs with conformal coatings were found to be less susceptible to SIR degradation than uncoated PCBs, with silicone providing better protection than urethane, and acrylic providing the least protection of the three coating materials evaluated. Conductor spacing was observed to represent a factor in the electrochemical migration (ECM) process independent of electric field, indicating that updated test structures are required to predict reliability of today's high-density assemblies. The SIR failure rate with rosin-based no-clean flux was observed to be greater than that with aqueous-based no-clean flux. A higher failure rate was also observed for tests conducted at 40 degC/93% RH than for 85 degC/85% RH. Due to the more rapid evaporation of weak organic acids in the flux residues at higher temperatures, test results obtained at 85 degC/85% RH will not accurately predict reliability at lower temperatures for PCBs processed using no-clean flux. PCB specimens were exposed to temperature/humidity/bias conditions in order to evaluate the effects of conformal coating, conductor spacing, voltage bias, flux chemistry, and test environment on reduction of surface insulation resistance. Results indicate that, in the absence of contamination, conformal coatings improve reliability View full abstract»
21. Drop-on-Demand Solder Droplet Jetting System for Fabricating MicrostructureLee, Taik-Min ; Tae Goo Kang ; Jeong-Soon Yang ; Jeongdai Jo ; Kwang-Young Kim ; Byung-Oh Choi ; Kim, Dong-SooPage(s): 202 - 210| | Quick Abstract | PDF (1481 KB)
The novel drop-on-demand (DOD) solder droplet jetting system, which can be characterized as the non-heat affection of the piezoelectric actuator, the control mechanism of the piston head-to-nozzle distance, and disposable nozzle parts, is devised. This system consists of the piezoelectric actuator, insulator, piston head-to-nozzle distance control apparatus, pressure control unit, and furnace. For the modulation of the droplet size, the distance from piston head-to-nozzle exit can be controlled by using the piston head-to-nozzle distance control apparatus. The working temperature is improved by locating the piezoelectric actuator outside of the furnace and by inserting the insulation block between the print head and the actuator. From a practical point of view, the DOD solder droplet jetting system has a simple structure for easily interchangeable nozzle parts. We derived the equation of the ejected droplet volume as a function of design parameters and operating conditions. The prototype of the DOD solder droplet jetting system was fabricated and the performance was verified. The diameter, volume and velocity of the ejected solder droplet are around 65-150 mum, 140 pl-1.8 nl, and 2.8-4 m/s, respectively. We also experimented with the effect of varying the chamber pressure, piston head-to-nozzle distance, and operating frequency on the ejected droplet diameter and velocity. The high aspect ratio vertical columns and inclined columns were fabricated by using the DOD solder droplet jetting system. View full abstract»
22. Optimizing the IC delamination quality via six-sigma approach
Integrated circuit (IC) delamination defects occur due to a poor adhesion between wafer passivation and the assembly-molding compound. Most of the components with minor delamination are not detected during the testing process, but they have the potential to cause functional failure in the application field. Unfortunately, reworking these components is not permitted, and the IC manufacturer can incur heavy costs if the suspected defective products have to be recalled. The industry is constantly striving to improve the delamination quality. However, this task is complicated and difficult. This is mainly because of insufficient knowledge of how to effectively detect when a delamination problem occurs. The quality control plan and reliability testing methods used in current processes are simply inadequate. This paper applies the six-sigma approach to assess the entire process, reduce the occurrence of delamination, and establishes a better quality control plan for the IC assembly process. This study also identifies the contact angle in order to quantify wafer surface contamination that results in delamination. The proposed method has been implemented in a semiconductor assembly factory in Taiwan. The analytical results of this study have demonstrated the feasibility of the proposed six-sigma approach and can be used as a disciplined problem solving approach for engineers for optimizing the IC process in the future. View full abstract»
23. An integrated theory of whisker formation: the physical metallurgy of whisker formation and the role of internal stresses| | Quick Abstract | PDF (3664 KB) | | HTML
Over 50 years of whisker research (cadmium, zinc, and tin) has not resulted in consensus about whisker formation fundamentals for metal films. New analytical tools have recently provided new insights into microstructural changes that occur during whisker formation. Integration of these newer observations with historical data led the authors to propose an Integrated Theory of Whisker Formation. The Integrated Theory incorporates physical attributes such as microstructure and internal stress states. Particular emphasis is placed on recrystallization, grain boundary diffusion, film-substrate interdiffusion (i.e., the Kirkendall effect), and stress gradients. The Integrated Theory does not require dislocation mechanisms for material transport to the whisker location. Material is transported to a whisker grain by the surrounding grain boundary network under the driving impetus of positive stress gradients. Transported atoms then move from the grain boundary network into the whisker grain. This movement into the whisker grain pushes the free surface of the whisker grain upward and, thereby, grows the whisker structure. View full abstract»
24. Comparative study of fluid dispensing modeling| | Quick Abstract | PDF (656 KB) | | HTML
Computational fluid dynamics is used to calculate flows in the time-pressure dispenser. The analysis of different factors such as the yield stress, the power-law constants, the needle length, etc. will be useful in understanding the dispensing mechanism and thus allow for performance improvement. The numerical solution can provide more information about the wall shear stress and the pressure drop caused by a sudden contraction. The approximation error associated with the analytical method can be understood through comparison with the numerical results. Thus, an approximation compensation model may be derived for the analytical method to improve modeling accuracy. View full abstract»
25. High Lateral Resolution Auger Electron Spectroscopic (AES) Measurements for Sn Whiskers on Brass| | Quick Abstract | PDF (1990 KB) | | HTML
We report high lateral resolution Auger electron spectroscopic (AES) measurements on high aspect ratio Sn whiskers. The whiskers were grown from compressively stressed thin films (~ 6000 Å) of Sn on brass using a magnetron sputtering system. The Auger spectra show that, after sputter cleaning, the whisker is nearly 100% Sn at all locations along the whisker shaft, at the growing blunt end of the shaft, and with depth (~ 1000 Å) into the side of the whisker. The "as received" Sn whisker surface shows the expected ~ 200 Å of native Sn oxide at all locations and the O signal nearly disappeared (~ 3 atom%) after 200 Å of sputter cleaning. There was no evidence of high amounts of oxygen within the bulk of the whisker. That brass is not observed in the whisker shaft supports the notion that whisker formation is accompanied by material mass transport through interfaces and grain boundaries which causes stress (usually compressive) relief. This is supported by the most remarkable aspect of the whisker growth; namely, that high aspect ratio Sn whiskers ~ 100-500 μm in length containing no brass can be grown from a ~ 0.6 μm thin film of Sn. View full abstract»
26. Power Device Packaging Technologies for Extreme Environments| | Quick Abstract | PDF (4465 KB) | | HTML
Silicon carbide is a wide-bandgap semiconductor capable of operation at temperatures in excess of 300degC. However, high-temperature packaging to interface with the other elements of the electrical system is required. Die attach, wire bonding, and passivation materials and techniques have been demonstrated for use at 300degC. Transient liquid phase bonding has been developed with Au:Sn/Au, yielding high die shear strength after 2000 h at 400degC. Large diameter (250 mum) gold and platinum wire bonding was evaluated for top side electrical contact. Au wire was reliable after 2000 h at 300degC with Ti/Ti:W/Au pads over passivation on the SiC. However, Au wire on Ti/Pt/Au and Pt wire on both Ti/Tl:W/Au and Ti/Pt/Au exhibited passivation fracture with aging. Polyimide has been demonstrated for 2000 h at 300degC in air as a high-voltage passivation layer. View full abstract»
27. Flip Chip Assembly of Thinned Silicon Die on Flex Substrates| | Quick Abstract | PDF (1921 KB)
Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented. View full abstract»
28. Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping| | Quick Abstract | PDF (1872 KB) | | HTML
Thin wafers of 100-μm thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass. View full abstract»
29. Performance of Printed Polymer-Based RFID Antenna on Curvilinear Surface| | Quick Abstract | PDF (885 KB) | | HTML
The performance of flexible printed RFID tags affixed onto cylindrical containers is dependent on the inductive behavior of the bent antenna on the tag. Conductive polymeric coil antennas were screen printed onto flexible substrates, and the coil resistances, the inductances, and the S-parameters of the antenna coils were measured and analyzed. The RFID dies were mounted onto the antenna coils and the read ranges were characterized as a function of curvature. The results show that the coil inductance decreased slowly with increasing curvature, and the maximum read range of the tags was markedly reduced with the curvature. The decrease in the coil inductance and the maximum read range were hypothesized to vary with the projected bent coil area instead of the geometric coil area. Experimental results confirmed that the maximum read range of an RFID tag affixed on a curvilinear surface can be predicted by the classical inductive coupling model with the bent projected coil area. On the basis of the experimental and analytical results, a reading reliability factor of two is proposed as a design parameter for flexible RFID tags. View full abstract»
30. A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages| | Quick Abstract | PDF (1519 KB) | | HTML
As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables View full abstract»
31. Sn Corrosion and Its Influence on Whisker Growth| | Quick Abstract | PDF (6865 KB) | | HTML
The microstructure and crystal structure of condensation-induced corrosion products, vapor phase induced oxidation products, Cu-Sn intermetallics, and Sn whiskers that formed on electroplated matte Sn on Cu-alloy after exposure 2500 h in a 60 degC/93%RH ambient were characterized with scanning electron microscopy, (SEM), focused ion beam (FIB) microscopy, energy dispersive spectroscopy (EDS), transmission electron microscopy (TEM), and selected area electron diffraction (SAD). The corrosion product was identified as crystalline SnO2. The oxidation of Sn in condensed water was at least four orders of magnitude larger than that in moist vapor at 60 degC. All Sn whiskers were found to be within 125 mum of the corrosion product. Based on these observations, a theory was developed. The theory assumes that oxidation leads to the displacement of Sn atoms within the film. Because the grain boundaries and free surfaces of the film are pinned, the oxidation-induced excess Sn atoms are constrained within the original volume of the Sn-film. The trapped excess Sn atoms create localized stress, excess strain energy, in the Sn-film. If and when the pinning constraint is relaxed, as for example would occur when the surface oxide on the film cracks, then the Sn atoms can diffuse to lower energy configurations. When this occurs, whisker nucleation and growth begins. The theory was tested by detailed measurements and comparison of the corrosion volume and the whisker volume in two different samples. The volume comparisons were consistent with the theory View full abstract»
32. Scheduling selective disassembly for plastics recovery in an electronics recycling center
High-value engineering plastics demand in the electronics industry reaches nearly 1.5 million tons annually. Since these plastics are derived from nonrenewable petroleum-based resources, research for scheduling of plastics-to-plastics recycling is warranted. Recent research has shown the feasibility of extending the reverse electronics supply chain, driven primarily by remanufacturing and metals recovery, to include plastics recovery. The extended recycling process adds plastic cover disassembly for separation of the majority of the plastics in electronics prior to bulk processes for metals separation. In anticipation of recovered plastics demand for product housings, we develop scheduling rules for plastics demand-driven disassembly processes and test them in a discrete event simulation model of a recycling center. In our experimental design, we vary disassembly scheduling rules, the mix of end-of-life electronic product arrivals, and plastics demand. Although the mix of incoming products has a significant impact on plastics recovery rate, our results demonstrate that the application of plastics demand-driven or supply-based disassembly scheduling rules perform similarly in maintaining metals and plastics throughput from consumer electronics. View full abstract»
33. Electrode sticking during micro-resistance welding of thin metal sheets| | Quick Abstract | PDF (1510 KB) | | HTML
The electrode sticking mechanism and factors affecting the sticking, including welding current, weld time, electrode tip coating, electrode force and electrode spacing, were studied during micro-resistance welding of very thin nickel-plated steel to nickel sheets in the assembly of a cell-phone battery package. The results indicated that electrode sticking was caused by local metallurgical bonding between the electrode and the nickel-plated steel sheet. The sticking force was proportional to the total area of the local bonds and to the bonding strength between the electrode and sheet. Reducing welding current and weld time, and increasing electrode force and electrode spacing were found to reduce electrode sticking. Welding electrodes with tips coated with TiC metal matrix composite were tried as an alternative to the regular CuCrZr electrode and were found to be more resistant to sticking. View full abstract»
34. Void Formation Study of Flip Chip in Package Using No-Flow Underfill| | Quick Abstract | PDF (1588 KB)
The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials. View full abstract»
35. Correlation of flip chip underfill process parameters and material properties with in-process stress generation| | Quick Abstract | PDF (1276 KB)
Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing View full abstract»
36. Geometric and Compaction Dependence of Printed Polymer-Based RFID Tag Antenna Performance| | Quick Abstract | PDF (750 KB)
Radio frequency identification (RFID) tags with printed antennas are lower in cost but have lower performance than those with metal antennas. Printed antennas can replace metal ones if the performance is increased without raising cost. The performance of printed antennas can be increased if the series resistance in the antennas is lowered. The resistance is dependent on the line thickness and the resistivity of the conductive ink. Printed antennas with different line thicknesses were fabricated to investigate the effect of compaction and thickness on the resistance. The resistance of the printed antenna coils decreased by more than 40% after compaction, while the inductance and the parasitic capacitance were unchanged. RFIDs with compacted printed antennas were found to have significantly increased read range. RFIDs with thick printed antennas were fabricated and tested. These RFIDs were shown to have read ranges comparable to the RFIDs with copper wire antennas. Moreover, a geometry-independent plateau for the read range was found. The presence of a plateau is valuable for thick-line printed antenna since the plateau will enable the usage of low precision printing techniques to lower tag fabrication cost. View full abstract»
37. Effect of the plasma cleaning process on plastic ball grid array package assembly reliability| | Quick Abstract | PDF (391 KB)
Interface delamination is recognized as one of the major failures of microelectronics packaging. It can result from various factors, including stresses from mismatch of adherent materials, hygrothermal stress from the release of vapor pressure of moisture during soldering reflow process, and interface material adhesion strength. The failure mechanisms are associated with cyclic loads, temperature and moisture condition as well as interface adhesion strength degradation. This paper focuses on the evaluation of plasma cleaning on PBGA assembly, including resistance to interface delamination. Two different plasma systems, powered by radio frequency (RF) and microwave (MW) energy, are studied. The optimized plasma cleaning process parameters are obtained by surface contact angle measurements. The plasma cleaning results are also verified by scanning electron microscopy (SEM) as well as physical pull and shear tests. The test vehicles are 27×27 mm 292-ball PBGAs. The results from encapsulation peel tests, die and encapsulant pull tests, bonding wire pull tests and C-Mode SAM (C-SAM) examination are presented. It is clear that an optimal plasma cleaning process can be achieved with different plasma systems. The experimental results also demonstrate that plasma cleaning has little effect on wire bonding process and die attach pull strength for given substrates and assembly materials. In all the cases, optimal plasma cleaning steps improve PBGA resistance against interface delaminations for cases where plasma cleaning is carried out before encapsulation process. Moreover, different plasma cleaning techniques would affect the assembly productivity, investment and yield. This paper demonstrates that the optimized plasma cleaning process would enhance PBGA package qualification level and improve the process yields and productivity. View full abstract»
38. Parameter Modeling for Wafer Probe Test| | Quick Abstract | PDF (1703 KB) | | HTML
This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test. View full abstract»
39. Fine-line conductor manufacturing using drop-on demand PZT printing technology| | Quick Abstract | PDF (430 KB) | | HTML
An emerging selective metallization process to fabricate fine-line conductors based on drop-on-demand (DOD) ink jet printing and novel nano-particle fluid suspensions (NPFS) was studied. The suspensions consist of 1-10 nm silver or gold particulates that are homogeneously suspended in an organic carrier. A piezo-electric droplet generator driven by a bipolar voltage signal is used to dispense 50-70 μm diameter droplets traveling at 1-3 m/s before impacting a compliant polyimide substrate. The deposit/substrate composite is subsequently processed at 300°C for 15 min to allow for complete evaporation of the carrier and for sintering of the nano-particles, thereby yielding a finished circuit interconnect. Test vehicles created using this technique exhibit features as fine as 120 μm wide and 1 μm thick with resistivities on the order of 3.5×10-5 Ωcm. The circuitry performed well under environmental conditioning. As expected, repeatability of circuitry fabrication showed sensitivity to the generation of steady, satellite-free droplets. In an effort to generate droplets consistently, it is essential to develop a strong fundamental understanding of the correlation between device excitation parameters and dispensed fluid properties, and to resolve the microrheological behavior of the NPFS when flowing through the droplet generator View full abstract»
40. Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board| | Quick Abstract | PDF (392 KB)
In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies View full abstract»
41. Tin Whisker Test Development—Temperature and Humidity Effects Part I: Experimental Design, Observations, and Data Collection| | Quick Abstract | PDF (5260 KB) | | HTML
The effects of temperature and humidity on tin whisker growth were investigated through a collaborative project sponsored by the International Electronics Manufacturing Initiative (iNEMI) and its member companies. A broad range of testing conditions was adopted to test a variety of components with matte tin (Sn) plating and copper (Cu)-based leadframes. The primary goal of the study was to collect data that could be used to develop mathematical models (acceleration functions) that describe the dependence of tin whisker growth and corrosion on temperature and humidity. This paper describes the background, experimental design, data collection and reports results. Part II of the study (J. W. Osenbach et a. ?Tin whisker test development-Temperature and humidity effects part II: Acceleration model development,? Electronics Packaging Manufacturing, Vol. 33, no. 1, pp., Jan. 2010) discusses in the data analyses and acceleration model development. Storage testing was performed over a wide range of temperature and humidity conditions from 30?C to 100?C and from 10% to 90% relative humidity (RH). Commercially produced components with both 3 ?m and 10 ?m thicknesses from three sources were evaluated. For components with the 10 ?m-plating, the plating was evaluated in both the as-plated and reflowed (260?C) conditions. These variations resulted in a large experimental matrix that included 13 different Sn platings, aged at ten different temperature and humidity combinations. Further, the aging test was done at five different laboratories with inspections performed at eight different laboratories. The data collected include 1) corrosion incubation time, 2) tin whisker incubation time, and 3) dependence of the maximum whisker length on storage time at each temperature/humidity condition. Data suggest that corrosion is not a unique driving force for whisker initiation and growth. Whisker formation differs in corroded and non-corroded regions. Due to the scope of this work, it is br- - oken down into two papers. The data and experimental observations are discussed in this paper. The mathematical model development, discussion of results and conclusions are included in Part II of this study. View full abstract»
42. Modeling of positive-displacement fluid dispensing processes
Dispensing has been widely used in industry to precisely control the delivery of fluid materials. Among several approaches, positive-displacement dispensing by employing the linear movement of a motor-driven piston is recognized as the most promising because the approach is assumed to be "true" volumetric dispensing. This is true for dispensing a large volume of fluid with continuous piston motion. As the volume of fluid decreases to the micro-liter range, however, this assumption is no longer valid because the fluid properties, in particular the compressibility and flow behavior, can have a significant influence on the volume of fluid dispensed. Taking into account the influence, This work presents the development of a model for the positive-displacement dispensing process. The model is then used to investigate the process performance, with the emphasis on identifying the influence of such factors as the fluid volume in a syringe, the needle temperature, and the fluid properties on the consistency in volume of fluid dispensed. View full abstract»
43. Solder Joint Reliability in Electronics Under Shock and Vibration Using Explicit Finite-Element Submodeling| | Quick Abstract | PDF (1982 KB) | | HTML
Modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric symmetry or loading symmetry. The problem involves multiple scales from macroscale transient-dynamics of electronic assembly to microstructural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling using a half test PCB board, shell-to-solid submodeling technique using a quarter-symmetry model. Inclusion of model symmetry in state-of-the-art models saves computational time but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and antisymmetric modes, which may dominate an actual drop-event. Approaches investigated include smeared property models, Timoshenko-beam element models, explicit submodels, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data View full abstract»
44. Processing and Characterization of Nanosilver Pastes for Die-Attaching SiC Devices| | Quick Abstract | PDF (1259 KB) | | HTML
Screen/stencil-printable nanosilver pastes were processed and characterized for die-attaching SiC devices. The nanosilver pastes were made by mixing silver particles in diameter with an organic binder vehicle. For the die-attachment, the nanosilver pastes were printed onto silver-coated or gold-coated direct-bond-copper (DBC) substrates. After die-attaching the SiC devices, the assemblies were heated to 300 with a 40-min dwell time to develop bonding up to 40 MPa on the silver-coated substrates, which was comparable to that of the Pb37Sn63 solder die-attachment. Scanning acoustic microscopy (SAM) of the sintered silver die-attachment did not reveal any detectable voids, while scanning electron microscopy (SEM) showed the presence of uniformly distributed microscale pores. Because of the porous microstructure of the sintered silver and its low apparent elastic modulus, it could help relieve thermomechanical stresses in the die-attachment assembly. Finally, since silver die-attachment is almost pure in constituent (>99%), the die-attachment could enable packaging of wide bandgap semiconductors devices, such as SiC or GaN, for high-temperature operation. View full abstract»
45. New techniques for the design of advanced ultrasonic transducers for wire bonding| | Quick Abstract | PDF (1078 KB) | | HTML
A new high-frequency ultrasonic transducer, in particular for the application wire-bonding, has been conceived, designed, prototyped, and tested. In the design phase an advanced approach was used and established. The method is based on the two basic principles of modularity and iteration. The transducer is decomposed in its elementary components. For each component an initial draft is obtained with finite-elements-method simulations (FEM). The simulated ultrasonic modules are then built and characterized experimentally through laser-interferometry measurements and electrical resonance spectra. The comparison of simulation results with experimental data allows the parameters of FEM models to be iteratively adjusted and optimized. The achieved FEM simulations exhibit a remarkably high predictive potential and allow full control on the vibration behavior of the ultrasonic modules and of the whole transducer. The new transducer is fixed on the welding device with a flange whose special geometry was calculated by means of FEM simulations. This flange allows the converter to be attached on the welding device not only in longitudinal nodes but also in radial nodes of the ultrasonic field excited in the horn. This leads to a total decoupling of the transducer to the welding device, which has so far been unheard of. The new approach to mount ultrasonic transducers on a welding-device is of major importance not only for wire-bonding but also for all high-power ultrasound applications. View full abstract»
46. The absorption ink transfer mechanism of gravure offset printing for electronic circuitry| | Quick Abstract | PDF (711 KB) | | HTML
The gravure offset method has been developed toward an industrially viable printing technique for electronic circuitry. In order to obtain the optimum ink resin for printing lines of required thickness (>5 μm) of narrow lines (down to 25 μm), several ink resin systems have been assessed in previous studies by the authors. The best printed results were obtained with a novel ink using a hydrocarbon resin. This ink did not comply with the traditional ink transfer mechanism based on evaporation of the solvent, but with a postulated new "absorption mechanism.". View full abstract»
47. Sn whiskers: material, design, processing, and post-plate reflow effects and development of an overall phenomenological theoryOsenbach, J.W. ; Shook, R.L. ; Vaccaro, B.T. ; Potteiger, B.D. ; Amin, A.N. ; Hooghan, K.N. ; Suratkar, P. ; Ruengsinsub, P.Page(s): 36 - 62| | Quick Abstract | PDF (8912 KB) | | HTML
Replacement of Pb/Sn terminations on electronic devices with pure Sn has proven to be much more difficult than expected. The main problem is Sn whisker formation. Sn whiskers are typically single-crystal, mechanically strong, metallic filaments that can nucleate and grow over time in such a way as to lead to device failure in the field. In this study, we present the results of Sn whisker formation and growth studies for plated matte-Sn on Cu Pb frames. We include data on the effects of Sn-thickness, post-plate annealing, and simulated board attach reflow. Also included are data on two different bath base chemistries, methane sulfonic acid (MSA) and mixed acid, three different plating bath suppliers, and three different lead-frame plating suppliers. The effects of trim and form as well as lead-frame alloy type were also investigated. Whisker testing was completed by storing devices for at least 1 year at room ambient, 60°C/93%RH, and 60°C/<10%RH. Additional tests were done by subjecting devices to temperature cycling between -55°C and +85°C. Finally, condensing environmental testing and bias/temperature/humidity tests were completed. The results indicate that the propensity for whisker formation and growth decreases with increasing Sn thickness, and with a post-plate heat treatment. The data imply that the improvement is one of increasing the incubation time, not one of complete elimination of the potential for whiskers. Analysis of the data also indicates the interpretation of Sn whisker formation and growth data taken from a small set of experimental conditions and or small number of devices or leads may lead to incorrect conclusions when compared to a larger data set. When taken in totality, no exact systematic dependency on the propensity for whisker formation was found between dependent variables of trim and formed and nontrim and formed lead frames or for stamped versus etched lead frames. With the exception of 60°C/93%RH exposure, no systematic interaction with process conditions and/or process/stress conditions were found. For stressing at 60°C/93%RH, there was a clear indication that the trim and form devices were significantly more susceptible to whisker formation than nontrim and formed devices. The pr- opensity for whisker growth was found to be similar at room ambient and 60°C/<10%RH. The propensity for whisker formation is lowest for the room temperature and 60°C/<10%RH storage, followed by temperature cycling, followed by noncondensing 60°C/93%RH storage. A condensing 60°C/93%RH environment was found to result in an accelerated corrosion assisted whisker growth mechanism producing locally dense clusters of whiskers or "flowers". No effects of electrical bias on the propensity for whisker growth were observed, and it is concluded that electrical bias itself does not appear to be a promary driving mechanism for Sn whisker growth. Finally, the application of a post-plate solder reflow is found to significantly impact the propensity for whisker growth. In particular, the incubation time for whisker growth in 60°C/93%RH was found to be of order 10-15 weeks for all devices subjected to a simulated board-attach reflow process at peak temperatures greater than 232°C. Whereas for devices not subjected to a simulated reflow, the incubation time was 26 weeks for 7-μm-thick films and 61 weeks for 15-μm-thick films. We have observed whisker growth on all samples independent of lead-frame alloy type, plating chemistry, and plating supplier. Finally, we have found that a Ni-underplate, if implemented correctly, eliminated whisker growth for at least 52 weeks at 60°C/93%RH independent of simulated reflow process. We present a model that reveals the improvements afforded by the post-plate anneal is one of extending the incubation time not one of complete elimination of whiskers. Finally, we propose a model tha View full abstract»
48. Time–Frequency and Autoregressive Techniques for Prognostication of Shock-Impact Reliability of Implantable Biological Electronic Systems| | Quick Abstract | PDF (2140 KB) | | HTML
In this paper, autoregressive and time-frequency-based techniques have been investigated to predict and monitor the damage in implantable biological electronics such as pacemakers and defibrillators. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in under variety of stresses in electronic systems. The approach is based on monitoring critical solder interconnects, and sensing the change in test-signal characteristics prior to failure, in addition to monitoring the transient strain characteristics optically using digital image correlation and strain gages. Previously, SPR based on wavelet packet energy decomposition and the Mahalanobis distance approach have been studied by the authors for quantification of shock damage in electronic assemblies ("Solder-joint reliability in electronics under shock and vibration using explicit finite element sub-modeling," P. Lall, et al. Proc. 56th ECTC, May-Jun. 2006, pp. 428-435, "Life prediction and damage equivalency for shock survivability of electronic components," P. Lall, et al. Proc. ITherm, May-Jun., 2006, pp. 804-816). In this paper, Autoregressive (AR), wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in implantable biological electronic systems. One of the main advantages of the AR technique is that it is primarily a signal-based technique. Reduced reliance on system analysis helps avoid errors which otherwise may render the process of fault detection and di- - agnosis quite complex and dependent on the skills of the analyst. Results of the present study show that the AR and TFA-based health monitoring techniques are feasible for fault detection and damage-assessment in electronic units. Explicit finite-element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff, and solder ball failure. View full abstract»
49. Surface Resistivity Characterization of New Printed Circuit Board Materials for Use in Spacecraft Electronics| | Quick Abstract | PDF (1505 KB) | | HTML
New dielectric materials have been introduced for printed circuit board applications, such as Thermount and polyimide with the aim to match the requirements for high speed and high density of electronic devices that are planned for new spacecraft electronic boards. Before these newer substrate can fully replace the well-known space-approved material epoxy FR-4, it is necessary to investigate more deeply their electrical and mechanical properties. The scope of this study is to report quantitative characterization of the surface resistivity for the different material samples under various testing conditions that include relative humidity, temperature, solder flux contamination, and corona discharge. The surface resistivity results are reported for sets of samples measured under a combination of testing conditions. View full abstract»
50. Application of Wide-Band Material Characterization Methods to Printable ElectronicsPynttäri, V.J. ; Makinen, R.M. ; Palukuru, V.K. ; Ostman, K. ; Sillanpää, H.P. ; Kanerva, T. ; Lepisto, T. ; Hagberg, J. ; Jantunen, HeliPage(s): 221 - 227| | Quick Abstract | PDF (2112 KB) | | HTML
In this paper, characterization methods are presented with results from test structures printed with varying printing parameters and materials. It is shown that different process parameters affect both physical and electrical material properties and hence high-frequency material characterization is a vital part of the process providing important information for design purposes. The conductivities and loss information of nanoparticle inks and properties of dielectric material are achieved in addition to structural properties. In particular, dc measurement results from 1.1e7 S/m to 3.7e7 S/m and high-frequency attenuation values from 0.5 dB/cm to 2.8 dB/cm (at 10 GHz) are achieved for printed conductors. View full abstract»
Aims & Scope
IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.
This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.
Meet Our Editors
R. Wayne Johnson
Auburn University
Further Links
Aims & Scope
This journal addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.
Persistent Link: http://ieeexplore.ieee.org/servlet/opac?punumber=6104 More »
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- Components, Circuits, Devices & Systems
- Power, Energy, & Industry Applications
R. Wayne Johnson
Auburn University
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Auburn, AL 36849 36849 USA
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Fax:+1 334 844 1898
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Previous Titles
- ( 1999 - 2010 ) Components and Packaging Technologies, IEEE Transactions on
- ( 1999 - 2010 ) Advanced Packaging, IEEE Transactions on
- ( 1999 - 2010 ) Electronics Packaging Manufacturing, IEEE Transactions on
- ( 1994 - 1998 ) Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on
- ( 1994 - 1998 ) Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
- ( 1996 - 1998 ) Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on
- ( 1978 - 1993 ) Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
- ( 1971 - 1977 ) Parts, Hybrids, and Packaging, IEEE Transactions on
- ( 1972 - 1977 ) Manufacturing Technology, IEEE Transactions on
- ( 1965 - 1971 ) Parts, Materials and Packaging, IEEE Transactions on
- ( 1963 - 1965 ) Component Parts, IEEE Transactions on
- ( 1963 - 1965 ) Product Engineering and Production, IEEE Transactions on
- ( 1961 - 1962 ) Product Engineering and Production, IRE Transactions on
- ( 1955 - 1962 ) Component Parts, IRE Transactions on
- ( 1956 - 1959 ) Production Techniques, IRE Transactions on
- 1954 - Component Parts, Transactions of the IRE Professional Group on
R. Wayne Johnson
Auburn University


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text:
Champions League: Takeaways From Round Of 16 Draw
On Monday morning, UEFA held the draw for the Champions League's Round of 16. The draw is significant on many levels. For starters, getting what is considered a favorable draw can help a team, especially one that is not one of the 'super teams' expected to have a deep run in the competition. One needs to look no further than 2012-13 finalists Borussia Dortmund as an example of what a favorable draw in the Round of 16 can do for a team.
With all that mind, the eight Round of 16 matchups each offer their own unique storylines and at the same time, we can infer a number of takeaways. The first is that a few teams, in particular a couple of English teams, paid the price for not doing what was necessary in order to finish first in their respective groups.
Both Manchester City and Arsenal find themselves drawn into ties against two of Europe's elite teams, as Manchester City will play against FC Barcelona while Arsenal take on Bayern Munich in a rematch of a Round of 16 tie from last season. The moment each of these two finished their games and found themselves as group runner-ups, they knew there would be a distinct possibility that they would have to faceoff against a tough team in the Round of 16.
On the other end of the spectrum, two teams who ended up with favorable Round of 16 draws because they took care of business by winning their respective groups are Atletico Madrid and Paris Saint-Germain. Atletico will play against a struggling AC Milan while PSG will get Bayer Leverkusen, and given that both those teams are good and capable, these matchups should not trouble Atletico and PSG if they play their best games.
The final takeaway from the draw is that two high-profile teams who have had their struggles were also given favorable draws, which will help them aspire to reach the quarterfinals and beyond. The two teams are Borussia Dortmund, who take on Zenit St. Petersburg and Manchester United, who will take on Olympiacos.
While both Dortmund and Manchester United have had their struggles for different reasons, they most likely let out a sigh of relief when they found out whom they will take on when the competition resumes in the middle of February 2014.
Lucas Carreras is a contributing Soccer and San Francisco 49ers writer for RantSports.com. You can follow Lucas on Twitter by following him @maldini3fan and you can add him to your network on Google.
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text:
AVI-SPL And JBL Professional VLA Line Arrays Blaze Audio Trails At The Rose Garden
Demonstrating the ease of installation and even dispersion of JBL VLA line arrays, leading audio video products and services provider AVI-SPL oversaw the redesign of the audio system at the Rose Garden, home of the NBAâs Portland Trail Blazers. The new system features six line array clusters of VLA loudspeakers.
The redesign of the audio system at the Rose Garden was a part of a major capital improvements project that included a new video scoreboard, powered by a state-of-the-art HD control room. The improvements also included a facelift of the Rose Gardenâs main concourses, restaurants, party suites, as well as upgraded LED stats boards and auxiliary scoreboards.
To meet these heightened entertainment standards, AVI-SPL needed a loudspeaker system that would provide powerful, controlled sound while retaining a visually discrete appearance. âIf we had gone with a central cluster approach, the scoreboard would not have been able to recess all the way into the ceiling,â? said Nathan Thomas of AVI-SPL. âWe needed the scoreboard and loudspeakers to be located completely above the rigging points on the low steel frame so they could hold different kinds of events that used other rigging points.â?
Because of their combination of power and flexibility, AVI-SPL opted for JBL VLA line arrays, installing six line array clusters. The two side arrays are each comprised of eight VLA901 loudspeakers, while the four corner arrays each include six VLA601 and two VLA901 array modules. âWe chose the VLA loudspeakers knowing that we would need a highly controllable system,â? Thomas said. âThe VLAâs offer that controllability, and the horizontal splay angles drove us to ultimately go with that product.â?
Building on the proven success of the legendary JBL VERTEC® line array series and Precision Directivity® series, VLA (Variable Line Array) series loudspeakers are designed for permanent installations requiring high-impact sound reinforcement at throw distances beyond the reach of traditional loudspeaker designs. The VLA Series includes six large format horn-loaded modules with three horizontal horn coverage patterns (30, 60 and 90 degrees). This modular horn-loaded concept incorporating JBLâs Precision Directivity series technology provides system designers additional flexibility to vary the horizontal pattern within a vertical array. This can be achieved by incorporating different modules with wider or narrower coverage patterns while still maintaining consistent vertical directivity.
According to Thomas, the system has performed beyond expectations since being installed. âThe coverage is spectacular and the clarity is very good. With the current setting, we can get the system up to 115 dB with another 10 dB of headroom,â? he said. âThe main operator at the arena said itâs one of the clearest systems heâs ever heard, and I tend to agree.â?
JBL is a unit of Harman International Industries, Incorporated (www.harman.com). Harman International designs, manufactures and markets a wide range of audio and infotainment products for the automotive, consumer and professional markets, and maintains a strong presence in the Americas, Europe and Asia, employing more than 11,000 people worldwide. The Harman International family of brands includes AKG®, Audioaccess®, Becker®, BSS®, Crown®, dbx®, DigiTech®, Harman Kardon®, Infinity®, JBL®, Lexicon®, Mark Levinson®, Revel®, QNX®, Soundcraft® and Studer®. Harman Internationalâs stock is traded on the New York Stock Exchange under the symbol âNYSE: HAR.â?
To read more or to download images, please click here.
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text:
Winnipeg Free Press - ONLINE EDITION
Motorcycle crash kills man and woman
Both people involved in a motorcycle crash Friday have now died, Brandon RCMP report.
On Friday at about 3 p.m., Brandon RCMP and local emergency services were dispatched to the scene on the Trans-Canada Highway at the intersection of Highway 270.
The motorcycle was westbound on the Trans-Canada Highway when it was in collision with a van that was southbound on Highway 270.
There were two riders on the motorcycle, a man and woman. Both were taken to hospital. The man, a 26-year-old from the Selkirk area, died from his injuries Friday.
His passenger, a 25-year-old woman from Winnipeg, died in hospital.
Neither of their names will be released.
The driver of the van, a man, was transported to hospital with undetermined injuries.
There were no other vehicles or persons involved.
Highway 270 is controlled by a stop sign at the location of the collision.
Police continue to investigate.
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