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US 4262497 A Abstract Multi-element transparent gemstones comprising pleochroic materials are provided which evidence enhanced colors or other unusual optical properties, based on the pleochroic behavior of the material. Doublet stones, comprising two pleochroic materials, and triplet stones, comprising two pleochroic materials separated by an optical rotator, are described. The multi-element gem may have a rotatably mounted pleochroic element or a rotatably mounted optical rotator.
Claims(15) 1. A multi-element transparent gemstone comprising an optically active rotator element disposed between two pleochroic elements, each element being fixedly mounted to the adjoining element said elements being arranged, relative to each other, in a manner so that the color displayed by individual ones of said pleochroic elements is modified in the combination at least through the action of said rotator element.
2. The gemstone of claim 1, including a pleochroic element at each end, wherein each of said end pleochroic elements is contiguous to the adjoining element at a substantially planar mating face, each of said mating faces being substantially parallel to the other and having substantially in its plane a principal optical direction, the principal optical direction in the mating face of the element at one end being substantially aligned with the principal optical direction in the mating face of the element at the other end.
3. The gemstone of claim 7, wherein said optically active rotator comprises alpha-quartz.
4. The gemstone of claim 3, wherein said alpha-quartz is cut perpendicular to its c axis and has a thickness of at least about 0.5 mm.
5. A multi-element transparent gemstone comprising at least two pleochroic elements having different crystal orientations, including a pleochroic element at each end, wherein each of said end pleochroic elements is contiguous to the adjoining element at a substantially planar mating face, each of said mating faces being substantially parallel to the other and having substantially in its plane a principal optical direction, the principal optical direction in the mating face of the element at one end forming with the principal optical direction in the mating face of the element at the other end an angle within the range of about 20 160 pleochroic elements is modified in the combination, each element being fixedly mounted to the adjoining element.
6. The gemstone of claim 5, wherein the principal optical directions in the planes of the mating faces form with each other an angle within the range of about 60
7. The gemstone of claim 5, wherein said pleochroic elements are independently selected from the group consisting of alexandrite, andalusite, axinite, beryl, chrysoberyl, cordierite, dichroite, emerald, epidote, kyanite, peridot, ruby, sinhalite, spodumene, tourmaline, and zoisite.
8. The gemstone of claim 7, wherein said pleochroic elements are independently selected from the group consisting of alexandrite and tourmaline.
9. The gemstone of claim 5 comprising two pleochroic elements.
10. The gemstone of claim 9, wherein said pleochroic elements comprise alexandrite which contains about 0.005 to 1.0 atom percent chromium in place of aluminum, the mating face of each said element having substantially in its plane the b crystal axis of that element.
11. The gemstone of claim 9, wherein one element comprises tourmaline cut with its mating face having substantially in its plane the c crystal axis and the other element comprises alexandrite cut with its mating face having substantially in its plane the b crystal axis.
12. A multi-element transparent gemstone comprising at least two pleochroic elements having different crystal orientations, including a pleochroic element at each end, wherein each of said end pleochroic elements is continuous to the adjoining element at a substantially planar mating face, each of said mating faces being substantially parallel to the other and having substantially in its plane a principal optical direction, one of said end pleochroic elements being disposed, relative to the remainder of the gemstone, in continuously variable rotational configuration about an axis normal to its mating face.
13. The gemstone of claim 12, wherein said pleochroic elements are independently selected from the group consisting of alexandrite, andalusite, axinite, beryl chrysoberyl, cordierite, dichroite, emerald, epidote, kyanite, peridot, ruby, sinhalite, spodumene, tourmaline, and zoisite.
14. The gemstone of claim 12 additionally comprising an optically active rotator element disposed between two pleochroic elements.
15. The gemstone of claim 14, wherein said optically active rotator element comprises alpha-quartz.
Description This is a continuation-in-part of copending application Ser. No. 870,386, filed Jan. 18, 1978. 1. Field of the Invention This invention relates to gemstones and, more particularly, to multiplet gemstones, such as doublets and triplets, which incorporate pleochronic crystals. 2. Description of the Prior Art Many of the well-known gem minerals are pleochroic. That is, a single piece of such a material exhibits various colors, depending on the direction of viewing and/or the polarization direction of the illuminating light. The fundamental effect involves the polarization direction of the light. The viewing angle dependence in unpolarized light arises from the elimination of light polarized parallel to the viewing direction, since light waves are purely transverse excitations. These effects arise in non-cubic, optically uniaxial or biaxial crystals from the influence of an anisotropic host crystal structure on the transitions between electron energy levels of the impurity ions which give rise to the color. Well-known gem crystals which exhibit pleochroism to a greater or lesser extent include alexandrite, andalusite, axinite, beryl, chrysoberyl, cordierite, dichroite, emerald, epidote, kyanite, periodot, ruby, sinhalite, spodumene, tourmaline and zoisite. In the course of cutting crystals of these minerals to obtain faceted gem stones, it is well-known that often one must control the crystallographic orientation of the stone to obtain the desired color in the finished gemstone, or alternatively, that the color of the finished gem may be varied to some extent by varying the crystallographic orientation. This is particularly important, for example, in the faceting of certain types of tourmaline. Such a stone cut with the table (top) facet parallel to the c plane may appear nearly opaque or black, while the same stone cut with the table facet perpendicular to the c plane exhibits a desirable blue or green color. Similarly, certain cordierites may appear nearly colorless in certain orientations and deep blue in others. Multiplet gemstones have been used in the past for various purposes. For example, D'Esposito in U.S. Pat. No. 1,745,607, issued Feb. 4, 1930, describes doublet stones in which two components of natural beryl are cemented together with a transparent cement incorporating an appropriate coloring agent to produce a composite stone exhibiting the color of emerald. In this way, the refractive properties of beryl, which resemble those of emerald, are combined with the color of the intervening colored cement. However, if an originally pale or colorless beryl is formed into a colored composite gem by means of a colored cement, the resultant composite is pleochroic only to the extent that the original stone was colored, D'Esposito's contrary implication notwithstanding. Other attempts to alter or control the optical properties of gemstones have been employed. For example, Boone, in U.S. Pat. Nos. 2,663,171 and 2,699,706, issued Dec. 22, 1953 and Jan. 18, 1955, respectively, discloses a variety of combinations of birefringent, polarizing and reflecting layers over and/or under transparent supporting elements. These layers provide rainbow-like interference colors, which Boone refers to in his claims as "variegated." The choice of angle (e.g., 45 polarizing and birefringent directions affects the extent of the rainbow effect. The support element generally makes no direct contribution to the color, although Boone does disclose that a dye could be incorporated in the supporting element to modify the interference colors. None of Boone's embodiments provides a gemstone with a "pure color"; i.e., transmission in a narrow wavelength band. In highly doped natural or synthetic alexandrite, the daylight green color is often obscured by red overtones, especially in thicker sections. Cline et al. in U.S. Pat. No. 3,912,521, issued Oct. 14, 1975, disclose addition of iron as an impurity as a means of improving the daylight green coloration of highly doped synthetic crystals of larger size. However, we have observed that this method is not totally effective. The present invention is directed to the improvement or modification of the color displayed by pleochroic materials, either alone or in various combinations, by constructing multi-element gemstones comprising these materials, natural or synthetic. The unique features of this invention result from joining into a multielement gemstone pleochroic elements having different crystal orientations. Since light transmission in these crystals depends in general or crystal orientation, a multiplet comprising elements having different orientations possesses light-transmitting properties, and, consequently, color characteristics, not matched by singlets. One embodiment of this invention comprises a gemstone including a pleochroic element at each end, wherein each of said end pleochroic elements is contiguous to the adjoining element at a substantially planar mating face, each of said mating faces being substantially parallel to the other and having substantially in its plane a principal optical direction, the principal optical direction in the mating face of the element at one end forming with the principal optical direction in the mating face of the element at the other end an angle within the range of about 20 160 Each element of a gemstone may be fixedly mounted to the adjoining element. Alternatively, an attractive gemstone also results when a pleochroic element at one end is disposed, relative to the remainder of the gemstone, in continuously variable rotational configuration about an axis normal to its mating face. Constructions comprising an optical rotator element sandwiched by pleochroic elements may also be used to obtain the unique color characteristics of this invention. The optical rotator element may be included in gemstones having all elements in fixed relation to one another or in gemstones having a rotatable pleochroic element at one end. FIG. 1 is a plot of the absorption spectra of synthetic alexandrite in polarized light; and FIG. 2 is a diagrammatic sectional view of a doublet gemstone construction. One of the most spectacular of the pleochroic minerals is alexandrite, BeAl.sub.2 O.sub.4 containing chromium ion (Cr.sup.3+) as an impurity. It is one of the few trichroic minerals, that is, exhibiting three distinct colors corresponding to the three possible polarization directions of light traveling through its orthorhombic cystal structure. We use the crystal lattice parameter assignment of Farrel et al. in American Mineralogist, 48, 804-810 (1963), where a=0.9404 nm, b=0.5476 nm and c=0.4427 nm. A polished cube of alexandrite containing about 0.05 to 0.1 atom percent chromium substituted for aluminum and having dimensions of about 1 cm on an edge, when viewed in transmission in unpolarized daylight, appears blue or purplish-blue in the a direction, orange or reddish-orange in the b direction and green or reddish-green in the c direction. FIG. 1 shows the polarized absorption spectra which give rise to these colors in a typical piece of synthetic alexandrite. FIG. 2 depicts a doublet gemstone of this invention in cross-section. A top or crown portion 1 is disposed in effectively fixed relation to a lower or pavilion member 2. Mating faces 3 of parts 1 and 2 are first lapped and polished prior to bonding portions 1 and 2 together. A suitable bonding agent may be any transparent, colorless, strong adhesive, such as epoxy, Canada balsam, polymethyl methacrylate, cyanoacrylate or other material known in the art. Other agents requiring the application of heat, such as low melting-point glasses or polymers, may also be used. The gem cut may be any of the type usually employed, such as brilliant-cut, emerald-cut, or other cuts employing facets to produce a stone pleasing to the eye. The faceting is generally done such that the planar mating faces lie parallel to the table facet and near the girdle of the stone. Some care may be required during facet grinding and polishing to avoid damage to the glue joint from excessive mechanical force or heat, since the joint may not be as strong or as heat resistant as the gem material. In accordance with one aspect of the invention, the three crystal directions, a, b and c, of an alexandrite crystal (natural or synthetic) are first determined by means of visual inspection, optical methods or X-ray diffraction. The crystal is then cut in two parallel to the c crystal plane (i.e., perpendicular to the c direction) to form two c-axis plates. The cut mating faces are polished flat and held in contact in their original orientation. One of the pieces is then rotated with respect to the other through an angle θ about an axis normal to the mating faces. When viewed in transmission along said axis, the stone demonstrates a dramatic change in color from reddish or reddish-green with no rotation to a blue-green color for θ about 20 coloration is produced over the range of about 60 accordingly, that range is preferred. Alternatively, a stone may be cut parallel to the a crystal plane to form two a-axis plates, in which case a relative rotation of a plate by about 90 color. The angle of rotation again may vary from about 20 160 60 case of both c-axis and a-axis plates, the b axis lies in the plane of the mating face. However, if a stone is cut in two perpendicular to the b axis (i.e., a b-axis plate), little or no color change results from rotation. It is sometimes desirable to combine a-axis and c-axis plates in a single multiplet. In this case, the color varies from blue-green, when the b directions of the two plates are at 90 when the b directions are parallel. The principle which underlies this invention may be understood by considering first the light absorption process in general and the absorption process in alexandrite in particular. The intensity of light transmitted by an absorbing medium is given by I/I.sub.o =e.sup.-αx where I.sub.o is the incident intensity, I the transmitted intensity, α the absorption coefficient, and x the absorber thickness. Consider a beam of unpolarized white light incident normally on the face of a c-axis plate of alexandrite. Within the plate, the light is resolved into two orthogonally polarized beams, one with E//a and the other with E//b. (No component of E//c is transmitted in the c direction.) Viewed separately (as with a polarizer), the E//b beam appears deep blue-green because of the relatively strong absorption of this beam in the orange spectral region near λ=0.6 μm (FIG. 1). The E//a beam, viewed separately, appears yellow because of the absorption of this beam in the blue (between 0.40 and 0.45 μm). Both beams are transmitted with little absorption in the blue-green (λ�0.5 μm) and red (λ>0.65 μm) spectral regions. the ratio of blue-green light intensity, I.sub.g, to red light intensity, I.sub.r, is less than one and is given by I.sub.g /I.sub.r =e.sup.-(α.sbsp.g.sup.-α.sbsp.r.sup.)x, where the subscripts g and r refer to the above-mentioned wavelengths. For small values of x (i.e., for thin sections of crystal) the intensity ratio is nearly 1 and the crystal appears green, because the eye is more sensitive to green light than to red. As the section thickness (or dopant concentration) is increased, however, the ratio becomes smaller, and increasingly thicker crystals appear increasingly red. The undesirable red overtones are enhanced by the high transmission of orange-red light by the E//a beam, which passes appreciable orange-red light even in thick crystals. Of course, the spectrum of transmitted light depends on the spectrum of incident light as well. Thus, a crystal may appear either green under illuminations such as skylight or fluorescent light, which are rich in green, or red under illuminations such as candle-light or incandescent light, which are rich in the red and poor in the blue-green spectral regions. However, with a given illuminant, the blue-green coloration can only be deepened to a very limited extent by increasing the thickness and/or dopant concentration, since the crystal will thereby be made redder, obscuring the blue-green color. We overcome this limitation in the present invention. If an alexandrite c-axis plate is cut in two along a plane perpendicular to the c direction and the two elements held in the original orientation, the light absorption properties are substantially unchanged from those of the uncut plate. If, however, one element is rotated relative to the other about the c-axis (normal to the mating faces), the light absorption, and consequently the color, changes. We can understand this by considering the effect of the two elements successively. As discussed above, incident light is resolved into two orthogonally polarized beams E//a and E//b. In passing through the first element, orange light (λ�0.6 μm) is strongly absorbed in the E//b beam but absorbed very little in the E//a beam (FIG. 1). Blue light (λ�0.40-0.45 μm) is strongly absorbed in the E//a beam and also absorbed to an appreciable extent in the E//b beam as well. If the second element is rotated 90 relative to the first element, as shown in FIG. 2, then the polarizations of the two transmitted beams are interchanged as they pass from the first element into the second. The beam which was E//a in the first element and was transmitted with relatively low absorption of orange light becomes E//b in the second element and experiences strong orange absorption. As a result, much less orange light is transmitted than was transmitted by the singlet or the "unrotated" crystal. The beam which was E//b in the first element and experienced appreciable blue light absorption becomes E//a and experiences stronger blue absorption. As a result, somewhat less blue light is transmitted than was transmitted by the unrotated sample; however, the reduction in blue transmission is not as great as the reduction in orange light. Blue-green light (λ�0.5 μm) is passed with little absorption. The rotated doublet of FIG. 2 thus appears green as greater thickness/dopant concentrations than does a singlet or unrotated doublet. The deep green color achieved by the rotation cannot be achieved in a singlet by any combination of thickness and dopant concentration. Natural or synthetic alexandrite doublet gem-stones constructed as described above exhibit a strikingly pure daylight green coloration while still possessing the characteristic raspberry or columbine red color of alexandrite when illuminated by incandescent light or light from a wood fire, oil lamp or candle. In general, optimal coloring of a pleochroic doublet results when the crown contains a higher level of doping than the pavilion, because the crown section of the stone is generally thinner than the pavilion section and therefore requires deeper coloring. For example, the daylight green color of alexandrite can be enhanced most effectively by using two natural or synthetic c-axis plates as described above, in which the crown contains from 1 to 5 times as much chromium as the pavilion. The chromium concentration of the alexandrite crystals should, in general, be in the range of from about 0.005 to 1.0 atom percent substitution of chromium for aluminum ions. The preferred concentrations for gems with final dimensions of about 0.2 to 2 cm in diameter are about 0.06 to 0.6 atom percent in the crown and about 0.02 to 0.2 atom percent chromium in the pavilion. Furthermore, high doping levels, up to 1.0 atom percent and higher (substitution of Cr.sup.3+ for Al.sup.3+ in BeAl.sub.2 O.sub.4) can be used to obtain very deep green colors. Such high concentration levels inevitably cause serious or complete degradation of the green color in conventional singlet alexandrite gems. A number of desirable color modifications similar to those described above can be achieved by the method of this invention using other pleochroic crystals instead of or in addition to alexandrite. One such case involves a doublet comprising a plate of c- or a-axis alexandrite cemented to a plate of tourmaline cut so that the tourmaline c axis lies substantially in the plane of the plate. Certain varieties of tourmaline, which exhibit an undesirable yellowish-green color alone, can be made to change to a deep pure emerald green color by rotating the tourmaline plate relative to the alexandrite plate about an axis normal to the plates, the strongest effect occurring when the tourmaline c axis lies parallel to the alexandrite b axis. Similarly, certain other tourmaline varieties, known collectively as watermelon tourmaline because they contain regions of both red and green color in the same crystal, can be combined in the doublet configuration with the a- or c-axis alexandrite plates in such a way as to increase the depth and contrast of their unique coloration. This is particularly useful in the case of lightly colored material which is otherwise of good quality but appears pale and low in color contrast. Again, the effect is maximized when the tourmaline c axis lies parallel to the alexandrite b axis. The color of certain varieties of aquarmarine, morganite, beryl and ruby can be adjusted by combining them with dichroic plates of tourmaline or cordierite in doublet configurations as described above, with the rotation angle being adjusted to produce the desired color. The effects discussed above for a pleochroic doublet can also be produced using an optically active rotator element disposed between two pleochroic elements. This variation relies on the known optical rotatory power or optical activity of α-quartz (and certain other compounds of the same crystal structure, such as berlinite) to rotate the polarization directions of light beams traveling in the quartz. A beam of linearly polarized light traveling parallel to the c axis in a crystal of α-quartz undergoes a progressive rotation of its plane of polarization, depending on the distance traveled and the wavelength. (Generally, in a given path length, light of short wavelength is rotated more than light of longer wavelength). An alexandrite-quartz-alexandrite triplet illustrates a preferred embodiment of this aspect of the present invention. It will be recalled that an alexandrite doublet comprising suitably oriented c-axis plates transforms the E//a beam in one element into the E//b beam in the other element, thus causing greater absorption of light in the λ�0.6 μm spectral region than would take place without the invention. In the present invention, the rotational transformation is accomplished by the use of a quartz c-axis plate interposed between two plates of similarly oriented alexandrite. The thickness of the quartz plate is chosen to produce a rotation of approximately 90 transforming the E//a beam into the E//b beam) for 80 �0.6 μm. The rotatory power in this region is about 20 required thickness is about 4.5 mm. In practice, we have found that thinner quartz plates (0.5 mm and up) can also be used if the balance of the rotation is accomplished by rotation of one alexandrite element relative to another about an axis normal to its mating faces. As a practical matter, the maximum thickness for a quartz plate employing in triplet gem-stones is about 10 mm. The preferred position of the quartz plate in the finished gem is generally near the girdle. The chromium concentration ranges and ratios discussed above in connection with alexandrite doublets also apply to multiplets which include optical rotators. An alexandrite doublet gem was constructed as follows. Two polished c-axis plates of synthetic alexandrite, one containing 0.3 atom percent chromium and the other containing 0.1 atom percent chromium, were cemented together using Devcon 5-minute epoxy glue with a 90 that the a axis in one plate lay parallel to the b axis in the other plate. After allowing adequate time for the epoxy to cure, the composite was formed into a standard brilliant-cut gem by conventional lapidary diamond grinding and polishing techniques. Using the traditional crown and pavilion angles for alexandrite, the crown plate, containing 0.3 atom percent Cr.sup.3+, had a final thickness of 1.53 mm, and the pavilion plate, containing 0.1 atom percent Cr.sup.+3, had a final maximum thickness (at the culet or point) of 4.58 mm. The glued joint in the finished gem was parallel to the table or top facet and at the level of the girdle or widest diameter of the gem. The finished gem had a girdle diameter of 9.8 mm, a total height, from table to culet, of 6.1 mm and a weight of approximately 0.8 g (4 carats). The color of the finished gem was deep green by daylight or fluorescent light and deep raspberry red when illuminated by an incandescent bulb or candlelight. Two standard emerald cut alexandrite gems were produced following the general procedures outlined in Example 1. In this case, both the crown and pavilion elements were c-axis synthetic alexandrite plates containing 0.05 atom percent Cr.sup.3+. Both stones had final width and length dimensions of 10 and 12 mm, respectively. In the first stone (stone A), the a axis of the pavilion plate was parallel to the width (short dimension) of the finished gem, as was the b axis of the crown plate. In the second stone (stone B), the b axis of the pavilion element and the a axis of the crown element were both parallel to the width dimension; i.e., the reverse of stone A. Both stones appeared raspberry red under incandescent light or candlelight and green in daylight. The daylight tint of stone A, however, was decidedly bluish-green, while that of stone B was more of a pure green. In this example, a doublet combined two different pleochroic materials to produce a unique effect. A dichroic natural andalusite crystal and a crystal of the blue, strongly pleochroic variety of cordierite (also known as iolite or dichroite), were placed together with the surface perpendicular to the orange-appearing direction in the andalusite crystal (containing the optical X direction) contacting the surface perpendicular to the blue-appearing direction in the cordierite crystal (also containing the optical X direction). (The optical X direction is the polarization direction of light with the smallest index of refraction.) Rotation of the elements such that the optical X directions of both crystals were parallel produced a violet color by daylight illumination, which changed to red under incandescent light. Thus, a color change with illumination was produced. A standard emerald-cut gemstone measuring 6 these elements using the general procedures outlined in Example 1. The crown plate was formed from the andalusite crystal with the polished surface perpendicular to the orange-appearing direction in the crystal so that the polished surface contained the optical X direction. The pavilion plate was formed from the cordierite crystal in such a way that the optical X direction of the crystal lay in the plane of the plate. The plates were cemented together so that the optical X directions of both crystals lay parallel in the finished gem and along the long dimension. The finished gem was a pleasing violet color by daylight illumination, changing to red under incandescent light. In this example, a quartz rotator plate was used to accomplish a part of the rotational transformation of polarizations in an alexandrite-quartz-alexandrite triplet. Two cubes of alexandrite, 8 mm on edge, with edges oriented parallel to the a, b and c directions, were placed on either side of a 4 mm thick c-axis α-quartz plate such that faces perpendicular to the c axis of the cubes contacted with faces perpendicular to the c axis of the plate. Alignment of the cubes such that their a axes were parallel produced the characteristic green color under daylight illumination and the characteristic raspberry red color under incandescent illumination, when viewed along the c axis. A standard brilliant-cut gemstone was prepared as follows. A crown plate of c-axis synthetic alexandrite containing 0.15 atom percent chromium was cemented to one side of a 2 mm thick c-axis α-quartz plate. To the other side of the quartz plate was cemented a pavilion plate of c-axis synthetic alexandrite containing 0.05 atom percent chromium and oriented with its a axis rotated 45 direction producing the characteristic color change (the direction of rotation required depends on whether right or left-handed rotating quartz is used). The composite so produced was then fabricated into a 15 mm diameter brilliant-cut gemstone, with the quartz plate parallel to the table facet and centered at the girdle plane. The resulting gem appeared the characteristic green color in daylight when viewed at right angles to the tablet facet, but changed to reddish-orange when rotated by a small angle. Under incandescent illumination, there was a decided color change to the characteristic raspberry red color. Patent Citations
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text: Patent ReferencesReconfigurable hardware emulation system Method and apparatus for debugging reconfigurable emulation systems Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus Virtual interconnections for reconfigurable logic systems Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation Transition analysis and circuit resynthesis method and device for digital circuit modeling Routing methods for use in a logic emulation system Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation InventorsAssigneeApplicationNo. 11056961 filed on 02/11/2005US Classes:703/23, EMULATION703/27, Compatibility emulation703/20, Target device703/17, Event-driven714/727, Boundary scan714/733, Built-in testing circuit (BILBO)714/724, Digital logic testing716/17, Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)703/28, In-circuit emulator (i.e., ICE)714/735, Device response compared to input pattern716/16, PLA, PLD, FPGA, OR MCM713/400, SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES703/25, I/O adapter (e.g., port, controller)714/33, Derived from analysis (e.g., of a specification or by stimulation)326/39, Array (e.g., PLA, PAL, PLD, etc.)716/12, Routing (e.g., routing map, netlisting)714/725, Programmable logic array (PLA) testing703/24, Of peripheral device703/16, Event-driven703/13, SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM326/41, Significant integrated structure, layout, or layout interconnections716/6, Timing analysis (e.g., delay time, path delay, latch timing)703/14, Circuit simulation716/4, Testing or evaluating710/317, Crossbar710/22, Direct Memory Accessing (DMA)307/87, Attainment of voltage, frequency or phase relationship375/141, End-to-end transmission system326/93, CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES702/108, TESTING SYSTEM714/48Error detection or notificationExaminersPrimary: Thangavelu, KAttorney, Agent or FirmInternational ClassG06F 9/455DescriptionBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to automation and validation techniques for designing electronic circuits. In particular, the present invention relates to automation and validation techniques for designing electronic circuits that are particularlyapplicable to system-on-a-chip type electronic circuits. 2. Description of the Related Art As the level of integration advances, many complex logic systems can now be implemented on a single integrated circuit. Such an integrated circuit, known as "system on a chip", includes a number of complex components (e.g., micro-processor,peripheral and memory controllers), many of which may be individually obtained as "off-the-shelf" electronic circuit designs from a number of vendors. These electronic circuit designs are known as "IPs1" to those skilled in the art. In the prior art, debugging a system that includes a user design integrated with one or more third party IPs is difficult, as the designer of the user design often does not have complete control over the IPs timing and logical behavior at theinterfaces between the user design and the IPs. For example, incorrectly behaving output signals of the user design may cause unpredictable behavior in the IPs, which may in turn be fed back into the user design to cause unpredictable states in the userdesign. Such errors are extremely difficult to diagnose and isolate. Thus, a design tool that provides the designer of the user design control over the interfaces between the user design and the IPs is desired. 1The term "IP" stands for"intellectual property." Designers of these electronic circuits provide the designs to their customers in the form of data files which are readable by popular electronic design automation (EDA) tools. The customers of these vendors then integrate these"IPs" into their own circuit designs. As an IP vendor does not provide a manufactured article--the electronic deign is typically provided as data represented in electronic form (e.g., stored in a storage medium, such as a compact disk, or as a stream ofbits downloaded from a server on the internet)--it has become customary in the art to refer to such electronic circuit design products as "IPs". SUMMARY The present invention provides a method and a system using a reconfigurable platform for designing and emulating a user design. The method of the present invention is particularly suited to an IP re-use methodology, such as system-on-a-chip typeuser design, in which a user's own design is implemented with the user's own design and frequently also with third party IPs. The present invention may be implemented on a platform including memories and a number of field programmable logic devices,such as programmable gate arrays. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design. According to one embodiment of the present invention, the system for designing and emulating a user design includes (i) a system controller having an interface to a user workstation and a data communication interface; and (ii) an emulationplatform coupled to the data communication interface having multiple field programmable logic devices and memories for implementing the user design and third party IPs, and an interface to a target system with which the user design interacts at run time. The data communication interface may include a configuration bus, a system utility bus, and a bus for clock signals. The interface to a target system includes signals originating from programmable input/output terminals of the programmable logicdevices. According to one embodiment of the present invention, using the system for designing and emulating the user design, a user generates a top-level module including the user design and one or more third party IPs. The user then synthesizes the userdesign. The user design and the third party IPs are then integrated into partitions each suitable for implementing in one or more of the programmable logic devices. In addition, each programmable logic device and each IP is assigned an interfacemodule. Through the interface module, each IP to be implemented in a programmable logic device is allowed communicate within any partition in that programmable logic device or with other partitions in other programmable logic devices. The partitionsand the interface modules are then placed and routed and implemented in the programmable logic devices. According to one embodiment of the present invention, the interface module assigned to each IP or each programmable logic device includes a control circuit and a programmable number of input/output cells, each providing a 1-bit interconnectionport. In that embodiment, each input/output cell includes a dynamically reconfigurable memory module, a multiplexer for selecting an output signal for output onto the 1-bit interconnection port from selected signals configured in the programmable logicdevice, and a number of latches each selectable to receive a signal from the 1-bit interconnection port. The multiplexer and the latches may be controlled by the words stored in the dynamically reconfigurable memory module, which may be implemented byone or more dynamically reconfigurable memory elements, and accessed by addresses generated by a state machine (e.g., a counter). The dynamically reconfigurable memory module may operate using a clock signal of a higher frequency that the clock signalsused by the user design. The interface module may be used to implement an output port, an input port, a bidirectional port or a tristate port. In addition, the port type implemented in the interface module may be dynamically changed. The interface module can also beconfigured to isolate the IP assigned to a programmable logic device from partitions in the same or other programmable logic device according to specified testing or debugging conditions (e.g., during boundary scan operations). According to one embodiment of the present invention, one or more of the programmable logic devices may be assigned a verification IP for verifying functional operation of the user circuit. Such a verification IP may include, for example, acircuit for simulating the operations of an industry standard data bus. According to another embodiment of the present invention, one or more of the programmable logic devices may be assigned a performance analysis IP, which may include, for example, an IP or a bus for bandwidth analysis. According to one embodiment of the present invention, the system may provide a configuration tool capable of dynamically reconfiguring logic circuits assigned to a selected programmable logic device. The configuration tool may also include abackplane configuration tool capable of dynamically reconfiguring buses on a circuit board on which the programmable logic devices are located. According to one embodiment of the present invention, the system may provide a system debugging tool for monitoring and analyzing signals in and between the programmable logic devices during run time. The system debugger tool may include an FPGAread back tool, a system utility bus access tool, an internal logic analyzer tool, a bandwidth analyzer tool, a symbol/transaction extraction tool, and a simulator linkage tool. The internal logic analyzer tool inserts into one or more of theprogrammable logic devices a circuit implementing a logic analyzer. The symbol/transaction extraction tool allows a user to associate one or more signals with a symbolic name and to specify a transaction involved multiple signals. The transaction maybe specified by the signal transitions in the waveforms of the signals over a selected duration. The debugging tool is capable of reporting detection of the specified transaction using the associated symbols. The simulator linkage tool allows the userdesign to interact with a simulator program running on the user station in a co-emulation arrangement. The present invention is better understood upon consideration of the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows SR prototyping system 100, in accordance with one embodiment of the present invention. FIG. 2 is a block diagram of system controller 102 of SR prototyping system 100. FIG. 3 shows one example of a schematic configuration of SR FPGA array 103. FIG. 4 shows an exemplary flow of a compiler program, in accordance with one embodiment of the present invention. FIG. 5 shows waveforms for a convention "write" transaction in a storage device. FIG. 6a shows schematically a system-on-chip design 620 including both user design circuits and IPs are partitioned into circuits 625-1 to 625-n, associated with TAI-IPs 626-1 to 626-n, respectively, in accordance with one embodiment of thepresent invention. FIG. 6b is a block diagram showing TAI IPs 601-1 to 601-n, when implemented in SR FPGA array 103, serving as interfaces among FPGAs 602-1 to 602-n. FIG. 7 is a block diagram of a TAI IP 700, according to one embodiment of the present invention. FIG. 8 shows TAI IP cell 800, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows electronically reconfigurable prototyping system 100, in accordance with one embodiment of the present invention. As shown in FIG. 1, electronically reconfigurable prototype system 100 includes scalable reconfigurable (SR)prototyping platform 103, which may be implemented by one or more arrays of field programmable gate array (FPGA) integrated circuits. SR prototyping platform 103 interacts with a target system 104 (i.e., the system with which the prototyped system isexpected to interface) over programmable input/output terminals 105, which are driven, for example, from the pins of the FPGA integrated circuits. SR prototyping platform 103 is controlled by system controller 102 over one or more data buses. In thisembodiment, the data buses include system configuration bus 108, system utility bus 107 and clock bus 106. System configuration bus 108 is provided for configuring the FPGA integrated circuits, system utility bus (SUB) 107 is provided to allow datacommunication between system controller 102 and SR prototyping platform 103 during system operations (e.g., prototyping), and clock bus 106 provides one or more time bases to operate SR prototyping platform 103. User station 101 provides a graphical user interface to a human user for controlling the operations of electronically reconfigurable prototyping system 100. Through the graphical user interface, a user of user station 101 may typically access auser design, a compiler for transforming a user design to configuration signals for SR prototyping platform 103, various IP libraries, various electronic design automation (EDA) software, and runtime software. User station 101 may be implemented by anengineering workstation or a personal computer. In this embodiment, user station 101 communicates with system controller 102 through industry standard communication interface 109, which may be implemented, for example, by a USB, PCI, IEEE-1394("fire-wire") or another industry standard bus. In this embodiment, a user design may be entered or edited using conventional circuit schematic tools or expressed in a behavior or hardware (e.g., circuit level) description language (e.g., HDL, SystemC, Verilog, SystemVerilog, SystemVHDL,VHDL), which may then be used to synthesize into a logic gate level schematic. The present invention allows the synthesized circuits to be emulated or verified in a hardware prototyping system, such as electronically reconfigurable system 100. FIG. 2 is a block diagram of system controller 102, which includes communication interface 204, SUB controller 202, clock generator 203 and configuration controller 201. Configuration controller 201 handles configuration signal protocols andtransfers configuration data from user station 101 to SR FPGA array 103 over configuration bus 108, so as to configure or down-load a user design in a preferred format to the FPGAs in SR FPGA array 103. Configuration bus 108 is also used to read backthe design in each FPGA for verification purpose and to retrieve state information and data in the user design during runtime. Typically, read back operations are performed using conventional techniques or using vendor provided protocols, such asSelectMap and JTAG. In one embodiment, configuration bus 108 may be used to test the FPGAs in scalable FPGA array 103 in prototyping system 100. SUB controller allows SUB 107 run-time access to registers, FIFOs, memories and other state elements in design and system specific components, such as special logic blocks (e.g., IPs) inserted to user design by compiler software. SUB 107 mayalso be used to reset or initialize the FPGAs in SR FPGA array 103 to designated working states. Clock generator 203 drives clock bus 106 to provide FPGA array with various clock signals of programmable frequencies and duty cycles to be used by the user design downloaded into SR FPGA array 103. As mentioned above, SR FPGA array 103 may be implemented using one or more scalable backplanes or circuit boards, FPGAs and dynamically configurable circuit switches. SR FPGA array 103 may contain any number of FPGAs and switches. FIG. 3 showsone example of a schematic configuration of SR FPGA array 103. As shown in FIG. 3, shows SR FPGA array 103 implemented by FPGA 304-1 to 304-n. Every of FPGAs 304-1 to 304-n has more than one connection to other FPGAs. In this embodiment, one or morebuses (e.g., buses 301-3032) are provided for interconnecting FPGAs 304-1 to 304-n. In this manner, signals can be routed from any FPGA to any other FPGA. Buses 301-303 may be configured as "global buses" (i.e., buses to which each FPGA is givenaccess). Alternatively, buses 301-303 also may be assigned in various configurations, so that each bus can be programmed to be dedicated to a selected group of FPGAs. The buses may also be interconnected with each other dynamically configurable circuitswitches. These circuit switches may be provided by custom switch circuits or configured into FPGAs 304-1 to 304-n. The FPGAs can also be configured into a hierarchical structure in which the FPGAs may be grouped, such that the FPGAs in each group areinterconnected by a "local" connection bus, and these local connection buses are interconnected with each other by one or more levels of dynamically reconfigurable switches. In addition, each FPGA may have one or more input or output (I/O) signals thatare provided on I/O bus 105 for communicating signals to and from target system 104. These I/O signals may also be interconnected through one or more levels of dynamically configurable switches to allow data communication among the FPGAs. However, thenumber of connections is not limited as technology improves and advances. Preferably, the interconnection buses and switches are implemented on one or more backplanes or circuit boards. Alternatively, any interconnection bus (e.g., any of buses301-303, configuration bus 108, SUB 107 or clock bus 106) may also be implemented by cables, optical fibers or other means of interconnection. 2 FIG. 3 shows three buses, buses 301-303. This number of buses is provided solely for illustrativepurpose. Any number of buses may be used in any implementation. A complex digital system (e.g., a system-on-a-chip (SoC) design or an application-specific circuit) typically includes multiple sub-systems. For example, an SoC design may include such subsystems as a multi-media sub-system, a signal processingsub-system, a peripheral controller sub-system, and a central processor. Each sub-system may be configured into, for example, a selected group of FPGAs interconnected by a common local bus. Dynamically configurable switches may then be used to couplethe common local bus to other buses in the system. The common local bus may also be a global bus configured to be in an "off"-mode (break connection), so as to dedicate the common local bus for use within the sub-system. Switches between local busesmay be configured in an "on"-mode for intercommunication between sub-systems. Global bus may be used for communication between sub-systems or point-to-point communication between FPGAs. To implement a user design into SR FPGA array 103, a compiler is invoked in user station 101. FIG. 4 shows an exemplary flow of a compiler program, in accordance with one embodiment of the present invention. As shown in FIG. 4, at step 401, asystem designer may invoke a top-level module generator to generate a top-level module for the user design, which may include custom design components and 3rd party IPs. This top-level module generator, which facilitates integration of variousdesigns and IPs from both the user's own library and 3rd party vendors, automatically connects user design components and 3rd party IPs using standard bus definitions and user defined bus and signal connection relationships. Alternatively, asystem designer may also manually create the top-level module without using an automatic top-level module generator. At step 402, a system or circuit designer causes the compiler (e.g., using a "import design" command) to import the designs of each component in the top-level module. The design is typically expressed in a hardware description language (HDL) ora netlist. The compiler checks the design for syntax, synthesizability and completeness (i.e., whether or not all logic components included in the design source are available or linkable in a predefined library or a database of logic representations). If an error exists in imported design or a logic block is not available in the library, the compiler software reports an import error. Step 402 may be performed as many times as necessary, until all input sources are checked and accepted by compiler. After the design is imported, at step 403, the designer may synthesize all remaining hardware descriptions (HDL or other formats) in the design using, for example, a "synthesize" command in the compiler or a 3d party synthesis tool callable bythe compiler. In one embodiment, the compiler synthesizes a third party IP in a bottom-up fashion to preserve the block signal boundaries of the third party IP and to preserve the run time performance. The synthesized design consists then of netliststhat can be used to configure the FPGAs in SR FPGA array 103 (e.g., EDIF files). In one embodiment, the compiler merges all the EDIF files into one EDIF file to represent the user design. In this embodiment, at step 404, after a design is synthesized, the designer may invoke a "symbol-definition" command in the compiler to start a symbol-definition process. In the symbol definition process, a user may define as a symbol anyindividual signal, or group of signals. Of significance is that any number of signals may be defined in one symbol. In addition, a user may also define a transaction, which is a set of events, or waveforms of arbitrary duration, for a specified groupof symbols or signals. When the state transitions of the signals or the symbols match the specified waveforms within a specified time period defined for the transaction, the transaction is deemed to have taken place. For example, FIG. 5 shows waveformsfor a convention "write" transaction in a storage device. As shown in FIG. 5, the "write" transaction involves the signal waveforms of a group of five symbols: individual signals "clk", "write", and "chipselect" and buses "address" and "data". In thisexample, the transaction has a two-cycle duration, shown in FIG. 5 as cycles 1 and 2 between time 0 ns to 100 ns. During this time, the "chipselect" and the "write" control signals are both asserted for one cycle of the "clk" signal. The waveforms ofthe specified signals within the two clock cycles define the transaction. To detect the occurrence of the transaction, prototyping system 100 may be configured to monitor the specified signals at run time and to compare the signal transitions to thepredefined signal transitions for the transaction. Unlike the prior art, when the transaction is detected, the software reports user the occurrence of the transaction, rather than a collection of signal states that are left to the user to decipher. Inthis manner, the transaction is reported to the user at a high-level abstraction, which may be used in debugging. In one embodiment, the signals states are sampled and stored in an on-board memory, or in a memory or file image on user station 101, toallow further analysis. The symbols and transactions defined are particular useful in debug mode, and the same signal comparison and transaction detection processes are performed during debug mode as in the run time described above. A circuit designermay define as many symbols and transactions as needed, so that a large amount of run time signal information may be specified at a high level for debug purpose. Symbols and transactions defined during debug can be transferred to allow observation andmanipulation during runtime. At step 405, a user may use a "partition" command in the compiler to partition the design into partitions of the user design, each partition being intended for implementation in a single FPGA. Third party IPs are also partitioned forimplementation in FPGAs. A large IP may be partitioned into more than one FPGA. In one embodiment, the partition command invokes a third party partition tool. Because of the interconnection scheme using the "TAI IP cell" described below, a partitiontool in prototyping system 100 can optimize partitioning according to an objective of maximizing the utilization of FPGA capacity, without being constrained by FPGA pin usage. The partitioner generates a separate netlist for each FPGA in SR FPGA array. Partitioning step 405 preserves all design information and functions of the user design. Alternatively, 3rd party partitioners or manual partition may be used to partition the design. The partitioner may allow constraints to be specified, whichguide the partitioner to generate a netlist that targets the intended hardware of SR FPGA array 103. At step 406, after a user design is partitioned, the compiler inserts into the netlist of each FPGA partition a customized circuit structure that is designed to provide "testability", "analysis" and "interconnection" capabilities. Thiscustomized circuit structure, called "TAI IP," is also inserted with each IP, or each portion of an IP partitioned into an FPGA. The resulting circuit topology is shown in a logical view in FIG. 6a. As shown in FIG. 6a, a system-on-chip design 620including both user design circuits and third party IPs are partitioned into circuits 625-1 to 625-n, each being with TAI-IPs 626-1 to 626-n, respectively, in accordance with one embodiment of the present invention. Each of circuits 625-1 to 625-n iseither a partition of a user design circuit to be implemented in an FPGA, an IP, or a portion of an IP to be implemented in an FPGA. In some instances, a partition of a user design may be assigned to the same FPGA. Each of circuits 625-1 to 625-ncommunicate with each other through their associated TAI IPs 626-1 to 626-n over one or more communication buses or channels, shown schematically as buses 630-1 to 630-2. (Although only two buses are shown in FIG. 6a, the communication channel mayconsist of a single bus or more than two buses, depending on user preference and the connectivity among the circuits). FIG. 6b is a block diagram showing TAI IPs 601-1 to 601-n, when implemented in SR FPGA array 103, serving as interfaces among FPGAs 602-1 to 602-n. As shown in FIG. 6b, each TAI IPs of an FPGA is connected to other TAI IPs of other FPGAs toprovide interconnectivity among the FGPAs of SR FPGA array 103. With respect to the IPs, each IP in an FPGA communicates with circuits assigned to that FPGA and with other circuits in other FPGA through its associated TAI IP. Under this arrangement,input into and output from an IP may be controlled through the TAI IP. For example, each output signal of the IP can be isolated from the user design and signal states be substituted in their stead for debugging purpose. In addition, the input andoutput signals of the IP can be independently monitored to improve testability, FIG. 7 is a block diagram of a TAI IP 700, according to one embodiment of the present invention. As shown in FIG. 7, TAI IP 700 includes control circuit 701, which controls TAI IP building block circuits ("TAI IP cells") 702-1 to 702-n. Thenumber of TAI IP cells in each TAI IP is a programmable design parameter, typically defined according to the number of FPGAs on a FPGA array board to be interconnected, the input and output requirements of the user designed, and user specification. EachTAI IP cell is connected to a bus on the circuit board of SR FPGA array 103 through 1-bit interconnection port (e.g., one of interconnection ports 703-1 to 703-n). Based on these requirements, the compiler determines the number of the TAI IP cellsrequired and generates the required TAI IP cells and control circuit in the TAI IP of each FPGA. FIG. 8 shows TAI IP cell 800, in accordance with one embodiment of the present invention. As shown in FIG. 8, TAI IP cell 800 includes dynamically reconfigurable tag memories 801 and 802, signal multiplexer 803, bi-directional buffer 806(including output buffer 806a and input buffer 806b) and signal latch 807. Dynamically reconfigurable tag memory 801 controls the multiplexing of both data output signals 808 and corresponding output enable (OE) signals 805. Data output signals 809 andcorresponding output enable signals 805 include the output signals in the user design configured in the FPGA, and signals at specified internal logic nodes. In addition, constant signals 8103 (including a constant "0" and a constant "1") may alsobe selected by signal output multiplexer 803 for transmission over interconnection port 703. Under this arrangement, one signal output is provided on interconnection port 703 at any given time. Unassigned signals in data output signals 809 may beconnected to any arbitrary values. As described below, such an arrangement allows incremental signal configuration at run time without full recompilation. Unused OE Signals are assigned to an unasserted signal state, so as to prevent unintentionallyoutputting a value onto interconnection port 703 at any time. Dynamically reconfigurable tag memory 802 controls a set of signal latches, each of which can be selected to latch the input signal on interconnection port 703. As discussed above, interconnect port 703 receives signals from other FPGAs throughover one bit of an interconnection bus. The output signals of signal latches 807 drive signals 808, which are coupled to input ports of elements in the user design. Unassigned signals in input signals 808 may be left disconnected. Both dynamically reconfigurable tag memories 801 and 802 are addressed by signals from control counters, so that dynamically reconfigurable tag memories 801 and 802 can be loaded from SUB bus 107 during run time. Multiplexer 804 controls thedirection of bi-directional buffer 806, thereby determining whether interconnection port 703 is an input port, an output port or a bi-directional port. The select signals at multiplexer 804 can be dynamically changed during run time to reconfigure theport type during run time. In the embodiment shown in FIG. 8, multiplexers 803 and 804 select from the same number of signals and are controlled simultaneously by the same control signals from dynamically reconfigurable tag memory 801. In thisconfiguration, corresponding signals input to multiplexers 803 and 804 are selected. Such an arrangement is, of course, not necessary. Multiple multiplexers, controlled from different fields of an output word of dynamically reconfigurable tag memory801 may be used to select from design output signals 809 and OE signals 805. A tri-statable output port may be implemented by providing the data output signal as one of signals 809 and the corresponding OE signal as the corresponding one of OE signals 805. A high impedance state is achieved when the corresponding OEsignal is de-asserted. Similarly, a bi-directional port may be implemented by providing the bi-directional signal simultaneously as one of data output signals 809 and data input signals 808, and the corresponding OE signal as one of OE signals 805. Thecompiler ensures that the bidirectional port is correctly mapped, so that the corresponding locations in dynamically reconfigurable tag memories are always selected simultaneously. In one embodiment, the bi-directional signal is mapped into thelocations of the same address in dynamically reconfigurable tag memories 801 and 802. 3The constant signals may be used to isolate the user design on the FPGA during certain test or debug operations (e.g., in a test mode using boundary scan). A TAI IP (e.g., any of TAI IP 601-1 to 601-n) may operate from a faster clock than the user design. The faster clock increments or decrements the counter or counters which generate the addresses for accessing dynamically reconfigurable tagmemories 801 and 802. Each counter has a programmable maximum or minimum count. Typically, when the maximum or minimum count is reached, the counter wraps around when the upper limit is reached, the counter is reset to zero. When the counter is resetat least once within a clock cycle of the user design clock, input and output of the signals from the user design and signals to be latched are appropriately accomplished. In this embodiment, the maximum or minimum count in each of the counters isprogrammable at run time by through SUB 107, so that the number of signals interchanged in each faster clock cycle can be varied dynamically. Because dynamically reconfigurable tag memories 801 and 802 may be written by the user or by runtime softwarethrough SUB 107, the signals output to or input from interconnection port 703 may be determined dynamically on a user clock cycle basis. This capability allows signal values or connection to be varied during testing or debug. After the TAI IPs are inserted, at step 407, the compiler invokes place and route processes to operate on the netlist of each FPGA. The place and route processes are typically FPGA vendor-specific programs that translate each netlist into a fileof a binary format or an ASCII format. The output file can be down-loaded then into the FPGAs of SR FPGA array 103. In one embodiment, the place and route processes are run on more than one user station or processor to allow the FPGA place and routetasks to run in parallel. The place and route binary or ASCII output files may be stored in user station 104 for further runtime software processing. An IP library may be provided which includes, in addition to TAI IP, other IPs designed for circuit verification, circuit debug, and performance analysis functions. A system designer may include one or more such IPs to be included in a userdesign. Inclusion may be accomplished by a system designer directing the compiler to include such IPs or by manually instantiate the IPs in the source code for the user design. IP intended for circuit verification ("Verification IPs") may include such circuits for simulating a USB bus or PCI bus, so as to allow verification of the user design's operation with connected to a USB bus or PCI bus. Verification IPs used inprototyping system 100 allow the user or run time software to access operational information provided by the verification IP creators or vendors over SUB 107. Typically, verification IPs monitor activities in the user design, check compliance withstandardized communication or signal protocols, or compare the activities against a specified activity pattern ("golden pattern"). Verification IPs may provide analysis reports and error or warning information to the user or run time software. IPs intended for debugging purpose ("Debug IPs") include, for example, IPs implementing an internal logic analyzer ("Internal Logic Analyzer IP") or a flow/state analyzer. These IPs allow a system designer to debug the configured system atruntime. For example, an Internal Logic analyzer IP may be used at specified trigger points to sampling the values of signals in the user design and store them to memory elements for subsequent analysis. Runtime software may access and manipulate theseDebug IPs at runtime. IPs intended for performance analysis ("Performance Analysis IPs") may IPs for bandwidth analysis. These IPs are used to gather performance information and analyze the performance of the user design. As with the other IPs, Performance AnalysisIPs may communicate over SUB 107 with the user or runtime software to accomplish a performance analysis. The runtime software in prototyping system 100 may include a dynamic configuration tool set and a system debugger tool set. The dynamic configuration tool set receives user commands to configure the FPGAs of SR FPGA array 103, the backplane andthe TAI IPs to modify the operation modes, interconnections and even design functions at runtime. In one embodiment, in response to an FPGA configuration command, a FPGA configuration tool reads binary or ASCII FPGA configuration files and transfers thefiles to configuration controller 201 in system controller 102. This FPGA configuration tool may configure one or more FPGAs in SR FPGA array 103 separately, or even part of an FPGA, as required. For example, the user may modify a logic block in oneFPGA. The modified logic block may be downloaded to the FPGA using the FPGA configuration tool, without reconfiguring any other FPGA. In response to a backplane configuration command, a backplane configuration tool configures the configurable switches on a circuit board or backplane of SR FPGA array 103. Typically, any switches may be configured into an "on" state or an "Off"state. When a switch is in an "on" state, conductors coupled by the switch are connected. When a switch is in an "off" state, conductors coupled by the switch are electrically isolated from each other. The backplane configuration tool may be used, forexample, to selectively configure portions of interconnection buses into local buses. In response to a TAI IP configuration command, a TAI IP configuration tool generates data to be stored in one or more dynamically reconfigurable tag memories in the TAI IP cells over SUB 107. The data may represent interconnections between FPGAsor user requirements. For example, a user may wish to provide a value "1" at an input signal of a specified FPGA without recompilation. To accomplish this result, the TAI IP configuration tool re-calculates the tag memory word to implement the inputsignal, and writes the modified tag memory word to the selected dynamically reconfigurable tag memory. The system debugger tool set gathers and analyzes design and debug information, and sets special conditions and signals to manipulate the operation of the user design at runtime. In one embodiment, the system debugger tool set includes (a) anFPGA read back tool, (b) a SUB access tool, (c) an internal logic analyzer tool, (d) a bandwidth analyzer tool, (e) a symbol/transaction extraction tool and (f) a simulator linkage tool. The FPGA read back tool reads at run time the content of a specified FPGA or the states of specified signals in the user design. The FPGA read back tool may be obtained from a vendor, and may use a vendor-specific protocol, such as JTAG orSelectMAP, to read the content of a specified FPGA. Many FPGA vendors provide a tool to read any register or memory element in an FPGA. In this embodiment, after the data is read back from the FPGA, the FPGA read back tool translates the informationread to signal values and map the information to the signal names and symbols in the user design. In this way, full visibility of any signal inside an FPGA is easily achieved. The SUB access tool is used to access components, whether in the user design or included by prototyping system 100, connected to SUB 107. Components are address-mapped, so that access is accomplished by the SUB access tool reading and writingdata into the components by providing commands, addresses and data to SUB controller 202 in system controller 102. In one embodiment, SUB 107 is extended to allow reading and writing data into any component on a circuit board of SR FPGA array 103. The internal logic analyzer tool sets trigger conditions in a logic analyzer embedded in prototyping system 100. The logic analyzer is a specialized IP ("Logic Analyzer IP") down-loaded into one or more of the FPGAs in SR FPGA array 103. TheLogic Analyzer IP may be provided the same functions as a conventional logic analyzer. With the TAI IPs in the FPGA, the Logic Analyzer IP can provide samples of a large number of signals and handles a large number of trigger conditions. In oneembodiment, the internal logic analyzer tool sets trigger conditions at the embedded Logic Analyzer IP, waits for a trigger condition or event to happen, reads the signal sample data from embedded sample memory of the Logic Analyzer IP, and translatesassociates the sample data with the user defined symbols. In one embodiment, the internal logic analyzer tool sets a complicated event state machine embedded in the Logic Analyzer IP. The event state machine operates according to the event statemachine to sample signal data for a debugging purpose. The internal logic analyzer tool, along with the Logic Analyzer IP, gives user the ability to monitor signals at run time conditions (e.g., an in-circuit mode operation), without interfering withthe runtime operation of the user design. The bandwidth analyzer tool analyzes the bandwidths of all system buses in SR FPGA array 103. The bandwidth analyzer tool gathers bus activity information from a "Bandwidth Analysis IP," which may be configured with the user design as required. The bandwidth analyzer tool analyzes and reports bandwidths, bus access latencies, arbitration overheads of the system buses. In one embodiment, the results may be displayed graphically, such as in a multi-dimensional graph. The symbol/transaction extraction tool interprets the symbol and transaction level information from sampled signal data. The symbol/transaction extraction tool maps symbols and transactions from the sampled signal data and presents them to theuser in a symbolic format. For example, in the bus "write" transaction described above, when the symbol/transaction extraction tool detects an instance of the "write" transaction, a message is created for the user indicating the time of occurrence ofthe bus "write" transaction, the write address and the write data involved in the transaction. This capability is valuable, for example, to a firmware designer in designing and debugging firmware programs. The simulator linkage tool links a simulator running on user station 101 with the configured user design in SR FPGA 103 to perform a hardware/software co-emulation. The simulator linkage tool can handle simulators accessible through variousknown interfaces. For example, in one embodiment, a PLI or VPI interface is provided for communication with Verilog simulators, a FLI interface is provided for communicating with VHDL simulators and a SCEMI interface is provided for communicating withsimulators with SCEMI interfaces. Other standard interfaces or user-defined interfaces may also be supported. The above detailed description provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. Thepresent invention is set forth in the following claims. * * * * * Field of SearchOf instructionCompatibility emulation Event-driven Target device Boundary scan Built-in testing circuit (BILBO) Digital logic testing Error detection or notification Attainment of voltage, frequency or phase relationship Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES End-to-end transmission system TESTING SYSTEM |


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Britney Spears went on another post-intervention shopping spree today -- barely covering her lady parts in a sheer white top.
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Let's face it, if Brit hadn't been pushed to perform as a child, she would have ended up as a prostitute living in a trailer park somewhere. Money can't buy class - she's proof positive of that!
That sheer top was completely see-through and she knew it. How long before she puts out some kind of sex tape?. This girl is a total basket case and we are only seeing the beginning of how bad she is.
She only wore the jacket going in to the store because she probably knew there was a chance, however slight, that someone might have called the police for her indecent exposure.
well she is the top story once again. maybe she is just fine and playing us all for some negative attention? my nephew does it all the time but he is six....his parents fall for it, as we are falling for this daily fake story. She is just a self-promoting twit who shops, parties, misses work and lost her kids and can't show up to court to get them back, She is not mental, she may not even be on drugs , but she is lead entertainment story for two years straight and that speaks volumes...
I think it is quite obvious that she suffers from post-partem depression. She was not this maniacal until the kids were born and they were almost vorn back to back. Then she has K F*ckup in her life and out chasing poon when she was pregnant. He is no saint here just ask my wife, right honey? These jerk offs, Lufti and Adnan would have not be any where near her if she had the mental stability that she had before the kids. WHY is she not being treated for this? Who the hell is her doctor? L. RonTom Cruise?????
whatever!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! like i said she loves all the media in her face. She just had to take off the jacket right before she gets in the car for everyone to see her boobs thur her shirt. Like any celeb. would ever wear that. Stop being a trashy hoe britney.
Ok, enough is enough. I've had it with "I be-a flashin' my boobies & my cooter, y'all" DUMBASSney. What a slutty skank. Good thing she has all that money; it's the only thing she's going to have left after this whole mess is over & done with...
I see her hurting herself in the future ,if not worst...Its sad but she hasn't hit bottom. for some of us it takes a little longer...
Hi Shelly long time no see.....
Damn Brit. I've never been a fan of yours, but I have to say I felt sorry for you last night as a human being. Now you're back to the same ole same ole again. Whats it going to take for you to wake up and get your butt as far away as possible from all the paps? Go for a nice vacation for a couple of weeks , stay at home for awhile, or better yet move away and let your family help you. If you don't trust or want anyone help you then for god sakes help yourself! You still have a chance at getting your boys back if you stop all the chaos, admit you have problems and be accountable them, and get help. Sam and Adnan are both toxic people for you to be around right now. Anyone who tries to turn you against your family is no good! Please wake up!!! Its getting old seeing you attract all of this negative attention to yourself. The paps I agree are getting out of hand and I'm sure it isn't easy on you- but wheather you realize it or not, you are also contributing to pimping yourself out to them. At least try to get well Brit, use all of your energy and smarts to help you take charge of your life!
OMG, she deserves everything she gets. She took her coat off just to show off her boobies. What a skank!
WHY OH WHY do idiot people who see her whoring around on the streets scream "i love you Britney" ?? I mean, really. You love a woman who has lost ALL visitation and custody of her kids? You love a woman who cant be bothered with going to court? You love a woman who cant take care of her physical or mental health? You love a woman who shows her dirty snatch to whoever will look? Really..you have to yell out how much you love her? Its you sicko fans that are feeding her delusions that she is still admired. people should be throwing stones at her ..not complimenting her.
She is followed everywhere she goes because people like "you" and like "me" somehow enjoy watching her. She has probably gone nuts from years of stalking abuse!
Just when I might be feeling sorry for her something comes up like this and I come to my senses. I know I'm guilty of clicking on Brit stories and I can't stop. Its like watching a trainwreck..I know I should not watch but its so hard to look away. Seriously, Jenna the porn star covers up more when she goes out. :(
#44 She wouldnt be stalked if she kept her ass at home! Send assistants to pick up your crap. Take a friggen vacation in some remote island. She isnt stalked...she BEGS for attention..and thats what they give her. She acts crazier and crazier in public so they WILL follow her and hound her more. Shes a needy skank. If i saw her on the street id throw a tomato at her. Hmmph see if i care.
This really reminds me of a book I once read....about the custody battle over heiress gloria vanderbilt.
Gloria was a child and everyone fought over her due to the wealth she was going to inherit...and the custody battle consumed the American media during that time. Gloria was tossed back and forth and everyone around her had a huge battle and she remained lost and confused being tossed around and a pure pawn of money. Concern for her well being was lost in the drama of it all.
No Britany isn't a child, but with her mental state she may as well be, and the public battle over who will take charge of her is playing out to be the same


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CapitaLand China, a subsidiary of Singapore property group CapitaLand, has acquired a residential site in Sunjia, Ningbo for S$232 million.
SINGAPORE: CapitaLand China, a subsidiary of Singapore property group CapitaLand, has acquired a residential site in Sunjia, Ningbo for S$232 million.
The 57,370-square-metre site has been secured through a government land tender.
CapitaLand plans to build about 1,100 units of small and medium-sized units on the site, catering to both first-time homebuyers and upgraders.
Construction for the project is expected to begin in Q3 this year, with the first phase targeted for launch in 2015.
The site is also near CapitaLand's two other projects in Ningbo -- the Raffles City Ningbo and Summit Residences.
Raffles City Ningbo is a mixed-use development which was opened in 2012.
Meanwhile, residential project Summit Residences launched its Phase 2 at the end of 2013.
CapitaLand China's chief executive officer Jason Leow said in a statement: "Ningbo is China's second-largest port with residents' disposable income that is comparable to Shanghai's.
"Ningbo belongs to one of the five city clusters that CapitaLand is focused on, namely Shanghai/Hangzhou/Suzhou/Ningbo, Beijing/Tianjin, Guangzhou/Shenzhen, Chengdu/Chongqing, and Wuhan."
- CNA/gn
Tweet Photos, Videos and Update on this Story to #cna


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Curtis Woodhouse fulfills an important promise on his glory night in Hull
It was getting late in Hull, and the chants of "Yorkshire, Yorkshire" echoed throughout the Ice Arena crowd in a passionate rendition tinged with hope. The locals were witnessing something special. Their man,Curtis Woodhouse, was taking it to the British junior welterweight champion, Darren Hamilton. On paper, it doesn't seem anything out of the blue. These kinds of title defenses...
Via Pro Boxing Fans
5 days ago
Emotional title win for Curtis Woodhouse
All the doubters and cynics were shown once again that fairy tales do come true, as former footballer Curtis Woodhouse made good his promise to his dying father by winning the British title (at light-welterweight) in his very last fight. It proved to be just one of the highlights of Matchroom's terrific show at the Hull Ice Arena tonight.
Via Ringnews24
6 days ago
Darren Hamilton brands Curtis Woodhouse 'A Salesman'
Darren Hamilton says Curtis Woodhouse is 'an excellent salesman' but won't take his British Light Welterweight title away on February 22 at the Hull Ice Arena live on Sky Sports.
Via Ringnews24
15 days ago
Curtis Woodhouse plans to defeat Derry Mathews on Saturday night & "switch his lights off"
Curtis Woodhouse has told Derry Mathews to 'stand and fight' when the fight for the Commonwealth Lightweight title at the sold-out Liverpool Olympia on Saturday night – and the hometown champion told the challenger he'll do exactly that.
Mathews defends the belt for the first time after his stunning late knockout of Tommy Coyle in Hull in July, a bill that Woodhouse boxed...
Via Pro Boxing Fans
September 19, 2013
Boxer Curtis Woodhouse finally gets face to face with his Twitter nemesis
Remember the story about former soccer player, current boxer Curtis Woodhouse showing up at the house of his twitter troll, after the guy popped off at the mouth one time too many following Woodhouse losing a match? Well Woodhouse finally got to meet James O'Brien – the Twitter harasser- face to face and get an apology on live television. 'Embarrassed' James O'Brien apologised...
Via Jocks and Stiletto Jill
March 15, 2013
Curtis Woodhouse, Twitter Troll Apologize To Each Other On TV Show
You may have heard about English boxer Curtis Woodhouse showing up to a man's house after the man trolled him on Twitter for losing his English light welterweight title to Shayne Singleton. Well, Woodhouse finally got to meet his troll on the English show DayBreak.
The boxer sat down with the two hosts of DayBreak to discuss what went on that day and why Woodhouse decided...
Via Next Impulse Sports
March 14, 2013
Boxer finds Twitter tormentor
British boxer Curtis Woodhouse got so mad, he decided to track his Twitter tormentor down.
Woodhouse, a former footballer who played with Hull, set off to find the Twitter user who had been abusing him via the social media networking site following his English light-welterweight title fight loss on Friday.
Woodhouse tweeted: ''I'll give (pounds) 1,000 to anybody who...
Via AP on Fox
March 12, 2013
Twitter Action: Dude trolls boxer...boxer shows up outside his house
Curtis Woodhouse used to play soccer. He's now a boxer. After a recent loss -- he got into a battle with a troll from the world that is the cesspool of Twitter users. Hilarity...
Full story at Bob's Blitz ~ http://www.bobsblitz.com
Via Bob's Blitz
March 12, 2013
Boxer Curtis Woodhouse Shows Up At House Of a Twitter Troll
We are all aware of that guy or group of keyboard gangsters, who get on Twitter or Facebook and because they are sitting at a computer, feel the need to talk tough, or insult their celebrity of choice because they think or know he won't do anything.
Hopefully this story courtesy of Deadspin changes that perception.
Curtis Woodhouse was once a professional soccer player, but took...
Via BlackSportsOnline
March 11, 2013
Former Soccer Player Turned Professional Boxer Curtis Woodhouse Makes House-Call on Twitter Troll
Twitter trolls, beware. Curtis Woodhouse is on the case … and he just might inspire a few copycats. Woodhouse, a former professional soccer player turned professional boxer, got fed up with the constant abuse stream of abuse he received from one Twitter user, so he decided to pay the troll a visit and have a man-to-man chat. Woodhouse, 32, once graced the Premier League for Birmingham...
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Welcome to the 'furniture' tag page at Technorati. This page features content from the farthest reaches of the Blogosphere that authors have "tagged" with 'furniture'.
Are you an expert about 'furniture'? Do you want to be the Technorati authority on 'furniture'? You can write a description that will appear right here: Join Blogcritics!
Original Technorati articles tagged "furniture"
in LifestyleDecorating The Vintage Modern Home
Some people have a talent for pulling together diverse elements, the rest of us need to consult them.by missbobetier / on Jun 26, 2011 -
in GreenCertified Wood Is The Key To Sustainable Forests
The future of all wood-producing industries will hinge on keeping forests alive and renewable.by wisno / on Apr 4, 2010
Latest blogosphere posts tagged "furniture"
This Beautiful Wooden Table Only Weighs 4.5 Kilos
— Authority:
This gorgeous wooden table, designed by Ruben Beckers, is called kleinergleich5—which means "less than five"—because it weighs just 4.5 kilos. What the hell? Read more...7 weeks ago -
Aenaon Villas by Giorgos Zacharopoulos
— Authority:
Aenaon Villas is a luxurious hotel perched atop the rocky hills of Santorini, Greece. It was designed by Giorgos Zacharopoulos and completed in 2009. Aenaon Villas by Giorgos Zacharopoulos: "Aenaon villas is situated at the highest and narrowest part of Santorini, right on the edge of the world-famous caldera, and ...7 weeks ago -
2 North Moore by Turett Collaborative Architects
Archnew — Authority: 117
The 2 North Moore project is located in New York City, USA and was designed by architectural studio Turett Collaborative Architects. This project is a new six story structure attached to the renovated historic brick structure, fully integrated internally, each responsive to the scale and character of the block in ...7 weeks ago -
numen/for use
— Authority:
these guys do everything from industrial design, to conceptual and spatial sculptures based on concepts such as tensegrity, pneumatics and much else with a common thread of originality and coolness7 weeks ago -
Extruded Pixel-Chair made from Wood
— Authority:
Ich liebe die Holzstühle von Ian Spencer und Cairn Youngs Yard Sale Project , rausgefräste Einrichtung aus schräg extrudierten Holzpixeln. Das Teil oben kann man wahrscheinlich für ein Schweinegeld bei Todd Merrill in New York kaufen. (via Adafruit )7 weeks ago -
Seaside House by Ultra Architects
— Authority:
Seaside House is a private residence located in Poland. It was completed by Ultra Architects in 2013. Seaside House by Ultra Architects: "The plot of land for which this building design has been developed is located in Marcelin district, near one of the most important gateways to Poznań, namely Ławica airport. It ...7 weeks ago -
Zeppelin Sofa by Mukomelov Studio
— Authority:
Zeppelin Sofa by Mukomelov Studio Zeppelin Sofa that mimics vintage airship from the company Mukomelov Studio That not only served as a paradigm for the new models of furniture ! An Italian cuisine, and pencil sketches, and all sorts of veggies and fruits. An Even human skull found its application in the ...7 weeks ago -
Your Friday Hunt Report
— Authority:
Greetings Fashionistas! It's Friday and that means it's time to tell you about all the really cool hunts going on… and in plenty of time for your weekend hunting enjoyment. So grab a backpack (for the tons of stuff you'll be picking up) and a friend (because hunting is more fun that way) and hit the hunt ...7 weeks ago -
Kids Furniture Sacramento
children bedroom furniture — Authority: 118
Order by Phone (916) 681-7936 At Furniture USA, we offer one low flat rate of $79 white glove delivery locally. You can check your location here. D&L Furniture Sacramento CA Furniture Store sells the finest Living Room, Leather, Dining Room, Bedroom, Mattresses, Kids Furniture, Home Office, Home Entertainment See ...7 weeks ago -
JP-UK Advise to Recalibrate the Projector When Changing Projector Lamps
— Authority:
Projectors are utilised in many professional and academic settings. This is because these items enable for information, data, images and videos to be easily and effectively displayed to large assembled audiences. The projected image from these devices is provided by the projector lamp or bulb. Like any bulb over time ...7 weeks ago -
Galatea by Details A Design Firm
— Authority:
Galatea is a stunning private residence designed by Details A Design Firm. It is located in Corona del Mar, California, USA. Photos courtesy of Details A Design Firm More...7 weeks ago -
How to build an outdoor table
— Authority:
This step by step diy woodworking project is about how to build an outdoor table. If you want to learn more about building an outdoor table made out of wooden components, we recommend you to pay attention to the instructions described in the article. There are many designs and plans to choose from, so make7 weeks ago -
— Authority:
If you are like me, you spend the majority of your day sitting in front of your computer. This can lead to a lot problems, health wise. I wish I could stand up to do some of my work. Well, now I can. The VARIDESK [$250 - $300] was developed to address the negative side-effects of being seated for the majority of the ...7 weeks ago -
Decorating and Furniture Tips for Moving into a New Home
Strategies Online Blog for Home Improvement — Authority: 113
Moving into your new home can be exciting, whether it's your first or fifth time. There's nothing like moving to a new place that makes you feel fresh and like you can start with a clean slate. However, moving can also be difficult and stressful for many people. It takes time, energy, and a lot of organizational ...7 weeks ago -
Ylofa Palme by AI-Studio
— Authority:
This 2,150 square foot modern apartment located in Moscow was designed by AI-Studio. The interior is elegant and clean, with large windows to allow natural light to permeate the space. Ylofa Palme by AI-Studio: "Covering the outside wall by a walnut wood, we left the rest of the space in light colors. All cabinets ...7 weeks ago -
Incredible Home Workspaces Furnished with Futuristic Furniture
— Authority:
7 weeks ago -
Coaster Fine Furniture 200432 Louis Philippe Style Nightstand, Cherry
— Authority:
Louis Philippe style nightstsand is made from selective hardwood and veneers in a cherry finish. Features include metal glides and antique brass metal handles. FEATURED Coaster Fine Furniture 200432 Louis Philippe Style Nightstand, Cherry Metal glides Antique brass metal handles Classic tradition style7 weeks ago -
Snows Furniture a Luxury Interior Design
— Authority:
7 weeks ago -
French Furniture Design
— Authority:
French Style Home Furniture Serious Solid Wood King Size Bed (A2101 By freshfurnitureidea.com french furniture design. Riverdale, NY — (SBWIRE) — 06/06/2012 — A person's home is their place of relaxation; their place to escape from the pressures of the world; their place to entertain close friends and family; ...7 weeks ago -
Casa Mirador by AR+C
— Authority:
Casa Mirador is a private residence completed by AR+C in 2013. It is located in Guayllabamba, Quito Canton, Ecuador. Casa Mirador by AR+C: "The project is residence house of 140 m2 (1,507 ft2) located in Guayllabamba, Ecuador. The house is conceived as a continuation of nature to which is embedded inside the ...7 weeks ago


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A collection of news and information related to Netherlands published by this site and its partners.
Top Netherlands Articles
Displaying items 34-44
Krul out as Dutch cut squad for French friendly
Story | Feb 28, 2014 | 6:11 AM(Reuters) - Goalkeepers Tim Krul and Maarten Stekelenburg were among 10 players cut by the Netherlands on Friday from a provisional 33-man squad named for next Wednesday's friendly against France. The English-based pair are now in jeopardy of missing out... -
Soccer-UEFA Europa League last 32 summaries
Story | Feb 27, 2014 | 10:57 AMFeb 27 (Infostrada Sports) - Summaries from the UEFA Europa League Last 32 second leg matches on Thursday Rubin Kazan 0 Real Betis 2 Nono 45, Ruben Castro 64 Halftime: 0-1; Attendance: 6,000 - - - Still being played (GMT): Thursday, February 27... -
Soccer-UEFA Europa League last 32 results
Story | Feb 27, 2014 | 10:57 AMFeb 27 (Infostrada Sports) - Results from the UEFA Europa League Last 32 second leg matches on Thursday Last 32 Thursday, February 27, second leg Rubin Kazan (Russia) - Real Betis (Spain) 0-2 (halftime: 0-1) First leg: Real Betis - Rubin Kazan 1-1. Real... -
7-night Alaska cruise on the Holland America ms Statendam from $499
First steel cut as Carnival Vista construction gets underway
State audit criticizes Quinn's anti-violence program
EEUU evalúa salida completa de tropas de Afganistán
Story | Feb 25, 2014 | 12:55 PMPor Steve Holland y Phil Stewart WASHINGTON (Reuters) - El presidente de Estados Unidos, Barack Obama, dijo al Pentágono que se prepare ante la posibilidad de que el paÃs no deje a ningún soldado en Afganistán tras su retiro de tropas a fin de año,... -
State audit criticizes Quinn anti-violence program
Brown Daub Kia renamed and other company news
Suffolk crews extinguish brush fires
02/24: New businesses


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Parkersburg South Holds On To Slim Playoff Hopes The Patriots must take care of business against John Marshall to have a shot at the postseason. Read more about Parkersburg South Holds On To Slim Playoff HopesComments
Tri-Valley And Tecumseh Set For Playoff Rematch The Scotties defeated the Arrows in 2011, and hope to do the same Friday Read more about Tri-Valley And Tecumseh Set For Playoff RematchComments
Ohio vs Eastern Michigan Video Preview Frank Solich and the Bobcats look to get back on the winning track this Thursday against Eastern Michigan Read more about Ohio vs Eastern Michigan Video PreviewComments
Ohio Men's Hoops' Next Big Thing Maurice Ndour may be the next great Bobcat to play in The Convo Read more about Ohio Men's Hoops' Next Big ThingComments
Mid-American Conference Recognized as Top-5 Football Conference by CBSSports.com The MAC ranks higher than two Bowl Championship Series conferences in the latest CBSSports.com power rankings Read more about Mid-American Conference Recognized as Top-5 Football Conference by CBSSports.comComments
Slideshow: 2012 TVC-Ohio Championship The sights of the 2012 TVC-Ohio Championship Game Read more about Slideshow: 2012 TVC-Ohio Championship Comments
Frank Solich Weekly Press Conference: "We're Horrible at Running the Option" Coach Solich says the Bobcats must utilize Tettleton more in the running game because defenses are keying in on the running backs Read more about Frank Solich Weekly Press Conference: "We're Horrible at Running the Option"Comments
Final Regular Season Standings The 2012 high school regular season has come and gone. Here are the final standings for conferences in the viewing area Read more about Final Regular Season StandingsComments
Route Running with the Bobcats Showcase reporter Pat Chiesa gets an inside look at the art of route running Read more about Route Running with the BobcatsComments
Undefeated No More: Ohio Stunned By Miami Tettleton sacked on the game's final play, ending the Bobcats' chance at a BCS bowl and putting their MAC Championship aspirations in jeopardy Read more about Undefeated No More: Ohio Stunned By MiamiComments