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halloween header© Davidus - See portfolio
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|Lifestyles Celebrations Halloween
["all saints' day","card","childish","children","coupon","creepy","curse","custom","dark","eerie","fairy tale","fear","full moon","gloom","halloween","imagination","invitation","night","october","silhouette","spider","spinning","superstition"]all saints' day card childish children coupon creepy curse custom dark eerie fairy tale fear full moon gloom halloween imagination invitation night october silhouette spider spinning superstition
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Decades of Radio - 90s rock top chart music. Hit rock music for every 315,569,259.936 seconds. We rock all decades. Check out our 90s playlist at http://90s.decade-radio.com. Request a song. Playlists are running 24/7. http://www.decadesofradio.com
The Christmas Station! Awesome Mix of popular Christmas music! from the classics of yesterday to the best holiday pop hits of the 80's, 90's and Today! A delightful blend of Holiday hits to put you in that holiday spirit From www.tscradionetwork.com


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Information Center
Job openings
The Hayes Presidential Center is accepting job applications for TWO part-time positions.
Lots of eggcitement for kids
The famous White House Easter egg roll traces its roots to Fremont, Ohio. It was 19th U.S. President Rutherford B. Hayes of Fremont who started the egg roll in 1878. The Hayes Presidential Center celebrates that historical fact with its Hayes Easter Egg Roll. The annual event takes place on the grounds of the Presidents Spiegel Grove estate from 2-3:30 p.m. Saturday, April 4 and is sponsored by Roots Poultry Inc. and Welly's Horseradish .
Children ages 3-10 are invited to compete in a variety of egg-rolling contests. Prizes are awarded in four age categories, and every child receives a balloon, a pass to the Hayes Home or Hayes Museum, and treats. Admission is three hard-boiled colored eggs for use in the contests. When the egg-rolling contests are finished, children are invited to participate in story time, face painting, corn-hole games, and visits by none other than the Easter Bunny.
Visit us on Facebook & please click " Like. " to let your friends, family, and friends' friends know about all the great things going on in Fremont!
View History Day projects Saturday!
Student competitors are set to gather Saturday, March28 at Terra State College to demonstrate their knowledge of history and its consequences during the annual District 2 Ohio History Day. The Rutherford B. Hayes Presidential Center sponsors the event. The public can view student projects from 12:30-2:00 p.m. in the Student Activity Center.
National History Day is an educational program that strives to make history come alive for students in grades 6-12. Participating in National History Day teaches students the skills and techniques of a historian and allows them to discover new insights.
Each year a different theme is selected for History Day participants to research in their projects. This years theme is Leadership and Legacy in History. Winners of the District History Day competition advance to the state contest. State winners then advance to the national level.


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Why you should use RO/DI in Reef Tanks
Why you should use RO/DI in Reef TanksOur first episode in this series is about why RO/DI should be used in a reef aquarium. RO/DI has pretty much become a staple of the saltwater aquarium hobby. In this series we will go over why reefers use RO/DI water in their reef tanks, how to install your system, proper maintenance, filter changes, common troubleshooting techniques, system upgrades , water savers, booster pumps and many other topics. Disclaimer
Maintain accurate test results with your Hanna CheckerEveryone loves Hanna Checkers for their easy, accu ...
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Campground: Olallie Lake
This campground, on the shores of Ollalie Lake, offers several small sites and one larger area with room for RVs. The sites offer scenic views of Mt. Adams from the lake. It's located in a high ...[more]
From Randle, Washington travel south on State Highway 131 (Forest Roads 23 and 25). Veer left in 1 mile at the Y of Forest Road 23 and Forest Road 25. Continue to follow Forest Service Road 23 for 30.2 miles and turn left on Forest Road 2329. Follow Forest Road 2329 for .78 miles. Road 2329 turns to the right at the junction of Forest Road 5601. Follow Forest Road 5601 (straight) for .8 miles and arrive at the campground on the right.
Additional InformationWashington State Tourism>Washington State Road Conditions>
Weather InformationNational Weather Service (NOAA)


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NPR Story
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Sat January 5, 2013
Kentucky's Andy Barr Says He'll Focus On Compromise In New Congress
Originally published on Sat January 5, 2013 5:10 pm
When Congress reconvened on January 3rd, it did so with 84 newly elected members. We've been profiling a few of the newcomers over the past week. Today, we'll learn a bit more about the latest Republican to join Kentucky delegation Andy Barr. Here's Kentucky Public Radio's Kenny Colston.
KENNY COLSTON, BYLINE: The halls of Henry Clay High School in Lexington aren't that much different than the halls of power its namesake served in: loud and busy. But this place brings back memories for Congressman-elect Andy Barr.
ANDY BARR: And it's great to be back in my alma mater, Henry Clay. Go Devils.
COLSTON: Barr moves around the room as he addresses a group of 70 people about his upcoming two-year term. Barr is a lawyer from central Kentucky. He defeated four-term Democrat Ben Chandler in November to win the seat. It was Barr's second run for the position. Barr will join some notable Republicans from his home state in Congress, including Senators Mitch McConnell and Rand Paul and Howell Rogers, the Chairman of the House Appropriations Committee.
While Barr's colleagues may not be known for compromise, Barr plans to take his cues from another Kentuckian Henry Clay. He was known as the great compromiser back in the early to mid 1800s.
BARR: But I don't believe the American people voted for the status quo. I think the American people want our leaders in Washington to work together to try to come to some consensus and solve these major problems.
COLSTON: Barr's first goal is to help community banks be released from recent regulations like Dodd-Frank. That was legislation from the bank bailouts which put tighter controls on how banks lend their money. Barr says those regulations are crippling smaller banks who have the cash to give but need to jump through too many hoops. Kentucky has more than 150 of these smaller chartered banks. And with the delegation already in multiple leadership positions, Barr sees his niche on the House Financial Services Committee.
BEN SWANSON: It is encouraging to me that Congressman-elect Andy Barr seem to embrace compromise. I was a little concerned that he didn't mention any specific proposals on which he would be willing to compromise.
COLSTON: That's Ben Swanson, president of the high school's Young Democrats. The school is known for its political activism and its academics. Barr's district is considered a swing district made up of a majority of Democrats. This is why Barr is talking up compromise and loyalty to his constituents and why another Henry Clay student Macy Early is giving Barr a chance to prove himself.
MACY EARLY: I think there's an old saying that says that a Kentucky Democrat is a New York Republican. And I think that regardless of politics, especially with the bipartisan block that we have going on in Washington and around the nation right now, we need to understand that we should supersede politics.
COLSTON: Which seem to be Barr's early goal, to rise above and in the gridlock.
BARR: And strip away the party labels. I think what the American people want are solutions. What they want - they care about the policy to get the country turned around.
COLSTON: As for which way it turns, that will be up to Barr and his colleagues in the House. For NPR News, I'm Kenny Colston in Louisville. Transcript provided by NPR, Copyright NPR.


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BARCELONA, Spain (AP) — Four days after affirming its European credentials by toppling Manchester City, Barcelona slumped to a stinging 3-1 loss at Real Sociedad to relinquish the provisional Spanish league lead to Real Madrid on Saturday.
Barca's 3-1 loss at Sociedad leaves Madrid on top
Gareth Bale scored a blistering long-range strike to help Madrid brush aside Elche 3-0 at home, and Barcelona was unable to match that with a win. Instead, it was overrun by Sociedad's dynamic attack led by forwards Antoine Griezmann and Carlos Vela.
Barcelona's defeat confirmed the change in course in the league title race over the past two months, leaving Madrid in command and waiting to see if Atletico can keep up when it visits Osasuna on Sunday. After starting the season with 13 wins and a draw, Barcelona has dropped points in four of its last seven games.
Barcelona coach Gerard Martino shuffled his lineup from Tuesday's Champions League victory at City and tried to reinforce his defense by playing with two holding midfielders in Sergio Busquets and Alex Song.
The move backfired when Song scored an own goal in the 32nd minute in the first of several defensive lapses that doomed the defending champions.
Lionel Messi equalized in the 36th, only for Griezmann to restore the hosts' advantage after an error by defender Marc Bartra in the 54th before setting up David Zurutuza in the 59th.
The loss left Barcelona three points behind Madrid, the first time it has trailed its fierce rival this season. Atletico is also three points behind Madrid before it plays on Sunday.
The last time Barcelona lost by more than one goal was a 3-0 defeat to Bayern Munich in May 2013.
Martino took the blame for the humbling defeat.
"Real (Sociedad) deserved to win," he said. "I didn't make the correct reading of the game. The decision not to change was also a mistake."
Madrid won its third straight game without Cristiano Ronaldo, who was finishing a three-game suspension.
Madrid midfielder Asier Illarramendi opened the scoring at the Santiago Bernabeu in the 34th. Bale then squashed Elche's timid second-half surge with a blast from about 25 meters in the 72nd before substitute Isco Alarcon sealed the victory in the 81st.
Continue reading this story on the...


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Children in Britain will be forced to attend at least one year of sex-education classes before their 16th birthday, according to new rules enacted in the United Kingdom. The BBC reports that parents cannot opt out children 15 or older, even if their children attend parochial or religious schools.
This week, as almost everyone is aware, marks the 20th anniversary of the dramatic fall of the Berlin Wall, an event that set in motion the domino-like collapse of communist regimes across Eastern Europe behind the so-called "Iron Curtain."
Venezuela Prepares for War, AgainWritten by Alex Newman
After sending 15,000 more troops to the border, leftist Venezuelan President Hugo Chavez is warning his military and the population to "prepare for war" against neighboring Colombia and the "Yankee empire," further inflaming tensions in the region.
Communist China has executed nine men for crimes committed during violent, ethnically motivated riots that took place in China's Xinjiang region in July. Eight of the men were from the Muslim Uighur minority, and the other was reported to be from the Han majority, although the official China News Service did not specify this.
The New York Times on November 8 reported that the highest court of the United Kingdom was facing as a legal issue the question of who is a Jew and who is not a Jew.


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Brainwave entrainment or "brainwave synchronization," is any practice that aims to cause brainwave frequencies to fall into step with a periodic stimulus having a frequency corresponding to the intended brain-state (at least according to Wikipedia). I have a fascinating App on my iPad called simply Headache. It's introduction in the App Store reports, "Advanced Brainwave […]
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Bio: Eight Belles is Jessi Phillips and a cast of multi-talented supporting players who create original yet classic sounding country music. The material is delicately layered by the instrumentation of drummer Shaun Lowecki, bassist Christian Carpenter, and guitarist Henry Nagle, with Jessi's large, r...See Full Bio
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Photo Galleries
< MyNorthwest
Even more respect for the Seattle Sea Gals
It's not just the Seahawks themselves the 12th Man misses during a bye week, but all things Hawk related: Blitz, Taima 'the hawk,' and of course, the SeaGals.
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Seattle Seahawks Sea Gals cheerleaders dance during an NFL football game between the Seahawks and San Francisco 49ers in the second half of an NFL football game, Sunday, Sept. 15, 2013, in Seattle. After getting glammed up, the Gals are sent out, with police escorts, to seven different locations in the stadium to sell calendars on game day. Two groups go to Touchdown City at noon to perform before the game. (AP Photo/Elaine Thompson)
Photo by (AP Photo/Elaine Thompson)
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Original article: Even more respect for the Seattle Sea Gals
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Amanda Knox and her family celebrate acquittal
Italy's highest court overturned the murder conviction against Amanda Knox and her ex-boyfriend Friday over the 2007 slaying of Knox's roommate, bringing to a definitive end to the high-profile case.
Week in Photos
Photos from around the world this week.
Hundreds gather to commemorate one-year mark of Oso mudslide
A solemn crowd gathered to honor 43 people who lost their lives a year ago in the deadliest landslide in U.S. history.
Photos: Oso one year after deadly mudslide
Sunday is the one-year anniversary of the slide, and although most of the mangled cars and homes have been cleaned up, reminders of loss are everywhere.
Week in photos
Take a look at the best photos of the week from around the world.
Tuesday in photos
St. Patrick's Day, March 17, 2015.
Monday in photos
Monday, March 16, 2015.
Week in photos
Photos from around the world this week.
Friday in photos
The second of three Friday the 13ths in 2015; Friday, March 13, 2015.
Thursday in photos
Thursday, March 12, 2015.


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Winnipeg Free Press - PRINT EDITION
Winnipeg probably won't offer buyouts
Same can't be said of Rangers, Oilers
THE talent pipeline -- the NHL's annual entry draft -- becomes the top focus for all 30 NHL teams once the Stanley Cup final is over.
The draft goes next Friday and Saturday in St. Paul, Minn., but clubs are already tuned into another less sexy yet critical phase of their existence.
The short annual window for buying out a player's contract begins today and lasts until June 30.
And qualifying offers to restricted free agents, a process that is required to retain a player's rights but one that can also trigger the usually unpleasant salary arbitration, must be issued by June 27.
There are no major earthquakes of news on those fronts as concerns the roster of the Atlanta Thrashers, who are moving to Winnipeg to resume play this fall.
While the buyout season is a method for teams to escape burdensome contracts, it's no walkaway freebie. For players under 26, clubs can settle for one-third the remaining value of a deal. If the player's 26 or older, it's two-thirds, and whichever the case, there's a salary-cap hit that shrinks the team's future available payroll.
Names often heard regarding buyouts this spring include Chris Drury of the New York Rangers and Sheldon Souray of the Edmonton Oilers.
There appear to be no obvious Thrashers/Winnipeg candidates in this category.
The Thrashers/Winnipeg, however, have seven restricted free agents who will require qualifying offers by one week from Monday.
Captain Andrew Ladd and fellow forwards Anthony Stewart, Blake Wheeler, Rob Schremp and Ben Maxwell and defencemen Zach Bogosian and Arturs Kulda, a top prospect, all have contracts that expire on June 30. Qualifying offers will make each of those seven Group 2 free agents, but only Ladd, Stewart, Wheeler and Schremp would qualify (age and experience) to choose salary arbitration.
That request must be made by July 5. Teams may also opt for a salary arbitration, thought it's not all that common. Players are only allowed to be subjected to that club-elected process once in their career and clubs may only do it a maximum of twice in any year.
Teams must file by today if they wish arbitration on Group 2's who made more than $1.5 million last season. Only Ladd ($2.35 million) and Wheeler ($2.2 million) would fall into that category but it's not expected that will happen today.
By July 5, teams may request salary arbitration for any Group 2's who have not accepted their qualifying offer, subject to the mentioned limits. Ladd, Wheeler, Stewart and Schremp are the only four who could fall into that process. Also by June 30, the NHL will have come up with its best estimate of what the 2011-12 salary cap and floor will be.
That number is expected to climb to somewhere between $62 million to $63.5 million from $59.4 million.
Republished from the Winnipeg Free Press print edition June 17, 2011 C2
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"It's a great time to be the coach at Cincinnati. It's a great time to be a fan." -Mick Cronin
Tweetcap: Mick Cronin's Press Conference Highlights
0 comments by Scott on 3/30/2015
0 comments by Scott on 3/30/2015
"It's a great time to be the coach at Cincinnati. It's a great time to be a fan." -Mick Cronin
0 comments by Scott
After not being able to coach the Bearcats most of last season, Mick Cronin has been cleared to return Cincinnati announced today. This is obviously great, great news both for the team on the court and much more importantly, great, great news for the health of Mick Cronin. Cronin has been dealing with an arterial […]
0 comments by Scott on 3/27/2015
Welcome to this Friday edition of the AAC news roundup. There is hot and fresh American conference news that we all need. That made the news sound like Little Caesars. I don't think we all need Little Caesars. Aim higher with your pizza needs tonight. You deserve it, ace. You are worth it. Let's cover […]
0 comments by Scott
If you are like me, you are a little down and out about the Bearcats season being over. What is needed is a pick me up. What we've got is that pick me up. Thanks to
0 comments by Scott on 3/26/2015
Hot, hot (just too) Sweet 16 action kicks off tonight with Wichita State taking on Notre Dame at 7:15. That's followed by Wisconsin taking North Carolina's best shot a half hour later and so on. Unfortunately for Bearcat Nation, our team is not involved in any of the action tonight or tomorrow. So who should […]
0 comments by Scott
On this bonus edition of the Bearcats BlogCast, I'm joined by
0 comments by Scott on 3/25/2015
On this edition of the Bearcats BlogCast,
0 comments by Scott on 3/24/2015
Select Kentucky 'fans' were incredibly awful to Octavius Ellis on twitter during and following Saturday's game. I didn't touch on it because I was not going to make myself read the hatred and ignorance of people who claim to be fans. Real fans don't go on twitter and rip on players. Let's rewind that a […]
0 comments by Scott
With the season over, here is some of the AAC news that's flying around the atmosphere. This is a little catch all for the things that don't desere full posts on their own. At his radio show last night, Larry Davis covered the status of Deshaun Morman. LD said that he and Mick Cronin would […]
0 comments by Scott on 3/23/2015
After a few days to ruminate about the Bearcats 64-51 loss to Kentucky, not a lot has changed. I'm still proud of how hard the Bearcats fought against the top team in the nation. I'm still impressed by the effort. I'm still discouraged that it didn't work out. Cincinnati learned the same lesson that the […]
0 comments by Scott on 3/21/2015
Today's 64-51 loss to Kentucky sucks. There's no other way to put it. Losing your final game of the season is always a downer. After this weekend, 16 teams will play on and Cincinnati won't be one of them. The finality of it all stings. Only one team doesn't feel that bitterness. The Bearcats ride […]
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Photo by Getty Images
0 comments by Scott
It's here. The Bearcats get their chance against the dominant team in college basketball. They get their chance to make Cincinnati the 1 in 35-1. As Octavius Ellis said "None of those 35 were us." I don't need to sell you on a Kentucky-Cincinnati game. It's going to be great. It's going to be fun. […]
0 comments by Scott on 3/20/2015
The Bearcats play Kentucky Saturday afternoon at around 2:40 eastern. With many burning questions about the game, I talked to Glenn Logan from A Sea of Blue. You can follow Glenn tomorrow
0 comments by Scott
The past couple of years of early NCAA tournament losses were ringing through my head last night. With Purdue up by 7 with 48 seconds left, it wasn't hard to get sullen about a reality where Cincinnati went down in the first round three straight seasons. Putting together the tweetcap was very bittersweet. Collecting tweets […]


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A good time was had by all at Wednesday's 1st Vegetarian Indian Cooking Class at the Black Rock Branch Library. Our instructor Jyothi did a great..
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Dolder Hotel AG+ Add to Watchlist
As of 06:30:42 ET on 02/17/2015.
Company Profile for Dolder Hotel AG (DHVN)
Dolder Hotel AG owns and operates hotels. The Company operates hotels in Zurich. Dolder Hotel provides meeting and banquet facilities, restaurants, shops, swimming pools, and other recreational facilities.
Contact Information
Dolder Hotel AG
Key Executives for Dolder Hotel AG (DHVN)
|Mark JacobChairman-Managing Board
|Andre G MeierMember-Managing Board
|Thomas SchmidMember-Managing Board
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Those who forget history are condemned to repeat it. The new rulers of Telangana would do well to remember that fulfilling the aspirations of the people should take precedence over raking up issues of the past, which would only harm the objectives of their 60-year struggle. Stoking regional prejudices and employing political opportunism to settle scores with fellow Telugu brothers would in no way help the new Chief Minister ("KCR is first CM of Telangana," June 3). In an era where development is the mantra, Mr. K. Chandrasekhar Rao should come up with out-of-the-box ideas to make the new State a model in terms of development and progress. The first discordant note was struck as the Andhra Pradesh Chief Minister-designate, N. Chandrababu Naidu, remained absent at his Telangana counterpart's swearing-in.
Entrepreneurs in both States must be allowed to invest in both States, in order to reduce regional imbalances. The trust deficit can also be reduced by collectively sorting out disputes over water-sharing, power and irrigation projects and investment.
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Keywords: Telangana state, 29th State of India


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Oh I must have misunderstood you. Could you clarify this
So according to that the total player base is
1.0% (7,472) 7.3% (53,088) 12.7% (92,732) 16.2% (118,014) 17.8% (129,569) 45.0% (328,639)
And the active player base should look something like this right? Is there a way to see on SC2ranks the actual active percentages?
2% 18% 20% 20% 20% 20%
That statement was in reference to the patch 1.3 change that will remove displayed losses for players below Master league. The effect the bonus pool has is that it increases your points but not your MMR, nor does it help to decide how many points you earn or lose per match (it only doubles your winnings). Since all you have to do to improve your rank within your division is earn more points, and because the majority of everyone's points will come from bonus pool, that means all you have to do is play and win more games. That may be the targeted effect of removing the losses display -- to emphasize that losses aren't a big deal because your wins will generally earn you more points than your losses will cost you.
In order to gauge what exactly constitutes an "active player" we need to look at individual players' remaining bonus pools. SC2Ranks can't actually do that, instead it just looks at entire divisions so we can't get bonus pool data. If we were able to determine what the activity threshold is and how much bonus pool these players are spending, we might start seeing populations more in line with what Blizzard has said.
Question on the Zero Points Bug:
If our MMR is constantly moving, as games are played, based on each players MMR, and we know that the MMR of both players is "Bugged" (isn't it safe to assume that the system matches players based on MMR, so "BUGGED" MMR players should be playing each other?), how can the system be using two "BUGGED" numbers in an equation to come up with a final (NOT BUGGED) number??
Basically, if you have bugged MMR, wont playing games just make it worse?
EDIT: Even if only one player has Bugged MMR, wont this still skew the ongoing MMR??
Edited by PenguinKillr on 3/14/2011 5:34 AM PDT
The MMR is not bugged, I think nothing is bugged, we call it bug just because it's unintended, but the system is working just as design.
I think they will have to change the design to "fix" it, like creating a bronze tier that is ridiculosly low or a new copper league just for these guys.
With all due respect SDream, I think you
1. Do not understand the problem
2. did not answer my question.
Something is happening that is "Unintended" but is at the same time "working just as design".... Is it me, or is that a serious contradiction?
If it's working as designed, what is there to "fix"??
Edited by PenguinKillr on 3/14/2011 11:12 AM PDT
With all due respect SDream, I think youThe only thing that needs fixing is the egos of really really bad players. They are stuck at 0 points on the ladder because their true ranking would be negative, but that's apparently too cruel for blizzard to implement. They'll probably end up fixing it by using a different curve for the low end of the ladder, such that it calculates the challenge rating for point assignment from 0, in the event the opponent's MMR is below zero. Matchmaking and MMR would be unaffected, but these players could get some ego food in the form of hundred or so points, before the low opponent rating starts skewing the amount of points they get from wins/losses again.
I'd rather the system tell me how much I suck, not some elitist Douche on the forum... thanks though.
Edit: Looks Like I called the wrong one of us a douche... sorry SDream.
Edited by PenguinKillr on 3/14/2011 2:13 PM PDT
SDream is right, in fact he knows the system as well as I do. MMR is not "bugged", and the points awarded to Bronze Zero players is actually acting according to design (MMR is below the point floor, means you are always favored, means you earn points according to being favored). However, Blizzard doesn't like that behavior because it's counterintuitive and confusing, not to mention frustrating for the lowest-level players having points earned from the last 10 straight wins wiped due to a single loss. So, they've classified it as a bug and scheduled it to be fixed with patch 1.3.
As far as MMR itself is concerned, there's no bug there. You are still gaining and losing appropriate levels of MMR with each game. Some players are just that far below the point floor and they have to make it up with a lot of wins. There are some players who earn zero points for a win, and those players are extremely far below the point floor. Players who earn 2, 4, 6 points are still pretty far below the point floor. Earning 8, 10, 12, 14, 16 means you're pretty close, and 24 (12+12 bonus) is the break-even point.
I sure am glad I didn't call SDream an Elitist Douche!!!
My concern was that my MMR was also calculating as if I was always favored, like the points do.
I understand how the points thing works, and I have seen my points awarded go from zero to currently 10-18 (including bonus), and usually only lose the same 10-18.
Thanks ExcaliburZ and SDream.
Edited by PenguinKillr on 3/14/2011 2:45 PM PDT
An elitist douche? I guess I can work with that. I'm not going to apologize for my bluntness, it was the best way to get across the point of why blizzard doesn't allow point totals to go below zero. I never said it was what I would have done. I don't think points even matter until after you use up all the bonus pool, especially in lower leagues, where you can see huge skill shifts in small amounts of time.The only thing that needs fixing is the egos of really really bad players. They are stuck at 0 points on the ladder because their true ranking would be negative, but that's apparently too cruel for blizzard to implement. They'll probably end up fixing it by using a different curve for the low end of the ladder, such that it calculates the challenge rating for point assignment from 0, in the event the opponent's MMR is below zero. Matchmaking and MMR would be unaffected, but these players could get some ego food in the form of hundred or so points, before the low opponent rating starts skewing the amount of points they get from wins/losses again.
Edited by SoulWager on 3/14/2011 3:04 PM PDT
XxGaLLoWsxX #913
Posts: 13
thankyou so much this sheds some light on the whole league ladders ranking system you really did your homework on this so goodjob and thank you dude
Here's my questions:
1) Why doesn't Blizzard show us our MMR?
2) Why is there a points system at all, instead of just the MMR?
3) How exactly are points earned per match calculated? I read the OP but unfortunately it's still not entirely clear to me. I understand the Bonus Pool bonus, but not how the base points per match is calculated based upon relative MMRs and whatever else.
PrimeMnister #514
Posts: 19
really helpful in understanding the ladder system thanks.
AllwayzCrazy #586
Posts: 14
Okay. i seriously have read alot of these posts and threads and stuff and I have probably overlooked it somewhere but i still would appreciate some clarification.
Do you have to be ranked in top 10 in each: 1v1 2v2 3v3..etc to finally move from bronze to silver?
Okay. i seriously have read alot of these posts and threads and stuff and I have probably overlooked it somewhere but i still would appreciate some clarification.
No, your points and your rank have nothing to do with it. The moving average of your hidden MMR dictates everything about promotion.
Added an image near the top that better illustrates how points are determined for a game.
So I have a question about how points match up with MMR. I read the OP but I don't feel like I fully understand it. Lets take a look at my 1v1 division for example:
I'm currently at rank 15 with 37W-22L (~62.5% ratio). All of the guys above me have worse ratios. Most of them have played many more games so far this season than I have. If MMR is supposed to be closely matched with points, does that mean that everyone above me probably has a higher MMR than I do? Or am I more likely to have a higher MMR than they because I've won a greater percentage of my games; I just haven't been able to play as many games as these guys have and rack up a lot of points.
Thanks for putting this guide together. Its a huge help.
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Dielectrically isolated semiconductor devices such as DMOS and ZGBT devices comprise a substrate having upper and lower surfaces. Source, drain and channel regions are disposed along the upper surface. The drain region extends downwardly to the lower surface of the substrate and laterally beneath the source and channel region. The drain merges with an underlying region of high conductivity. The underlying region is generally flat except for an upwardly extending portion thereof laterally disposed from the source region and providing a lower resistance path for current through the drain region. The DMOS devices can be included within an integrated circuit chip containing other types of semiconductor devices.
1. An MOS device comprising a substrate having first and second oppositely disposed surfaces, a gate electrode overlying a portion of said first surface and extending continuously between first and second positions on said first surface, a first region disposed within said substrate at said first surface, said first region being disposed within a second region within said substrate, said first and second regions forming therebetween a p-n junction having a first intercept with said first surface and underlying said gate electrode at said first position, said second region and said substrate forming therebetween a p-n junction having a second intercept with said first surface and underlying said gate electrode at a third position spaced from said first and second positions, said substrate including a third region of a first electrical conductivity type underlying and contiguous with said second region and extending to said first surface between said third and second positions, and a fourth region of a second electrical conductivity type contiguous with and underlying said third region said third and fourth regions forming a p-n junction therebetween, the distance between said fourth region and said first surface being less where said fourth region underlies said first surface between said second and third positions than where said fourth region underlies said second region.
2. An MOS device according to claim 1, wherein said substrate is of silicon, said substrate second surface is in contact with a layer of silicon dioxide overlying a layer of polysilicon, said polysilicon layer being generally flat where it underlies said substrate second surface except for a first ridge projecting upwardly towards first surface and along a direction intersecting said first surface between said second and third positions thereof, said layer of silicon dioxide including an upwardly projecting second ridge overlying and conforming in shape to said first ridge, and said substrate second surface including an upwardly projecting third ridge overlying and conforming in shape to said second ridge.
3. An MOS device comprising a substrate of semiconductor material having upper and lower oppositely disposed surfaces, said substrate containing source, channel and drain regions disposed in succession adjoining said upper surface, said drain region extending to said lower surface and underlying said source and channel regions, said source region being disposed within a first doped region forming a p-n junction with said drain region and underlying said source region, and a second region of opposite conductivity type as said drain region electrical conductivity extending along said lower surface and spaced from said upper surface, the spacing between said second region channel and said upper surface being less where said drain region adjoins said upper surface than where the p-n junction underlies said source region.
4. An MOS device comprising a substrate having top and bottom surfaces, said substrate including a first region extending from a first portion of said top surface downwardly towards said bottom surface and being of a first type conductivity, a second region of a second type conductivity disposed within said substrate at said top surface and spaced from said bottom surface, said second region forming a first p-n junction with said first region, said first junction having a first intercept with said top surface, a third region of said first type conductivity disposed within said second region and forming a second p-n junction therewith, said second p-n junction having a second intercept with said top surface, a gate electrode overlying said first portion of said top surface and said first and second intercepts, a fourth region of said second conductivity type being disposed within said substrate underlying and spaced from said second region and underlying said first region, said fourth region having a higher electrical conductivity than said first region, and said fourth region being shaped such that the vertical distance between said fourth region and said top surface is less under said first portion of said top surface than under said second region.
5. An MOS device according to claim 4 wherein said top and bottom surfaces are generally parallel except for an upwardly extending protrusion in said bottom surface underlying said first portion of said top surface, said fourth region having a layer-like shape conforming to the shape of said bottom surface.
6. An integrated circuit comprising a semiconductor chip containing a plurality of tubs therein, each of said tubs comprising a bottom wall and a side wall extending upwardly therefrom, said walls being of an electrically insulating material, a substrate of semiconductor material of a first conductivity type disposed within each of said tubs, said substrate having an upper surface, a first doped region within said substrate disposed along said bottom wall, a second doped region within said substrate disposed along said upper surface and vertically spaced from first region, said first region having, spaced from said side wall, a vertically extending protrusion providing, along the bottom of said substrate, a variable spacing between said first region and said substrate top surface; and wherein, in a first of said tubs, said first region is of said first conductivity type, and, in a second of said tubs, said first region is of a second conductivity type.
7. An integrated circuit according to claim 6 wherein, one of said first and second tubs contains a DMOS device, and the other one of said first and second tubs contains a bipolar device.
This invention relates primarily to dielectricaly isolated devices within semiconductor integrated circuits, and particularly, to such devices having "vertical" configurations providing high voltage capability. The invention also relates to discrete DMOS devices, particularly to Double Diffusion Metal Oxide Semiconductor (DMOS) and Insulated Gate Bipolar Transistor (IGBT) devices.
Integrated circuits with which the present invention has utility are known. One class of such circuits is described in "An Analog/Digital BCDMOS Technology with Dielectric Isolation-Devices and Processes", Chih-Yuan Lu, et al, IEEE Transactions on Electron Devices, Vol. 35, No. 2, February 1988, pages 230-237. In such integrated circuits, various different types of semiconductor devices, e.g., bipolar, Complimentary MOS (CMOS), DMOS, p-n-p-n, Junction FET (JFET) and Dual Gate DMOS (DGDMOS) devices are integrated within a single semiconductor chip. This is made possible by the use of device structures and processes which are compatible with all the different types of devices included on the chip, even though not all the devices are optimized in their performance. In particular, and with respect to the present invention, in order to provide certain ones of the devices with high voltage capability, particularly the DMOS and IGBT devices (described further hereinafter), the devices are formed within deep tubs providing large vertical distances for withstanding high voltages. Doped regions are formed at both the top and bottom surfaces of the tubs, and, in the different devices within the chip, the different doped regions provide different functions, depending upon the particular devices involved. For example, in the DMOS devices, the bottom doped region serves as a highly conductive channel for current passing between source and drain regions of the device. In bipolar transistors, the bottom doped region serves as the device collector. A problem, however, is that while the distance of the bottom doped regions from the upper doped regions is optimized for the DMOS devices, such distance is generally higher than optimal for the other devices within the chip.
The present invention has utility for better optimizing the dimensions of various devices in integrated circuits of the type described above.
In addition, the present invention has utility in DMOS and IGBT devices in general, whether integrated or not.
DMOS devices are well known, wherein the "D" stands for "diffusion" or "double diffusion". Such devices comprise (FIG. 1) a substrate 10 of semiconductor material having on a surface thereof a layer 12 of gate oxide covered by a gate electrode 14. The device is of cellular type, including spaced apart portions connected in parallel. Plural source regions comprise first doped regions 16, e.g. of N type conductivity, formed within second doped regions 18 of opposite type conductivity, e.g. of P type conductivity, with the regions 18 being formed within the substrate, e.g. of N type conductivity. The regions 16 and 18 are formed by successive ion implantations using the gate electrode 14 as a mask and by heating for causing lateral diffusions of the various regions under the gate electrode. The second doped regions 18 extend laterally further beneath the gate oxide than the first regions 16, and the portions 20 of the second regions 18 extending beyond the first regions 16 beneath the gate oxide comprise the channel regions of the device. The gate electrode 14 also overlies surface portions 22 of the N type substrate 10. The substrate beneath the surface portions 22 comprises the drain region of the device.
In operation, when the channel regions 20 are in a conductive state, under control of the gate electrode, current flows from a source electrode 24 contacting surface portions of the first 16 and second 18 regions through the first regions 16, through the channel regions 20, and into the substrate 10 at the surface portions 22. The current flows through the substrate 10 (drain region) to a drain electrode 26 contacting the substrate surface at a position laterally remote from the first and second regions.
Such DMOS devices are used in power controlling applications involving relatively high voltages and currents and, to this end, the substrate portions directly adjoining the second regions 18 are lightly doped and overlie a heavily doped region 28 which extends laterally along the bottom of the substrate and then vertically upwardly to the drain electrode 26. Accordingly, when the device is in the switched-on state, current flows first laterally through the channel regions 20 beneath the gate electrode 12 to the substrate portions 22 and then vertically downwardly through the substrate 10 to the underlying heavily doped region 28 which conducts the current to the drain electrode 26.
When the device is in its switched-off state, with a voltage applied between the source and drain regions, the applied voltage is "withstood" across the p-n junctions 30 between the P regions 18 and the N substrate 10; that is, the applied voltage reverse biases the p-n junctions 30. Depletion regions are thus formed on opposite sides of the p-n junctions 30, and, because of the low doping of the substrate (much lower than that of the second region 18) the width of the depletion regions within the substrate 10 primarily determines the stand-off voltage capability of the device. The maximum widths of the depletion regions correspond substantially to the distance between the p-n junctions 30 and the heavily doped region 28 beneath the second regions 18. Thus, when the depletion regions reach the heavily doped region 28, further expansion of the depletion regions with increasing applied voltage substantially ceases, the electric field intensity through the substrate increases, and voltage breakdown of the device occurs.
The vertical distance Ba between the second regions 18 and the underlying region 28 largely influences two parameters of the device. One parameter is the on-current resistance of the device because the current flows through this vertical distance to reach the region 28. The other parameter is the breakdown voltage rating of the device. The vertical distance, however, has opposite effects on these two parameters. A desired low on-current resistance requires a short vertical distance, while a desired high voltage breakdown requires a long vertical length.
Insulated Gate Bipolar Transistors (IGBT) can be identical to the DMOS devices illustrated in FIG. 1 except that the high conductivity region 28 is of opposite type conductivity to that of the overlying region 10. In terms of the foregoing, conflicting requirements of DMOS devices are also present in IGBT devices.
The present invention provides a means for better reconciling these conflicting requirements. Also, as described hereinafter, such reconciling means is useful in integrated circuits of the type hereinafter described for better optimizing the characteristics of various types of devices contained therein.
In accordance with one aspect of the invention, semiconductor devices comprise a substrate having upper and lower surfaces. Disposed directly over a first portion of the upper surface is a gate structure comprising a gate electrode overlying a dielectric material layer. Disposed within the substrate at the upper surface and partially underlying the gate structure are first and second doped regions. The second doped region forms a first p-n junction with the substrate, which first junction extends to and has an intercept with the substrate upper surface. The first region is disposed within the second region and forms a second p-n junction also having an intercept with the substrate upper surface. Both p-n intercepts are overlaid by the gate structure. Disposed within the substrate along the lower surface is a highly conductive region which underlies both the upper surface first portion and the first and second doped regions. The highly conductive region is shaped such that the vertical distance between the region and the substrate upper surface is less beneath the surface first portion than beneath the first and second doped regions.
In accordance with another aspect of the invention, various devices according to the invention are disposed within identical tubs within a semiconductor chip. Each tub includes a substrate extending between top and bottom surfaces of the tub, and each tub includes a first doped region disposed along the tub bottom surface. Each first doped region has a generally centrally disposed portion which projects upwardly towards the tub upper surface and towards a second doped region at the tub upper surface forming, in cooperation with the first doped region, components of vertically oriented semiconductor devices.
FIG. 1 is a cross-sectional view of a prior art DMOS device;
FIG. 2 is a plan view of the surface of a semiconductor wafer containing a dielectrically isolated DMOS device in accordance with this invention, such surface lying in the plane marked 2--2 in FIG. 3;
FIG. 3 is a section of the device shown in FIG. 2 taken along line 3--3 of FIG. 2;
FIGS. 4, 5, 7 and 8 are views similar to FIG. 2 but showing successive steps in the fabrication of the DMOS device shown in FIGS. 2 and 3;
FIG. 6 is a plan view of the device shown in FIG. 5;
FIG. 9 is a view in section of a portion of an integrated circuit chip showing several dielectrically isolated devices in accordance with the invention;
FIG. 10 is a view similar to FIG. 9 but showing a prior art Zener diode;
FIG. 11 is a view similar to FIG. 2 but showing a variation therefrom; and
FIGS. 12-14 are views similar to FIGS. 4, 5, 7 and 8 but showing successive steps an the fabrication of another device in accordance with this invention.
With reference to FIGS. 2 and 3, a portion of an integrated semiconductor device is shown, such portion comprising a small part of a silicon chip 34 containing the integrated circuit. Integrated semiconductor devices of the type with which the present inventive device has utility are well known and described in the afore-cited IEEE article. Generally, the present invention provides an improvement in known DMOS and IGBT devices and can be used in such devices whether integrated or not. The invention has particular utility, however, in dielectrically isolated DMOS and IGBT devices, and a DMOS device, identified by the reference numeral 32, is first described. Disposed within the chip 34, and dielectrically isolated from it by a layer 38 of silicon dioxide, is a body 40 of silicon. For generalizing the description, the silicon body 40 is referred to as a substrate. In this embodiment, the substrate is of N-type conductivity.
The substrate 40 has two opposed surfaces, that is, an upper surface 42 and a lower surface 44 joined by a side surface 46. Adjoining the lower 44 and side 46 surfaces is a region 48 of N+ material, that is a portion of the substrate 40 which is heavily doped with an impurity providing N-type conductivity. The region 48 extends to the upper surface 42 of the substrate 40 where it is contacted by a drain electrode 50, e.g., of aluminum. The purpose of the heavily doped region 48 is to provide a low resistance path for current to the drain electrode 50. For this reason, the region 48 is hereinafter referred to as the "conductive channel" 48.
Disposed over a central portion of the substrate 40 is a gate electrode structure 54 comprising a dielectric layer 56, e.g., silicon dioxide, overlaid with a gate electrode 58, e.g., of doped polysilicon.
The device 32 shown is of the cellular type and comprises (FIG. 2) four cells C connected in parallel and sharing common elements of the composite device. FIG. 2 is a plan view of the device from the surface 42 thereof and does not show the various layers on the surface 42. As generally known, the gate electrode structure 54 (FIG. 3) covers substantially the entire surface 42 but has openings 55 therethrough. The various cells C are connected together by a conductive layer (shown schematically by a dashed line 59) which overlies the gate structure 54 but is separated therefrom by a layer of insulating material.
Disposed within the substrate 40 and within each cell C (there being four identical cells C in this embodiment) is a first doped region 60 having (FIG. 2) an annular shape, the first doped region 60 being disposed within a square shaped second doped region 62. The first doped region 60 is of N+ conductivity and forms a p-n junction 64 with the second region 62 of P-type conductivity.
The second region 62 forms a p-n junction 66 with the substrate 40. Both p-n junctions 64 and 66 extend towards and have surface intercepts with the substrate upper surface 42. The p-n junction 64, owing to the annular shape of the first region 60, forms two spaced apart surface intercepts 64a and 64b (FIG. 2) with the surface 42, and the outer intercept 64a (of each cell C) is disposed beneath the gate electrode structure 54. The surface intercept 66a of the p-n junction 66 is also disposed beneath the gate structure 54, and the upper portion 70 of the second region 62 (surrounding the outer periphery of the first region 60 and disposed between the two surface intercepts 64a and 66a) comprises the channel region of the DMOS device.
The first region 60 comprises the source region of the DMOS device cells, and a source electrode 72, e.g., of aluminum, contacts the surface of the first region 60. The electrode 72 also contacts the surface of the second region 62. As schematically indicated in FIG. 3, the source electrodes 72 of the two cells C (as well as the other two cells C shown in FIG. 21 are connected together by a conductive layer 59. The substrate 40 comprises the drain region of the composite device, i.e., it underlies all the cells C and is contacted by the previously described annular drain electrode 50.
To the extent so far described, the DMOS device shown in FIGS. 2 and 3 is substantially identical to the prior art DMOS device shown in FIG. 1 (and substantially identical, when the region 48 is of P type conductivity, to known IGBT devices). In accordance with this invention, a difference from the prior art is the shape of the conductive channel 48 at the bottom of the substrate 40. As shown in FIG. 3, the channel 48 at the center of the device includes an upwardly extending protrusion 76, e.g., having the shape (in this embodiment of the invention) of a four sided pyramid. In the prior art (FIG. 1) the conductive channel 28 is flat along the entire flat bottom-surface of the substrate.
As shown in FIG. 3, the pyramidal protrusion 76 is formed around a pyramid 78 formed in the silicon dioxide layer 38, and the pyramid 78 is formed around a pyramid 80 in the wall of the chip 34 underlying the substrate 40. The fabrication of the various pyramids is described hereinafter.
The effect of the pyramid 76 in the conductive channel 48 is to reduce the vertical distance between the channel 48 where the channel underlies a central portion of the substrate surface 42 surrounded by the second regions 62. More specifically, the height of the pyramid 76 is such that the distance A between the peak 82 of the pyramid 76 and the surface intercepts 66a of the p-n junctions 66 is substantially equal to the vertical distance B between the bottom-most portion of the p-n junction 66 and the underlying upper surface 48a of the conductive channel 48.
In contrast, in the prior art devices (FIG. 1), the distance between the conductive channel 28 and the substrate upper surface is uniform throughout the device (excepting where the conductive channel 28 rises to the substrate upper surface).
The importance of this structural change from the prior art is explained as follows:
During use of the DMOS device 32, a voltage is applied between the source electrode 72 and the drain electrode 50, with the drain electrode voltage being positive with respect to the source electrode. Such polarity voltage across the device 32 reverse biases the p-n junction 66 between the second region 62 of each cell C and the substrate 40. As previously explained, the device will withstand the applied voltage, without voltage breakdown, provided the depletion region formed within the substrate 40 does not penetrate substantially into the conductive channel 48. Accordingly, with a given low level doping of the substrate 40, the voltage breakdown capability of the device is a direct function of the vertical distance B. Note that, in the prior art device shown in FIG. 1, the distance Aa is greater than the distance Ba, but this greater distance has no effect on the breakdown capability of the device. That is, once the depletion region from the bottommost portion of the second region 18 reaches the conductive channel 28, voltage breakdown will shortly occur (with further increases of applied voltage).
When the inventive device 32 is switched on, as by applying a positive voltage to the gate electrode 58 for switching the conductivity of the channel region 70 between the source region 60 and the drain region 40 of each of the cells C, current flows from the source regions 60 through the channel regions 70 of the cells C and into the drain region 40. The channel regions 70 are switched only closely adjacent to the substrate surface 42 and the current from the various channel regions 70 enters the drain region 40 just beneath the substrate surface 42. From there, the current travels vertically downwardly to the conductive channel 48 through which the current passes to the drain electrode 50.
The on-resistance of DMOS devices, that is the resistance to current flow when the device is switched on, is a function of the length of the current path through the device. In the prior art device shown in FIG. 1, the path Aa for the current through a portion of the substrate 28 of low conductivity is longer than the corresponding path length A in the inventive device shown in FIG. 3. Accordingly, the on-resistance of the FIG. 3 device, all other parameters being equal, is less than that of the FIG. 1 device.
As previously noted, because the voltage breakdown capability of the device is a function of the distance B, reducing the distance A, providing the distance A does not become less than distance B, does not affect the device voltage breakdown capability. In practice, the distance A is made slightly greater than the distance B. The actual dimensions involved depend upon the size of the DMOS device and its ratings, and such dimensions can be readily selected by persons of skill in this art.
Reducing the distance A, however, does reduce the on-resistance of the device. In a situation where the parameters of the devices shown in FIGS. 1 and 3 are identical, except for the central pyramid 76 in the FIG. 3 device, the inventive FIG. 3 device has lower on-resistance than the FIG. 1 device and the same voltage breakdown capability. Conversely, the inventive device can be provided, in comparison with the FIG. 1 device, with a larger voltage breakdown capability by increasing the distance B, while providing the same on-resistance of the FIG. 1 device.
IGBT devices perform similarly to DMOS devices and the foregoing discussion applies, in general, to IGBT devices.
The particular shape of the upwardly extending protrusion 76 (FIG. 3) is not critical. However, as previously indicated, the invention has particular utility in the fabrication of dielectrically isolated DMOS and IGBT devices, and, in such devices, the particular pyramidal structure shown in FIG. 3 follows automatically from a preferred method of fabrication. This is now described.
The starting workpiece (FIG. 4), for the fabrication of an N-channel DMOS, is a wafer of monocrystalline silicon of N type conductivity. Herein is shown only a small portion 82 of the wafer, that is, a portion in which a single, dielectrically isolated DMOS is to be made. The processing of wafers to simultaneously form a plurality of individual, dielectrically isolated DMOS devices within integrated circuits is well known, and known processing details are omitted from the following description.
The (100) surface 86 of the silicon wafer is oxidized to form a layer 88 of silicon dioxide which is patterned to provide a number of openings 90 and 92 (FIG. 4) therethrough. The wafer is then exposed to an etchant (KOH) for anisotropically etching grooves 90a and 92a (FIGS. 5 and 6) into the surface having a V-shaped cross-section. The depths of the grooves are a function of the dimensions of the openings 90 and 92. As shown in FIG. 6, a continuous V-shaped groove 90a is provided around the outer sides of the wafer portion 82 and a pyramidal shaped groove or cavity 92a is formed in the center of the wafer portion.
Then, the oxide layer 88 is removed, and (FIG. 7) N type conductivity ions, e.g., arsenic, are implanted through the surface to form an N+ layer 48 (see, also, FIG. 2) which underlies the various grooves 90a and 92a. The surface 86 is then oxidized to form a layer 38 of silicon dioxide overlying the N+ layer 48.
The process described herein can be used to fabricate IGBT devices except that P type conductivity ions, e.g., boron, are used to form a P+ region 48.
A layer 34 of polysilicon is then deposited onto the oxide layer 38 and into the grooves 90a and 92a.
FIG. 8 shows the workpiece turned upside down from the position shown in FIG. 7. Also, the (now) upper portion of the wafer has been ground away to provide a surface 42 extending just through the tops 94 of the V-shaped "ridges" 90a (i.e., the bottom of the V-shaped grooves 90a shown in FIG. 7). The new surface 42 cuts through the oxide layer 38 overlying the ridges 90a, which surface exposed oxide layer 38 forms a surface boundary for the DMOS device being made.
At this stage in the fabrication sequence, the wafer portion 82, shown in FIG. 8, corresponds to portions of the device 32 shown in FIG. 2.
Completion of the device 32, from the workpiece shown in FIG. 8, can be by identical processes used in the fabrication of known DMOS devices of the type shown in FIG. 1.
Indeed, in terms of fabrication of the inventive DMOS devices, all the processes used can be identical to those used in the fabrication of the prior art DMOS devices. The only difference present in the fabrication processes is the provision of the opening 92 (FIG. 4) through the oxide layer 88 in the center of the wafer portion 82. This opening 92 and 92a shown in FIGS. 5, 6, 7 and 8, not present in the prior art process, gives rise to the pyramidal shaped protrusion 76 (FIG. 3) in the inventive device 32 and provides the described improved device characteristics. Significantly, however, providing the additional opening 92 through the oxide layer 88 adds no cost to the prior art process (merely requiring a change in the photomask used in the process), and the structural change from the prior art devices described herein can thus be obtained at no additional processing cost over that of the prior art devices.
While the use of such pyramidal protrusions 76 is desirable because of its compatibility with existing fabrication processes, the device improvements can be obtained using other configurations, e.g., conical or cylindrical protrusions and the like.
As previously noted, the invention is not limited for use in DMOS and IGBT devices. FIG. 9 is a view of a portion of an integrated circuit chip including a plurality of identical tubs 100, 102 and 104, each of which includes a body 40 of semiconductor material surrounded by a wall 38 of silicon dioxide providing dielectric isolation for the device within the tub. Another two, not shown in FIG. 9, can include a DMOS device such as the device 32 shown in FIGS. 2 and 3. Also, the various tubs can be formed using the identical process described in connection with FIGS. 4 through 8. Thus, all of the tubs contain a central pyramidal protrusion 76 in a highly doped region 48 (N-type in the illustrated embodiment) providing a variable spacing between the region 48 and various overlying doped regions. Although not illustrated, tubs containing P type regions 48 would normally also be provided, such tubs containing IGBT devices, as well as various devices illustrated herein but of opposite type polarity, e.g., P type channel DMOS devices rather than, or in addition to, the N type channel DMOS devices herein described.
Considering the devices shown in the tubs 100 and 102 (but not the tub 104), it is first noted that, except for the pyramidal protrusion 76, the devices illustrated are identical to known devices of the type described in the afore-cited IEEE Transaction article. That is, as is the situation with the prior art device shown in FIG. 1, all the known devices are formed in tubs having flat bottom surfaces.
All the various tubs 100, 102 and 104 have the same vertical dimension. This results from the fact that all the tubs are simultaneously formed in the integrated circuit chip. Basically, the vertical dimension is determined by the voltage rating of the devices in the integrated circuit having to withstand the largest voltages and, generally, the vertical dimension is greater than the optimal value for devices other than the high voltage devices. The presence of the pyramidal (or other shape) protrusion serves to reduce the effective vertical height of the devices, hence tends to better optimize the characteristics thereof.
Thus, the tub 100 contains an n-p-n transistor comprising an N emitter 110, a P base 112 and an N collector 114. Current flows first vertically from the emitter 110 through the base 112 to the collector 114, thence horizontally and vertically through the highly doped region 48 to the collector electrode 116. While the highly doped region 48 is part of the collector region 114, the resistance thereof is so much less than the remainder of the collector region overlying it, that the region can be considered part of the collector electrode 116. The presence of the protrusion 76 thus at least partially reduces the length of the vertical path for current through the collector 114, hence results in lower collector resistance and lower collector-emitter saturation voltage.
The tub 102 contains a diode comprising an anode region 118 and a cathode region 120. Similarly, as before described, the protrusion 76 reduces the length of the vertical path for current through the cathode region 112, hence results in lower on-resistance of the device.
The device in the tub 104, owing to the presence of the protrusion 76, is different from a corresponding prior art device shown in FIG. 10. The FIG. 10 prior art device is a Zener diode of the surface type comprising an anode region 122 overlapping a cathode region 124, the overlapped regions providing a junction 128 between the two regions 122 and 129.
Within the tub 104, however, the Zener diode, in accordance with this invention, is of the buried type wherein the anode region 130 forms a p-n junction with the upwardly protected portion 76 of the highly doped region 48. As known, Zener diodes of the buried type (made possible because of the protrusion 76) are more stable and reliable than Zener diodes of the surface type because of avoidance of a surface intercept of the p-n junction.
As previously noted, the vertical heights of the various tubs 100, 102 and 104 are the same as a result of how the integrated circuit chip is fabricated, particularly as the result (FIGS. 7 and 8) of the grinding operation resulting in a flat surface exposing the tops 94 of the silicon dioxide ridges. This requires that all the V grooves 90a (FIG. 5) have the same depth. Conversely, however, different height protrusions 76 can be provided by varying the depths of the central groove 92a (FIG. 5) used to form the protrusions. As previously noted, this is accomplished by varying the size of the opening 92 (FIG. 4). Varying the height of pyramidal protrusions also varies the base dimensions thereof because the angles of inclination of the pyramid sides are fixed by the anisotropic etching of the silicon crystal.
Additionally, even with protrusions formed by anisotropic etching, other protrusion shapes can be formed, e.g., elongated ridges of inverted V shape. Also, the ridges can be of different heights and two or more ridges can be provided in various parallel and perpendicular configurations. FIG. 11, for example, shows four cells C, such as shown in FIG. 2, where each of the cells is completely surrounded by ridges 76a forming a grid of intersecting ridges. The ridges 76a can be formed identically as the peripheral ridges 90a (FIG. 8), but of shorter heights.
As explained, the pyramidal protrusions, as well as elongated ridge protrusions, can be provided without additional expensive steps (except for a minor photomask revision expense) using presently used fabrication processes. While this is desirable for cost reasons, it does not preclude the use of other processes for providing the protrusions in the highly doped regions 48 at the bottoms of the devices. For example, FIG. 12 shows a workpiece at a stage of fabrication where grooves 90a have been formed (similarly as in FIG. 5); but no central groove 92a. Instead, the surface of the workpiece, including the grooves 90a, is covered with a photoresistant layer 150 which is patterned to provide an opening 152. Then, a dopant is introduced to form a downwardly extending highly doped region 154. Then, FIG. 13, the photoresistant layer 150 is removed and a similar conductivity type dopant is introduced through the entire exposed surface of the workpiece to form the highly doped region 40a. Subsequent processing is as shown in FIGS. 7 and 8 resulting in a workpiece, such as shown in FIG. 14, having a flat bottomed substrate 40a, that is, without a pyramidal protrusion, but with an upwardly extending portion 76a of the region 40a. In terms of function, the workpiece shown in FIG. 14 is the equivalent of the workpiece shown in FIG. 8.
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