An in-vehicle system for identifying turn-only and shared turn lanes and identifying turn rules according to visual indicia captured from turn signs. An image apparatus configured to obtain image data including graphic data and/or text data from a roadway sign, as well as street light image data for an intersection on the roadway. The image data may be processed to detect a graphic image and/or text from the image data relating to the roadway sign. Street light image data may also be captured and processed to determine a street light status. An identification module may determine rules for turning on the intersection of the roadway based on the processed image data relating to the roadway sign, wherein the identification module is further configured to determine if the turn on the roadway is allowed based on the determined street light status.

The present disclosure relates to systems, components, and methodologies for determining a position and turning status identification for a vehicle. In particular, the present disclosure relates to systems, components, and methodologies that improve determinations of allowable turning conditions for a vehicle on a roadway having intersections or exits using captured visual indicia.

Early detection of turning condition identification using perception technology


A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.

The present invention relates to a non-volatile memory. Specifically, the present invention relates to a system and method for restoring charge lost from a charge storage element in a non-volatile memory.
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage/non-volatile medium so that the data and computer programs is not lost when power is removed.
Flash memory (or Flash RAM) is an example of a non-volatile memory device. Flash memory devices use a memory cell transistor with a floating gate structure. The typical memory cell in a flash memory device comprises an access transistor and a storage element, such as a floating gale. Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, across a thin insulating film between a substrate and a storage element (e.g., floating gate). Programming of the memory cells occurs by applying a sufficient voltage difference to the transistors to cause excess electrons to accumulate on the storage element. Erasure of the memory cell is done by applying a voltage difference that causes the charge on the storage element to be extracted.
Prior Art FIG. 1A shows a diagram of a typical memory cell with a floating gate 120. A source 130 and drain 135 are fabricated in a substrate 105, and separated from the floating gate 140 by an oxide 125. The control gate 110 is separated from the floating gate by an oxide 115. In writing to the memory cell, a charge 140 is transferred across the oxide 125 into the floating gate 140. The charge transfer may be effected by either Fowler-Nordheim tunneling or channel hot electron injection. The memory cell of FIG. 1A may be used to store multiple bits of information by injecting different amounts of charge. In the floating gate, the charge is mobile and not localized.
Prior Art FIG. 1B shows a diagram of another memory cell structure that replaces the floating gate 140 of FIG. 1A with a dielectric storage element 160. The dielectric storage element 160 may be injected with two distinct charges 175, each located near a symmetric drain/source 170. In contrast to the floating gate in which different bits (or combinations of bits) are associated with a charge level, the dielectric charge storage element provides for the representation of bits through discrete localized charges. The control gate 150, oxide 155, oxide 165 and substrate 145 are similar to the control gate 110, oxide 115, oxide 125 and substrate 105 of FIG. 1A.
Prior Art FIG. 2 shows a diagram 200 for the threshold voltage of a multi-level (or multi-bit) memory cell array. The example shown in FIG. 2 corresponds to a two-bit memory cell that has four nominal threshold voltages (VT11, VT10, VT01, and VT00,) associated with four possible logical bit combinations (11, 10, 01, and 00). The association between logical values and threshold values is arbitrary. In a memory cell array, or large population of memory cells, each group of cells associated with a logical value will have a distribution of threshold values distributed about the nominal threshold value (VT). Distributions 205, 210, 215, and 220 correspond to threshold voltages VT11, VT10, VT01, and VT00, respectively. N represents the number of cells as a function of the threshold voltage VT.
In order for the logical values in a multi-level memory cell to be distinguishable, they must be separated by a read margin M. In the multi-level example of FIG. 2, distributions 205 and 210 are separated by read margin M1, distributions 210 and 215 by M2, and distributions 215 and 220 by M3. The width of the distribution for a threshold voltage is in part a function of geometry and process variations, and defects.
A fundamental difference between dynamic random access memory (DRAM) and similar memory types is that non-volatile memory cells such as those shown in FIGS. 1A and 1B is that they are programmed by transferring charge across a dielectric layer, whereas DRAM memory cells are programmed by charging a capacitor through a transistor switch. The leakage characteristic of DRAM cells requires that the cells be refreshed on a regular basis, whereas non-volatile memory cells are designed to maintain their programmed state virtually indefinitely, without refresh, hence the name xe2x80x9cnon-volatile memory.xe2x80x9d
Although fundamental properties of the materials used to fabricate non-volatile memory cells provide a basis for fabricating highly stable non-volatile memory devices, the quest for smaller device geometries and higher information densities has resulted in a reduction in the margin of stability for many devices at high write/erase cycle counts and at high temperatures. This trend is expected to continue as critical dimensions for photolithographic processes continue to decrease, and thinner films arc employed to reduce working voltages.
Even high quality dielectric films are susceptible to tunneling and thermally assisted conduction if they are made thin enough, and charge losses that were previously expected to occur on a geologic time scale, even at elevated temperatures, are now within the realm of normal operating conditions and lifetimes. The loss of ability of a memory cell to retain charge is manifested in shifting threshold voltages and compromised read margins. What is needed is a method for offsetting threshold voltage shifts and maintaining read margins.
A non-volatile memory device comprising logic for charge restoration is disclosed. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.
In a method embodiment of the present invention, boundary values are established for the allowable range of threshold voltages associated with each logical value of a memory cell. These boundary values define the read margins between logical values/threshold voltage values for the memory cell, and are related to the distribution of threshold voltages for the population (e.g., array) to which the memory cell belongs. Periodically, a memory cell is selected from the array and read to determine a value. The read value is compared to at least one boundary to determine whether the cell value has drifted into a margin. In the event that the memory cell value has drifted into a margin, a write procedure is performed to push the cell threshold value back across the boundary.
In another embodiment of the present invention, a non-volatile memory device includes restore logic coupled to read and write circuits for sensing and altering the state of memory cells belonging to an array of memory cells. The read and write circuits are coupled to decoder circuits for selecting a memory cell from the array of memory cells. The restore logic may include a processor for performing a statistical analysis on the memory cell array. Certain memory cells within the memory cell array may be reserved for use by the restore logic.

System and method for charge restoration in a non-volatile memory device


The present invention refers to a supply cartridge (1) comprising a package casing (11) and a support (2) of single portions, provided as a strip-like support, or similar, presenting a plurality of single dose portions (21) of an edible substance, such as for example coffee, disposed successively along a respective longitudinal direction. In particular, the cartridge (1) according to the present invention includes a support (2) of single portions adapted so that provides a more efficient and reliable movement of said support (2) of single portions out of said package casing (11).

The prior art includes several solutions relating to beverage preparation machines based on edible substances, and adapted so as to process a plurality of single doses provided in a strip-like or similar support that is displaced so as successively supply an extraction device adapted so as to extract a respective beverage.
Documents U.S. Pat. Nos. 3,143,954 and 3,213,777 disclose beverage preparation machines that present an actuation device adapted for moving a strip with a plurality of single doses successively up to an extraction device.
Document GB 2266228 discloses a machine of the same type adapted for operating with storage means of a strip presenting a plurality of single dose portions. Said document discloses a solution for the problem of the traction of the strip of multiple portions that is based upon providing a plurality of holes disposed along the side edges of the strip and adapted to be engaged by corresponding engagement saliences provided in an actuation mechanism. This solution presents several constrains, including in terms of greater construction complexity of said machine.
Document WO 2013/169134 A2 filed by the applicant of the present invention, discloses a machine for preparing beverages of the same type and adapted for processing a conduction support that provides a substantially hermetic envelope to a plurality of single doses. However, said document also does not disclose a solution that guarantees the transfer of movement by means of traction between the surfaces of the actuation element and the last single doses disposed furthest upstream in the support of single portions.
None of the documents in prior art disclose a solution for the efficient and reliable displacement of the end part of said support of single portions out of the respective packaging.
Moreover, none of the documents disclose a solution for fixating said package in simple manner in ergonomic terms and in reliable manner in operational terms, in a respective beverage preparation machine, so that the latter resists to the traction force exerted upon said support of single portions.

Supply cartridge, machine for preparing beverages and process of operation of a machine using said supply cartridge

Abstract: The present invention further refers to a machine (10) for preparing beverages, adapted for using a supply cartridge (1), as well as to a process of preparing beverages based upon a machine (10) for preparing beverages of the type of the present invention.

NOVADELTA—COMÉRCIO E INDÚSTRIA DE CAFÉS S.A.


The invention relates to an electric element, whose conductance is quantized in units 2e.sup.2 /h realized in a multi-dimensional charge carrier gas, which is provided with a part of reduced width having a width of the order of the Fermi wavelength and a length smaller than the average free path length. Due to the small width of the part of reduced width, the energy levels are subdivided, as a result of which, at a temperature at which the distance between the levels is comparable with kT, the charge transport through the constriction is determined by quantum-mechanical effects. For the charge carrier gas, for example, a two-dimensional electron gas near a GaAs-AlGaAs hetero-junction may be used, for example, in a voltage divider.

The invention relates to an element for use in an electric circuit having a layer or a layer structure; in which a multi-dimensional charge carrier gas can be formed and in which two regions are situated, which communicate with each other via a channel for the transport of charge carriers.
The term "multi dimensional charge carrier gas" is to be understood to means a three- or two-dimensional gas. A charge carrier gas of the last-mentioned kind is situated, for example, in the proximity of a hetero-junction between a doped semiconductor layer having a relatively large energy gap and an intrinsic semiconductor layer having a relatively small energy gap, the conduction band edge in the last-mentioned semiconductor material behaving energetically at a lower level than in the first-mentioned material. Due to the fact that an energy minimum occurs in the semiconductor material having a relatively small energy gap at a small distance from the junction, a cloud of electrons of very small thickness, i.e. practically a two-dimensional cloud, is generated by transport of electrons from the material having the relatively large energy gap near the hetero-junction. The electrons present in this cloud have a strongly increased mobility due to their spatial separation from the donor ions from which they orginate.
An element of the kink mentioned above is in the form of a HEMT (High Electron Mobility Transistor) known from Nishizawa, "Semiconductor Technologies", Tokyo, 1982, p. 258-271. The HEMT is essentially a field effect transistor, in which the conduction takes place in a practically two-dimensional electron gas. Due to the increased mobility in the electron gas, a high switching speed can be attained with the HEMT. The transistor is normally operated at such a temperature that the electron gas is not completely degenerated. The dimensions of the HEMT are usual for other more conventional types of transistors.
In practically all the elements for use in electric circuits, briefly designated hereinafter as electric elements, deviations in the electrical properties of the element occur. These deviations may be due to spreading in their manufacturing steps. As a result, the electrical properties of the finished products practically always deviate more or less from the values aimed at. Moreover, many electric elements are subjected during operation to ageing processes, as a result of which their electrical properties change.
Besides, deviations may be caused by changes in the environment in which the element is used, such as, for example, variations in the ambient temperature.
Thus, for example, the temperature coefficient of the resistivity of most materials has a value different from zero, as a result of which many elements are more or less sensitive to temperature.

Semiconductor structure having a conductive channel


Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.

1. Field of the Invention
The present invention relates to a flash memory having redundant circuits, and more particularly, to a flash memory capable of improving yields.
2. Description of the Prior Art
FIG. 13 is a configuration for illustrating a conventional flash memory device. In FIG. 13, reference numerals 1 to 5 represent memory blocks, respectively. Reference numerals 11 to 15 represent redundant circuits (redundant memory blocks), respectively. The redundant circuits 11 to 15 are positioned adjacent to the memory blocks 1 to 5, respectively. In the flash memory device being illustrated, bit lines BL0 to BL15 are located across the memory blocks 1 to 5. In addition, spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. For example, when a memory cell 8 is at fault in the memory block 5 in the flash memory device being illustrated, the memory cell 8 is replaced with the redundant circuit 15.
By the way, a wafer test 0 (WT0) is carried out in concern to a wafer in order to check whether or not a wafer has a malfunctioned memory cell after a wafer process finishes. More particularly, the WT0 is for checking whether or not the flash memory device has the malfunctioned memory cell. When the flash memory device has the malfunctioned memory cell, the location of the malfunctioned memory cell is stored which may be a malfunctioned memory cell 8 in FIG. 13. By laser trimming and so on, saving information is produced which is for use in replacing the bit line BL8 with the spare bit line SBL1 of the redundant circuits 11 to 15. The malfunctioned memory cell 8 is positioned at the bit line BL8.
After the above-mentioned WT0 is completed, the bit line BL8 having the malfunctioned memory cell 8 is replaced with spare bit line SBL1 of the redundant circuits 11 to 15 by the laser trimming on the basis of the remedy or saving information. A wafer test 1 (WT1) is carried out which is for testing the flash memory device in addition to the spare bit line SBL1 of the redundant circuits 11 to 15. When the flash memory device passes the test, the flash memory device is conveyed to a next process.
FIG. 14 shows a view for illustrating a structure of the memory cell. Reference numeral 101 represents a control gate (CG). A predetermined voltage is applied to the control gate 101 on carrying out a writing/erasing operation. Reference numeral 102 represents a floating gate. The floating gate 102 traps electrons on the basis of the writing/erasing operation. Reference numeral 103 represents an insulating film having an ONO structure. Reference numeral 104 represents a tunnel oxide film through which the electrons travel between the floating gate 102 and a base 105 in accordance with tunnel phenomenon.
In FIG. 14, +10V may be, for example, applied to the control gate 101 and 0V may be applied to the base 105 in case of setting a threshold voltage Vth of the memory cell to a high voltage, on the writing/erasing operation. On the other hand, xe2x88x9210V may be applied to control gate 101 and +10V is applied to the base 105 in case of setting the threshold voltage Vth of the memory cell to a low voltage.
As described above, the voltage of 20V is applied between the control gate 101 and the base 105 in case of setting the threshold voltage Vth of the memory cell to the low voltage. As a result, an electrical breakdown often occurs in each of the tunnel oxide film 104 and the ONO insulating film 103 when the memory cell has a defect or a foreign particle.
There is the breakdown of the insulating film and so on which are based on applying the high voltage to the tunnel oxide film 104 and the ONO insulating film 103, as a memory cell destruction mode on the wafer test. In the above-mentioned WT0 and WT1, the malfunctioned memory cell is removed which is based on the breakdown of the insulating film.
In general, the writing/erasing operations are repeated in concern to the memory blocks 1 to 5 at the WT0 and the WT1, in order to carry out the sufficient testing of the memory blocks 1 to 5. On the other hand, a minimum testing is carried out in concern to the redundant circuits 11 to 15 on the WT0, taking the testing time and the testing cost into consideration, inasmuch as there are some questions as to whether or not each of the redundant circuits 11 to 15 is actually used. For example, only one reading/writing operation is carried out in concern to the redundant circuits 11 to 15, in order to check whether or not data are correctly written in the each of the redundant circuits 11 to 15.
Under the circumstances, the probability of discovery of the malfunctioned memory cell is very high in concern to each of the memory blocks 1 to 5. It is often difficult to discover the malfunctioned memory cell and to remove the malfunctioned memory cell in concern to each of the redundant circuits 11 to 15.
As described above, there is a problem in a case where it is impossible to remove the malfunctioned memory cell in the WT0 even if any one of the redundant circuits has the malfunctioned memory cell. In other words, it is impossible to use the part corresponding to the memory cell of the memory block 2 that is positioned on the bit line BL8, when an error or destruction occurs in the memory cell (for example, the memory cell 9 of the redundant circuit 12) positioned on the spare bit line SBL1 of the replaced redundant circuit in the middle of repeating the writing/erasing operation in the next WT1. As a result, there is a problem in which the flash memory becomes an inferior product.
More particularly, it is necessary to carry out a serious testing inasmuch as the number of the writing/erasing operations inevitably increases, when the memory block is a boot memory block in which accessing frequencies are very high. When there is the malfunctioned memory cell in the redundant circuit 12 which corresponds to the boot memory block 2 after the malfunctioned memory cell of the boot memory block 2 is replaced with the redundant circuit in the WT0, there is a problem in which it is impossible to use the flash memory device although the malfunctioned memory cell of the boot memory block 2 has a very small memory area in comparison to the entire memory area of the flash memory device.
In addition, a potentially malfunctioned memory cell may be included in each of the redundant circuits inasmuch as the testing is not perfectly carried out in concern to each of the redundant circuits through the WT0 and the WT1. There is a problem in which the potentially malfunctioned memory cell becomes an actually malfunctioned memory cell when the flash memory device is under an actual use.
In a case where the malfunctioned memory cell is replaced with the redundant circuit (spare memory cell) in the manner described above, the replaced memory cell is destroyed on the basis of a great number of rewriting operations so that the word line concerned to the replaced memory cell becomes at fault. As a result, the flash memory device becomes at fault. In this event, it is necessary for the memory block to have no potentially malfunctioned memory cell in case where a great number of rewriting operations are carried out in concern to the memory block.
In addition, dummy bit lines may be positioned at both sides of each memory cell in the flash memory device, in order to make a work shape become stable in the wafer process. A memory cell exists on each of the dummy bit line which is connected to the memory cell of the memory block and the memory cell (spare memory cell) of the redundant circuit.
In this case, it is impossible to carry out testing of dummy bit lines through the WT0 and WT1. For example, when the dummy bit line corresponding to the boot memory block is destroyed on the basis of a great number of rewriting operations, the word line concerned to the memory cell of the dummy bit line becomes at fault. As a result, the flash memory device may be at fault. Under the circumstances, it is also necessary for the memory block to have no potentially malfunctioned memory cell in the dummy bit line in order to ensure the memory block to carry out a great number of rewriting operations. However, there is a problem in which quality assurance is difficult inasmuch as it is impossible to carry out the testing of each of dummy bit lines in the WT0 and WT1.
In order to dissolve the above-mentioned problems, it is an object of this invention to provide a flash memory device capable of preventing reduction of the yield that is based on a memory cell failure of a redundant circuit.
In addition, it is another object of this invention to provide a flash memory device capable of preventing occurrence of failure that is based on a potentially malfunctioned memory cell of a redundant circuit, in an actual use.
Furthermore, it is still another object of this invention to provide a flash memory device capable of preventing occurrence of failure that is based on a potentially malfunctioned memory cell positioned on a dummy bit line, in an actual use.
A flash memory device according to this invention comprises a plurality of memory blocks and redundant circuits corresponding to said memory blocks, respectively. The flash memory device further comprises replacing means for carrying out replacement by remaining redundant circuits except a particular one of the redundant circuits that corresponds to at least predetermined one of the memory blocks, when a memory cell failure occurs in at least one of the remaining memory blocks except the predetermined memory block.
In a flash memory device according to this invention, bit lines are located across the memory blocks and spare bit lines are located across the redundant circuits. The replacing means makes a specific one of the spare bit lines turn the particular redundant circuit to connect the specific spare bit line to the predetermined memory block when the memory cell failure occurs in at least one of the remaining memory blocks and when the bit line corresponding to the memory cell failure is replaced with the specific spare bit line.
In a flash memory device according to this invention, the predetermined memory block is a memory block which has highest access frequencies among the memory blocks.
In a flash memory device according to this invention, the predetermined memory block is a memory block which has a least memory capacity among the memory blocks.
A flash memory device according to this invention comprises a plurality of memory blocks and redundant circuits corresponding remaining memory blocks, respectively, except at least predetermined one of said memory blocks. The flash memory device further comprises bit lines located across said memory blocks, spare bit lines located across said redundant circuits, and means for connecting the predetermined memory block to a specific one of the spare bit lines when a memory cell failure occurs in at least one of the remaining memory blocks so that the bit line corresponding to the memory cell failure is replaced with the specific spare bit line.
In a flash memory device according to this invention, a word line is located along each pair of the memory block and the redundant circuit. The word line located along the predetermined memory block is disconnected between the predetermined memory block and the particular redundant circuit. A predetermined voltage is applied to the word line located along the predetermined memory block, at a side of the particular redundant circuit.
In a flash memory device according to this invention, a word line is located along to each pair of the memory block and the redundant circuit. The word line located along the predetermined memory block is disconnected between the predetermined memory block and the particular redundant circuit. The word line located along the predetermined memory block is put into a floating state at a side of the particular redundant circuit.
In a flash memory device according to this invention, a word line is located along each pair of the memory block and the redundant circuit. Well are formed in each of the predetermined memory block and the particular redundant circuit to be independent of each other. A predetermined voltage is applied to the well formed in the particular redundant circuit.
In a flash memory device according to this invention, each of the memory blocks and the redundant circuits has a memory cell. The memory cell of the particular redundant circuit has no floating gate.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along each pair of the memory block and the dummy cell. A selected word line located along a selected memory block is selectively disconnected between the memory block and the dummy cell. A predetermined voltage is applied to the word line at a side of the dummy cell for the word line disconnected between the memory block and the dummy cell.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along to each pair of the memory block and the dummy cell. The word line located along each of the memory blocks is selectively disconnected between the memory block and the dummy cell. The word line is put into a floating state at a side of the dummy cell when the word line is disconnected between the memory block and the dummy cell.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along each pair of the memory block and the redundant circuit. Wells are selectively formed in each pair of the predetermined memory block and the dummy cell so as to be independent of each other. A predetermined voltage is applied to the well formed in the dummy cell.

Flash memory having enhanced yield and having enhanced reliability in redundant and dummy circuits


When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

After an integrated circuit is manufactured, it is typically tested both to check that manufacturing defects are not present in the silicon (manufacturing testing), and to verify that it correctly performs its specified function (functional testing). While manufacturing test is done with a tester, functional testing is typically done "in-system," where the target IC is coupled to other ICs to form a system, and the system is tested with signals that might be expected during the intended use. In general, the input stimuli that the IC receives during such in-system testing are not known in advance and, hence, the expected values of these stimuli cannot be predicted.
In accord with one form of conventional functional testing, different aspects of the IC behavior are checked during its normal at-speed operation, but such testing is typically not automated. Moreover, such testing suffers from the lack of observability of internal IC signals. Assertion checking would be an ideal form of verification for an environment where expected values are not known, because assertions rely on expected relations between signals. However, assertions are not usually implemented in hardware (i.e., built within the IC) because of the high cost of the additional hardware required for a large number of assertions.
In accord with another form of functional testing, diagnostic programs are executed on an embedded processor, in which case the final results out of the IC can be predicted after a sequence of operations.
Once functional testing detects an error, the task that naturally arises next is to locate the root cause of the observed misbehavior. Although integrated circuits are extensively verified before manufacturing, their typically immense complexity often results in logic and timing errors being still discovered in many of the chips tested at-speed in-system. Consequently, a systematic procedure for locating logic errors detected by in-system at-speed functional testing, which is currently not available, is highly desirable.
It is also worth noting that a functional test may fail not because of a logic error but because of a manufacturing defect. Although functional testing is usually preceded by manufacturing testing, manufacturing tests are often not exhaustively complete. Consequently, there may be certain manufacturing defects that escape detection during manufacturing tests. If the functional test detects such a defect, the conventional tester-based diagnosis techniques are not applicable, since it is difficult to reproduce the at-speed functional test on a tester. With in-system testing, on the other hand, a first problem is to determine whether the failure is due to a logic error or to a manufacturing defect. A systematic procedure for locating manufacturing defects detected by in-system functional testing is currently also not available.
The above-mentioned '993 application and the applications to which this '993 relates disclose numerous techniques and advantages of integrated circuits that are constructed with wrapped cores (blocks of the integrated circuit). Specifically, the '101 application discloses a system-on-a-chip (SoC) with configurable wrappers, the '854 and '774 applications disclose assertion checking of SoCs with the use of the configurable wrappers, the '774 and '709 application disclose effectively masking the effects of an error in the SoC by use of the configurable wrapper, and the '993 application discloses a method that enables determining the value of any signal (target signal) in a combinatorial circuit of an SoC that is otherwise unobservable.
When an assertion checking run discovers an error, however, the methods disclosed in the above-identified applications do not identify the particular signal or signals that cause of the error. If discovery of such an error can lead to a correction in the SoC's design then, of course, finding the source of the error (in contradistinction to merely masking its effect) is desirable. It is also desirable to find out whether the error is caused by a manufacturing defect and to locate it, because in such a case there is no need to correct the error, but to enhance the manufacturing test to detect that defect.

Method to locate logic errors and defects in digital circuits


An ultrasonic probe includes a substrate having an opening section, a support film disposed on the substrate, a piezoelectric body disposed on the support film at the opening section, first and second resin sections, and a communicating section. The first resin section is disposed at a position overlapping the opening section in the plan view and spaced apart from the support film with the liquid being arranged therebetween. The communicating section is connected to the first resin section. The second resin section is connected to the communicating section to house the liquid flowing in through a communication hole of the communicating section. At least portions of the first and second resin sections are configured to deform such that a first liquid filled volume formed between the first resin section and the support film and a second liquid filled volume formed by the second resin section are changed.

1. Technical Field
The present invention relates to an ultrasonic probe that transmits an ultrasonic wave to a test object and receives a reflected wave (echo) from the test object and also relates to an ultrasonic image diagnostic device that uses the ultrasonic probe.
2. Related Art
There is a known conventional ultrasonic sensor that detects a position or state of a test object using an ultrasonic transducer configured to emit and receive ultrasonic waves (see Japanese Laid-Open Patent Publication No. 2009-25179).
Japanese Laid-Open Patent Publication No. 2009-25179 discloses an liquid detecting unit (ultrasonic sensor) comprising an ultrasonic wave output section equipped with an ultrasonic transducer and an acoustic impedance matching layer provided on the ultrasonic wave output section. This liquid detecting unit has an ultrasonic wave receiving/emitting surface formed on a portion of one side of the ultrasonic wave output section. The acoustic impedance matching layer is formed on the one side of the ultrasonic wave output section, and an output surface that outputs ultrasonic waves is provided on the opposite side of the acoustic impedance matching layer as the ultrasonic wave output section. A fluid binder holding recess is formed in the output surface and when the output surface of the liquid detecting unit is to be put into contact with a container, the fluid binder holding recess is filled with a fluid binder before the output surface is made to contact the container. Also disclosed is a configuration in which a cylindrical recess forming member is provided in the one side of the ultrasonic wave output section and a fluid binder holding recess is formed by filling an interior of the recess forming member with ah acoustic impedance layer. When the output surface is to be touched against a container, the fluid binder holding recess is filled with a fluid binder.

Ultrasonic probe and ultrasonic image diagnostic device


A bicycle training apparatus having an elevator assembly, a wheel support assembly operatively coupled to the elevator assembly, and a resistance interface assembly operationally coupled to the elevator assembly. The elevator assembly operates to raise and lower the wheel support assembly, and the resistance interface assembly provides an output signal proportional to the height of the wheel support assembly.

1. Field of the Invention
The present invention relates generally to devices for exercise, and more specifically to, devices for stationary bicycle training.
2. Background of the Related Art
Aerobic exercising apparatuses are well known in many forms which emulate real-world, non-stationary activities in a stationary manner. These include, among others, stationary exercising devices which emulate rowing, cycling, cross-country and downhill skiing, ice skating, walking, running, stair climbing, and rock climbing.
A wide variety of exercisers are known in the field of stationary bicycle exercisers. These include, among others, the devices disclosed in the following patents.
First, U.S. Pat. No. 4,834,363 to Sargeant, et al., entitled "Bicycle Racing Training Apparatus," discloses an exercising apparatus for supporting a bicycle. The apparatus includes a flywheel and variable load means connected to a roller in contact with the bicycle's rear wheel to simulate the inertia and variable load experienced by a rider during a real-world ride. U.S. Pat. No. 4,938,475, also to Sargeant, et al. and entitled "Bicycle Racing Training Apparatus", discloses, in addition to the apparatus disclosed in the previously discussed patent, means for varying the load applied from the variable load means to simulate real-world bicycle race conditions.
Next, U.S. Pat. No. 4,955,600 to Hoffenberg et al. and entitled "Bicycle Support and Load Mechanism" discloses an apparatus for receiving a bicycle to enable stationary exercise thereupon. The device includes a mechanism for applying differing loads to the rear wheel to simulate real world cycling conditions such as road incline, wind resistance, and tire to road friction. U.S. Pat. No. 6,702,721 to Schroeder, entitled "Bicycle Trainer with Movable Resistance Device" discloses a similar device.
In a like manner, U.S. Pat. No. 6,056,672 to Tendero, entitled "Training Apparatus for Cyclist and for Physical Exercise" discloses a device which receives a bicycle. The bicycle is positioned on a running belt and is constrained so as to permit lateral movement while restraining linear movement.
Somewhat similar to the foregoing is U.S. Pat. No. 6,648,802 to Ware, entitled "Variable Pitch Stationary Exercise Bicycle", which discloses a bicycle-like exercise apparatus which varies rear wheel resistance based on user controlled inclination or declination of the pseudo bicycle frame. U.S. Pat. No. 5,035,418 to Harabayashi and entitled "Cycle Type Athletic Equipment" also discloses a bicycle type exercise apparatus that tilts in a variety of orientations. U.S. Pat. No. 5,549,527 to Yu, entitled "Stationary Bike," likewise discloses a bicycle-like apparatus that alternates between an inclined and declined orientation to simulate uphill and downhill terrain. The device further includes a brake shoe which engages with a wheel to increase friction when the apparatus is in a simulated uphill orientation.
U.S. Pat. No. 5,240,417 to Smithson et al., entitled "System and Method for Bicycle Riding Simulation" discloses an interactive, computer controlled bicycle simulation arcade style game. The disclosed apparatus includes a simulated bicycle that includes front and rear wheels solely for visual appearance. A computer and user each partially controls the movement of the simulated bicycle in connection with an animated bicycle displayed on a screen. The computer controls the simulated bicycle in part to simulate changes in track terrain, including uphill and downhill gradations.
Similarly, U.S. Pat. No. 5,890,990 to Bobick et al., entitled "Interactive Exercise Apparatus" discloses a computer manipulated exercise device in which a computer controls various feedback components such as resistance to simulate a real world or artificial environment for an exerciser. The computer disclosed also updates a display of a virtual environment on a screen based on user inputs such as pedal speed and steering changes.
U.S. Pat. No. 5,785,631 to Heidecke, entitled "Exercise Device", discloses a bicycle-like apparatus that includes partial computer control over pedal resistance, as well as device orientation, so as to simulate inclined terrain and the like. The disclosed apparatus also may include a display device displaying simulated environments.
Still other exercise apparatuses simulate bicycling in a minimal manner. One such apparatus is disclosed in U.S. Pat. No. 5,354,251 to Sleamaker, entitled "Multifunction Exercise Machine with Ergometric Input-Responsive Resistance." The apparatus disclosed in this reference includes, among other configurations, a means for a user to exercise via pedals with resistance provided by the user's weight.
The foregoing devices have several shortcomings. For example, the several apparatuses discussed above that include simulated bicycles do not permit exercisers to use their own bicycles—a significant flaw for serious cyclists such as those involved in competitive cycling. These users generally desire to train on the same bicycle used in actual competition, not a different, simulated bicycle. Likewise, none of these apparatuses allow a user to mount his or her own bicycle in a device that simulates inclinations and declinations through varied bicycle orientation and cycling resistance proportional thereto. Furthermore, none permit a user to mount a bicycle into an apparatus that simulates real world conditions through video displays and the like.
With these considerations in mind, it is desirable to have an apparatus and method for using the same which permits serious cyclists to use


The present invention provides an adapter for use inconjunction with a paint can having an opening at one end and an inwardly extending rim adjacent the open end of the can. A continuous groove is provided around the rim and this groove has a preset width and a preset depth. The adapter includes an annular body which is dimensioned to be insertable into the can groove and to form a seal between the adapter and the paint can rim. The precise dimension of the body may vary between different can manufacturers. An annular channel is provided around an outwardly facing side of the body and this channel is adapted to receive and sealing engage a sealing flange on a standardized lid for the can.

I. Field of the Invention
The present invention relates to an adapter to enable a standardized lid to be used with different-sized cans.
II. Description of the Prior Art
Conventional paint cans typically comprise a tubular cylindrical casing having an opening at one end. An inwardly extending rim is provided adjacent the open end of the paint can and this rim includes an annular and inwardly extending groove. This groove is adapted to cooperate with the sealing flange on the lid provided with the paint can.
In many operations, however, it is impractical to repeatedly remove the lid provided with the paint can and, after use, replace the paint can lid provided with the paint can. For example, in automotive body shops it is necessary that paint of many different colors be mixed and ready for application without any appreciable time delay. The time required to remove the paint can lid provided with the paint can, mix the paint and thereafter replace the paint can lid unacceptably increases labor cost.
Consequently, many body shops and the like use paint mixing equipment having a plurality of shelves in a rack which supports paint cans of different colors. Additionally, the conventional lid of the paint can is replaced by a substitute lid having both a stirring element and a spout. Upon insertion of the paint can into the paint can rack, mechanical means engage the stirring element so that the paint in the paint cans is continuously mixed or stirred while the can is positioned in the rack. Thus, when paint in the can is required, the paint can is removed from the rack with this lid, dispensed through the dispenser on the lid and then replaced within the rack so that mixing of the paint continues.
One difficulty in manufacturing paint mixing equipment of the type used in body shops is that there is little standardization of the size of the paint can rims even for the same quantity of paint, e.g. quart size or gallon size. Thus, a quart size paint can from two different manufactures may have different size rims. This is particularly true in Europe where liter paint cans are employed and there is virtually no standardization from one country to the next.
Consequently, in order to provide paint mixing equipment capable of accepting cans from different paint manufacturers, it has been previously required to separately manufacture a different paint can lid with the mixing element and dispensing spout for each different manufacturer. Typically, these lids include a sealing flange which extends into the paint can opening and is secured in place by locking feet. The size of the sealing flange, however, still varies from one manufacturer to the next.
The previously known requirement of separately manufacturing different lids for different manufactures increases the overall costs of the paint mixing equipment.


The present invention is a system, method, and computer program product for compression and reconstruction of a color image using principal components transformation. The method is performed on a computer or other programmable data processing apparatus. The method is performed in combination with the standard JPEG image compression technique. According to the invention, the method receives color image information. The received color image information is converted into intrinsic color information. The intrinsic color information is based on the color image""s intrinsic and unique color distribution.

The present invention relates to true color image compression and reconstruction. More particularly, the present invention relates to lossy compression and reconstruction using an image specific color transformation.
JPEG (pronounced xe2x80x9cjay-pegxe2x80x9d) is a standardized image compression mechanism. JPEG stands for Joint Photographic Experts Group, the original name of the committee that wrote the standard. JPEG is designed for compressing either full-color or gray-scale images of natural, real-world scenes. It works well on photographs, naturalistic artwork, and similar material; not so well on lettering, simple cartoons, or line drawings. JPEG handles only still images. JPEG is xe2x80x9clossy,xe2x80x9d meaning that the decompressed image isn""t quite the same as the one you started with. JPEG achieves much greater compression than is possible with lossless methods. JPEG is designed to be lossy, and thus exploits the known limitations of the human eye. More specifically, the fact that small color changes are perceived less accurately than small changes in brightness. Thus, JPEG is intended for compressing images that will be looked at by humans. In contrast, the small errors introduced by JPEG may be a problem for images intended to be machine-analyzed.
A useful property of JPEG is that adjusting compression parameters can vary the degree of lossiness. This means that the image-maker can trade off file size against output image quality. You can make extremely small files if you don""t mind poor quality, such as indexing image archives. Conversely, if you aren""t happy with the output quality at the default compression setting, you can increase the quality until you are satisfied, and accept lesser compression.
The JPEG compression algorithm may be implemented in both software and hardware. For example, C-Cubed Microsystems introduced the first JPEG chip for compressing digital video images. Hardware provides the requisite speed for real-time compression. JPEG++, an algorithm described in U.S. Pat. No. 5,014,198, developed by Storm Technology, is an extension to JPEG.++ JPEG allows selected picture areas to be compressed at different ratios depending on the significance of the visual impact to the area in the image.
A problem with the traditional JPEG algorithm, and each of the aforementioned techniques, is that they all employ a fixed color space transformation. Generally, a fixed color space transformation is employed to transform an image from RGB into a luminance/chrominance color space (i.e., xe2x80x9cYUVxe2x80x9d), where luminance is the first component and chrominance the second and third components. To perform the transform a fixed predetermined matrix is employed that transforms the image from a RGB color space into a luminance/chrominance color space represented in an unsigned byte form (i.e., xe2x80x9cYCrCbxe2x80x9d). The rationale for using a luminance/chrominance color space is that some chrominance information can be lost in an image since the human eye is less likely to perceive the changes in the chrominance or color component of a reconstructed image. As a result, the chrominance components are subsampled or reduced, while the luminance component is left at full resolution.
Unfortunately, the use of a predetermined matrix to execute the transformation does not assure that the most information is presented in the first component because it does not consider the wide variety of possible scene content. More specifically, the transformation does not actively control or attempt to provide the most information about an individual image in the first component. Consequently, all images are treated equally despite the errors that may occur when reconstructing a compressed image, and thus affect image perception. Accordingly, images or applications that have a lower tolerance for loss are compressed at lower ratios since more information in the second and third components is required. This results in larger files, and thus less file storage space. In addition, larger files require significantly more time to transmit from a host to a remote site than smaller files. As a result, a method is needed that provides optimal image compression to improve file storage capacity and transmission time, while reducing image quality degradation.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a computer system and corresponding operating method which overcomes the above-described deficiencies. The present invention was motivated by a desire to overcome the drawbacks and shortcomings of the presently available technology, and thereby fulfill this need in the art.
It is therefore a feature and advantage of the present invention to provide an image compression and reconstruction technique that improves the image quality of a reconstructed image.
It is another feature and advantage of the present invention to reduce image quality degradation at high compression ratios.
It is another feature and advantage of the invention to optimize utilization of file space.
It is a further feature and advantage of the invention to compress a color image utilizing a transformation that is different for each image.
It is another feature and advantage of the invention to generate a transformation based on the color image""s color distribution.
It is a further feature and advantage of the invention to reduce transmission time in sending compressed images.
Further features and advantages of the invention will become apparent to those skilled in the art with reference to the accompanying figures and written description below.
The present invention is a system, method, and computer program product for compression and reconstruction of a color image using principal components transformation. The method is performed on a computer or other programmable data processing apparatus. The method is performed in combination with the standard JPEG image compression technique. According to the invention, the method receives color image information. The received color image information is converted into intrinsic color information. The intrinsic color information is based on the color image""s intrinsic and unique color distribution. This intrinsic color information characterizes the color image in a manner that increases the image quality of a reconstructed image, reduces the size of a compressed file as well as image transmission time.

Lossy JPEG compression/reconstruction using principal components transformation


A reflector with focused output is disclosed. The reflector comprises a reference parabolic portion and a plurality of non-reference parabolic portions. A focal length of the plurality of non-reference parabolic portions is determined from a focal length of the reference parabolic portion. In one embodiment, the focal length of the plurality of non-reference parabolic portions is a perpendicularly projected distance from a focus of the reference parabolic portion onto a central axis of the plurality of non-reference parabolic portions. In one embodiment, the focal lengths of the reference parabolic portion and the plurality of non-reference parabolic portions are scaled by a constant. A method of designing a reflector and an obstruction light that uses the reflector is also disclosed.

A planar parabolic reflector focuses a wave such as a light beam along the parabolic plane, as shown in the prior art FIG. 1. However, the intensity profile along the plane perpendicular to the parabolic plane is fixed and it is not versatile enough to be used in specific applications.


A membrane-electrode assembly for a fuel cell includes an anode and a cathode facing each other and a polymer electrolyte membrane interposed therebetween. At least one of the anode and the cathode includes a conductive electrode substrate and a catalyst layer formed thereon, and the catalyst layer includes a first catalyst layer including a first metal catalyst that grows from the polymer electrolyte membrane toward the electrode substrate and a second catalyst layer including a second metal catalyst covering the first catalyst layer.

(a) Field of the Invention
The present invention relates to a membrane-electrode assembly for a fuel cell, a method of manufacturing the same, and a fuel cell system including the same.
(b) Description of the Related Art
A fuel cell is a power generation system for producing electrical energy through an electrochemical redox reaction of an oxidant and hydrogen in a hydrocarbon-based material such as methanol, ethanol, or natural gas.
Such a fuel cell is a clean energy source that can replace fossil fuels. It includes a stack composed of unit cells, and produces various ranges of power output. Since it has four to ten times higher energy density than a small lithium battery, it has been high-lighted as a small portable power source.
Representative exemplary fuel cells include a polymer electrolyte membrane fuel cell (PEMFC) and a direct oxidation fuel cell (DOFC). The direct oxidation fuel cell includes a direct methanol fuel cell, which uses methanol as fuel.
The polymer electrolyte membrane fuel cell has an advantage of a high energy density, but it also has problems in the need to carefully handle hydrogen gas and the requirement of accessory facilities such as a fuel reforming processor for reforming methane or methanol, natural gas, and the like in order to produce hydrogen as the fuel gas.
On the contrary, a direct oxidation fuel cell has a lower energy density than that of the polymer electrolyte membrane fuel cell, but it has advantages of easy handling of fuel, being capable of operating at room temperature due to its low operation temperature, and no need for additional fuel reforming processors.
In the above fuel cell, the stack that generates electricity substantially includes several to scores of unit cells stacked in multi-layers, and each unit cell is formed of a membrane-electrode assembly (MEA) and a separator (also referred to as a bipolar plate). The membrane-electrode assembly has an anode (also referred to as a fuel electrode or an oxidation electrode) and a cathode (also referred to as an air electrode or a reduction electrode) attached to each other with an electrolyte membrane between them.
Fuel is supplied to an anode and absorbed in a catalyst thereof, and the fuel is oxidized to produce protons and electrons. The electrons are transferred into a cathode via an external circuit, and the protons are transferred into the cathode through a polymer electrolyte membrane. An oxidant is supplied to the cathode, and the oxidant, protons, and electrons are reacted on a catalyst at the cathode to produce electricity along with water.

Membrane-electrode assembly for a fuel cell and a fuel cell system including the same

Gongse-dong, Giheung-gu, Yongin-si, Gyeonggi-do


An example integrated circuit for use in a power supply includes a feedback terminal, a controller and a clamp. The feedback terminal is to be coupled to receive a feedback signal that is representative of a bias voltage across a bias winding of the power supply. The controller is to be coupled to control switching of a power switch included in the power supply in response to the feedback signal. The clamp is coupled to clamp the feedback terminal to a voltage for at least a time that the bias voltage is negative with respect to an input return of the power supply.

Many electrical devices such as cell phones, personal digital assistants (PDA's), laptops, etc. are powered by a source of relatively low-voltage DC power. Because power is generally delivered through a wall outlet as high-voltage AC power, a device, typically referred to as a power supply, is required to transform the high-voltage AC power to low-voltage DC power. The low-voltage DC power may be provided by the power supply directly to the device or it may be used to charge a rechargeable battery that, in turn, provides energy to the device, but which requires charging once stored energy is drained. Typically, the battery is charged with a battery charger that includes a power supply that meets constant current and constant voltage requirements required by the battery. In operation, a power supply may use a controller to regulate output power delivered to an electrical device, such as a battery, that may be generally referred to as a load. More specifically, the controller may be coupled to receive feedback information about the output of the power supply in order to regulate power delivered to the load. The controller regulates power to the load by controlling a power switch to turn on and off in response to the feedback information to transfer energy pulses to the output from a source of input power such as a power line.
One particular type of power supply that may be used is a flyback power supply. In one type of flyback power supply, an energy transfer element isolates the input of the power supply from the output of the power supply. The energy transfer element provides the isolation that prevents DC current from flowing between the input and the output.
A typical way to generate a feedback signal for use by the controller in a flyback power supply and still maintain isolation is to use an optocoupler on the output to send a signal to the controller. Another known way is by using sensing circuitry on the input side of a galvanically isolated power supply, also referred to as "primary-side control". One example of primary side control is to include an additional "auxiliary" or "bias" winding in the energy transfer element that is magnetically coupled to the output side to generate a voltage that is representative of the output of the power supply. Additionally, the bias winding may provide a voltage that is representative of an input voltage of the power supply.
However, utilizing the waveforms generated on the auxiliary winding often requires the inclusion of numerous electrical components external to the controller to condition the signals for receipt by the controller.

Variable time clamp for a power supply controller


A hand tool has a plurality of similarly or identically shaped rollers aligned end-to-end along an axle such that the outer surface of each respective roller moves about an axis define by the axle. The hand tool may be a roofing roller tool that enables an impermeable vapor membrane or sheet to be applied to a vertical wall extending upwardly from an outer perimeter of a roof. The tool may be manipulated by an elongated pole handle coupled to a roller head or roller head frame.

Sheets of roofing membrane are commonly used in many industrial and commercial roofing applications wherein large sheets of a waterproof membrane, are overlapped and then heated and pressed together to form a heat weld. These sheets are usually an elastomeric-type of material such as various rubber compositions, or thermoplastic sheets and the like. When done properly this method forms a strong water impervious seam which prevents subsequent peeling apart of the seam and prevents the penetration of water into the roof of a structure below the membrane. Various types of devices have been developed for initially heating the edges of the overlapped membrane sheets, such as power propelled roller mechanisms which move along the seam and applies pressure to the overlapped sheets with a following roller. These machines work well for long flat horizontal seams (i.e., parallel to the foundation of the building) but cannot function as well along vertical seams (i.e., orthogonal or perpendicular to the foundation of the building).
In another type of apparatus and method, an installer using a hand-held heat gun such as disclosed in U.S. Pat. No. 4,894,112, presses the heated overlapped membrane sheets together by use of a hand roller which is moved along the heated edges. This manual heating of the overlapping membrane edges followed by the subsequent roller pressure applied thereto, is used at various locations on a roof, especially to form the overlapping joints around various protrusions and joints which occur on a roof such as around skylights, ducts, overhanging locations, corners, etc. It has been found that the locations around such protrusions and joints are more time-consuming to do properly and are more difficult to form the water impervious seam than in the flat straight seams. Thus, such seams and joints almost always will be formed with hand-held roller and hand-held heat applying gun.
Some buildings include a vertical wall adjacent a portion of the perimeter edge of the building that extends upwardly above the flat horizontal portion of the roof. This may function as a façade to mount a sign that is visible to persons from below. Additionally, the vertical wall on the roof blocks persons from below from viewing various industrial components, such as satellites, HVAC units and the like, which are typically considered an eyesore.
The interior vertical face of the vertical wall is at least partially covered with the roof membrane. Usually, a length of the roof membrane is longer than the flat portion of the roof such that the end of the membrane runs upwardly from the bottom corner of the roof. The membrane forms a rounded corner that prevents water from accumulated near the outer peripheral edges of the roof.
It is often difficult to apply the membrane to the vertical wall of the roof due to the relatively large surface area of the portion of the membrane that extends up the vertical wall. Further, the vertical seams formed by adjacent overlapped membranes are difficult to seal because the vertical orientation makes it difficult for an installer to apply the required force and leverage to seal the seam.
Impermeable membranes are also used in other areas of the building. For example, the foundation of the building typically includes an impermeable membrane attached or adhered in order prevent fluid from entering the building. This is sometimes referred to as waterproofing. The foundation of the building is also a vertical surface that is difficult to apply membranes to due to the large surface area that needs covered.
Some references teach rolling tools that could be used with impermeable membranes. These exemplary rolling tools are: DE2928300A1; U.S. Pat. No. 6,135,934; US2004/0002414; US2016/0201333; and WO2017/183023. However, these tools would prove difficult for applying the impermeable membranes to a vertical surface due to their construction and configuration.

Roller for applying a sheet or membrane to a generally vertical surface


An orbital downhole separator for separating well fluids into constituents of different specific gravities. Specifically, it is designed to separate water from oil or gas. The apparatus comprises a housing with a rotating member therein driven by a motor in the housing. Well fluid flows through the rotating member and is subjected to centrifugal force to separate the components. A flow conditioner is used to facilitate separation. The invention includes several different versions of the flow conditioner including an impeller, a stator and controllers for controlling the speed of the motor in response to signals related to the amount of petroleum in the water.

This invention relates to downhole separators used in oil and gas wells, and in particular, to an orbital downhole separator driven by an internal motor and having a flow conditioner to improve fluid separation and control systems for such separators.
Oil and/or gas wells quite often pass through a productive strata the yield of which includes oil, gas and other valuable products but also includes undesirable and unwanted constituents such as salt water. In oil well production operations, relatively large quantities of water are frequently produced along with the valuable petroleum products. This is particularly true during the latter stages of the producing life of a well. Bringing this water to the surface and handling it there represents a significant expense in lifting, separation and disposal.
Various methods have been employed for extracting the valuable petroleum yield from the unwanted constituents. Some have involved the pumping of the total yield of the well to the surface and then using various methods for separating the valuable products from the unwanted portion. In addition, the unwanted portion of the yield, after having been pumped to the well surface and separated, often has been pumped downwardly again through a remote wellbore into a disposal layer. This, of course, also increases expenses.
In some oil wells, the unwanted constituents can amount to as much as 80% to 90% of the total formation yield. Accordingly, to obtain a given volume of valuable petroleum from the well fluid, eight or nine times the volume of the petroleum must first be pumped to the surface and then separated from the unwanted portion. As already noted, this process can be very slow and expensive. Although the problem of producing substantially water-free oil from the well reservoir may occur at any state in the life of an oil well, the proportion of water to valuable yield generally increases with time as the oil reserves decline. Ultimately, when the lifting cost of the combined petroleum and water constituents exceeds the value of the recovered oil, abandonment of the well becomes the only reasonable alternative.
Many procedures have been tried for producing water-free oil from a formation that has a large quantity of water. For example, the oil and water produced are pumped or otherwise flowed together to the surface where they are treated to separate the petroleum from the water. Since the volume of water is usually much greater than that of the oil, the separator must handle large volumes of fluid and therefore is correspondingly large and expensive. Moreover, the water produced contains mineral salts which are extremely corrosive, particularly in the presence of air. Also, flowing the oil and water together upwardly through the well sometimes forms emulsions that are difficult to break. Such emulsions frequently must be heated in order to separate them even when in the presence of emulsion-treating chemicals. The heating of the large amount of water, as well as the small amount of oil requires an expenditure of large amounts of energy, reducing the net equivalent energy production from the well.
Water produced from deep formations within the earth frequently contains large amounts of natural salts. For this reason, the salt water brought to the surface cannot be disposed of by allowing it to flow into surface drains or waterways. Relatively small amounts of salt water can sometimes be disposed of by draining into a slush pit or evaporation tank. The normally required disposal method for large volumes of salt water, however, is to introduce the water into a subsurface formation. This requires a disposal well for receiving the produced salt water.
By returning the water to the same formation in this manner, the water is disposed of and also acts as a re-pressurizing medium or drive to aid in maintaining the bottomhole pressure for driving the well fluids toward the producing well. But, in those areas where producing wells are widely separated, the cost of drilling disposal wells for each producing well is often prohibitive. In such instances, it is necessary to lay a costly pipeline-gathering network to bring all of the produced water to a central location, or alternatively, to transport the produced water by trucks or similar vehicles. Regardless of the method for transporting the waste salt water from a producing well to a disposal well, the cost of the disposal can be, and usually is, prohibitive. Furthermore, fluids from subterranean reservoirs can have undesirable characteristics such as creating excessive pressure and super-heating of the fluids. If excessive pressure is present, then surface equipment, such as a choke manifold, must be installed to choke the flow pressure down to about 2,000 psi, a manageable pressure. If a highly pressurized fluid depressurizes within a short period of time, then a large portion of the gas is "flashed". This reaction adversely affects the desirable petroleum from the formation yield. In general, both well seals and surface equipment suffer in the presence of excessive fluid pressure and heat. This equipment is expensive in terms of maintenance and capital costs. Thus, it is highly desirable to minimize these undesirable characteristics of the well flow before being brought to the surface.
Downhole separation of water from oil in a well is a desirable approach for disposal of formation water in the well. It eliminates or reduces the excessive costs discussed above required to pump the water to the surface and dispose of it. Furthermore, the greatly reduced environmental impact of the produced water is another factor in making this approach attractive.
Earlier downhole separators are shown in U.S. Pat. Nos. 5,156,586; 5,484,383; and 6,367,547.
The use of downhole separators eliminates or reduces the excessive costs discussed above to pump the water and dispose of it. Furthermore, the greatly reduced environmental impact of the produced water is another factor in making this approach attractive.
Improvements of prior art separators are desirable to further improve efficiency. The present invention includes a separator with a rotating cylinder and a variety of flow conditioners to increase the efficiency of the separator. One embodiment of the present invention adds an impeller to pump the fluid into an annulus to increase tangential fluid velocities. In another, a stator is used to orient the fluid to enter the impeller with a minimum of shearing action. In still another, baffles are positioned in an annular space in the rotor to force the fluid to rotate at the shaft velocity which will improve the separation efficiency.
In another embodiment, a multi-lip cup designed to facilitate multi-density substances so that they are separated into different conduits is used.
In another embodiment, a smart controller is used to control the speed of the motor to modulate the oil concentration in the outlet water. This control function is achieved without the use of a sensor for oil-concentration feedback by measuring the voltage and the current of the motor. The voltage is a measure of the rotor speed, and the current is a function of the applied torque. The torque in turn varies with the water-cut (the ratio of water to oil). By establishing the relationship between the torque and the water-cut and the speed, the motor speed can be adjusted to operate at the desired set point.
A further embodiment utilizes a speed control which has an oil-in-water concentration sensor feedback in conjunction with a conventional PID controller or an adaptive controller for the control function. The motor speed is adjusted to achieve the oil concentration in the out fluid stream on the water side. One way of doing this includes using a valve on the downstream side of the water side which is modulated to achieve the quality of the water to be re-injected. A conventional controller is used to regulate the valve in response to the operating conditions to obtain a desired set-point of the oil content in the re-injection water. An adaptive controller can also be used to control the speed of the motor or the position of the valve using an adaptive algorithm for the controller to drive the concentration of the oil to the desired value.


An integrated down converter and interdigital filter apparatus having a down converter and a number of interdigital filters mounted on the same printed circuit board and installed in the watertight housing. The housing of each interdigital filter is cut from sheet metal, with a conductive surface on the printed circuit board as one side. A method for construction of the interdigital filter is also set forth.

1. Field of the Invention
The present invention relates to microwave down converters and interdigital filters and, more particularly, to the combining of one or more interdigital filters into the down converter and the method for constructing the integrated combination.
2. Discussion of Prior Art
Various types of down converters are readily available for converting microwave signals such as in the range of frequencies from 2150 to 2162 MHz (MDS) and 2500 to 2686 MHz (ITFS) received by an appropriate antenna such as an MDS antenna to a corresponding electrical signal for delivery to a receiver. A conventional down converter for an MDS antenna is of the type manufactured by Conifer Corporation, P.0. Box 1025, Burlington, Iowa 52601, available as the QL Series.
Conventional down converters generally use two types of integrated filters. The first type of integrated band pass filter is a printed filter and the second type is a dual cavity filter. While such filters function adequately for single channel MDS applications, they do not function adequately in multiple channel situations.
Interdigital filters exhibiting greater IF rejection, better out-of-band rejection and lower in-band insertion loss than printed and dual cavity filters are commercially available for use with down converters. The theoretical basis for the design of interdigital filters is well known as set forth in the article by Jerry Hinshaw and Shahrokh Monemzadeh, "Computer-Aided Interdigital Bandpass Filter Design." Ham Radio Magazine, January 1985, Pages 12-26. Such interdigital filters, however, are available only as separate circuits and, therefore, require a separate housing and a separate jumper cable to interconnect the interdigital filter with the down converter. Both the interdigital and the down converter are placed near the antenna in the outside environment thereby necessitating a waterproof housing for each. The provision of a separate waterproof housing for the interdigital filter is expensive. Likewise, the provision of a jumper cable not only adds to the cost, but also degrades the signal as well as provide an impedance mismatching problem.
Furthermore, a conventional interdigital filter such as those available from Microwave Filter Company, Inc., 6743 Kinne St., East Syracuse, N.Y. 13057 as Model No. 3746 are expensive to manufacture generally requiring machined components. For example, the interdigital filter Model No. 3746 for MDS applications from Microwave Filter is commercially available at prices from $95 to $135. The Conifer Down Converter is also commercially available at about a price of $80. The combined price with a $10 jumper cable would be about $185 for the two separate units. Under the teachings of the present invention, the integration of the interdigital filter into the down converter would result in a price of about $100.
Even more dramatic cost savings result if multiple interdigital filters are used in parallel to filter the input signal of the down converter. This permits a number of separate microwave frequency bands received by an appropriate antenna to be filtered and converted to corresponding predetermined output frequency bands by means of a single down converter. One interdigital filter is used for each input frequency band. For example, by using two interdigital filters, both the MDS and ITFS bands can be converted by a single down converter.

Integrated down converter and interdigital filter apparatus and method for construction thereof


A method for determining network topology of a provider network includes selecting a first network element, selecting a first port on the first network element, and iteratively performing connectivity validation tests using the first port, wherein each connectivity validation test is associated with a type of network element and yields a result that indicates whether a second port on a second network element of the associated type is connected to the first port. A system for discovering topology of a network, the system comprising a topology discovery engine in operable communication with a near network element and operable to identify a first port of a far network element that is connected to a second port of the near network element by remotely altering operation of the near network element to cause the second network element to respond in a manner that identifies the first port.

A communication network typically employs numerous network elements (NEs) for exchanging data across the network for delivery to a final destination. For example, within a Synchronous Optical Network (SONET), long-haul transport, ADMs, digital cross-connect systems, and other NEs communicate data to and from end-user buildings (EUBs) and other networks. SONET standards do not precisely define every aspect of the communications protocol, thereby allowing for different vendor NEs with different operational specifications. Also, a SONET network typically supports large numbers (e.g., thousands to millions) of communication sessions simultaneously. Thus, SONETs typically include numerous types of NEs from many different vendors interconnected with each other in very complex configurations. In addition, changes are frequently made to the NE configurations and interconnections. Consequently, maintaining an accurate record of these complicated configurations and interconnections at any point in time is a significant challenge.
To attempt to keep track of the NE and circuit configurations, some network providers use provisioning databases that store data representing the configuration of NEs and circuits in the network. A significant problem that has been identified relates to inaccurate representation of the actual network configuration in the provisioning database. Generally this problem arises when changes to the network are not updated in the provisioning database. Exemplary changes are a change in the model of an NE, or a change to port connections between NEs.
While most network changes are properly provisioned, some are erroneously provisioned. For example, a Fujitsu ADM may be replaced with a newer model, with connections to the ports of existing NEs being correctly provisioned. However, loopback conditions that are made for testing purposes are often not deprovisioned after the test. As another example, technicians may simply make mistakes, such as connecting the wrong ports between NEs. Regardless of whether such changes are made properly or in error, changes in NE configuration are very common (e.g., occurring throughout a network everyday), and often occur in an uncontrolled and/or undocumented manner.
Due to the complexity of NE configurations, the large number of interconnections, and the frequency of change, the current state of NE configuration can be extremely difficult to identify if the provisioning database is not updated when changes are made; and if errors are made during provisioning, the current state is not easily discernible even if the provisioning database is updated. Once connections are made between NEs, manually identifying them can be a painstaking, and time-consuming task because of the vast number of connections between NEs. Unfortunately, as indicated above, the provisioning database is frequently not updated, and provisioning errors are made. Consequently the provisioning database typically does not accurately reflect the actual network configuration.
If the provisioning database does not accurately reflect the actual NE configuration of the network, this can pose significant problems for the network provider. For example, if equipment fails on the network, the database will not provide accurate information to enable network administrators to quickly identify the source of the problem, and fixing the problem may take much longer than necessary. In addition, customers may be billed incorrectly because of incorrect assumptions about the network configuration. Furthermore, network capacity may be wasted, particularly in situations when loopback conditions are erroneously left on the network. In addition, provisioning errors may not be known until a fault condition occurs.

Systems and methods for discovering network topology


Provided is a position transducer which can be manufactured at low cost, improve the signal-to-noise ratio of an output obtained from a detector, and obtain a stable output even if the temperature changes. A position transducer 100 includes a butterfly-shaped reflector 7 attached to a rotating shaft 2 of a rotation restriction motor 1, an LED die 4 disposed to face a central portion of the reflection surface of the reflector 7, a diffused-light absorbing member disposed on the surfaces of a diffused light absorber 3 and a case 5, installed on the fixed side of the motor 1 so as to surround the reflector 7 with a distance from the reflector 7 at the rear of the reflector 7 as viewed from the LED die 4 and absorbing illumination light from the LED die 4 which has not illuminated the reflection surface, and detectors 11 mounted on the same printed circuit board 6 as the LED die 4 to detect an image reflected by the reflector 7.

Patent Literature 1 discloses a configuration of a conventional reflection-type optical position transducer system. FIG. 13A to FIG. 13E are diagrams for explaining the reflection-type optical position transducer system. FIG. 13A to FIG. 13E respectively show an illustrative schematic isometric view of the position transducer system, an illustrative schematic isometric bottom view of a reflector element in the position transducer system, an illustrative schematic plan view of a light source and a detector circuit of the position transducer system, an illustrative schematic bottom view of the reflector element, and an illustrative schematic side section view of a rotation restriction motor system.
The conventional reflection-type optical position transducer includes a single LED light source 26, a reflector 12 attached to a rotating shaft of a rotation restriction motor and alternately having regions providing specular reflection and regions providing illumination absorption, and a detector 14 that receives reflected illumination light from the reflector. The reflector 12 is attached to the upper end part of a rotator shaft 30 that rotates within a housing 32. On the surface of the reflector 12 facing the detector 14, three specular reflection regions 16 and three illumination absorption regions 18 are formed and disposed alternately. In the detector 14, the single LED light source 26 is disposed at the center, a light shielding unit 28, such as an O-ring, is attached on the periphery thereof, and further three pairs of detector regions 20a and 20b, 22a and 22b, and 24a and 24b are provided on the periphery of the light shielding unit 28. Light emitted from the single LED light source 26 is reflected by the specular reflection regions 16, and received by the detector regions 20a and 20b, 22a and 22b, and 24a and 24b. The received light output is processed in a processing circuit.
Patent Literature discloses a structure of an optical system of an optical rotary encoder. The encoder includes a light source, a rotary scale, a reflector, and a light-receiving element. The light source is provided in the vicinity on the rotation center line of a rotating shaft. The rotary scale is attached to the rotating shaft so as to be capable of rotating about the rotation center line, and has an optical pattern including light-transmitting parts and light shielding parts formed alternately in the circumferential direction. The reflector is disposed with an interval from the rotary scale, and reflects light from the light source so that the light forms a parallel light flux whose width almost does not change within the section including the rotation center line, and thereby, the parallel light flux illuminates the light-transmitting parts of the rotary scale and the light having passed through the light-transmitting parts travels toward the periphery of the light source. The light-receiving element receives the light having passed through the light-transmitting parts. The optical rotary encoder according to Patent Literature 2 is a transducer that detects bright and dark light from the reflector by a detector, encodes the light in a circuit in the subsequent stage, and thereby obtains position information.
Patent Literature 3 relates to an encoder as in Patent Literature 2, and discloses an optical system that utilizes a reflective cylindrical surface. In this encoder, a module including a photo-detector and a light source is disposed to face a drum. On the surface in the circumferential direction of the drum, stripe-shaped non-reflection regions are provided at regular intervals. The drum is illuminated with light of the light source, and the light reflected thereby is detected by the photo-detector. Patent Literature 3 discloses an optical system and a detection method unique to an encoder that illuminates non-reflection regions disposed in the form of a stripe on the surface of the drum and the reflection regions therebetween with light, and that detects the rotation position of the non-reflection regions by reflected light.
Patent Literature 4 discloses a structure of a rotary motor for detecting a rotation position. In this rotary motor, in order to detect the rotation position thereof, a butterfly-shaped diffusion surface having an angle width of 90 degrees is attached to a rotor shaft. The diffusion surface has an opaque surface in the shape of a disc in the vicinity of the central part (see Patent Literature 4, FIG. 1B). A lens is disposed to face the diffusion surface, and behind the lens, a stationary detector is installed. As a light source, four LEDs are disposed on both sides of the lens. Light emitted from the four LEDs is reflected by the rotating diffusion surface, and the reflected light is concentrated by the lens and received by the stationary detector. In the rotary motor in Patent Literature 4, the LEDs and the detector are disposed not on the same plane but in different spaces, and from each of the four LED light sources, light is illuminated toward each of the reflection surfaces.