Distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion is added to each of the portions (step ST2). Each time a cell forming a specific region of a logic circuit is laid out, a layout of the logic circuit in that region is analyzed, a logic optimization is executed to rewrite the net list of the logic circuit in that region so as not to alter the number of ports located on the boundary of the logic layer by using the distinguishing information, and the layout of the logic circuit in that region is modified on the basis of the rewritten net list (step ST3).

1. Field of the Invention
The present invention relates to an automatic placement and routing apparatus, automatic placement and routing method, and automatic placement and routing program that are of use for designing a semiconductor integrated circuit.
2. Description of the Prior Art
FIG. 10 is a block diagram illustrating a conventional automatic placement and routing apparatus. In FIG. 10, there are shown a net list 101, constraint information 102, a library 103, a read means 104, a placement means 105, a logic optimization means 106, and a routing means 107. In the net list 101, specified are information concerning cells constituting a logic circuit, information concerning nets defining connectional relations between the cells of the logic circuit, and information concerning logic layers that divide the logic circuit into an appropriate size. The constraint information 102 defines various constraints on logic circuits, such as routing delay, power consumption, and signal integrity. The library 103 registers the cells used for designing the layout of a logic circuit. The read means 104 reads the net list 101 and the constraint information 102. The placement means 105 places the cells registered in the library 103 on the basis of the net list 101. The logic optimization means 106 analyzes, each time a cell forming a specific region of a logic circuit is arranged by the placement means 105, the layout of the logic circuit in that region, performs a logic optimization that rewrites the net list 101 of the logic circuit in that region so as to satisfy the constraints defined in the constraint information 102, and modifies the layout of the logic circuit in that region on the basis of the rewritten net list. The routing means 107 routes, after the logic optimization means 106 performs a logic optimization and a layout modification over the entire logic circuits, the cells so as to satisfy the connectional relations defined in a net list 108 of all the rewritten logic circuits. The logic optimization means 106 outputs the net list 108 of all the rewritten logic circuits.
Next, the operation will be described.
FIG. 11 is a flow chart for a conventional automatic placement and routing method.
First, the read means 104 reads the net list 101 and the constraint information 102 (step ST101).
Thereafter, the placement means 105 fetches the net list 101 from the read means 104. Then, on the basis of the net list 101, the placement means 105 places the cells registered in the library 103. Also, the logic optimization means 106 fetches the net list 101 and the constraint information 102 from the read means 104. In addition, each time a cell forming a specific region of a logic circuit is arranged by the placement means 105, the logic optimization means 106 analyzes the layout of the logic circuit in that region, performs a logic optimization that rewrites the net list 101 of the logic circuit in that region so as to satisfy the constraints defined in the constraint information 102, and modifies the layout of the logic circuit in that region on the basis of the rewritten net list (step ST102). The net list 101 is rewritten when anew cell and net, for example, are added.
After the logic optimization means 106 performs the logic optimization and the layout modification over the entire logic circuits, the routing means 107 routes the cells so as to satisfy the connectional relations defined in the net list 108 of all the rewritten logic circuits (step ST103).
Thereafter, the logic optimization means 106 outputs the net list 108 of all the rewritten logic circuits (step ST104).
The steps ST103 and ST104 may be replaced in the order.
FIG. 12 illustrates an example of the contents defined in the net list of a logic circuit before a logic optimization in the conventional example. In FIG. 12, there are shown a first to a fourth buffer circuit cell 111 to 114 constituting the logic circuit, a logic layer 115 furnished with the first buffer circuit cell 111 and the second buffer circuit cell 112, a net 116 that crosses the logic layer 115, and a port 117 that is located on the boundary of the logic layer 115 where the net 116 passes through. The net 116 represents that the second through fourth buffer circuit cells 112 to 114 are connected to one another in parallel, and the first buffer cell 111 is connected in series to the second through fourth circuit buffer cells 112 to 114.
FIG. 13 illustrates an example of the contents defined in the net list of a logic circuit after a logic optimization in the conventional example. In FIG. 13, there are shown a newly added buffer circuit cell 118 that is added to the net 116 in order to improve the routing delay from the first buffer circuit cell 111 to the second buffer circuit cell 112 and the third buffer circuit cell 113, a newly net 119 produced by the buffer circuit cell 118 being added to the net 116, and a newly port 120 produced by the buffer circuit cell 118 being added to the net 116, located on the boundary of the logic layer 115 where the net 119 passes through. The other components are identical or equal to those illustrated with the same symbols in FIG. 12, and the detailed explanations will be omitted. The net 116 represents that the first buffer circuit cell 111 and the fourth buffer circuit cell 114 and the added buffer circuit cell 118 are in the connectional relation; and the net 119 represents that the added buffer circuit cell 118 and the second buffer circuit cell 112 and the third buffer circuit cell 113 are in the connectional relation.
Thus, in some cases, the conventional automatic placement and routing apparatus and automatic placement and routing method may increase the number of the ports located on the boundary of the logic layer 115 through the process of a logic optimization. Therefore, there can be a case that the same test pattern cannot be used before and after a logic optimization, which presents a problem of effective use of the test patterns.
The present invention has been made in view of the foregoing, and an object of the invention is to provide an automatic placement and routing apparatus and automatic placement and routing method that performs a logic optimization so as not to alter the number of ports located on the boundary of a logic layer, and an automatic placement and routing program that makes a computer perform such a logic optimization function.
According to a first aspect of the present invention, there is provided an automatic placement and routing apparatus including: a placement means that places cells registered in a library, on the basis of logic circuit information in which are specified information concerning the cells constituting a logic circuit, information concerning nets defining connectional relations between the cells constituting the logic circuit, and information concerning logic layers that segment the logic circuit into appropriate sizes; a routing means that routes the cells so as to satisfy connectional relations defined in the logic circuit information; a distinguishing information adding means that analyzes the logic circuit information, and adds distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion to each of the portions; and a logic optimization means that executes a logic optimization to rewrite the logic circuit information, in such a manner that the number of ports located on the boundary of the logic layer is not altered by using the distinguishing information.
Therefore, the same test patterns before and after the logic optimization is available, resulting in an effective use of the test patterns.
According to a second aspect of the present invention, there is an automatic placement and routing method including: a placement step that places cells registered in a library, on the basis of logic circuit information in which are specified information concerning the cells constituting a logic circuit, information concerning nets defining connectional relations between the cells constituting the logic circuit, and information concerning logic layers that segment the logic circuit into appropriate sizes; a routing step that routes the cells so as to satisfy connectional relations defined in the logic circuit information; a distinguishing information adding step that analyzes the logic circuit information, and adds distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion to each of the portions; and a logic optimization step that executes a logic optimization to rewrite the logic circuit information, in such a manner that the number of ports located on the boundary of the logic layer is not altered by using the distinguishing information.
Therefore, the same test patterns before and after the logic optimization is available, resulting in an effective use of the test patterns.
According to a third aspect of the present invention, an automatic placement and routing program makes a computer perform: a placement function that places cells registered in a library, on the basis of logic circuit information in which are specified information concerning the cells constituting a logic circuit, information concerning nets defining connectional relations between the cells constituting the logic circuit, and information concerning logic layers that segment the logic circuit into appropriate sizes; a routing function that routes the cells so as to satisfy connectional relations defined in the logic circuit information; a distinguishing information adding function that analyzes the logic circuit information, and adds distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion to each of the portions; and a logic optimization function that executes a logic optimization to rewrite the logic circuit information, in such a manner that the number of ports located on the boundary of the logic layer is not altered by using the distinguishing information.
Therefore, the automatic placement and routing program makes it possible to use a computer as an automatic placement and routing apparatus that can use the same test patterns before and after a logic optimization, resulting in using effectively the test patterns. In addition, the automatic placement and routing program allows a computer to perform an automatic placement and routing method capable of using the same test patterns before and after the logic optimization, resulting in using effectively the test patterns.

Automatic placement and routing apparatus


A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

A processor core may be designed to execute code written in a particular coding language. In order to have a program executed by a particular core, program code may need to be translated from a first coding language that is incompatible with the particular core to a second coding language that is compatible with the particular core, known as binary translation.
Self modifying code (SMC) refers to code that becomes modified during execution, e.g., one or more instructions of the SMC upon execution modify other instructions of the SMC. Cross modifying code (XMC) refers to first code that is executable on a first processor core and that when executed causes modifications to second code that is executable on a second processor core. SMC or XMC may be partially translated or entirely translated prior to execution. Translation of several instructions prior to their execution may introduce anomalies in the translated code, as compared with translation and execution of each instruction prior to advancement to the next instruction. The anomalies in the translated code can result in mistakes in output.

Handling of binary translated self modifying code and cross modifying code


Disclosed is an improved structure of a composite fiber racket, which includes a frame comprising a head portion and a handle, wherein a catgut string is laterally and longitudinally inserted through the through-holes set around the head portion to form a taut striking surface, characterized by the head portion having thereon a plurality of reinforcement elements inset at several predetermined positions. Each of the reinforcement elements has an elongate foam piece disposed therein and is covered with a layer of composite fiber which is of the same material as used by the head portion. One side of the reinforcement element is attached to the corresponding inner side wall of the head portion, and the other side thereof has a small space separating it from the corresponding outer side wall of the head portion, so as to reinforce the strength of the head portion and increase the weight distribution around the periphery of the racket frame.

The present invention relates to a racket structure and more particularly to an improved structure of a composite fiber racquet.
According to the manufacturing of composite fiber rackets as adopted in the prior art, a polyethylene tube, of oblate form, is generally covered with a layer of fiber, then put into a molding die with an opening through which high-pressure heated air from a pump is blown in to complete the molding process. Alternately, the polyethylene tube can be filled with expandable polyurethane to form the tube within the mold.
A major deficiency of these methods is that when the polyethylene tube is placed in the mold the inner side thereof tends to wrinkle upon bending. Making it impossible to keep the thickness of the fiber layer even. Consequently, at the positions of the through-holes, after the head frame is strung, cracks tend to occur due to the stress concentrations from the taut strings. Thus the wrinkling of the inner side not only degrades the appearance of the racquet but also reduces the service life of the head frame.


A forearm support is provided for use within electrostatic sensitive areas. The forearm support has a bottom and one or more sides. Preferably, the top, bottom and sides are made of a flexible electrically conductive fabric which forms an interior filled with a resilient foam. As measured from the support's top surface to its bottom surface, the support has an electrical resistance value of less than 1×109 ohms.

Operators of scientific equipment are known to experience discomfort and fatigue of their fingers, wrists and/or arms after extended periods of operating various devices. For example, operators of microscopes must constantly manipulate various controls and knobs of the microscope to bring various specimens into view. Hours of such manipulation may cause one's arms, hands and/or fingers to become sore, fatigued and may even lead to painful musculo-skeletal disorders like tendonitis and carpel tunnel syndrome. In addition, persons performing benchwork, such as working on printed circuit boards, whether for inspection, manufacturing or repair, are often positioned in unnatural positions and must repeatedly manipulate various devices and tools during their job. In order to support their body, workers often rest their elbows, forearms and wrists on hard work surfaces. Persons also lean against desks to prevent painful muscular skeletal stain associated with working in awkward positions which, over time, can cause alternative physical maladies.
Various devices have been developed in at attempt to reduce the strain upon the body for those working on scientific equipment. For example, a product sold under the trademark Wedge-Ease® has been sold to reduce the strain for those persons who utilize microscopes for extended periods of time. The Wedge-Ease® consists of a cushioning pad 1-3 inches thick, 10 inches long and 3-5 inches wide. The Wedge-Ease® includes a vinyl cover encasing a foam interior. Persons utilizing the Wedge-Ease® place their forearm, wrist or elbow upon the pad which has been found to relieve fatigue and discomfort to one's upper extremities, neck and back. The device also eliminates resting one's elbows and forearms on a hard work surface. Unfortunately, devices such as the Wedge-Ease® are not suitable for use in proximity to electrostatic sensitive devices as the pad does not properly dissipate static charge and therefore can cause damage to sensitive devices.
Static electricity is commonly defined as an electrical charge resulting from the imbalance of electrons on the surface of a material. Most people are quite familiar with the every day effects of static electricity, as it is the shock that one experiences when touching a door knob or other device having a different electrical potential. The scientific name for the electrical shock is electrostatic discharge ("ESD").
In every day situations, ESD can be an annoyance, but it is rarely a problem. However, the problems resulting from ESD are magnified within industrial settings, such as where persons are utilizing ESD sensitive electronics. In addition, static discharge can cause the unintentional ignition of flammable materials and the attraction of contaminants such as charged dust particles within a clean room environment. Even centuries ago, people were concerned with ESD ramifications as it was found to ignite black powder ammunition.
Today, the electronics industry is most concerned with ESD damage. It can destroy or degrade semiconductor devices by changing operational characteristics. In clean rooms it has been found to cause charged particles to adhere tightly to the surface of a silicon wafer, resulting in distinct problems with circuit board production and efficiency.
ESD control programs are typically implemented to dissipate ESD. These techniques include coating work surfaces, including floors and bench tops, with ESD resistive coatings. An additional ESD device is known as a grounding strap. A grounding strap is physically connected between an electrostatically charged source, such as a human being or other electronic device, to an electrical ground. In practice, any electrical potential between a human body and ground is reduced as charged electrons pass through the body and grounding strap. Unfortunately, the physical straps are cumbersome to attach and wear. In addition, due to their annoyance, persons will intentionally avoid using their ground straps which can cause damage to electrically sensitive devices.
The level of ESD protection provided by an object is directly related to the time needed to discharge its electrical potential. For example, it is known that the electrical resistance between two points can be correlated to the ESD potential, and thus electrical resistance values between two points are indicative of the effectiveness of the objects for resisting ESD. While in reality, the time it takes for an object to discharge is related to factors in addition to resistance, such as capacitants, contact resistance and discharge paths, it has been found that the resistance measurements provides an effective predictor of the potential for ESD. Accordingly, objects within electrostatic sensitive areas, such as flooring materials, packaging materials, and bench tops, are measured point-to-point to determine their ground resistance.
Various standards have been developed for measuring the resistance of work surfaces and other objects as a predictor of ESD potential. For example, ANSI/ESD STM 97.1-1999 is an accepted standard for testing flooring materials and footwear. In addition, ANSI/ESD STM S20.20-1999 provides a standard for determining whether objects as acceptable for use within an electrostatic discharge sensitive area. Both ANSI/ESD STM 97.1-1999 and ANSI/ESD STM S20.20-1999 are incorporated herein by reference in their entirety.
Perhaps because of the complexity and problems posed by ESD, upper extremity supports do not exist for operators working in ESD sensitive areas. Accordingly, persons using microscopes or working on electronics within an ESD sensitive area cannot use existing upper extremity supports as they unduly collect electrical charge and pose a significant ESD hazard.
Therefore, there is a significant need for a device which will reduce the discomfort and musculo-skeletal disorders that are suffered by those working in ESD sensitive areas.
It would be advantageous to provide a device which reduced worker fatigue and discomfort also complied with various ESD standards.
Furthermore, it would be advantageous if the device were inexpensive to manufacture, easy to use, and affordable to the end user.

Electrostatic dissipative ergonomic forearm support


A system, to migrate a shortest-path-first (SPF) routed network from a first routing state to a second routing state, includes a changeover module to generate a sequence of intermediate network plans, each of which modifies a preceding network state according to a preceding network plan, such that a routing of at least one demand in the network changes. The sequence of intermediate network plans migrates the network from the first routing state to the second routing state. A network controller sequentially configures the network according to the sequence of intermediate network plans to migrate the network from the first routing state to the second routing state. Each intermediate network plan of the sequence configures the network to operate within at least one predetermined constraint.

The shortest-path-first (SPF) routing method is used in a variety of data networks to determine the path data should be routed from any source node to any destination node in the network. Examples of data networks that use the SPF routing method are Internet Protocol (IP) networks using OSPF or IS-IS versions of the Interior Gateway Protocol (IGP).
The nodes in an SPF-routed network are connected by unidirectional links. Each link is assigned a positive number called a metric. The length of any path through the network is defined to be the sum of the metrics on the links comprising that path. Data traveling from a source node to a destination node travels along the shortest path, according to this definition, between these two nodes. If more than one path is of equal cost, the data load, or bandwidth, is shared in some manner between these equal-cost paths.
The choice of network metrics, then, determines the routing of data through the network. Certain choices of routings through a given network may be more desirable than others. Metric-based traffic engineering is the process of choosing metrics to achieve desirable routings. Certain routings may be preferred over others for any of a number of reasons, for example:    1. To keep the bandwidth utilization (e.g., the percentage of link capacity utilized) below a certain percentage, or as low as possible, for each link in the network, to prevent congestion.    2. To keep bandwidth utilization below a certain percentage, or as low as possible, for each link in the network, even when certain elements of the network (links or nodes, for example) fail, or are purposefully deactivated, and bandwidth must be routed elsewhere through the network.
Two aspects of this field have been the subjects of some prior academic research:    1. Estimation of point-to-point bandwidth demands in a network from measurements of link utilizations. See, for example, "An Information-Theoretic Approach to Traffic Matrix Estimation", by Yin Zhang, Matthew Roughen, Carsten Lund, and David Donoho, ACM SIGCOMM 2003. Knowledge of the point-to-point demands is necessary to calculate future link utilizations under modifications to the metrics and/or the topology of the network.    2. Algorithms for selecting metrics in a network to avoid congestion through over utilization of links under normal network operation. See, for example, Traffic engineering with traditional IP routing protocols, IEEE Communications Magazine, 40(10): 118-124, 2002.

Methods and systems to perform traffic engineering in a metric-routed network


An image sensor device of the frame transfer type comprises a substrate having a first region (10) of a first n type, a second region (12) of the opposite p-type and charge transfer channels (15) as well as an arrangement of electrodes (1A . . . 1D) of charge transfer.. A photosensitive layer (50) is arranged on the surface (19) of the substrate and has window regions (100, 200) in electrical contact with the channels (15) through windows (40) provided in the arrangement of electrodes, for example through electrodes (1B, 1D). Insulating strips (24) and conductive strips (30) serve to prevent the drift from one window region to the other of charges to be transferred and to evacuate the charges of a sign opposite to that of the charges to be transferred.

The invention relates to an image sensor device of the frame transfer type comprising a semiconductor substrate having a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type arranged above the first region of the substrate, parallel charge transfer channels of the first conductivity type arranged in the second region in a direction of charge transfer and an arrangement of charge transfer electrodes perpendicular to the direction of charge transfer provided at the surface of the second region and electrically insulated therefrom in such a manner that they permit, when they are brought to suitable potentials, the transfer of charged of a first sign stored in elementary cells in response to incident light in the direction of charge transfer along the said parallel channels.
Such a device is known from European Pat. No. 143,496 filed by the Applicant.
In this prior art document, the channel regions are photosensitive and consequently only a part of the surface of the device is utilized, which limits the effectiveness.
Otherwise, it has been proposed for image sensor devices of the interline type to provide a photosensitive layer on the whole surface of the crystal and to connect this photosensitive layer electrically pointwise through electrodes to charge accumulation zones. An example of such a sensor is disclosed in European Pat. Application No. 139 366.
The charge transfer is effected, as is usual with this type of image sensor, due to a transfer channel distinct from the charge accumulation zone.
When a photosensitive layer is provided on the whole surface of the crystal, the advantage is obtained that the effectiveness of the device is increased because no geometric factor will reduce the dimensions of the sensitive surface.
However, the structure described is absolutely specific for an image sensor of the interline type (I.L.). In fact, in such sensors, since the charge accumulation zones and the charge transfer channels are mutually separated, the interconnections are formed due to multi-layer structures usual in the semiconductor industry.
The invention proposes for an image sensor device of the frame transfer type to provide a photosensitive layer on the surface of the crystal so that its effectiveness is increased.
The structures known hitherto for the sensors of the interline type (I.L.) are, as mentioned above, specific for such sensors. Their use in frame transfer devices would lead to utilizing a substantial part of the surface available for the interposition especially of electrodes connecting the photosensitive layer and charge transfer regions to each other.

Image sensor device of the frame transfer type


Preventing transmission loops in a ring network that utilizes label switching involves generating right side and left side ring packets from an ingress packet and setting right and left TTL values for the packets that prevent the packets from traveling on the same transmission link. Setting the right and left TTL values of the ring packets to values that prevent the packets from traveling on the same link transforms the physical topology of the ring into a logical arc. In an embodiment, the logical arc established by a network node can be dynamically rotated in response to various network conditions to avoid packet transmissions on a particular link of the ring network.

The invention relates to label switching, and more particularly to a method and system for preventing transmission loops between a group of network nodes that are connected to form a ring.
In packet-switched networks, packets traveling from a source address to a destination address may be transmitted through many intermediate network nodes, such as switches or routers. Intermediate network nodes that receive packets headed for the destination address utilize look-up tables to determine where the packets should be forwarded next. If an intermediate network node is familiar with the destination address of the packets, the packets are forwarded to the appropriate next hop. However, if the destination address of the packets is unknown to the network node, the network node may forward the incoming packets onto all of its ports, except for the port at which the packets were received, in order to deliver the packet to the unknown destination address. This technique for locating an unknown destination address, referred to as xe2x80x9cflooding,xe2x80x9d is repeated at each network node that is unfamiliar with the destination address of the packets until the packets eventually reach their destination or a network node that is familiar with the destination address of the packets. Return packets are then transmitted from the destination to the source through the intermediate network nodes. Once one of the packets is received by an intermediate network node, information regarding the destination address of the packet is learned by the intermediate network nodes so that subsequent packets do not have to be flooded. Although flooding works well to learn an unknown destination address, in mesh and ring network topologies, flooding at each network node often causes transmission loops that can quickly multiply and overwhelm a network node, causing traffic delays and network crashes. The occurrence of transmission loops is also a problem with multicast and broadcast packet transmissions.
One technique that is used at the Data Link layer (layer 2) to prevent transmission loops in a group of network nodes involves breaking the network topology down into a loop-free topology, also referred to as a spanning tree. A spanning tree protocol (STP) for determining, establishing, and maintaining a loop-free topology that includes every reachable link in a given network has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE 802.1D. The STP involves determining a Root Bridge, determining the Designated Bridges and Designated Ports for each link, and maintaining the spanning tree topology over time. Although the Spanning Tree Protocol works well to create loop-free topologies, establishing and maintaining the spanning tree is a cumbersome and resource intensive process.
As described above, packets traveling from a source address to a destination address may be transmitted through many intermediate network nodes. Performing forwarding look-ups at the intermediate network nodes based on the destination address of each packet adds delay to the packets. Label switching is a technique that has been developed to expedite the look-up process at each hop as packets travel from a source address to a destination address. In brief, label switching involves attaching a label to a packet that enables the next hop of the packet to be quickly determined by an intermediate network node that has received the packet. One label switching protocol that is being standardized by the Internet Engineering Task Force (IETF) is known as multi-protocol label switching (MPLS).
FIG. 1 depicts a group of network nodes 102 that utilize MPLS to forward packets. The network nodes are referred to as label switch routers (LSRs) and a group of interconnected LSRs define an MPLS domain 104. LSRs that are at the edge of the MPLS domain and provide an interface to non-MPLS network nodes are referred to as edge LSRs (also as ingress LSRs and egress LSRs with respect to packets that are entering or leaving the MPLS domain). The path that labeled packets travel through an MPLS domain is referred to as the label switch path (LSP). FIG. 1 depicts an example LSP 106 that extends through the MPLS domain. MPLS is often used in conjunction with the Internet protocol (IP) at the Network layer (layer 3) and a Data Link layer (layer 2) protocol such as the Ethernet protocol (IEEE 802.3x). According to the MPLS protocol, an MPLS label, also referred to as a xe2x80x9cshim header,xe2x80x9d is inserted between the Network layer header and the Data Link layer header to guide a labeled packet through an MPLS domain. MPLS can also be used in a layer 2 environment where the shim header is located between two layer 2 headers.
FIG. 2 depicts an example of a labeled packet that includes a MAC (Data Link layer or layer 2) header 208 (the destination address, the source address, and the type), a label switching header 210 (also referred to as the shim header), an IP header 212, an IP payload 214, and a MAC trailer 216 (the CRC). As described by the IETF (RFC 3032, January 2001) and shown in the expanded view of FIG. 2, the shim header includes a 20-bit MPLS label field 218, a 3-bit experimental use field 220, a 1-bit stacking field 222, and an 8-bit time-to-live (TTL) field 224. The MPLS label field carries the label value that is used to forward a packet to the next LSR. The experimental use field is not yet fully defined, the stacking field is used to identify when an MPLS header is the last MPLS header in a stack of MPLS headers, and the TTL field carries a TTL value that places a limit on the number of hops an MPLS packet can traverse within an MPLS domain. The TTL field limits the number of hops a packet can take within an MPLS domain. Typically, in an IP environment, the TTL value of an MPLS label is initially set from the TTL value of the underlying IP packet and the IP packet TTL value is typically set by a host to an arbitrary number of hops. Although MPLS can increase transmission efficiency in an MPLS network, setting the TTL value in the MPLS Shim header to the TTL value of the underlying IP packet does not prevent loops within an MPLS domain. Additionally, in a layer 2 environment, the underlying MAC header does not include a TTL value that can be used to set the TTL value in the MPLS shim header.
In view of the problems caused by flooding, multicasting, and broadcasting, what is needed is a technique that prevents transmission loops and that is compatible with a label switching protocol such as MPLS.
A method and system for preventing transmission loops in a ring network that utilizes label switching involves generating right side and left side ring packets from an ingress packet and setting right and left TTL values for the packets that prevent the packets from traveling on the same transmission link. Setting the right and left TTL values of the ring packets to values that prevent the packets from traveling on the same link transforms the physical topology of a ring into a logical arc. In an embodiment, the logical arc established by a network node can be dynamically rotated to avoid packet transmissions on a particular link of the ring network.
In an embodiment, a method for preventing transmission loops is implemented between a plurality of network nodes that are connected by transmission links to form a ring, wherein each network node on the ring includes a right side ringport that is connected to a right side neighbor and a left side ringport that is connected to a left side neighbor and wherein each of the network nodes in the ring utilizes a label switching protocol that includes a label, the label including a label field for carrying a label value and a time-to-live (TTL) field for carrying a TTL value. The method involves generating, at a first one of the plurality of network nodes, a right side packet and a left side packet from an ingress packet and setting a right side TTL value for the right side packet and a left side TTL value for the left side packet to values that prevent the right side packet and the left side packet from traveling on the same transmission link on the ring.
An embodiment of the method includes learning the number (N) of network nodes on the ring. A further embodiment includes setting the right side TTL value and the left side TTL value to values that are a function of N. A further embodiment includes setting the right side TTL value and the left side TTL value such that the maximum number of right side hops (MaxRightHops) plus the maximum number of left side hops (MaxLeftHops) is less than or equal to Nxe2x88x921, the function of N being expressed as: MaxRightHops+MaxLeftHopsxe2x89xa6Nxe2x88x921.
Another embodiment of the method includes setting the right side TTL value and the left side TTL value such that the number of hops for the right side packet is equal to the number hops for the left side packet.
Another embodiment of the method includes setting the right side TTL value and the left side TTL value such that the number of hops for the right side packet differs from the number hops for the left side packet by one hop.
Another embodiment of the method includes setting the right side TTL value and the left side TTL value such that the furthest transmission link from the first network node is a transmission link that is not utilized by either the right side packet or left side packet.
Another embodiment of the method includes setting the right side TTL value and the left side TTL value in response to link performance information related to the transmission links that connect the network nodes into the ring.
Another embodiment of the method includes dynamically adjusting the right side and left side TTL values.
Another embodiment of the method involves transmitting the right side packet on the right side ringport of the first network node and the left side packet on the left side ringport of the first network node. A further embodiment includes decrementing the right side TTL value of the right side packet at each network node on the ring that receives the right side packet and the left side TTL value of the left side packet at each network node on the ring that receives the left side packet.
In an embodiment of the method, the label is located between two Data Link layer headers.
In an embodiment of the method, the network nodes utilize Ethernet at the Data Link layer.
In an embodiment of the method, the label is a Multiprotocol Label Switching (MPLS) header. In a further embodiment, the method includes establishing, at the first network node, multiple label switch paths that have different quality of service characteristics and setting the same right side TTL values and left side TTL values for all packets transmitted on the multiple LSPs.
In another embodiment, a method for preventing transmission loops is implemented between a plurality of network nodes that are connected by transmission links to form a ring, wherein each network node on the ring includes a right side ringport that is connected to a right side neighbor and a left side ringport that is connected to a left side neighbor and wherein each of the network nodes in the ring utilizes a label switching protocol that includes a label, the label including a label field for carrying a label value and a time-to-live (TTL) field for carrying a TTL value. The method involves learning, at a first one of the plurality of network nodes, the number (N) of network nodes on the ring, generating, at the first network node, a right side packet and a left side packet from an ingress packet, and setting a right side TTL value for the right side packet and a left side TTL value for the left side packet to values that are a function of N.
An embodiment of the method includes setting the right side TTL value and the left side TTL value to values that prevent the right side packet and the left side packet from traveling on the same transmission link on the ring.
Another embodiment of the method includes setting the right side TTL value and the left side TTL value such that the maximum number of right side hops (MaxRightHops) plus the maximum number of left side hops (MaxLeftHops) is less than or equal to Nxe2x88x921, the function of N being expressed as MaxRightHops+MaxLeftHopsxe2x89xa6Nxe2x88x921.
An embodiment of a system for preventing transmission loops in a ring network includes a plurality of network nodes, with each network node including a right side ringport, a left side ringport, a packet processor, and a loop protection module. The network nodes are connected by transmission links to form a ring, wherein each of the network nodes on the ring utilizes a label switching protocol that includes a label, the label including a label field for carrying a label value and a time-to-live (TTL) field for carrying a TTL value. The right side ringport of each network node is connected to a right side neighbor and the left side ringport is connected to a left side neighbor. The packet processor of each network node generates a right side packet and a left side packet from an ingress packet and the loop protection module sets a right side TTL value for the right side packet and a left side TTL value for the left side packet to values that prevent the right side packet and the left side packet from traveling on the same transmission link on the ring.
Another embodiment of a system for preventing transmission loops in a ring network includes a plurality of network nodes, with each network node including a right side ringport, a left side ringport, a packet processor, and a loop protection module. The network nodes are connected by transmission links to form a ring, wherein each of the network nodes on the ring utilizes a label switching protocol that includes a label, the label including a label field for carrying a label value and a time-to-live (TTL) field for carrying a TTL value. The right side ringport of each network node is connected to a right side neighbor and the left side ringport is connected to a left side neighbor. The packet processor of each network node generates a right side packet and a left side packet from an ingress packet. The loop protection module learns the number (N) of network nodes on the ring and sets a right side TTL value for the right side packet and a left side TTL value for the left side packet to values that are a function of N.
In an embodiment of the system, the right side TTL value and the left side TTL value are set such that the maximum number of right side hops (MaxRightHops) plus the maximum number of left side hops (MaxLeftHops) is less than or equal to Nxe2x88x921, the function of N being expressed as MaxRightHops+MaxLeftHopsxe2x89xa6Nxe2x88x921.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

Method and system for preventing transmission loops in a label switching domain


The magnetic balance is verified of a magnetically-levitated impeller of a centrifugal pump with a pump housing having levitation magnets. The impeller includes embedded magnets and is movable within a chamber in the pump housing between first and second sides of the chamber. The centrifugal pump is mounted on an acceleration fixture while the impeller is held against a predetermined one of the first and second sides by the levitation magnets. A plurality of predetermined accelerations are applied to the acceleration fixture to exert a plurality of different forces of acceleration on the impeller. A determination is made whether the impeller detaches from the predetermined side as a result of each different force of acceleration to identify adjacent forces for which a transition occurs between detaching and not detaching. The transition is compared with a desired retention force to determine whether the pump achieves magnetic balance.

The present invention relates in general to circulatory assist devices having a centrifugal blood pump with a levitated impeller, and, more specifically, to a testing method to verify whether a manufactured pump provides the proper magnetic forces on the impeller to maintain a balanced, center position of the levitated impeller.
Many types of circulatory assist devices are available for either short term or long term support for patients having cardiovascular disease. For example, a heart pump system known as a left ventricular assist device (LVAD) can provide long term patient support with an implantable pump associated with an externally-worn pump control unit and batteries. The LVAD improves circulation throughout the body by assisting the left side of the heart in pumping blood. One such system is the DuraHeart® LVAS system made by Terumo Heart, Inc., of Ann Arbor, Mich. The DuraHeart® system employs a centrifugal pump with a magnetically levitated impeller to pump blood from the left ventricle to the aorta. The impeller acts as a rotor of an electric motor in which a rotating magnetic field from a multiphase stator couples with the impeller and is rotated at a speed appropriate to obtain the desired blood flow through the pump.
The centrifugal pump employs a sealed pumping chamber. By levitating the impeller within the chamber when it rotates, turbulence in the blood is minimized. The spacing between the impeller and chamber walls minimizes pump-induced hemolysis and thrombus formation. The levitation is obtained by the combination of a magnetic bearing and a hydrodynamic bearing. For the magnetic bearing, the impeller typically employs upper and lower plates having permanent magnetic materials for interacting with a magnetic field applied via the chamber walls. For example, a stationary magnetic field may be applied from the upper side of the pump housing to attract the upper plate while a rotating magnetic field from the lower side of the pump housing (to drive the impeller rotation) attracts the lower plate. The hydrodynamic bearing results from the action of the fluid between the impeller and the chamber walls while pumping occurs. Grooves may be placed in the chamber walls to enhance the hydrodynamic bearing (as shown in U.S. Pat. No. 7,470,246, issued Dec. 30, 2008, titled "Centrifugal Blood Pump Apparatus," which is incorporated herein by reference). The magnetic and hydrodynamic forces cooperate so that the impeller rotates at a levitated position within the pumping chamber.
A particular pump design will specify the strength and placement of all the interacting magnets in such a way that the impeller receives a desired balancing force when it is at the centered (i.e., levitated) position. Each magnet and the various plastic parts can be tested for compliance with their design specifications in an attempt to make sure that the pump will perform as intended. During assembly, however, small variations both from assembly tolerances and from aggregate small errors in the components can appear which impair the magnetic balance.
The magnetic balance is not intended to be perfect. Impeller rotation in the presence of a pumped fluid (e.g. blood) is necessary so that the hydrodynamic and magnetic forces can cooperate to achieve the balanced position. When the pump is empty and the impeller is not rotating, the lack of hydrodynamic force means that the impeller is not suspended but is magnetically held against one of the sides of the chamber. Thus, visual inspection cannot reveal whether a satisfactory magnetic balance is present. It would be desirable to verify proper force balancing without requiring pump operation with a fluid.

Verification of magnetic balance for magnetically levitated impeller


A method of providing secure signaling connections and media connections for packet data network telephony calls. A secure registration request message containing an encryption technique and public key is sent from an originating gateway 105 over a packet data network 100 to a terminating gateway 105. The terminating gateway 105 returns a secure confirmation message containing a digital certificate over the packet data network 100 to the originating gateway 105. Once registered, further communication between the gateways 105 is encrypted over the packet data network 100 using the public key and encryption technique specified in the secure registration request message. The gateways 105 can be linked to other incompatible networks such as the PSTN 115 or wireless telephony 120 networks in order to provide telephone capability among POTS 125, wireless 130, and IP 140 phones.

The present invention relates generally to providing enhanced security for Internet telephony calls and more particularly to providing a secure connection for Voice Over IP (VoIP) calls using the H.323 protocol.
The Internet explosion has spawned new means of data, voice, and video communication and Internet Protocol (IP) telephony is a fast developing field of telecommunications. The Internet, however, is faced with two significant obstacles to fast secure communications. The first obstacle is usable bandwidth. Bandwidth affects the rate at which data can be transferred. The second obstacle pertains to security. The Internet is not a direct point-to-point connection between computers. Rather, it is a network to which computers (or other devices) can connect for the purpose of communicating with one another. As such, there is increased opportunity for eavesdropping on data, voice, or video transmissions over the Internet. One method of enhancing the security of Internet based communications is to encrypt the data being transmitted before sending it out over the network and de-encrypting the data once it is received by the far end device.
The present invention addresses security issues with respect to Voice Over IP (VoIP) telephone calls. Currently, a call signaling channel is secured by using either a Transport Layer Security (TLS), a Secure Sockets Layer (SSL), or an IP Security Protocol (IPSec) on a secure well known port. These approaches, however, suffer from delays in call setup time, complex handshaking procedures, and significant protocol overhead. Moreover, current H.323 VoIP implementations do not prevent signaling information from being viewed by unscrupulous computer hackers on the IP network used for VoIP calls. For instance, when a SETUP message is sent over the IP network using H.323,the calling name and calling number is visible to sniffers or other such tools used on the Internet. What is needed is a method that increases security, simplifies VoIP handshaking procedures, and reduces call setup time without adding significant protocol overhead.
The present invention calls for an originating H.323 gateway to send a Secure Registration Request (SRR) message to a far end H.323 gateway prior to sending the SETUP message. An SRR message includes information requesting a secure connection as well as other parameters such as, for instance, a sender""s digital certificate and an encryption algorithm. The far end H.323 gateway can either accept the SRR via a Secure Connection Confirm (SCF) message or reject the SRR via a Secure Connection Reject (SCR) message. Once an SCF message is returned, all further communication between the H.323 gateways is encrypted using a public key and encryption method specified in the SRR message. The advantages of the present invention include simplicity of use and lower call setup time than TSL, SSL, or IPSec.
In accordance with a first embodiment of the invention is a method of providing secure signaling connections for packet data network telephony calls. A secure registration request message containing an encryption technique and public key is sent from an originating gateway over a packet data network to a terminating gateway. The terminating gateway returns a secure confirmation message containing a digital certificate over the packet data network to the originating gateway. Once registered, further communication between the gateways is encrypted over the packet data network using the public key and encryption technique specified in the secure registration request message.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

System and method for enabling secure connections for H.323 VoIP calls


The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.

1. Field of the Invention
The invention relates to a chip package, and in particular, to a wafer-level chip package and fabrication method thereof.
2. Description of the Related Art
A wafer level packaging technique for chip packaging has been developed. A wafer level package is first completed and then a dicing step is performed to form separated chip packages. A redistribution pattern in a chip package is mainly designed to be in direct contact with metal pads. Thus, the process for forming the redistribution pattern must correspond with the design of the metal pads.
It is desired to have a novel chip package and a fabrication method thereof to address the above issues.

Chip package and fabrication method thereof


A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.

The present invention relates to multithreaded computer programs, and more particularly to the modification of such computer programs during execution.
Many modern computer programs are "multi-threaded", that is, the computer program is split into a plurality of simultaneously executing, or virtually simultaneously executing, tasks or "threads". In the case of a computer system having a plurality of processors, the various threads may actually execute simultaneously. In the case of a computer system having a single processor, the threads will typically be executed sequentially by the processor, with the switching between the threads being so fast as to be virtually simultaneous. While such threads typically execute independently of one another, they usually share resources such as memory.
In many instances, it is necessary or desirable for certain portions of the computer program code to be modified while the code is being executed by the computer system. In a multithreaded context, such modification presents a number of difficulties.
One problem associated with such modification is that because the threads share resources, where more than one thread attempts to modify a section of code at the same (or substantially the same) time, problems can be introduced into the code. For example, a second thread may begin modifying the code section before a first thread has completed its modifications, so that the resulting code no longer produces the desired results. When such undesired interactions between threads occur, the situation is said not to be "thread safe"; conversely, when such interactions are prevented, the code is "thread safe".
Conventionally, there have been two main approaches used to avoid the problems associated with multiple threads attempting to modify the same section of code at the same time.
The first approach is to use a "lock" to synchronize access to the section of code so that all threads other than the thread that is modifying the section of code are prevented from executing until the modification is complete. This approach, understandably, will usually degrade the performance of the computer program.
The second approach is to direct all threads, other than the thread that is modifying the section of code, to a "spin loop" until the modification is complete. A "spin loop" is a section of code which causes the threads to carry out pointless programming tasks, that do not advance any of the objectives of the computer program, until the modifications are complete. The threads in the spin loop are in essence "spinning their wheels", also known as "busy waiting", while they wait for the relevant thread to finish modifying the code. The use of spin loops can lead to "live lock" situations, where a higher priority thread is trapped in the spin loop and is unable to escape because a lower priority thread is modifying the code. As a result, the program can seize or "hang" such that it is unable to proceed with further productive execution.
Accordingly, it is desirable to provide a technique by which sections of computer code can be modified during execution in a multithreaded environment, without resorting to locks or spin loops.

This patent is subject to a terminal disclaimer.

Runtime code modification in a multi-threaded environment

International Business Machines Corporation


The disclosure includes a system, method, and tangible memory for generating a simulation. The method may include receiving real-world sensor stream data that describes a real-world data stream that is recorded by onboard sensors in one or more test vehicles, wherein the real-world sensor stream data describes real-world active agents and real-world environmental elements. The method may further include generating three-dimensional (3D) models of active agents and 3D models of environmental elements in a vehicle environment. The method may further include generating a simulation of the vehicle environment that synthesizes the real-world active agents with 3D models of active agents and synthesizes the real-world environmental elements with the 3D models of environmental elements.

The specification relates to a mixed reality simulation system for testing vehicle control system designs.
Advanced Driver Assistance Systems ("ADAS system" if singular, "ADAS systems" if plural) include autonomous vehicle control systems that need to be tested to ensure the safety of autonomous vehicles. Testing takes two forms: (1) real-world road testing, and (2) virtualized simulation testing methodologies.
Real-world testing methodologies record sensor data while a driver navigates roadways in the real world. Real-world testing is inadequate for designing ADAS systems because it is time consuming, expensive, fails to capture a wide enough range of driving scenarios, and risks collisions.
Virtualized simulation testing methodologies generate 3D virtual worlds from geometric models and estimate sensor data streams. Virtualized simulation testing methodologies are not as expensive as real-world road testing and do not risk collisions. However, virtualized simulations of road testing are inadequate for designing ADAS systems because it is not possible for a test engineer to design an entire virtual world with enough variation to yield accurate and reliable results that can be used to safely design an ADAS system.

Mixed reality simulation system for testing vehicle control system designs


A new and distinct Dracaena cultivar named ‘Fudrafut’ is disclosed, characterized by distinctive variegated leaves, with dark green margins and lighter Yellow-Green colored interior. The new variety is a Dracaena, typically produced as an ornamental plant.

The new cultivar is the product of induced mutation. The new variety originated as an induced mutation, by treating tissue cultured plantlets of an unnamed variety of Dracaena godseffiana with a known mutagen. The known chemical mutagen used was 10 ppm of 6 Benziylaminopurine.
The new variety was discovered by the inventor, Edwin John Frazer, a citizen of Australia, in 1995 in a commercial laboratory in Brookfield, Queensland, Australia. After identifying the new variety as a potentially interesting selection, the inventor continued selecting and propagating by tissue culture for several years until establishing a stable clone.
Asexual reproduction of the new cultivar 'Fudrafut' was first performed at the commercial laboratory in Brookfield, Queensland, Australia by meristem tissue culture. Access to all plants was restricted, as access to the laboratory was not open to the public. Through subsequent propagation by meristem tissue culture, multiple generations have been reproduced, which have shown that the unique features of this cultivar are stable and reproduced true to type.


A method and an apparatus for automatically sensing and configuring a termination in a network bus configuration are provided by input logic signals indicating whether or not a device connected to the network bus is located at an end position. If the device is at an end position, the network is automatically terminated by a matched load impedance located in the device. Because the load resistance at the ends of the network match the impedance of the communication medium, data loss due to signal reflections is eliminated.

This invention relates to local area networks and particularly to connections between nodes in bus-type local area networks. When signals are transmitted in a local area network (LAN) certain problems arise due to imperfect electrical termination of the wire medium used for transmitting the signals. In particular, data errors may result from signal reflections caused by a mismatch between the characteristic impedance of the wire communications medium and the impedance at the ends of the network. In order to overcome this problem, the ends of the network must be terminated properly in an impedance which matches the characteristic impedance of the medium. Proper termination may be accomplished by inserting a resistive impedance load having the same impedance as the characteristic impedance of the transmission wire at each end of the network. When this resistive load is driven by a reference voltage, it matches the characteristic impedance of the transmission wire, thus effectively removing reflections which may cause data loss. For example, if a transmission cable is used which has an impedance of 100 .OMEGA., then a 100 .OMEGA. termination resistor may be inserted at the ends of the cable.
A problem arises where an end of a LAN is moved due to the connection of another device to the chain of devices which form the network. A common way that this problem has previously been overcome has been the manual placement of a terminator cap on the end of the chain following the last device. This adds extra costs and the possibility for damage or error due to the need to manually identify the end of the chain. Moreover, the terminator caps may be inadvertently removed or disconnected, threatening the performance of the entire LAN.
What is needed is a mechanism for eliminating the source of potential failure in a LAN connected through a wire medium.

Method and apparatus for automatically sensing and configuring a termination in a bus-based network


A system for controlling a swarm that includes a plurality of autonomous objects may include a processing system and a controller. The processing system may compute the primitives to be applied to each pair of objects in the swarm, and may combine the primitives to generate higher-level primitives. The processing system may generate a graph of the computed primitives, and identify the cliques in the graph. The controller may cause the primitives to be applied between each pair of objects in the swarm, and cause each object to maximize its respective set of primitives so as to induce the desired group behavior. The controller may detect the desired group behavior in the swarm by monitoring the primitives computed by the processing system and the cliques identified by the processing system.

A number of applications require that large numbers of autonomous units, which may be referred to as swarms or swarming systems, be controlled. As just one of many possible examples, a plurality of small autonomous units may have the capability of penetrating and sensing the integrity of mechanical devices. By way of example, an aircraft engine, turbine, or wind generator, may be non-destructively evaluated by many small robotic devices swarming through the interior searching for defects.
Swarms may be made up of a large number of simple entities that undergo local interactions, which may include interaction with the environment. In some applications, the autonomous objects or agents that make up a swarm may be assumed to be small, and to have limited processing capabilities. Simple, on-board processing procedures may therefore have to be adopted in order to control the autonomous agents in these applications.
It has been recognized that complex group behaviors may emerge in swarms, and that results may achieved as a group by combining microscopic behaviors of the individual entities that make up a swarm.
Controlling swarms is a complex activity. Systems and methods for efficient large-scale control of swarming systems remain a challenge.


A mixing and dispensing device which selectively mixes liquids has two filling stations. Each filling station uses water pressure to siphon the liquids from their source container through the valves to an eductor to mix the chemicals with water and, then, to receiving containers, At least one of the valves is constructed to reduce cross-contamination by reducing the surface area of the delivery system.

1. Field of the Invention
This invention relates to devices for dispensing and mixing liquids, and more particularly to such devices that dispense and mix chemicals, and even more particularly to devices that dispense and mix cleaning chemicals.
2. Prior Art
Devices for dispensing and mixing cleaning chemicals have been recognized for several years as a major safety feature for personnel who are required to handle the chemicals. Such devices permit personnel to fill containers with cleaning products without having to come into physical contact with the chemicals that are mixed to produce the products. In addition to their safety features, these devices reduce waste and reduce spillage.
Typifying such dispensing and mixing devices is that commercially known as "Oasis" and which is distributed by Ecolab of St. Paul, Minn. The system is a single or multiple station fluid pressure operated device which dispenses to a three or five gallon mixing jug. This system is mountable on a shelf or a wall rack.
The "Oasis" device deploys a water gun, a metering device and a product concentrate tube which are assembled to and communicate with a filling jug. The product concentrate or cleaning chemical is brought to the jug through the concentrate tube. When the water gun is activated, the pressure created by the water draws the concentrate through the concentrate tube and the metering device and into the jug where it mixes with the water. After the jug is full, an operator can then fill a use solution container from a faucet or tap provided in the jug. In multiple filling stations, to prepare another cleaning chemical, the water gun is simply moved to another jug.
Processing one cleaning chemical at a time prevents cross-contamination. However, the movement of the water gun is time consuming and limits the system to processing only one chemical mixture at a time until the gun is moved to the next station. Generally, such a system is not capable of mixing and dispensing directly into a small sized container, such as a one-gallon container. Thus, there is a two-step process of mixing in one container, then dispensing into another container.
Another type of device used to mix and dispense chemicals is a siphon-type device such as that commercially made and marketed by Hydro Systems Company. Essentially, the system uses water flowing through a water valve and an eductor to draw a cleaning chemical to the educator. The water and cleaning chemical are mixed to a concentration based on the size of a metering tip disposed in the eductor. This device essentially comprises a source of water connected to a T-shaped educator, which, in turn, is in fluid communication with the source of chemical to be mixed with the water, As water flows through the eductor, it creates a vacuum, thereby drawing chemical thereinto which mixes with the water as it flows through the eductor and into a filling container. A manually operated gate, such as a spring-loaded shut-off controls the water flow through the eductor. This system eliminates the need to move a gun, but it still can only mix one chemical from a single source.
Another type of system, permitting up to four chemicals to be processed through one valve, is made and marketed by Hydro under the name "Streamline Select Four". In this system, up to four chemical sources are connected to the eductor via a single selector switch which functions as a valve. The selector switch selects the cleaning chemical to be mixed with water and is delivered therethrough to the eductor. However, the selector switch creates cross-contamination when it is changed from one chemical to another. The residue of the formerly processed chemical remains within the switch and mixes with the new chemical.
The cross-contamination is generally not a problem when filling large containers because the large amount of the new chemical significantly dilutes the former chemical. However, for small containers, such as one-gallon containers, the former chemical is usually not diluted sufficiently to meet quality and federal guidelines.
Moreover, other problems exist with present-day devices. For example:
(a) Excess operator handling to prevent cross-contamination when transferring from a large container to a small container; PA1 (b) Selector-type systems are currently not usable for small containers because of cross-contamination; PA1 (c) The known devices are primarily effective only when processing large volumes of cleaning products; and PA1 (d) Generally, multiple stations are required in order to handle multiple chemicals. PA1 (a) means for delivering water from a source thereof; PA1 (b) plural sources of chemical to be mixed with the water; PA1 (c) a first container filling station including: PA1 (d) a second container filling station for filling containers of a size different than those at the first filling station including:
Thus, it is apparent that the use of the presently known selector switches to process multiple cleaning chemical sources are practical only for large containers. It would be desirable to provide a single system that incorporates the features of the selector switch for mixing cleaning product and filling both large and small containers with the product without cross-contamination of the small volume containers.


In situ removal of selected or patterned portions of semiconductor layers is accomplished by induced evaporation enhancement to form patterned buried impurity layers in semiconductor devices, such as heterostructure lasers and array lasers, which function as buried impurity induced layer disordering (BIILD) sources upon subsequent annealing. These layers may be formed to either function as buried impurity induced layer disordering (BIILD) sources or function as a reverse bias junction configuration of confining current to the active region of a laser structure. Their discussion here is limited to the first mentioned function.

This invention relates generally to semiconductor laser structures and more particularly to laser structures having internal sources for forming, during growth or during anneal treatment after growth, buried impurity induced layer disordered (BIILD) regions that function as optical and current confinement mechanisms for such laser structures.
The employment of impurity induced layer disordering (IILD) is well known in the art for fabricating after growth buried or confined active regions in such semiconductor laser devices. However, there is no report or disclosure known by us that attempts or contemplates the fabrication and patterning of such sources in situ during growth. What is desired is a process, particularly as implemented in either MBE or MOCVD, wherein layer patterning can be achieved in situ without growth interruption by some off-line or nongrowth procedure or process.
There are two examples known to us where patterning may be achieved by quasi-in situ thermal processing wherein thermal etching is employed to selectively remove GaAs. In one example, a n-GaAs layer over a p-AlGaAs layer is first, selectively chemically etched in a particular region followed by thermal etching to remove the remaining thin GaAs left from chemical etching before proceeding with regrowth of the p-AlGaAs layer. This forms a buried reverse biased current confinement mechanism in a double heterostructure laser. H. Tanaka et al, "Single-Longitudinal-Mode Self Aligned AlGa(As) Double-Heterostructure Lasers Fabricated by Molecular Beam Epitaxy", Japanese Journal of Applied Physics, Vol. 24, pp. L89-L90, 1985. In the other example, a GaAs/AlGaAs heterostructure partially masked by a metallic film is thermally etched in an anisotropic manner illustrating submicron capabilities for device fabrication. A. C. Warren et al, "Masked, Anisotropic Thermal Etching and Regrowth for In Situ Patterning of Compound Semiconductors", Applied Physics Letters, Vol. 51(22), pp. 1818-1820, Nov. 30, 1987. In both of these examples, AlGaAs masking layers are recognized as an etch stop to provide for the desired geometric configuration in thermally etched GaAs, although it is also known that, given the proper desorption parameters, AlGaAs may also be thermally etched at higher temperatures with different attending ambient conditions vis a vis GaAs.
However, none of these techniques employ in situ photo induced evaporation as a technique in a film deposition system to incrementally reduce, on a minute scale, film thickness in patterned or selective locations at the growth surface either during or after film growth, producing smooth sculptured surface morphology which is a principal objective of this invention.
It is another object of this invention to bring about in situ removal or desorption of selected surface regions or layers of compound semiconductors employing induced evaporation enhancement in metalorganic chemical vapor deposition (MOCVD) epitaxy and to apply this method in the fabrication of buried optical waveguides or buried heterojunction lasers and laser arrays formed via buried impurity induced layer disordering (BIILD).

Buried disordering sources in semiconductor structures employing photo induced evaporation enhancement during in situ epitaxial growth


Methods and systems for using a laser type clock to produce a train of ultra-stable optical pulses. The methods and systems include generating an approximately 10 GHz ultralow noise pulse train from a harmonically modelocked laser having an intracavity Fabry-Perot etalon filter from a semiconductor lasers such as ring lasers, and the like. System output can have residual phase modulation(PM) noise values of approximately 18 fs and amplitude modulation(AM) noise values of approximately 0.05% RMS, and residual phase modulation(PM) noise values of approximately 94 fs and amplitude modulation(AM) noise values of approximately 0.05% RMS.

The erbium-doped fiber amplifier (EDFA) is an optical gain medium that is widely used in the telecommunications arena and it possesses an intrinsically low gain per unit length. In optical resonator applications, this forces the need for an extended gain medium, which causes the fundamental cavity frequency to remain rather low (typically 1-10 MHz). Such systems, therefore, require modelocking at extremely high orders to operate at typical (multi-GHz) bit rates.
Harmonically modelocked laser oscillators suffer a unique type of noise first encountered by that is now commonly referred to as supermode noise. See M. F. Becker, D. J. Kuizenga, and A. E. Siegman, xe2x80x9cHarmonic mode locking of the Nd: YAG laserxe2x80x9d, J. Quantum Electron. 8, 687 (1972). This noise results from the statistical independence of individual intracavity pulses, each of which must originate from a slightly different photon noise fluctuation. The resulting small differences between intracavity pulses cause a small amount of amplitude noise to appear at every harmonic of the cavity fundamental.
Suppression of this noise has been attempted lasers using various experimental techniques: incorporation of an intracavity etalon(See G. T. Harvey, L. F. Mollenauer, xe2x80x9cHarmonically mode-locked fiber ring laser with an internal Fabry-Perot stabilizer for soliton transmissionxe2x80x9d, Opt. Lett. 18, 107 (1993)); cavity length dithering at kHz rates(See X. Shan and D. M. Spirit, xe2x80x9cNovel method to suppress noise in harmonically modelocked erbium fibre lasersxe2x80x9d, Electron. Lett. 29, 979 (1993)); and by the use of two-photon absorption to prevent pulse dropouts(See 4. E. R. Thoen, M. E. Grein, E. M. Koontz, E. P. Ippen, H. A. Haus, and L. A. Kolodziejski,xe2x80x9cStabilization of an active harmonically mode-locked fiber laser using two-photon absorptionxe2x80x9d, Opt. Lett. 25, 948 (2000)). However, none of these techniques adequately reduces the noise problems enough.
Various patents have been proposed in the area. See for example, U.S. Pat. No. 5,381,426 to Fontana et al.; U.S. Pat. No. 5,450,427 to Fermann et al.; U.S. Pat. No. 5,590,143 to Takara et al.; U.S. Pat. No. 5,619,320 to Eiselt et al.; U.S. Pat. No. 5,761,228 to Yano; U.S. Pat. No. 5,781,327 to Brock; and U.S. Pat. No. 6,256,328 to Delfyett et al., the latter having the same assignee as that of the subject invention. However, none of the prior art adequately solves the noise problems referenced above.
A primary objective of the present invention is to provide a method and system for ultralow noise and supermode suppression in an actively modelocked external-cavity semiconductor diode laser.
The invention includes a method and system for the suppression of supermode noise in an approximately 10 GHz external-cavity semiconductor diode laser by using a high-finesse intracavity etalon. Using a recently-developed wideband modification of the homodyne noise measurement technique of Derickson, et. al.(D. J. Derickson, A. Mar, and J. E. Bowers, xe2x80x9cResidual and absolute timing jitter in actively modelocked semiconductor lasersxe2x80x9d, Electron. Lett. 26, 2026 (1990).), the inventors have made extended noise sideband measurements out to the Nyquist offset frequency (approximately 5 GHz). Measurements reveal that the supermode suppression is almost total over the entire Nyquist band, attenuating the noise spikes below the approximatelyxe2x80x94140 dBc/Hz white noise floor of the system. The invention also compares the noise of this harmonically-modelocked laser with a similar fundamentally-modelocked laser (also operating at approximately 10 GHz) to illustrate the advantages and disadvantages of each approach.

Ultralow noise optical clock for high speed sampling applications


An illuminated aerial marker for a high voltage transmission line using a spherical colored opaque capacitor with gas filled lamps electrically connected, exterior to the capacitor with one electrode of the lamps connected to the high voltage source and the other to the conductive area of the capacitor or capacitors. The lamps are spaced and sized to provide illumination with nighttime conspicuity of at least 4,000 feet when the lamps are activated.

This invention relates to aerial markers, and more particularly to markers having various configurations of neon lamps that cooperate with the exterior of colored spherical balls designed as capacitors to provide daytime and nighttime conspicuity of at least 4000 feet when the lamps are activated.
Many miles of high voltage transmission lines are constructed to be elevated to sufficient height, relative to the surrounding terrain, to minimize ground vehicle contact with the line. These lines are not easily visible from the air and present a hazard to low-flying aircraft. It is common to mark these transmission lines in strategic locations; the markers being spherical shaped fiberglass shells with a highly visible color to increase daytime visibility. It would, of course, be quite desireable to increase nighttime visibilty by illumination.
Existing technology includes a single neon tube encased inside a transparent tube filled with conductive fluid with one electrode of the neon tube connected to the high voltage source and the other to a rod of a precise, and considerable, length supported parallel to the high voltage source. U.S. Pat. No. 3,124,712 discloses the use of a high voltage source to operate a neon lamp but uses a light pervious rather than opaque enclosure, a single tube, and a rectifier to cause flashing of the single tube.


There is provided a coating composition comprising (A) a thermoplastic non-fluorine-containing polymer, (B) inorganic ferroelectric particles, (C) an affinity-improving agent comprising at least one of a coupling agent, a surfactant and an epoxy group-containing compound, and (D) a solvent, and there is provided a film formed using the coating composition which has highly dielectric property and low dielectric loss, can be made thin, is excellent in winding property (flexibility) and is suitable as a highly dielectric film for a film capacitor.

In recently years, plastic insulating materials are expected as film materials for film capacitors for communication, electronic devices, electric power, medium and low voltage phase advancement and inverter, piezoelectric devices, pyroelectric devices and dielectric materials for carrying transferring substance since they have a high insulation resistance, excellent frequency characteristics and excellent flexibility.
A film capacitor is usually comprised of a film structure comprising a dielectric polymer film subjected to aluminum or zinc deposition on its surface, or a film structure comprising multi-layers of aluminum foils and dielectric polymer films, and recently there are used a lot of film capacitors comprising a dielectric polymer film and an electrode formed thereon by metal deposition.
Hydrocarbon polymers such as polypropylene, polyester and polyphenylene sulfide are studied as a dielectric polymer for a film of film capacitor. However, a dielectric constant of such a film alone is only about 2.3 to about 3.
It is known that a capacity of a film capacitor is proportional to a dielectric constant of a film used and reversely proportional to a film thickness.
Therefore, making a film thinner has been studied, but if a film is made too thin, film formation becomes difficult, and lowering of a withstand voltage is recognized. Accordingly, there is a limit in making a film thinner.
For making a dielectric constant of a film itself higher, highly dielectric polyvinylidene fluoride polymer and cyano-ethylated pullulan have been studied as a polymer. However, dielectric constants of any of these films are not more than 20, and in addition, it is difficult to make the films thinner.
In recent years, making a size of a film capacitor smaller and its capacity larger has been advanced, and as a result, it is strongly demanded to make a dielectric constant of a film capacitor higher.
A proposal of incorporating inorganic particles having an especially high dielectric constant with a polymer to make a film was made as one of means for making a dielectric constant of a capacitor film higher.
For mixing inorganic ferroelectric particles to a polymer and making a film, there are known (1) a melt-kneading method and (2) a coating method.
The melt-kneading method (1) is a method of kneading inorganic ferroelectric particles and a polymer at a temperature of not less than a melting temperature of the polymer, making the mixture into a film by a melt-extrusion method or an inflation method, and if necessary, subjecting the film to stretching treatment. In this method, there are known the use of a hydrocarbon polymer such as polyphenylene sulfide, polypropylene or polyester (JP2000-501549A and JP2000-294447A) and the use of a vinylidene fluoride polymer (for example, JP59-43039A, JP60-185303A and JP58-69252A). However, it is difficult to produce a thin film having a high dielectric constant and few voids.
The coating method (2) is a method of producing a film by dissolving a polymer in a solvent, adding and mixing inorganic ferroelectric particles thereto to make a coating composition, and then forming a film by a coating method.
In the coating method (2), the use of thermosetting hydrocarbon polymers or precursors thereof being excellent in heat resistance and mechanical strength such as aromatic polyamide, aromatic polyimide and an epoxy resin (JP2001-106977A, JP1-248404A, JP4-160705A, JP2-206623A and JP2002-356619A), and the use of a vinylidene fluoride polymer (JP54-129397A) are known.
In the case of using a thermosetting hydrocarbon polymer, it is possible to produce a thin film having high mechanical strength, but a dielectric loss of the film is large and the film becomes hard. Therefore, it cannot be said that such a film is suitable as a film for a film capacitor which is required to have excellent winding property (flexibility). Especially, a system obtained by adding and mixing inorganic ferroelectric particles is very hard, and is used for an embedded capacitor, making use of its property of being hard.
In the case of using a polyimide precursor, heat treatment at 200° to 400° C. for 20 minutes is necessary, and productivity is lowered.
In the case of using a vinylidene fluoride polymer, it is difficult to obtain a film in which inorganic ferroelectric particles are homogeneously incorporated in a vinylidene fluoride polymer, and further improvement in making a film thin and increasing a dielectric constant is required.
Further, it is proposed to produce a sheet comprising highly incorporated inorganic ferroelectric particles by press-molding composite particles prepared by coating inorganic ferroelectric particles with a vinylidene fluoride polymer (JP61-224205A). However, the film is as thick as 150 μm, and cannot be said to be suitable as a film for a film capacitor which is required to have excellent winding property (flexibility).


A vehicle chassis having substantially all of the mechanical, electrical, and structural componentry necessary for a fully functional vehicle includes at least an energy conversion system, a steering system, and a braking system. The chassis is configured for matability with a variety of different types or styles of vehicle bodies. Various prior art mechanical control linkages between a driver and controlled systems are replaced with non-mechanical control signal transmission components. Fuel cell technology is also implemented. A substantially flat and relatively thin vehicle chassis enables compact storage of multiple vehicle chassis. This compact storage is achieved by high density vertical stacking of the vehicle chassis, which improves packaging and shipping efficiency, reduces plant floor usage for storage during or before testing, assembly or shipping processes, and may reduce overall manufacturing, assembly, shipping, and/or vehicle costs. The chassis is characterized by the absence of a front engine compartment, with energy conversion, energy storage, steering and braking systems contained substantially within a generally flat frame, having substantially flat upper and lower faces to facilitate optimal stacking efficiency.

This invention relates to the compact stacking of vehicle chassis for optimized storage and shipping efficiency.
Mobility, being capable of moving from place to place or of moving quickly from one state to another, has been one of the ultimate goals of humanity throughout recorded history. The automobile has likely done more in helping individuals achieve that goal than any other development. Since its inception, societies around the globe have experienced rates of change in their manner of living that are directly related to the percentage of motor vehicle owners among the population.
Prior art automobiles and light trucks include a body, the function of which is to contain and protect passengers and their belongings. Bodies are connected to the numerous mechanical, electrical, and structural components that, in combination with a body, comprise a fully functional vehicle. The nature of the prior art connections between a vehicle body and vehicular componentry may result in certain inefficiencies in the design, manufacture, and use of vehicles. Three characteristics of prior art body connections that significantly contribute to these inefficiencies are the quantity of connections; the mechanical nature of many of the connections; and the locations of the connections on the body and on the componentry.
In the prior art, the connections between a body and componentry are numerous. Each connection involves at least one assembly step when a vehicle is assembled; it is therefore desirable to reduce the number of connections to increase assembly efficiency. The connections between a prior art body and prior art vehicular componentry include multiple load-bearing connectors to physically fasten the body to the other components, such as bolts and brackets; electrical connectors to transmit electrical energy to the body from electricity-generating components and to transmit data from sensors that monitor the status of the componentry; mechanical control linkages, such as the steering column, throttle cable, and transmission selector; and ductwork and hoses to convey fluids such as heated and cooled air from an HVAC unit to the body for the comfort of passengers.
Many of the connections in the prior art, particularly those connections that transmit control signals, are mechanical linkages. For example, to control the direction of the vehicle, a driver sends control signals to the steering system via a steering column. Mechanical linkages result in inefficiencies, in part, because different driver locations in different vehicles require different mechanical linkage dimensions and packaging. Thus, new or different bodies often cannot use xe2x80x9coff-the-shelfxe2x80x9d components and linkages. Componentry for one vehicle body configuration is typically not compatible for use with other vehicle body configurations. Furthermore, if a manufacturer changes the design of a body, a change in the design of the mechanical linkage and the component to which it is attached may be required. The change in design of the linkages and components requires modifications to the tooling that produces the linkages and components.
The location of the connections on prior art vehicle bodies and componentry also results in inefficiencies. In prior art body-on-frame architecture, connection locations on the body are often not exposed to an exterior face of the body, and are distant from corresponding connections on the componentry; therefore, long connectors such as wiring harnesses and cables must be routed throughout the body from componentry. The vehicle body of a fully-assembled prior art vehicle is intertwined with the componentry and the connection devices, rendering separation of the body from its componentry difficult and labor-intensive, if not impossible. The use of long connectors increases the number of assembly steps required to attach a vehicle to its componentry.
Furthermore, prior art vehicles typically have internal combustion engines that have a height that is a significant proportion of the overall vehicle height. Prior art vehicle bodies are therefore designed with an engine compartment that occupies about a third of the front (or sometimes the rear) of the body length. Compatibility between an engine and a vehicle body requires that the engine fit within the body""s engine compartment without physical part interference. Moreover, compatibility between a prior art chassis with an internal combustion engine and a vehicle body requires that the body have an engine compartment located such that physical part interference is avoided. For example, a vehicle body with an engine compartment in the rear is not compatible with a chassis with an engine in the front.
A self-contained chassis has substantially all of the mechanical, electrical, and structural componentry necessary for a fully functional vehicle, including at least an energy conversion system, a suspension and wheels, a steering system, and a braking system. The chassis has a simplified, and preferably standardized, interface with connection components to which bodies of substantially varying design can be attached. X-by-wire technology may be utilized to eliminate mechanical control linkages. Fuel cell technology may also be implemented in the energy conversion system.
A result is the reduction in the amount of time and resources required to design and manufacture new vehicle bodies. Body designs need only conform to the simple attachment interface of the chassis, eliminating the need to redesign or reconfigure expensive components.
Further, a multitude of body configurations to share a common chassis, enabling economies of scale for major mechanical, electrical, and structural components.
Connection components, exposed and unobstructed, increase manufacturing efficiency because attachment of a body to the chassis requires only engagement of the connection components to respective complementary connection components on a vehicle body.
Vehicle owners can increase the functionality of their vehicles at a lower cost than possible with the prior art because a vehicle owner need buy only one chassis upon which to mount a multitude of body styles.
A substantially flat and relatively thin vehicle chassis enables compact storage of multiple vehicle chassis. This compact storage is achieved by high density vertical stacking of the vehicle chassis, which improves packaging and shipping efficiency, reduces plant floor usage for storage during or before testing, assembly or shipping processes, and may reduce overall manufacturing, assembly, shipping, and/or vehicle costs. In particular, as viewed in the various figures, the chassis is characterized by the absence of a front engine compartment, with energy conversion, energy storage, steering and braking systems contained substantially within a generally flat frame, having substantially flat upper and lower faces to facilitate optimal stacking efficiency.
According to an aspect of the invention, a vehicle chassis includes a structural frame; a steering system mounted with respect to the structural frame; a by-wire braking system mounted with respect to the structural frame; an energy conversion system mounted with respect to the structural frame and controllable by wire; and at least one vertical load bearing member mounted with respect to the structural frame and configured to bear a vertical load of a second chassis stacked thereon.
A method for improving chassis packaging efficiency includes vertically stacking a first chassis above a second chassis, wherein the first chassis and the second chassis include a structural frame, a by-wire steering system mounted with respect to the structural frame, a by-wire braking system mounted with respect to the structural frames, and a by-wire energy conversion system mounted with respect to the structural frame. The method may further include employing a pallet to facilitate the stacking. The pallet may include a horizontal member configured to support the first chassis above the second chassis and at least one vertical member configured to transfer vertical load caused by the first chassis to a surface not on the second chassis
The above objects, features, and advantages, and other objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.