Black liquor from a cellulose pulp processing plant is treated, including by using a direct contact (cascade) evaporator, without need for oxidizing the black liquor, without substantial sulphur emissions at the cascade evaporator, and by maximizing the solids content of the black liquor so that the loss of heating value of the black liquor is minimized. The black liquor is heated under temperature and time conditions sufficient to drive off most of the organic sulphur compounds as off gases, which gases are converted primarily to methane and hydrogen sulfide, with the methane separated by selective absorption in white liquor. The black liquor is then stripped of most remaining sulfur by bringing it into stripping contact with flue gases from the recovery boiler, the flue gases taken from downstream of the direct contact evaporator. After stripping, the solids content of the black liquor is increased (as by passing it to another evaporator), then it is led into association with the cascade evaporator, and then passed into the recovery boiler where it is combusted. The sulphur constituents of the off gases from the stripping operation are also passed into contact with white liquor.

In chemical recovery plants associated with the production of paper pulp, direct contact evaporators (cascade evaporators) are sometimes associated with the recovery boiler/furnace. In such systems, the black liquor from the pulping process is oxidized and is fed at approximately a 50% total solids concentration to the cascade evaporator. In the evaporator its solids concentration is increased to about 65% (the increase in solids content is limited by the high viscosity of the oxidized black liquor), and then it is fed to the recovery boiler as fuel. This commercial system has a number of disadvantages, including:
The solids concentration of the black liquor when fed to the boiler is limited due to high viscosity; PA1 The oxidizing process causes a reduction of the fuel value of the black liquor by wet oxidizing Na.sub.2 S to Na.sub.2 SO.sub.4 ; and PA1 There is the potential for sulphur off gases at the cascade evaporator because of the presence of significant amounts of particular sulfur containing chemicals in the black liquor at that stage. This last problem has caused some installations to replace direct contact evaporators that were otherwise properly functioning since it is difficult to remove the sulfur off gases generated at this particular location.
According to the present invention, a method and apparatus are provided for treating black liquor associated with direct contact evaporators to overcome the drawbacks, and solve the problems, set forth above. According to the present invention, it is possible to increase the solids content of the black liquor up to about 80%. Sulfur is removed as H.sub.2 S so there is no need to oxidize the black liquor, thereby eliminating the loss of its heating value caused by oxidation, and minimizing the sulfur compounds that reach the direct contact evaporator. Further, the sulfur that is removed can be used in other beneficial ways within the pulp plant.
Some of the more basic aspects of the present invention are the heating of the black liquor--such as disclosed in U. S. Pat. No. 4,929,307 (the disclosure of which is incorporated by reference herein)--to drive off organic sulfur containing gases, such as DMS; removing the sulfur containing compounds from the off gases and using them in the pulp mill--such as disclosed in copending U.S. application Ser. No. 07/651,462, filed Feb. 6, 1991 now abandoned (the disclosure of which is incorporated by reference herein); and passing the black liquor (after heat treatment) into stripping contact with flue gases from the recovery boiler.
According to one aspect of the present invention there is provided a method of treating black liquor from a cellulose pulp producing facility, using a direct contactor evaporator and a recovery boiler having a flue gas discharge, comprising the following steps: (a) Heating black liquor at a temperature and for a time period sufficient to drive the majority of the sulfur containing organic compound gases from the black liquor. (b) Removing substantially the remaining sulfur in the black liquor by utilizing flue gases from the boiler flue gas discharge. (c) Passing the hot flue gases through the direct contact evaporator. (d) After step (b), feeding the black liquor to the direct contact evaporator to increase the solids content thereof; and (e) feeding the increased solids content black liquor to the recovery boiler to effect combustion thereof and produce hot flue gases. Desirably, the flue gases for step (b) are removed from the flue gas discharge at a point of withdrawal; and the method comprises the further step (f) of cleaning the removed flue gases after step (b) to remove the sulfur therefrom, and then returning the cleaned gases to the flue discharge downstream of the point of withdrawal. Also, preferably step (b) is practiced by bringing flue gases from the flue gas discharge, from a point downstream of the direct contact evaporator, into contact with the black liquor.
According to another aspect of the present invention there is provided a method of treating black liquor from a cellulose pulp producing facility, using a direct contactor evaporator and a recovery boiler having a flue gas discharge, comprising the following steps: (a) Heating black liquor at a temperature and for a time period sufficient to drive tile majority of the sulfur containing organic compound gases from the black liquor. (b) Passing the hot flue gases through the direct contact evaporator. (c) After step (a), feeding the black liquor to the direct contact evaporator to increase the solids content thereof. (d) Feeding the increased solids content black liquor to the recovery boiler to effect combustion thereof and produce hot flue gases; and (e) treating the gases with sulfur containing organic compounds to produce sulfur containing chemicals useful in thee pulping of cellulose in the cellulose pulp producing facility. The method also preferably comprises the further step (f), between steps (a) and (c), of stripping off the remaining sulphur from the black liquor, by passing it into contact with flue gases from the recovery boiler.
In the practice of the method of the invention, there may also be the further step of increasing the solids content of the black liquor, as by feeding at least a portion thereof to another evaporator (such as a falling film evaporator) to increase the solids content thereof before it is fed to the cascade evaporator. Normally, the black liquor in step (a) has a solids content of roughly 50%, which is increased to roughly 75-80% prior to feed to the recovery boiler. Step (e) may be practiced by converting the off gases to primarily methane and hydrogen sulfide, and then separating the methane and hydrogen sulfide, e.g. by passing the converted off gases into contact with white liquor from the pulp processing facility, and then using the enhanced sulfidity white liquor in the pulp processing facility.
According to another aspect of the present invention, there is a method of treating black liquor according to the following steps: (a) Stripping off sulphur containing compounds from the black liquor. (b) After step (a), feeding the black liquor to the direct contact evaporator to increase the solids content thereof. ( c ) Feeding the increased solids content black liquor to the recovery boiler to effect combustion thereof and produce hot flue gases; and (d) passing the hot flue gases through the direct contact evaporator. Step (a) is preferably practiced by bringing flue gases from the recovery boiler, from a point downstream of the direct contact evaporator, into contact within the black liquor.
According to yet another aspect of the present invention, apparatus for treating black liquor in a cellulose pulp processing facility is provided. The apparatus comprises the following structures: A recovery boiler having a black liquor inlet and a flue gas outlet, for combusting black liquor fed to the inlet to produce flue gases. A direct contact evaporator. A first conduit leading from the flue gas outlet to the direct contact evaporator, and a second conduit leading downstream from the evaporator. Means for bringing black liquor into stripping contact with hot gases. Means for feeding flue gases from the second conduit to the means for bringing black liquor into stripping contact with hot gases. Means for feeding black liquor to said means for bringing black liquor into stripping contact with hot gases; and means for feeding black liquor from the means for bringing black liquor into stripping contact with hot gases to the direct contact evaporator.
Means for increasing the solids consistency of black liquor (such as a falling film evaporator) may be disposed in the means for feeding black liquor from the means for bringing black liquor into stripping contact with hot gases to the direct contact evaporator. The means for feeding flue gases from the second conduit to the means for bringing black liquor into stripping contact with hot gases may comprise a conduit and a fan in the conduit. There may further be means for heating black liquor to drive off the majority of the organic sulphur compounds therefrom, the heating means connected to the means for feeding black liquor to the means for bringing black liquor into stripping contact with hot gases.
It is the primary object of the present invention to provide for the treatment of black liquor with a cascade evaporator to maximize the fuel value of the black liquor, minimize the possibility of significant sulfur emissions from the evaporator, and/or utilize sulfur from the black liquor in advantageous manners in other parts of the facility. This and other objects of the invention will become clear from the detailed description of the drawings, and from the appended claims.

Sulphur removal from gases associated with boilers having cascade evaporators


The present invention discloses a stack capacitor structure and method of making the same. The top plate of the stack capacitor structure is connected to each other through a connecting node. The method of forming the stack capacitor structure includes providing an insulating substrate with a doped insulating material layer disposed therein. Then, the insulating substrate is patterned to form a trench, wherein an inner sidewall of the trench has a first region and a second region and the doped insulating material layer within the second region is entirely removed to form a hole. Later, a top plate is formed to surround the inner sidewall of the trench, and the top plate fills in the hole. Next, a capacitor dielectric layer is formed to surround the top plate. Finally, a storage node is formed to fill up the trench.

1. Field of the Invention
The present invention relates to a stack capacitor structure and a method of forming a stack capacitor structure. More specifically, the present invention relates to a stack capacitor structure having a connecting node for coupling two adjacent top plates, and a method of forming the stack capacitor structure.
2. Description of the Prior Art
As high density and high performance are required for a DRAM, cell capacitor technology needs to be developed to provide the required performance. Various types of capacitors have been proposed, such as a trench type and a stack type.
Generally, an increase in the cell capacitance can be achieved by both using high-k materials and increasing the surface area of the storage node. Even when high-k materials are used, much effort must be focused on enlarging the storage node surface area to maximize the cell capacitance. The surface area of a storage node is mostly increased by increasing the height since the design rule limits the horizontal dimension of the storage node.
However, if the capacitor is too high, the capacitor may collapse during the fabricating processes.

Stack capacitor structure and forming method


The present invention provides a flexible abrasive article containing minimal releaseable amounts of physical and chemical contaminants that may be used to clean surfaces. The abrasive article is made of a foraminous substrate, at least one binder and abrasive particles. Methods of making such abrasive articles are also provided.

This invention is related to abrasive articles, particularly abrasive articles especially suited for use in critical or controlled environments.
An ever increasing number of industrial operations require isolation from potential ubiquitous physical and chemical contaminants. Conversely, other industrial operations may require quarantine from the general environment due to their toxic or infectious nature. Such needs are generally met by the design, fabrication, and use of so-called xe2x80x9cclean roomsxe2x80x9d (also known as xe2x80x9cwhite roomsxe2x80x9d).
Such facilities have found widespread use in the manufacture of semiconductor devices, where the presence of external contaminants such as unwanted particles and ions must be minimized. Operations such as, for example, crystal growth, ion implantation, metal deposition, and etching are typically carried out in low pressure (vacuum) chambers or reactors that are operated in clean room environments. Following use for a time, these chambers inevitably become soiled and therefore require cleaning. Depending on the nature of the contamination, abrasive articles may be required to remove tenaciously-held contaminants. Such abrasive operations by definition generate particulate materials that may contaminate the clean room environment. Further, the abrasive articles themselves may convey unwanted particles and/or ionic moieties into the chamber and/or clean room. There thus is a need for an abrasive article for use in critical, clean room environments. Such an abrasive article should efficaciously remove residue from reactor surfaces, minimize the release of particles into the clean room environment, and minimize transfer of ionic contaminants to the reactor and/or the clean room.
One embodiment of this present invention provides a flexible abrasive article comprising a foraminous substrate, at least one binder, and abrasive particles, wherein the abrasive article contains minimal amount of releaseable physical and chemical contaminants and when used to clean a surface provides a clean workpiece with minimal amounts of physical and chemical contaminants and does not damage the workpiece surface.
Another embodiment of this invention provides a method of making a flexible abrasive article comprising the steps of:
Providing a foraminous substrate;
Coating the foraminous substrate with a make coating;
Coating the coated substrate with abrasive granules;
Curing the granule coated substrate;
Coating the granule coated cured substrate with a size coating;
Curing the size-coated substrate;
Converting the cured, size-coated substrate into useful shaped abrasive article;
Post-cleaning the abrasive articles to remove potential workpiece contaminants; and
Packaging the post-cleaned abrasive articles.
xe2x80x9cFlexible abrasive articlexe2x80x9d refers to an abrasive article, which when folded onto itself with the abrasive surface exposed, that does result in knife-edging of the abrasive coating.
xe2x80x9cForaminous substratexe2x80x9d refers to a porous, organic substrate having openings defined by interconnecting voids throughout at least one surface of the substrate. For example, either an open-celled foam substrate or lofty, fibrous, nonwoven web or fabric qualifies as a foraminous substrate.
xe2x80x9cMake coat precursorxe2x80x9d refers to the coatable resinous adhesive material applied to the coatable surfaces of the openings of the foraminous substrate to secure abrasive particles thereto.
xe2x80x9cMake coatxe2x80x9d refers to the layer of cured resin over the coatable surfaces of the openings of the foraminous substrate formed by hardening the make coat precursor.
xe2x80x9cSize coat precursorxe2x80x9d refers to the coatable resinous adhesive material applied to the coatable surfaces of the openings of the foraminous substrate over the make coat.
xe2x80x9cSize coatxe2x80x9d refers to the layer of cured resin over the coatable surfaces of the openings of the foraminous substrate formed by hardening the size coat precursor.
xe2x80x9cCuredxe2x80x9d or xe2x80x9cfully curedxe2x80x9d means a hardened polymerized curable coatable resin.
xe2x80x9cFine abrasive particlesxe2x80x9d refers to abrasively effective particles comprising any of the materials set forth herein and having distribution of particle sizes wherein a highly preferred median particle diameter is about 60 microns or less. A spherical particle shape is assumed in referring to the median particle diameter, based on standard test methods available for the determination of particle diameters such as, for example, ANSI test method B74.18-1884.
xe2x80x9cSubstantially uniformxe2x80x9d refers to the distribution of fine abrasive particles in the finished articles that are distributed along coatable surfaces of the contours and walls i.e., coatable surfaces, defined by interstices or voids without significant agglomeration of the resin and the particles, as may be visually observed by microscopic examination of the surfaces. In the finished article, the majority of the particles are positioned along the coatable surfaces of the openings to be abrasively effective in the initial application of the article.
The abrasive articles of this invention may be provided in the form of hand pads, endless belts, discs, densified or compressed wheels and the like. Additionally, the articles of the invention may be laminated to other articles such as nonwoven, closed cell foam, open cell foam, or rigid foam substrates and the like or the articles may be provided a in a roll form with or without perforations therein.
In the preparation of the foregoing articles, a foraminous substrate is prepared or is otherwise provided. A make coat precursor composition is applied to a surface of the foraminous substrate to form a first coating layer. A plurality of fine abrasive particles are applied to the first coating layer, and the make coat precursor composition is at least partially cured. Optionally, a size coat precursor composition is applied over the abrasive particles and the first coating layer to form a second coating layer. The first and second coating layers are cured to affix the abrasive particles to the coatable surfaces of the openings of the foraminous substrate to provide the abrasive article wherein the particles are affixed to the surfaces in a substantially uniform distribution along their contours.
The fine abrasive particles are deposited onto the make coat precursor, preferably by depositing the particles first on one major surface of the foraminous substrate and then over the second major surface of the foraminous substrate using the deposition method described in U.S. Pat. No. 5,863,305, incorporated by reference herein. Larger abrasive particles, i.e., greater than 60 micron diameter, are preferably applied to the make coat precursor by known methods such as drop coating or electrostatic coating. Preferably, the make and size coat precursors are thermosetting, coatable, polyurethane resins. Likewise, the optional size coat, when applied to the article, is preferably applied over the at least partially cured make coat. The make coat precursor and size coat precursor are then fully cured to provide the flexible abrasive articles of the invention, and the thus prepared articles may be further processed to provide hand pads, endless belts, discs, densified or compressed wheels and the like.


In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P+ regions connected to a pixel selection line conductive layer are formed on top layer portions of upper ends of the island-shaped semiconductors so as to adjoin the N regions and the P regions. In the P+ regions, a first P+ region has a thickness less than a second P+ region, and the second P+ region has a thickness less than a third P+ region.

1. Field of the Invention
The present invention relates to solid-state imaging devices, and more specifically to a solid-state imaging device for color imaging in which a pixel is formed using an island-shaped semiconductor (a pillar-shaped semiconductor), with a high pixel density, a high sensitivity, and a wide dynamic range being achieved.
2. Description of the Related Art
Solid-state imaging devices for color imaging, such as CCD and CMOS imaging devices, are generally used in video cameras, still cameras, and so forth. In these uses, solid-state imaging devices for color imaging are required to have improved performance such as a high pixel density, a high sensitivity, and a wide dynamic range.
FIG. 6 illustrates a cross-sectional structural diagram of a CMOS color solid-state imaging device of the related art (see, for example, U.S. Patent Application Publication No. 2005/0082627).
Isolation silicon oxide layers (hereinafter, represented by SiO2 layers) 101a to 101d are formed on a surface of a P-region (hereinafter, a P-type semiconductor region including acceptor impurities is represented by a "P region") silicon (hereinafter represented by "Si") substrate 100 using, for example, the LOCOS (Local Oxidation of Silicon) method. N regions (hereinafter, an N-type semiconductor region including donor impurities is represented by an "N region") 102a to 102c are formed between the isolation SiO2 layers 101a to 101d.
In FIG. 6, the P-region substrate 100 and the N regions 102a to 102c form photodiodes based on P-N junctions. Incident light (electromagnetic energy waves) incident on the upper surfaces of the N regions 102a to 102c undergoes photoelectric conversion in the N regions 102a to 102c and the P-region substrate 100 located below the N regions 102a to 102c, and signal charges (in this case, free electrons) are generated. The generated signal charges are accumulated in the photodiodes, and are extracted to an external output circuit as the signal output current in a certain period.
An interlayer SiO2 layer 103 is formed on the isolation SiO2 layers 101a to 101d and the N regions 102a to 102c. Metal wirings 104a to 104d are formed on the interlayer SiO2 layer 103. Further, a protective insulating layer 105 composed of, for example, a SiO2 or organic material layer is formed on the interlayer SiO2 layer 103 and the metal wirings 104a to 104d.
In FIG. 6, the upper surface of the protective insulating layer 105 is planarized. A color filter 106R for red (R), a color filter 106G for green (G), and a color filter 106B for blue (B) are arranged on or above the protective insulating layer 105 so as to surround the N regions 102a to 102c, which form photodiodes, when viewed in a direction perpendicular to the upper surface. Isolation insulating layers 107a to 107c are formed between the color filter 106R for red (R), the color filter 106G for green (G), and the color filter 106B for blue (B).
The color filter 106R for red (R) is a layer that transmits mainly red wavelength light in incident light incident on the upper surfaces of the N regions 102a to 102c. The color filter 106G for green (G) is a layer that transmits mainly green wavelength light in the incident light. The color filter 106B for blue (B) is a layer that transmits mainly blue wavelength light in the incident light.
The color filter 106R for red (R) (hereinafter, the "color filter 106R" for short), the color filter 106G for green (G) (hereinafter, the "color filter 106G" for short), and the color filter 106B for blue (B) (hereinafter, the "color filter 106B" for short) are formed by a photoresist containing pigments or dyes. The color filter 106G for green (G) is formed using photolithography technology, and is coated with the protective insulating layer 105 and is also coated with the isolation insulating layer 107a from above the color filter 106G. The color filter 106R and the color filter 106B are formed on or over the isolation insulating layer 107a using photolithography technology. The isolation insulating layer 107c also functions as a protection layer of the color filters 106R, 106G, and 106B.
The isolation SiO2 layers 101a to 101d, the N regions 102a to 102c, and the metal wirings 104a to 104d formed on or over the P-region substrate 100 illustrated in FIG. 6 are formed using advanced CMOS micromachining technology, which is a micromachining technology used for microprocessors, memories, and so forth. Although not illustrated in FIG. 6, CMOS transistors for forming a driver circuit, a signal processing circuit, and so forth are formed on or over the P-region substrate 100 using the advanced CMOS micromachining technology in a manner similar to that for the isolation SiO2 layers 101a to 101d, the N regions 102a to 102c, and the metal wirings 104a to 104d.
The advanced CMOS micromachining technology is not available for the formation of the color filter 106R, the color filter 106G, and the color filter 106B. The color filter 106R, the color filter 106G, and the color filter 106B are formed using photolithography technology that utilizes a different photoresist material.
The micromachinable dimensions (minimum machining dimensions) of the color filter 106R, the color filter 106G, and the color filter 106B which are realized by the photolithography technology are greater (larger) than the micromachinable dimensions which are realized by the advanced CMOS micromachining technology described above. In this manner, the inability to apply micromachining technology to the color filters 106R, 106G, and 106B hinders a further increase in the pixel density of CMOS solid-state imaging devices.
In addition, the process and apparatus for forming the color filters 106R, 106G, and 106B are different from the process and apparatus used in advanced CMOS micromachining technology described above, which may cause an increase in cost. This imposes a problem of reduction in the cost of solid-state imaging devices.
Additionally, the material of the color filters 106R, 106G, and 106B causes light absorption, which thus prevents the color filter 1068 from achieving a light transmittance of 100% in the red (R) wavelength region. Similarly to this, the color filter 106G and the color filter 106B are also prevented from achieving a light transmittance of 100% in the green (G) wavelength region and the blue (B) wavelength region, respectively. In this manner, light absorption which prevents improvements in the light transmittance of the color filters 106R, 106G, and 106B hinders the sensitivity of CMOS color solid-state imaging devices from increasing.
Hereinafter, another solid-state imaging device for color imaging of the related art will be described with reference to FIGS. 7A to 7C.
FIG. 7A illustrates a cross-sectional structural diagram of a solid-state imaging device in which one island-shaped semiconductor constitutes one pixel (see, for example, U.S. Patent Application Publication No. 2010/0200731).
Referring to FIG. 7A, a signal line N+ region 112 (hereinafter, a semiconductor region including a large number of donor impurities is referred to as an "N+ region") is formed on a substrate 111. An island-shaped semiconductor 110 is formed on the signal line N+ region 112. In the island-shaped semiconductor 110, an insulating layer 114 is formed on an outer periphery of a P region 113 adjoining the signal line N+ region 112, and a conductive layer 115 is further formed with the insulating layer 114 interposed between the conductive layer 115 and the P region 113. An N region 116 is formed on the outer periphery of the P region 113 above the conductive layer 115. A P+ region (hereinafter, a semiconductor region including a large number of acceptor impurities is referred to as a "P+ region") 117 is formed on the N region 116 and the P region 113. The P+ region 117 is connected to a pixel selection line conductive layer 118. The insulating layer 114 described above is continuously formed in such a manner as to surround an outer periphery of the island-shaped semiconductor 110. Similarly to the insulating layer 114, the conductive layer 115 is also continuously formed in such a manner as to surround the outer periphery of the island-shaped semiconductor 110.
In this solid-state imaging device, the P region 113 and the N region 116 in the island-shaped semiconductor 110 form a photodiode region 119. When light is incident on the P+ region 117 side on a top layer of an upper end of the island-shaped semiconductor 110, signal charges (here, free electrons) are generated in a photoelectric conversion region in the photodiode region 119. The generated signal charges are accumulated mainly in the N region 116 of the photodiode region 119.
The island-shaped semiconductor 110 further has a junction field-effect transistor having a gate which is defined by the N region 116, a source which is defined by the P+ region 117, and a drain which is defined by the P region 113 in the vicinity of the signal line N+ region 112.
In this solid-state imaging device, the drain-source current (output signal) of the junction field-effect transistor changes in accordance with the quantity of signal charges accumulated in the N region 116, and is extracted from the signal line N+ region 112 as the signal output.
The island-shaped semiconductor 110 further has a MOS transistor having a source which is defined by the N region 116 of the photodiode region 119, a gate which is defined by the conductive layer 115, a drain which is defined by the signal line N+ region 112, and a channel which is defined by the P region 113 between the N region 116 and the signal line N+ region 112.
In this solid-state imaging device, the signal charges accumulated in the N region 116 are discharged to the signal line N+ region 112 by the application of the ON voltage (high-level voltage) to the conductive layer 115 that is the gate of the MOS transistor.
Herein, the term "high-level voltage" refers to a positive voltage having a high level in a case where the signal charges are free electrons, and the term "low-level voltage" refers to a voltage whose absolute value is lower than the "high-level voltage". Accordingly, if the signal charges are positive holes, the "high-level voltage" implies a negative voltage having a low level, and the "low-level voltage" refers to a voltage that is closer to 0 V than the "high-level voltage".
The imaging operation of this solid-state imaging device includes the operations (1) to (3) below while the ground voltage (=0 V) is applied to the signal line N+ region 112, the conductive layer 115, and the P+ region 117:
(1) A signal charge accumulating operation for accumulating in the N region 116 the signal charges generated in the photoelectric conversion region (the photodiode region 119) by the incidence of light on the top surface of the upper end of the island-shaped semiconductor 110,
(2) A signal charge read operation for reading as the signal current the source-drain current of the junction field-effect transistor that has been modulated by the potential of the N region 116 which has changed in accordance with the quantity of accumulated signal charges while the ground voltage is applied to the signal line N+ region 112 and the conductive layer 115 and a positive voltage is applied to the P+ region 117, and
(3) A reset operation for discharging the signal charges accumulated in the N region 116 to the signal line N+ region 112 while the ground voltage is applied to the P+ region 117 and a positive voltage is applied to the conductive layer 115 and the signal line N+ region 112 after the signal charge read operation.
FIG. 7B illustrates a plan view of a solid-state imaging device of the related art in which island-shaped semiconductors P11 to P33 (each of which corresponds to the island-shaped semiconductor 110 in FIG. 7A) constituting pixels are arranged in a two-dimensional matrix. The island-shaped semiconductors P11 to P33 constituting pixels are formed on signal line N+ regions 112a, 112b, and 112c (each of which corresponds to the signal line N+ region 112 in FIG. 7A).
In the island-shaped semiconductors P11 to P33, pixel selection line conductive layers 118a, 118b, and 118c (each of which corresponds to the pixel selection line conductive layer 118 in FIG. 7A) are each continuously formed in each row extending in the horizontal direction. Similarly to this, in the island-shaped semiconductors P11 to P33 constituting pixels, conductive layers 115a, 115b, and 115c (each of which corresponds to the conductive layer 115 in FIG. 7A) are each continuously formed in each row extending in the horizontal direction.
Color filters B1, B2, and B3 for blue (B), color filters R1, R2, and R3 for red (R), and color filters G1, G2, and G3 for green (G) are formed on the island-shaped semiconductors P11 to P33.
With the configuration described above, the blue (B) signal current is obtained from the pixels of the island-shaped semiconductors P11, P21, and P31, the green (G) signal current is obtained from the pixels of the island-shaped semiconductors P12, P22, and P32, and the red (R) signal current is obtained from the pixels of the island-shaped semiconductors P13, P23, and P33.
In the configuration illustrated in FIG. 7B, spaces are required between the island-shaped semiconductors P11 to P33 in order to ensure a mask alignment margin in manufacturing, which is necessary to form a mask so as to surround the color filters B1, B2, B3, R1, R2, R3, G1, G2, and G3 and the island-shaped semiconductors P11 to P33. These spaces limit an increase in the density of the pixels. In this solid-state imaging device of the related art, furthermore, as in the solid-state imaging device illustrated in FIG. 6, light absorption in the color filters B1, B2, B3, R1, R2, R3, G1, G2, and G3 prevents an increase in sensitivity.
FIG. 7C illustrates a cross-sectional structural diagram taken along the line C-C′ in FIG. 7B.
Referring to FIG. 7C, the signal line N+ regions 112a, 112b, and 112c are formed on a substrate 111a, and the island-shaped semiconductors P11, P12, and P13 are formed on the signal line N+ regions 112a, 112b, and 112c. Insulating layers 120a are formed on the substrate 111a between the island-shaped semiconductors P11, P12, and P13, and the conductive layer 115a is formed on outer peripheries of P regions 113a, 113b, and 113c adjoining the signal line N+ regions 112a, 112b, and 112c of the island-shaped semiconductor P11, P12, and P13 with insulating layers 114a, 114b, and 114c disposed between the conductive layer 115a and the P regions 113a, 113b, and 113c. The conductive layer 115a is formed so as to connect the island-shaped semiconductors P11, P12, and P13 to one another, and N regions 116a, 116b, and 116c of photodiodes are formed on the outer peripheries of the island-shaped semiconductor P11, P12, and P13 above upper ends of the conductive layer 115a, which is located inside the island-shaped semiconductor P11, P12, and P13. Insulating layers 120b are formed on or over the conductive layer 115a and the insulating layers 120a between the island-shaped semiconductors P11, P12, and P13, and P+ regions 117a, 117b, and 117c are formed on top layers of upper ends of the island-shaped semiconductors P11, P12, and P13. The pixel selection line conductive layer 118a is formed on the insulating layers 120b so as to adjoin the P+ regions 117a, 117b, and 117c. An insulating layer 120c is formed on or over the insulating layers 120b, the pixel selection line conductive layer 118a, and the P+ regions 117a, 117b, and 117c. The top surface of the insulating layer 120c is planarized, and the color filter B1 for blue (B), the color filter G1 for green (G), and the color filter R1 for red (R) are formed on the insulating layer 120c. An overcoat insulating layer 120d is formed on the color filters B1, G1, and R1 and the insulating layer 120c. The color filters B1, G1, and R1 are formed using a manufacturing method similar to that for the solid-state imaging device illustrated in FIG. 6, unlike the micromachining technology used for the pixel structure of the island-shaped semiconductors P11, P12, and P13. Thus, there are problems in increasing the density of pixels and reducing cost.
Hereinafter, another solid-state imaging device of the related art which is capable of color imaging without using color filters will be described with reference to FIGS. 8A to 8D.
FIG. 8A illustrates a cross-sectional structural diagram of this solid-state imaging device (see, for example, U.S. Patent Application Publication No. 2012/104478).
Referring to FIG. 8A, an N region (N well) 122 is formed in a P-region substrate 121, and a P region (P well) 123 is formed in the N region 122. Here, an N region 124 is formed in the P region 123. A diode formed of the P-region substrate 121 and the N region 122, a diode formed of the N region 122 and the P region 123, and a diode formed of the P region 123 and the N region 124 are reversely biased.
Here, the depth of the N region 124 from the top surface of the P-region substrate 121 is desirably approximately 0.2 μm, the depth of the P region 123 from the top surface of the P-region substrate 121 is desirably approximately 0.6 jam, and the depth of the N region 122 from the top surface of the P-region substrate 121 is desirably approximately 2 μm.
Of the incident light incident on the top surface of the P-region substrate 121, mainly blue (B) wavelength light undergoes photoelectric conversion in a diode region 126a (in FIG. 8A, a region surrounded by a dotted line) that is formed of the P region 123 and the N region 124, and generated signal charges are accumulated in the diode region 126a. Mainly green (G) wavelength light undergoes photoelectric conversion in a diode region 126b (in FIG. 8A, a region surrounded by a dotted line) that is formed of the P region 123 and the N region 122, and generated signal charges are accumulated in the diode region 126b. Further, mainly red (R) wavelength light undergoes photoelectric conversion in a diode region 126c (in FIG. 8A, a region surrounded by a dotted line) that is formed of the P-region substrate 121 and the N region 122, and generated signal charges are accumulated in the diode region 126b.
Then, the signal charges accumulated in the diode region 126a are read as a blue (B) signal using an ammeter 125a, and the signal charges accumulated in the diode region 126a are read as a green (G) signal using an ammeter 125b, and the signal charges accumulated in the diode region 126c are read as a red (R) signal using an ammeter 125c.
The solid-state imaging device illustrated in FIG. 8A is capable of color imaging without using color filters because it utilizes the light absorption characteristics of the semiconductors (made of silicon (Si) in this case) illustrated in FIG. 8B.
As illustrated in FIG. 8B, a large proportion of the blue (B) wavelength light (λ=400 nm) is absorbed in the vicinity of the Si (silicon) surface, and light having a larger wavelength (λ) such as green (G) wavelength light (λ=550 nm) and red (R) wavelength light (λ=700 nm) penetrates further inside the Si (silicon), and is absorbed. Accordingly, mainly a blue (B) signal is obtained in the diode region 126a, mainly a green (G) signal is obtained in the diode region 126b, and mainly a red (R) signal is obtained in the diode region 126c.
FIG. 8C illustrates the light wavelength (λ) dependence of the outputs obtained from the ammeters 125a, 125b, and 125c.
As illustrated in FIG. 8C, the blue (B) signal output VB obtained from the ammeter 125a mainly has the blue (B) wavelength light output component, the green (G) signal output VG obtained from the ammeter 125b mainly has the green (G) wavelength light output component, and the red (R) signal output VR obtained from the ammeter 125c mainly has the red (R) wavelength light output component. A signal computation process such as white balance is performed on the signal outputs VB, VG, and VR to obtain desired RGB signals.
FIG. 8D illustrates a plan view of the cross-sectional structure illustrated in FIG. 8A, when viewed from above the P-region substrate 121, and also illustrates output circuits.
As illustrated in FIG. 8D, the N region (N well) 122 is formed in the P-region substrate 121, and the P region (P well) 123 is formed in the N region 122. The N region 124 is formed in the P region 123. A contact hole 127a, a contact hole 127b, and a contact hole 127c are formed in the N region 124, the P region 123, and the N region 122, which are on the same surface as the top surface of the P-region substrate 121, respectively.
The N region 124 and an output circuit 129a (in FIG. 8D, a region surrounded by a dotted line) are connected via the contact hole 127a and a lead 128a connecting with the contact hole 127a. The P region 123 and an output circuit 129b (in FIG. 8D, a region surrounded by a dotted line) are connected via the contact hole 127b and a lead 128b connecting with the contact hole 127b. The N region 122 and an output circuit 129c (in FIG. 8D, a region surrounded by a dotted line) are connected via the contact hole 127c and a lead 128c connecting with the contact hole 127c.
Each of the output circuits 129a, 129b, and 129c is constituted by an amplifier MOS transistor Am configured to sense the voltage of the corresponding one of the N region 124, the P region 123, and the N region 122, a row selection MOS transistor RS, and a reset MOS transistor Re for discharging the signal charges accumulated in the corresponding one of the diode regions 126a, 126b, and 126c. A blue (B) signal is read from a signal line 130a for blue (B), a green (G) signal is read from a signal line 130b for green (G), and a red (R) signal is read from a signal line 130c for red (R). The output circuits 129a, 129b, and 129c are formed on a surface of the P-region substrate 121 outside the N region 122.
The solid-state imaging device illustrated in FIGS. 8A and 8D has features in that, compared to the solid-state imaging device illustrated in FIG. 6, the solid-state imaging device is capable of color imaging without using color filters and the diode regions 126a, 126b, and 126c where photoelectric conversion is performed on RGB wavelength light overlap one another in the depth direction.
In this solid-state imaging device, however, since the N region 124 that receives blue (B) wavelength light, which is required to have the largest light-receiving area, is formed inside the P region 123 and the N region 122, a large pixel size is used to obtain desired blue (B) wavelength light sensitivity. There is another problem in that the solid-state imaging device is not capable of obtaining signals of white (W) wavelength light including all of blue (B) wavelength light, green (G) wavelength light, and red (R) wavelength light.
In the solid-state imaging device illustrated in FIG. 6, a new pixel having none of the color filters 106B, 106G, and 106R is formed separately from the pixels having the color filters 106B, 106G, and 106R, and a white (W) wavelength light signal is obtained from the pixel, thereby achieving a high sensitivity or a wide dynamic range (see, for example, H. Honda, Y. Iida, Y. Egawa, H. Seki; "A Color CMOS Imager with 4×4 White-RGB Color Filter Array for Increased Low-Illumination Signal-to-Noise Ratio", III Transaction on Electron Devices, Vol. 56, No. 11, pp. 2398-2402 (2009); and Y. Egawa, N. Tanaka, N. Kawai, H. Seki, A. Nakano, H. Honda, Y. Iida, M. Monoi: "A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range", ISSCC 2008, Digest of Technical Papers, pp. 52-53 (2008)).
This technology utilizes the ability of white (W) pixels to read larger signal current than RGB pixels, thereby obtaining a high SN ratio (signal/noise ratio). The solid-state imaging device illustrated in FIG. 8A, in contrast, is not capable of directly reading the signal current of white (W) wavelength light.
In the solid-state imaging devices of the related art illustrated in FIGS. 6 and 7C, the pixel structure formed below the color filters 106B, 106G, 106R, B1, G1, and R1 is formed using advanced CMOS micromachining technology.
However, the CMOS micromachining technology is not available for the formation of the color filters 106B, 106G, 106R, B1, G1, and R1. The color filters 106B, 106G, 106R, B 1, G1, and R1 are formed using photolithography technology that utilizes a different photoresist material.
Therefore, the micromachining dimensions of the color filters 106B, 106G, 106R, B1, G1, and R1 are greater (larger) than the micromachining dimensions which are realized by the advanced CMOS micromachining technology. The micromachining technology for the color filters 106B, 106G, 106R, B1, G1, and R1 thus limits a further increase in the pixel density of CMOS solid-state imaging devices.
In addition, the process and apparatus for forming the color filters 106B, 106G, 106R, B1, G1, and R1 are different from the process and apparatus used in advanced CMOS micromachining technology, which may cause an increase in cost. This imposes a problem of reduction in the cost of solid-state imaging devices.
Additionally, in the solid-state imaging devices of the related art illustrated in FIGS. 6 and 7C, the material of the R, G, and B color filters 106R, 106G, 106B, B1, G1, and R1 causes light absorption, which thus prevents the color filters 106R and R1 from achieving a light transmittance of 100% in the red (R) wavelength region. Similarly to this, the color filters 106G and G1 and the color filters 106B and B1 for blue (B) are also prevented from achieving a light transmittance of 100% in the green (G) wavelength region and the blue (B) wavelength region, respectively. In this manner, light absorption which prevents improvements in the light transmittance of the color filters 106R, 106G, 106B, B 1, G1, and R1 hinders the sensitivity of CMOS color solid-state imaging devices from increasing.
In the solid-state imaging device of the related art illustrated in FIG. 8A, furthermore, the diode regions 126a, 126b, and 126c where photoelectric conversion is performed on RGB wavelength light are formed so as to overlap one another in the depth direction, and the N region 124 that receives blue (B) wavelength light, which is required to have the largest light-receiving area, is formed inside the P region 123 and the N region 122. Thus, a large pixel size is used to obtain desired blue (B) wavelength light sensitivity. There is another difficulty in that the solid-state imaging device is not capable of directly obtaining signals of white (W) wavelength light including all of blue (B) wavelength light, green (G) wavelength light, and red (R) wavelength light, and it is difficult to achieve a high sensitivity and a wide dynamic range utilizing white (W) wavelength light signals.

Unisantis Electronics Singapore Pte. Ltd.


The present invention provides a composition containing a single-stranded nucleic acid molecule consisting of a nucleotide sequence shown by 5′-AGCAGAGUACACACAGCAUAUACC-P-GGUAUAUGCUGUGUGUACUCUGCUUC-P-G-3′ (SEQ ID NO: 1)

Pulmonary fibrosis is a disease in which fibrosis occurs in the stroma of the lung triggered by injury and collapse of pulmonary alveoli. In many cases, the cause is unknown. When the cause cannot be found, the pulmonary fibrosis is particularly termed idiopathic pulmonary fibrosis (IPF). As fibrosis progresses, the lungs harden and the oxygen exchange capacity decreases. At present, there is no definitive treatment method, and its treatment method is almost symptomatic therapy.
TGF-β is known as a cytokine that regulates cell proliferation and differentiation and is considered to also play an important role in liver or lung fibrillization. Thus, it is attracting attention as a treatment target of pulmonary fibrosis.
Nucleic acid medicine is expected as a next-generation drug discovery technology because it has both easy manufacturability of low molecular pharmaceutical products, and effectiveness and safety of antibody drugs. However, the development of the pharmaceutical products is not progressing as expected due to the barriers of instability of nucleic acid molecules in the body, side effects due to enhanced innate immune response, absence of development of efficient drug delivery system (DDS) and the like.
In the case of respiratory diseases, pulmonary fibrosis is an effective target disease of nucleic acid medicine, since topical administration of drugs to the lung is possible. To deal with the problems of nucleic acid molecule such as stability in the body and induction of innate immune response, a single-stranded nucleic acid molecule in which the terminals of a double-stranded nucleic acid of siRNA or miRNA are linked by various linkers has been developed (e.g., patent documents 1-5). Hamasaki et al. reported that symptoms were remarkably improved by intratracheal administration of a single-stranded nucleic acid molecule having the following structure carrying a TGF-β1 expression-inhibitory sequence (hereinafter to be also referred to as "PK-0051") to model mice of pulmonary fibrosis and acute lung injury (non-patent document 1).
(SEQ ID NO: 1)5′-AGCAGAGUACACACAGCAUAUACC (SEQ ID NO: 2)-P-GGUAUAUGCUGUGUGUACUCUGCUUC-P-G-3′(Underline shows a TGF-β1 expression inhibitory sequence. P is a proline derivative linker represented by the following formula (I)).

Composition stably containing single-stranded nucleic acid molecule that suppresses expression of TGF-β1 gene

Abstract: (in the sequence, P is a proline derivative linker represented by (I) in the DESCRIPTION) and a buffer, and having the following features:

Abstract: (a) being in the form of a solution at ambient temperature; and    (b) a content of the nucleic acid molecule after storage at 25° C., relative humidity 60% for 4 weeks, of not less than 80% relative to the content at the time of start of the storage.


Sensing apparatus includes a transparent window and a LiDAR assembly, including a beam source, which is configured to emit one or more beams of optical radiation along a beam axis, and which is configured to scan the one or more beams over an angular range about the beam axis. A diffractive structure is mounted approximately parallel to the transparent window and positioned to intercept the one or more beams emitted by the LiDAR assembly and turn the beam axis to pass through the transparent window at an angle greater than 30° relative to a normal to a surface of the transparent window.

Time-of-flight (ToF) imaging techniques are used in many LiDAR systems (also referred to as depth mapping, 3D mapping or 3D imaging systems). In direct ToF techniques, a light source, such as a pulsed laser, directs pulses of optical radiation toward the scene that is to be mapped, and a high-speed detector senses the time of arrival of the radiation reflected from the scene. The depth value at each pixel in the depth map is derived from the difference between the emission time of the outgoing pulse and the arrival time of the reflected radiation from the corresponding point in the scene, which is referred to as the "time of flight" of the optical pulses. The radiation pulses that are reflected back and received by the detector are also referred to as "echoes."

Compact optical packaging of LiDAR systems using diffractive structures behind angled interfaces


Custom traffic tagging on a control plane backend is disclosed. Information associated with a video session is obtained. Based at least in part on at least some of the obtained information associated with the video session, additional metadata to associate with the video session is determined. The additional metadata is determined from metadata obtained from one or more disparate sources. The video session is associated with the determined additional metadata.

Users are increasingly using networks such as the Internet to access content, such as video files and live streaming/video on demand content, via client machines. As demand for such content increases, there are challenges in distributing that content efficiently and with high quality. As one example, existing techniques are limited in the information that they are able to obtain about video playback.

This patent is subject to a terminal disclaimer.

Custom traffic tagging on the control plane backend


A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.

Persistent data storage is an integral and one of the most critical parts of modern Information Technology (IT) infrastructure. Various applications generate and process vast amounts of data to provide meaningful services to the end users. Many such applications are mission critical and need very fast and reliable access to the data. In addition to low latency, reliability, high performance, and high availability, storage devices such as Solid State Drives (SSDs) need to provide low power and low cost solutions.
Another aspect of the storage is security, which often times needs data encryption, compression, and other similar functions. These functions may have very demanding requirements and create complexities in SSDs. Most of that complexity is often concentrated in SSD Controller System-on-a-Chip (SoC) devices. Various data processing modules and engines must work efficiently and collaboratively in the SSD Controller SoC to achieve above goals. Having the host machine perform these application functions can impact the performance of the host machine and increase its resource requirements.
A need remains to improve host machine performance and resource utilization while still performing the functions requested by an application.

Efficient data movement method for in storage computation


A laser device includes a pump source, a ring resonator, a gain medium disposed in the ring resonator, and a holographic output coupler to partially transmit the laser radiation. The gain medium is configured to receive radiation from the pump source and generate laser radiation.

Passive Q-switching allows narrowing of the linewidth of a laser oscillator and can in principle provide the generation of single-frequency pulses. Typically, single-frequency laser pulses are generated using a passively Q-switched standing-wave cavity having a relatively short length. For example, solid state Nd-lasers passively Q-switched using saturable semiconductor structures can generate single-frequency laser pulses as short as ˜40 ps. Also Nd-lasers can be passively Q-switched by Cr4+-doped materials (such as Cr4+:YAG) or color center materials (such as LiF:F2− crystals); however, the laser pulsewidth in this case can be much longer-ranging from ˜1 s to ˜10 s of ns. For generation of single-frequency pulses, it is advantageous to have a short laser cavity so that the longitudinal mode spacing is maximized and the number of longitudinal modes matching the spectral gain curve of the laser active medium is minimized. Short length of the laser cavity facilitates the generation of short laser pulses. However, the time-bandwidth relationship dictates that the laser bandwidth increases as the laser pulses are shortened. This makes short, single-frequency laser pulses undesirable for various applications where the signal of interest has a small frequency shift, e.g., coherent LIDAR applications, or the laser source is used to excite various subjects with extremely narrow spectral lines, e.g., CO2 detection. The linewidth requirements can be satisfied for a pulsed laser by increasing the laser pulsewidth to hundreds of ns (while maintaining the single longitudinal mode operation), which decreases its transform-limited spectral linewidth.
FIG. 1A shows a prior art Q-switched oscillator using a standing-wave resonator. A pump source 90 provides pump light 100, which enters the resonator through a dichroic mirror 101, which is highly transmissive at the pump wavelength and highly reflective at the laser wavelength. The pump laser is incident on the gain medium/laser element 103 and is fully or partially absorbed in the laser element. The laser emission 105 escapes through the output coupler 102, which is a partial reflector at the laser wavelength. To achieve a pulsed regime of operation a Q-switch element 104 can be inserted in the cavity. Such Q-switching elements can be passive (e.g., a saturable absorber) or active (e.g., an electro-optic or acousto-optic Q-switch). The output coupler 102 can be a mirror, a surface grating, or a thick holographic (volume) grating.
Standing wave resonators typically produce short laser pulses (40 ps to ˜80 ns). An inherent disadvantage of a standing wave resonator is spatial hole-burning, which can lead to generation of other longitudinal modes. To overcome the limitations of the standing-wave oscillator, one can consider a ring resonator design that can eliminate spatial hole-burning and increase the laser pulsewidth due to the fact that the laser beam passes only one time through the gain medium per roundtrip.
FIG. 1B shows a prior art ring resonator. Typically, ring resonators are based on a 4-mirror design with two dichroic concave mirrors 101 and two flat mirrors 102, 106. One of two flat mirrors serves as an output coupler 102. An "optical diode" provides unidirectional operation. An optical diode can include a non-reciprocal Faraday rotator and a reciprocal rotator (such as half-wave plate).
To achieve laser operation at a specific wavelength and decrease the laser linewidth, a narrow-bandwidth element can be incorporated into the cavity. For example, a surface grating or an intracavity etalon (or a pair of etalons) can be used. However, intracavity etalons are extremely temperature and angle-alignment sensitive elements and make the design of wavelength-stable oscillators difficult. Surface gratings have relatively low laser damage threshold and require intra-cavity beam expansion to increase spectral resolution.
It, therefore, would be advantageous to develop a ring resonator that can utilize a thick Bragg grating (TBG) as a narrow-bandwidth reflector.

Ring resonator with a holographic reflector


A convertible chair includes a base frame, a seat connected to the base frame through first, second, and third legs, a back support connected to the seat via first and second support arms, and at least one hinge assembly interconnecting the chair components. A user can pivot the back support between an upright chair position and a lowered table position wherein an upper surface of the seat and a back side surface of the back support form an essentially planar table surface. At least one locking mechanism can be utilized to selectively lock the back support in the upright position. Additionally, the chair can be folded into an essentially flat storage position. A table leaf is also provided to fit between two adjacent convertible chairs in the table position, to produce an extended table configuration.

1. Field of the Invention
The present invention pertains to the art of furniture, and more particularly, to a convertible folding chair.
2. Discussion of the Prior Art
There is an increasing desire in the marketplace for furniture that can meet multiple needs of a user, including the need to make the most of smaller living spaces. In general, different types of folding chairs are well known, including folding chairs that can be folded into an essentially flat storage position. However, there remains a need for furniture that is both attractive and adaptable to different uses within a small environment.


This invention relates to a measuring device, which includes a body. A digital display is located in the body, the digital display being configured to show at least a linear measurement. The measuring device also includes a holding portion coupled to the body and configured to slidably engage an elongate member, such as a catheter or introducer sheath, in a space provided between the holding portion and the body. The measuring device also includes a sensor or transducer located in the body and configured to measure at least a linear distance traveled by the elongate member, such that the linear measurement is associated with the linear distance.

The present invention relates to medical treatment devices. In particular, the present invention relates to measuring the distance traveled of a catheter, introducer sheath or other devices. The present invention also concerns related processes, such as measuring the energy of a treatment device, which may include a laser for vein ablation in treating varicose veins, among other things.
Varicose veins exist because valves contained in the walls of the veins fail, allowing blood to stagnate, causing noticeable purple or red traces of the vein visible from the outside of the skin. During a normal vein ablation procedure for varicose veins, a practitioner first identifies a vein or veins for the procedure. The veins are then mapped as a guide for the practitioner in order for him to perform the procedure. Once the veins are mapped, the practitioner prepares the vein for ablation by introducing a sheath into the distal end of the vein, in preparation for introduction of a treatment device, such as a laser or radio frequency device.
The treatment device is introduced into the vein at the distal end and extended in the vein to a junction with a healthy branch of a larger vein to ensure that the entire damaged vein is treated. In a laser treatment procedure, a fiber-optic member is covered by a sheath for introduction and for the treatment procedure. As fiber-optic members are usually very slender fibers of glass, it is not desirable to introduce the fiber-optic member without a covering because the fiber can break off in the patient, or can puncture the vein walls, damaging surrounding tissues.
Thus the fiber-optic member is introduced in a sheath or catheter and advanced to the beginning of the treatment area. The practitioner can determine the location of the tip of the fiber-optic member in the patient by ultrasound imaging, transillumination of the anatomy using an aiming or targeting beam, by feel, and/or by estimating the location based on a calculated position inside of the vein targeted for treatment. Once the fiber-optic member reaches the beginning of the treatment area, the practitioner exposes a portion of the fiber-optic member by extending the fiber-optic member out of the end of the sheath, exposing about 2 cm of fiber, uncovered by the sheath at the treatment end. The laser is then activated and transmits energy through the fiber, thereby heating the tissue and fluid around the end of the treatment fiber, effectively destroying the vein and preventing further filling of the vein with stagnant blood. The ablation procedure removes the appearance of the varicose vein, alleviates the pain caused by the varicose vein and prevents further complications.
In performing the ablation procedure, the practitioner must withdraw the fiber and sheath together at a rate such that neither too much nor too little energy is applied along the vein. To aid the practitioner in determining the withdrawal rate and distance the treatment sheath and fiber remain to be withdrawn, previous treatment sheaths included marks on the sheath body at periodic intervals. By counting the marks, a practitioner could determine how far the sheath had been withdrawn and by subtracting the amount withdrawn from the original inserted length of the sheath, the practitioner could then determine the length of the portion of the sheath remaining inside the patient.
Additionally, in a traditional ablation procedure, a practitioner needs to monitor the energy expended by the laser to ensure sufficient treatment of the target veins. One way to see where the end of the treatment catheter is located inside of the patient is by seeing light through the patient's skin before or during the laser treatment of the target area. Light in the visible spectrum, which may be a targeting light, may be used. Thus, practitioners often dim the lights, allowing better viewing of the monitors and of the treatment location in the patient. A practitioner may also know that an area has been over-treated by patient discomfort and pain.
Thus, in a traditional ablation procedure, a practitioner needs to identify and count markings on the catheter in very low light, simultaneously monitoring the energy output, rate of treatment, location of treatment, and patient comfort.
Some previous efforts to aid the practitioner in managing all of the requirements of the procedure include, for example, a device and method disclosed in U.S. Patent Publication No. US 2006/0217692. In the disclosed device, a system monitors the withdrawal rate and automatically adjusts the energy level of the treatment laser. However, many practitioners do not like the automatic adjustment because the practitioner is consequently limited in her ability to adjust the treatment levels for different or difficult treatment regions. This loss of control forces the practitioner to constantly monitor, second-guess, override, and adjust the machine.
Thus what is needed is a device that aids the practitioner in providing information in an easy-to read and determine format, while still allowing the practitioner control over the procedure.

Measuring and testing device for retractable medical devices


A key-value store supporting GET, PUT and DELETE operations, serializes multiple clients using two locks, and that supports asynchronous resizing. The locking scheme includes an operation of holding two locks, one for the key involved in the operation, one for the page currently searched or updated. The store can either be a single volume holding keys and data or can be organized as a directory volume referencing a number of data volumes organized by data-size ranges. The scheme also supports asynchronous resizing of the directory while continuing to perform operations.

In a typical cloud-based data center, a large collection of interconnected servers provides computing and/or storage capacity for execution of various applications. For example, a data center may comprise a facility that hosts applications and services for subscribers, i.e., customers of the data center. The data center may, for example, host all of the infrastructure equipment, such as compute nodes, networking and storage systems, power systems, and environmental control systems.
Storage and retrieval of data may consume a considerable amount of the computational resources of the servers of the data center. For example, storage and retrieval of pictures, authentication credentials, documents, and other types of data may consume computational resources of the servers of the data center.

Data processing unit with key value store


A boundary detector includes a candidate line detecting unit that detects a candidate line of a lane boundary position drawn on the road surface based on image information from a camera. The detector also includes a lane boundary position selecting unit that selects the lane boundary position based on the candidate line; an additional lane boundary position selecting unit that selects a lane boundary position of an additional lane that is added to a main lane based on the candidate line; and an additional processing unit that stops adopting the lane boundary position for a predetermined time period when the additional lane boundary position selecting unit selects a lane boundary position of the additional lane.

1. Field of the Invention
The present invention relates to a boundary detector and a boundary detecting method that acquire image information based on an image supplied from a camera that is mounted on a vehicle and picks up an image of a road surface, and detect a boundary drawn on the road surface based on the acquired image information.
2. Description of the Related Art
In recent years, an apparatus has been developed for picking up an image of a road surface in front of a vehicle with a camera, detecting a boundary, i.e., a white line, drawn on the road surface based on the image picked up by the camera, and automatically driving the vehicle on a lane delineated by the white line. For the realization of automatic driving, the lane must be properly detected, in other words, a detector is required for processing the image picked up by the camera to detect the lane, i.e., the white lines. Such detectors are disclosed in Japanese Patent Applications Laid-Open Nos. H08-320997, and 2001-014595, for example.
A vehicle lane detector disclosed in Japanese Patent Application Laid-Open No. H08-320997, measures a maximum value of edge point counts of an edge component that represents a straight line component, based on image information on the right and the left sides of the vehicle and immediately in front of the vehicle. The vehicle lane detector, based on the measured maximum value, recognizes that the image belongs to a dotted lane marker when the maximum value changes periodically, and that the image belongs to a solid lane marker when the maximum value remains constant. Thus, the vehicle lane detector recognizes the lane of the vehicle based on the results of recognition of the right and the left lane markers.
Another vehicle lane detector disclosed in Japanese Patent Application Laid-Open No. 2001-014595, detects white line candidate points through processing of an image captured by a video camera attached to a front part of a vehicle. The vehicle lane detector selects only the white line candidate points that are determined to be a part of a white line among all the white line candidate points, to calculate a detection ratio, and determines a type of the white line based on the detection ratio.
On a bypass highway, for example, a plurality of main lanes is provided together with additional lanes such as a lane for right turn or a lane for left turn to allow a vehicle to turn right or left at an intersection ahead of the vehicle. With the lanes for right turn and left turn, an overall road width widens and white lines that mark the lanes are drawn so as to bend from the white line of the main lane to outward. When there is a right turn lane added to the main lane on which a vehicle runs, for example, a white line detector may mistakenly detects the white line of the right turn lane as the white line of the main lane. The white line detector is required to correctly determine whether the detected white line belongs to the main lane or to the right turn lane. Above described two patent applications do not particularly disclose techniques to prevent such inconvenience and therefore are not immune to detection error of the white lines delineating the lanes.


A systems management subsystem provides resources for managing components and allows components to be manageable. In particular, state information about managed components is encapsulated into objects that are visible in the global name space. The state of a single component may be partitioned into subcomponents that are stored in separate objects. These objects may, in turn, be encapsulated into a single container object that is associated with the managed component. By placing the state information in the global name space, local processes and remote processes may both gain access to internal state information and properly manage the component.

The present invention relates generally to data processing systems and, more particularly, to the integration of system management services with an underlying system object model.
In order for system management functions to properly perform their intended roles, the functions must be able to monitor the internal state of components that they manage. Conventional systems have not had access to the internal state of managed components. As a result, it has often been difficult for conventional systems to properly manage the components. Certain conventional systems have attempted to increase access to information concerning managed components by adding a separate framework and access technique for the internal state information. Such conventional systems, however, have not made the internal state information generally available through standard user-visible system interfaces and human interfaces.
In accordance with a first aspect of the present invention, a method is practiced in a distributed system having at least one memory device and processors for running processes. In this method, the internal state of a managed component is represented as an object in one of the memory devices. The object is visible to the processes on the processors. The object is then accessed on behalf of one of the processes to obtain the internal state of the managed component.
The managed component may be partitioned into a single subcomponent or into multiple subcomponents. Each of the subcomponents has an internal state. Furthermore, the method may include the additional step of encapsulating the object into a container object for the component. The container object is stored in one of the memory devices and is visible to processes run on the processor. The method is adaptable to use with multiple components to be managed. A system management object may be stored in the memory devices. The system management object manages the managed component.
In accordance with another aspect of the present invention, a distributed system includes memory devices and processors for running processes. The distributed system also includes a component to be managed that has an internal state. The distributed system includes a means for storing the internal state of the component in the memory device as an object. The distributed system further includes a means for making the object accessible by the processes run on the processors.
In accordance with yet another aspect of the present invention, a method is practiced on a distributed system having a remote procedure call facility, a first data processing system and a second data processing system. The first data processing system includes a processor running a process. The second data processing system includes a component having a state and a memory device. In this method, an object is stored in the memory device of the second data processing system. The object holds the state of the component. The process running on the processor of the first data processing system requests access to the state of the component that is held in the object. In response to the request, a remote procedure call is performed using the remote procedure call facility to gain access by the process to the information about the state of the component held in the object.
In accordance with a still further aspect of the present invention, a method is practiced in a distributed system having storage devices for storing objects having names, processors running programs having states and an operating system. The operating system includes a name service which provides a global name space for the names of objects stored in the storage devices. In this method, a variable is declared in a program to be a variable whose value is available in the global name space. The program is run on one of the processors so that the variable is assigned a value, and the value is stored in the object that is visible in the global name space. The variable may be a counter that is incremented in predetermined quantities, a meter whose value varies over a predetermined range or any other variable that holds state information about the program.
In accordance with an additional aspect of the present invention, a method is practiced in a distributed system having data processing resources and at least one memory device. In this method, the data processing resources, which may include hardware components and/or software components, are modeled as objects with names. The named objects are stored in the memory device. System management objects having names are also stored in the memory device. The system management objects are used to manage the data processing resources.

Integration of systems management services with an underlying system object model


In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to enhancing heat dissipation in semiconductor devices by providing a back side metallization.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs (central processing units), GPUs (graphical processing units) and the like. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
As the number of circuit elements, such as transistors and the like, per unit area increases in the device level of sophisticated semiconductor devices, the number of electrical connections associated with the circuit elements in the device level also has to be increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines providing the inner level electrical connections and vias providing intra level connections are formed on the basis of very conductive metals, such as aluminum, copper and the like, in combination with appropriate dielectric materials to reduce the parasitic RC (resistance capacitance) time constants. Generally, in semiconductor devices requiring a complex contact regime for connecting the metallization system with the device periphery, i.e., with a package substrate and the like, frequently, a bump structure is provided as the very last layer of the metallization system in which contact bumps, such as solder bumps or any other type of metal elements, such as pillars and the like, are provided in the passivation material of the semiconductor chip in order to act as contact areas for connecting to complementary contact elements of a package substrate and the like. For instance, solder material may be provided on at least one of the contact elements of the semiconductor chip and the substrate package, which may be subsequently re-flowed after mechanically contacting these two components. In this manner, an electrical and mechanical contact may be established between the semiconductor chip and the carrier substrate with high electrical performance due to a reduced contact resistance and a reduced parasitic capacitance. In this contact technology, the entire available chip area may be used for positioning individual bumps or metal elements without being restricted to the periphery chip area, as may be the case in well-established wire bonding techniques. Due to the increasing complexity of sophisticated semiconductor devices, typically, the input/output (I/O) capabilities and thus the number of bumps or metal elements in the bump structure also has to be increased, wherein, however, the requirement for an increased packing density in the device level and in the metallization system may also result in an increased packing density of metal elements in the bump structure. For example, in semiconductor devices including circuit elements including critical dimensions of 30 nm and less, a typical pitch between neighboring bumps may be approximately 180 μm with the prospect of pitches of 165-130 μm in further advanced device generations.
As previously explained, the high packing density typically in the device level, i.e., in the semiconductor material of the semiconductor device, typically results in an increased power consumption, as, for instance, the static and dynamic power consumption of very sophisticated transistor elements may increase, for instance due to a reduced thickness of gate dielectrics and the like, while, in other cases, in addition to the increased power consumption of individual transistors, the increased packing density may finally result in an increased power consumption per unit area, which in turn leads to the generation of an increased amount of waste heat. One path of dissipating heat from the semiconductor level to the periphery is heat conductivity via the metallization system and the bump structure into the substrate carrier, which in turn may be coupled to any appropriate heat sink arrangement. Due to the increased number of metallization levels in the metallization system of very complex semiconductor devices and due to the fact that increasingly dielectric materials of reduced dielectric constant are used in the metallization systems, the thermal resistance of the metallization system including the bump structure may no longer be compatible with the heat dissipation capabilities required in sophisticated applications. For this reason, frequently, the substrate back side of semiconductor devices may also be used as an efficient heat dissipation path, which may be connected to the periphery, for instance a package and the like, by an appropriate thermal interfacial material that thermally connects the substrate back side to the package substrate. For example, indium is frequently used as a thermal interfacial material due to its superior heat conductivity. In other cases, gallium, silver, copper and the like may also be efficiently used as a thermal interfacial material. Due to the material characteristics, such as diffusion behavior, adhesion with specific materials such as silicon and the like, the thermal interfacial material may typically not be directly formed on the substrate back side, such as a silicon surface, but may require additional material layers in order to obtain the desired thermal, mechanical or chemical behavior of the coupling between the substrate back side and a package. For this purpose, an adhesion layer is formed on the surface of the substrate in order to provide adhesion of the following materials to the semiconductor material of the substrate. For instance, aluminum, aluminum alloys, titanium, titanium nitride, tantalum, tantalum nitride, tantalum silicide are materials frequently used as an adhesion material. Thereafter, a barrier material, such as titanium, tantalum, tantalum nitride, tantalum silicide, nickel, chromium and the like, is provided in order to prevent the diffusion of indium, i.e., of the thermal interfacial material, into the material of the substrate, such as silicon and the like. In addition to these material layers, one or more layers are also provided to act as an adhesion layer appropriately attaching the thermal interfacial material to the back side metallization stack and thus to the semiconductor substrate. For this purpose, materials consisting of gold, gold alloys, platinum, gold/platinum alloys, copper, silver and the like may be used. Consequently, a moderately complex metallization layer stack is to be formed on the back side of the semiconductor substrate, in which a plurality of different materials have to be deposited, at least some of which may typically have a negative effect on the semiconductor devices and process techniques so that, in view of the prevention of any cross-contamination, the back side metallization layer stack is typically provided in a very advanced manufacturing stage, i.e., the back side metallization layer stack is formed at one of the last process steps in a semiconductor facility. It turns out, however, that the back side metallization stack may result in significant yield loss during the further processing of the semiconductor devices, in particular when a reduced pitch of a bump structure is required, as will be explained with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. As previously discussed, the substrate 101 may act as a carrier for forming therein and thereon circuit elements, such as field effect transistors, capacitors, resistors and the like, as are required for providing a complex integrated circuit. For example, the substrate 101 comprises a semiconductor layer 110, which may also be referred to as a device level, in and above which are provided a plurality of circuit elements (not shown) which may generate a significant amount of heat, as indicated by 110A. As discussed above, the packing density and the configuration of individual circuit elements may have a significant influence on the heat generation in the device level 110. For example, in sophisticated applications, transistor elements, such as field effect transistors, having a short channel in combination with a very thin gate dielectric material may exhibit an increased static power consumption, for instance due to leakage currents through a very thin gate dielectric material. Moreover, in digital circuits, the operating frequency is typically selected at several hundred MHz up to several GHz, thereby also contributing to significant dynamic losses in the form of high transient currents so that a very efficient heat dissipation is required in order to meet the specifications of sophisticated semiconductor devices. Moreover, the device 100 comprises a metallization system 120, which is to be understood as a plurality of individual metallization layers (not shown) that provide the network of electrical connections between the individual circuit elements in the device level 110. It should be appreciated that circuit elements may also be provided in the metallization system 120 and in the substrate 101 below the device level 110, for instance in the form of capacitors and the like, depending on the overall complexity and configuration of the device 100. For convenience, any such circuit elements are not shown in FIG. 1.
Furthermore, a bump structure 130 is provided on and above the metallization system 120 and represents a plurality of bumps 132, at least many of which are electrically connected to the metallization system 120, thereby providing the I/O capabilities of the device 100 for communication with the periphery, for instance in the form of a package substrate and the like. The bump structure 130 may comprise any appropriate dielectric material 131 for passivating the device 100, while the bumps 132, which may also be provided in the form of metal pillars and the like, are comprised of any appropriate metal material, such as solder material and the like. As previously explained, a pitch between neighboring bumps 132 may be 180 μm for sophisticated semiconductor devices and may have to be significantly reduced in even more complex semiconductor devices.
Moreover, at a back side 101B of the substrate 101, a metallization layer stack 140 is formed in order to allow the attachment of an appropriate thermal interfacial material, such as indium, in a later manufacturing stage. The layer stack 140 comprises an adhesion layer 141, such as an aluminum layer or a layer comprised of one of the materials mentioned above, with an appropriate thickness of, for instance, approximately 100 nm. The adhesion layer 141 is to provide desired high adhesion of the subsequent materials of the layer stack 140 and of the indium material to be provided in a further advanced manufacturing stage. Furthermore, a barrier layer 142, such as a titanium layer, having a thickness of approximately 100 nm is formed on the adhesion layer 141. Furthermore, a further metal-containing material, for instance in the form of nickel vanadium (NiV) 143, is formed on the barrier material 142 with any appropriate thickness, such as approximately 350 nm. Finally, the layer stack 140 comprises a further metal layer 144, such as a gold layer, which may be considered as an adhesion layer for ensuring a desired high degree of adhesion with respect to the thermal interfacial material, such as indium, to be formed on the layer 144 at a later stage. The layer 144 may be provided with a thickness of approximately 100 nm.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following processes. The semiconductor layer 110 may be appropriately processed in order to form circuit elements therein and thereabove, for instance by providing isolation structures (not shown) to divide the semiconductor layer 110 into appropriate semiconductor regions. Thereafter, the circuit elements in the form of transistors, resistors, capacitors and the like are formed in and above the semiconductor regions and above isolation structures, depending on the overall configuration of the device 100. As indicated above, in sophisticated devices, critical dimensions in the device level 110 may be 50 nm and significantly less. Thereafter, the circuit elements are embedded in a dielectric material (not shown), in which appropriate contact elements are provided to connect the circuit elements with the metallization system 120. Next, the metallization system 120 may be formed by providing a plurality of metallization layers, each of which may include an appropriate dielectric material in combination with metal features, such as metal lines and vias, in accordance with the circuit layout of the device 100. Finally, the bump structure 130 is formed by depositing the dielectric material 131 and patterning the same in order to form appropriate openings for receiving the bumps 132. The bumps 132 may be formed by providing any appropriate "underbump metallization system" (not shown) and depositing any appropriate conductive material, for instance by electrochemical deposition techniques, and finally removing any non-desired excess material.
During the entire process flow, well-established process techniques are used wherein the back side 101B of the substrate 101 may be exposed to various process environments, for instance by handling the device 100, which may typically be accomplished by contacting the substrate 101 at an edge region and/or on the back side 101B, by positioning the substrate 101 on substrate holders of process tools by exposing at least a portion of the back side 101B to the deposition atmosphere of many deposition processes and the like. Consequently, the back side 101B may at least be partially modified with respect to its chemical and mechanical characteristics during the entire process flow for forming the semiconductor device 100 as shown in FIG. 1. Furthermore, in a very advanced manufacturing stage, for instance after forming the bump structure 130, the back side metallization stack 140 is formed in order to avoid the contamination of other device areas of the device 100 and/or the contamination of process tools and the like. For example, a plurality of metal species may result in significant modification of device characteristics when diffusing into sensitive device areas. During the formation of the layer stack 140, typically, the device 100 is positioned in an appropriate process tool for establishing a sputter deposition ambient in order to form the aluminum layer 141 on the back side 101B. For this purpose, any appropriate process chamber, for instance of a cluster tool and the like, may be used in combination with an appropriate target material provided therein by establishing appropriate deposition conditions, such as plasma power for ionizing a carrier gas and to sputter off target atoms from the target material by directing ionized particles to the sputter material. The atoms and/or ions that are released from the target material upon the particle bombardment may then deposit on the surface 101B. Thereafter, the device 100 is positioned in a further sputter deposition chamber in which the titanium material of the layer 142 is deposited on the layer 141. Similarly, the material layer 143 may be provided by sputter deposition in a further sputter deposition chamber having an appropriate target material provided therein. Finally, the gold layer 144 may be formed by sputter deposition in a further sputter deposition chamber on the basis of appropriate process parameters. Consequently, in the example shown in FIG. 1, four sputter deposition tools or process chambers are used for providing the metallization stack 140. During the further processing of the device 100, the substrate 101 is to be separated into individual semiconductor chips, which is accomplished by appropriately dicing the substrate 101, as indicated by 102. During the process 102, the materials of the back side layer stack 140 are also separated, which may result in additional metal-containing contaminating particles 102A, which may also deposit on the bump structure 130. Consequently, these contaminants 102A stemming from the layer stack 140 may cause leakage paths in the bump structure 130 and may even result in a shorting of neighboring bumps 132. Consequently, significant yield loss may be generated in a very advanced manufacturing stage due to the presence of the back side metallization layer stack 140. Furthermore, as previously discussed, upon further reducing the pitch between adjacent bumps 132, the probability of causing yield loss in the bump structure 130 may even further increase. On the other hand, the layer stack 140 may be required for enabling the provision of a thermal interfacial material to be formed on the stack 140 so as to thermally couple the device level 110 to a package substrate when the heat dissipation via the metallization system 120 is not sufficient for meeting the thermal specifications of the device 100. Due to the increased probability of creating contamination during the patterning of the stack 140 during the process 102, it has also been proposed to remove the material of the stack 140 within scribe lanes of the device 100, thereby substantially avoiding the release of any contaminating particles, such as the particles 102A during the process 102. For this purpose, however, additional complex patterning strategies, such as lithography and etch processes, are required in a very advanced manufacturing stage thereby significantly contributing to increased production costs for sophisticated semiconductor devices.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which a back side metallization layer stack may be provided while avoiding or at least reducing one or more of the problems identified above.

Back side metallization with superior adhesion in high-performance semiconductor devices


A new hybrid miniature rose for garden decorating. The plant is of a dwarf, bushy, upright growth habit suitable for growing outdoor and may be distinguished from other presently available rose cultivars by the following combination of characteristics: abundant production of flowers, pointed buds, two-toned lavender coloration, and above average disease resistance and vigor, especially when compared to other lavender Miniatures.

This invention relates to a new and distinct variety of hybrid miniature rose. The plant is of a dwarf, bushy, upright growth habit suitable for growing outdoor and may be cultivated for garden decoration. It was bred by Thomas F. Carruth in Canoga Park, Calif., and has as its seed parent, the rose known as "Shocking Blue" (U.S. Plant Pat. No. 3,846) and as its pollen parent, the rose known as "Helen Boehm". The varietal denomination of the new variety is "Weklips".

Hybrid miniature rose plant named "Weklips"