An apparatus comprises a refueling system for a number of fuel tanks, a primary valve, and a secondary valve. The refueling system has branches capable of distributing fuel into the number of fuel tanks. The primary valve is associated with a primary branch in the branches. The primary valve and the secondary valve are independently controlled to change a distribution of the fuel through the branches into the number of fuel tanks.

1. Field
The present disclosure relates generally to aircraft and, in particular, to a method and apparatus for refueling aircraft. Still more particularly, the present disclosure relates to a method and apparatus for controlling the refueling of aircraft and increasing the rate at which refueling may be accomplished.
2. Background
Commercial aircraft and military aircraft may be refueled in between flights on ground, while at airport terminals, and/or at other locations within an airport or airfield. These aircraft are refueled by a fuel delivery system such as, for example, without limitation, an airport hydrant system, a tanker truck, and/or some other type of fuel delivery system. In addition, aircraft are also refueled in flight by aerial refueling tankers. These fuel delivery systems send fuel into fuel tanks in an aircraft through an aircraft refueling system. An aircraft refueling system includes a refueling manifold that distributes fuel to the fuel tanks. The refueling manifold is typically located within the wing structure of an aircraft. In some cases, the refueling manifold may extend to fuel tanks located within the fuselage and/or in the tail of the aircraft. The refueling manifold may have a number of branches that extend from the refueling manifold to a number of individual fuel tanks.
The aircraft fuel tanks may also include a fuel vent system, also referred to as a vent system. This vent system regulates pressure within the fuel tanks. During overfill conditions, fuel, gas, and/or vapors may pass through the fuel vent system to an overfill tank and/or overboard from the aircraft. The overfill tank is a tank where fuel overfill may flow before exiting an aircraft.
Currently, refueling of larger commercial and/or military aircraft can take longer intervals of time than desired. For example, a large air transport aircraft can hold up to around 50,000 gallons of fuel to around 60,000 gallons of fuel. Refueling of this aircraft can take over around an hour at lower refueling pressures even at several hundreds of gallons per minute.
Longer refueling times may cause aircraft to occupy airport terminals for longer durations. Longer refueling times may also cause longer turnaround times of aircraft and increased delays at airports. Further, longer turnaround times and increased delays may increase airport congestion. This airport congestion can increase carbon emissions at an airport and decrease airport safety.
Further, with aerial refueling, longer refueling times lead to longer intervals of time of physical contact between a receiver aircraft and a refueling boom on an aerial refueling tanker. The longer intervals of time of physical contact between the aerial refueling tanker and the receiver aircraft may increase the risk to both aircraft.
Factors that influence refueling times include refueling quantity, refueling rates, and the amount of fuel remaining from a previous flight or in reserve. The upper limits of aircraft refueling rates may depend on protection of the limits of tank bottom pressure during an overfill condition. Protection of the limits of tank bottom pressure, in turn, is dependent on the venting capacity of the vent system to flow fuel. The upper limits of aircraft refueling rates may also depend on the limiting of flow velocities of fuel entering the refueling tanks. For example, limiting flow velocities may limit or prevent electrostatic charge.
Tank bottom pressure is the pressure that is present at the bottom of a fuel tank in the aircraft. The tank bottom pressure limit is the structural limit selected for the fuel tank or wing structure of an aircraft to avoid undesired changes to the structure of the fuel tank or elsewhere in the wing. The tank bottom pressure is highest during an overfill condition due to fuel static head pressure and back pressure. The back pressure is due to fuel flow losses through the vent system as fuel flows to an overfill tank and/or overboard. Tank bottom pressure limits are protected by limiting the refueling rate for each fuel tank to a rate that can flow through the vent system and overboard without producing an undesired increase in back pressure in the tank.
Therefore, it would be advantageous to have a method and apparatus for refueling an aircraft that takes into account one or more of the issues discussed above, as well as possibly other issues.


A timer device comprising a first timer in communication with control means, the control means being in communication with an external component and the first timer sending an order to the control means after a first preset time period is counted by the first timer, the timer device also comprising a second timer in communication with the control means, the second timer counting a second preset time period that is a portion of the first preset time period. The timer device permits an accurate operation, even with changes of temperature and voltage, and with a reduced cost.

The timer devices based on microprocessors or microcontrollers are used to control a huge number of electronic and electromechanical devices in a wide range of environmental and temperature conditions, using different power supply methods, from a very stable power supply until batteries.
The main problem to solve for the development of low cost battery powered devices, including fragrance, soap and insecticide dispensers with a timer device comprising one control unit is the consumption control.
A typical method used is to place a control unit in sleeping mode when it is not used, and periodically in an awakening mode in order to allow it to check for some scheduled activities.
The sleep mode reduces the activity of the control unit and its related consumptions near zero. This awakening mode can be accomplished using a particular timer present inside the control unit, and if it is not cleared before it expires, resets the control unit.
However, in these timer devices there are two problems that reduce the timing precision: the voltage and temperature variations affect the accuracy of the internal timers of the control unit, with a consequently variation of the timing generated by them, and the timer usually used is less accurate than other timers.
Since the timing generation is one of the keys of any control system, the accuracy used to accomplish them is essential for a correct operation of the timer device.
Alternative solutions, useful for low cost devices and able to produce an adequately timing require a circuitry external to the control unit. This circuitry increases the cost and complexity of the device, and reduces the number of the available ports on the control unit, normally reduced in the low cost control units.
Therefore, it is evident the need of a timer device and method that permits an accurate operation, even with changes of temperature and voltage and with a reduced cost.

Timer device and method for operating said timer device


A pageable query can be generated based on an event-processing query. The pageable query is a form of the event-processing query that supports swapping the event-processing query into and out of memory. For instance, page-in and page-out triggers can be inserted. After detection of a page-in trigger, the event-processing query can be loaded into the memory, and after detection of a page-out trigger, the event-processing query can be unloaded from memory.

Event-processing systems continuously process events in real time as they are received. Events are data items that include a payload of data and an associated time. Event processing operates with respect to asynchronous event sequences or event streams, which are sequences of events that happen over time. Examples of event sequences include stock ticks identifying changes in price of a stock and social media messages. Processing is specified over an event sequence with a query to enable projection, filtering, and aggregation, for instance. Unlike traditional database queries, event-processing queries are not evaluated once over stored data. Rather, event-processing queries are evaluated continuously over events as the events occur. To enable substantially real time processing, event-processing systems store queries in memory and evaluate the queries as events arrive in the system.


A rear tire assembly for mounting an oversize tire to a motorcycle includes an intermediate pulley assembly mounted on a swing arm and driven by a drive of the transmission. The intermediate pulley assembly includes first and second intermediate pulleys rotating in concert about a common shaft. The second pulley is spaced apart from the first intermediate pulley to align with the driven pulley and accommodate the oversized tire.

This invention is an assembly and for mounting an oversized rear wheel along the centerline of a motorcycle.
Typically, motorcycles are equipped with standard sized front and rear wheels of the same width. Motorcycle owners enjoy spending time on the care and maintenance of their motorcycle and often seek to make their motorcycle unique by adding custom features. A popular custom feature is the installation of an oversized rear wheel. An oversized rear wheel highlights the appearance of power sought by many owners of larger motorcycles. Installation of an oversized tire adds to the aesthetic appearance of the motorcycle, and provides practical benefits. One practical benefit is the improvement in ride obtained by the increased width of the oversized tire. Further, an oversized tire improves the handling, maneuverability, and traction of the motorcycle.
Installation of an oversized tire presents certain design challenges, the main challenge being installation of the oversized wheel within the original frame members. A further challenge is presented in routing power from the transmission to the oversized rear tire. As appreciated, a rear tire with an increased width will no longer align with the drive pulley or sprocket from the drive transmission. Prior art assemblies have attempted to account for this misalignment by moving the rear tire to one side and the engine and transmission to the opposite side to provide additional room required to account for the increased width of the oversized tire. Such modifications purposely mis-align the front and rear wheels in an effort to accommodate the oversized rear tire, thereby creating a less stable ride. Further, movement of the engine and transmission changes the center of gravity of the motorcycle from that of the factory design to further increase the instability of the motorcycle.
Another means of accounting for the larger tire is to provide a sprocket or drive pulley spaced outwardly from the transmission to align with the oversized rear tire. Such a solution can practically accommodate only slightly oversized tires. Further, increasing the distance of the drive pulley from the transmission creates a safety hazard in that the drive belt or chain is positioned at a point closer to a rider""s leg.
For these reasons it is desirable to produce an assembly that provides for proper alignment of the front and rear tires, can accommodate any width oversize tire and does not create safety hazards for riders.
The assembly of this invention is a rear tire assembly for mounting an oversized tire including an intermediate pulley assembly driven by a drive of the transmission including first and second intermediate pulleys rotating in concert about a common shaft. The second pulley is spaced apart from the first intermediate pulley to accommodate extra width of the oversized tire.
The swing arm of this assembly includes extension arms spaced apart to accommodate the oversized tire along with the driven pulley. The swing arm includes a drive plate for mounting the intermediate pulley assembly and an idler pulley. The single drive belt is replaced by short and long drive belts or chain links. The short drive belt transmits torque from the transmission of the motorcycle to the first intermediate pulley. The first and second intermediate pulleys are connected such that rotation of the first intermediate pulley rotates the second intermediate pulley. The second intermediate pulley is spaced apart from the first intermediate pulley to align the long drive belt with the driven pulley on the oversized pulley. The intermediate pulley assembly pivots with the swing arm and the idler pulley maintains tension on the short drive belt during such pivoting.
Accordingly, the assembly of this invention provides proper alignment between front and rear tires, and can accommodate any width oversize tire while providing improved ride and performance.

Oversize wheel assembly for a motorcycle


An armrest includes a gear assembly with a crown gear directly coupled to the armrest that imparts rotational motion to the armrest, a planetary gear engaged with the crown gear, and a pinion gear coupled to the crown gear that imparts vertical motion of the entire gear assembly, and the armrest, along a rack.

Vehicles are often provided with a variety of comfort settings and features that improve a ride experience for users or occupants. However, execution of deployment and stowing operations for various features often remain simplistic and utilitarian. Accordingly, additional executions of the operations for various features are needed to provide the users and occupants with the best possible experience.


A circuit for maximizing dynamic range in a digital to analog signal path comprises an input for receiving an input signal, a first gain stage coupled to the input having a first gain setting, an second gain stage coupled to the first gain stage, the second gain stage having an second gain setting, a controller configured to selectively increase the first gain setting and decrease the second gain setting according to the input signal level and an output coupled to the second gain stage for transmitting an output signal. A method for maximizing dynamic range in a digital to analog signal path comprises detecting a digital input signal level, detecting a desired user gain level, applying a first gain to the digital input signal, converting the digital input signal into an analog signal, and applying a second gain to the analog signal, wherein the first and second gain are selectively and inversely manipulated according to the digital input signal while maintaining a desired user gain level.

Dynamic Range is an important metric in an integrated circuit or a system having a digital to analog signal path. One example of such a circuit or system is a digital audio playback device, such as an mp3 player, CD player, or mobile phone. Such playback devices have means, described below, for transforming digitally stored or transmitted data into a usable analog signal. Dynamic range (DR) is the ratio between the smallest and largest possible values of a changeable quantity, such as audio signal amplitude. DR is typically measured as a ratio, such as a base-10 (decibel) or base-2 (doublings, bits or stops) logarithmic value. In most electrical systems, including digital audio playback, the decibel measure is standard. For example, the 16-bit compact disc has a theoretical dynamic range of about 96 dB. Digital audio with 20-bit digitization is capable of approximately 120 dB DR; similarly, 24-bit digital audio calculates to approximately 144 dB DR. In audio playback systems, it is common practice to measure DR as total harmonic distortion plus noise (THD+N) relative to full scale with a −60 dB input signal. Furthermore, the approximate theoretical maximum DR values are sometimes calculated relative to a full Nyquist frequency bandwidth measurement. In some measurement techniques, measured bandwidths are reduced from the Nyquist rate to an audible bandwidth resulting in an increase in the reported dynamic range value. Also, the frequency spectrum of the measured output can be altered using industry accepted filters that may alter the DR value. For example, some measurement techniques filter an output through an A-weighted filter that approximates the perceptive response of the human ear.
Conventionally, digital audio recording and playback chains include input and output converters and associated analog circuitry, which may result in significantly limiting practical DR below the theoretical optimum. Observed 16-bit digital audio DR can be noticeably lower, even 90 dB or below, when multiple circuits in the audio path individually contribute integrated noise at the −96 dB level. A DR measurement is a useful indication of signal quality when the desired signal level is low. In an audio example, soft music or low volume music can suffer from the effects of poor DR more than loud music.
FIG. 1 shows such a prior art digital to analog signal path 100 that may have limited DR performance. Digital input data 110 is coupled to a digital gain block 120. Digital input data 110 can be a digital transmission received by an antenna, stored digital data in a memory, or any other digital input source. It is important to note that the digital source need not be limited to audio data, but can be any type of quantized or digital information. In practice, the digital input data 110 is modeled as a combination of the digital input data 110 and the inherent quantization noise 112 due to the quantized nature of the signal. In FIG. 1, the quantization noise 112 is shown summed with the digital input data 110 but it is important to note that no physical summer 115 exists. Rather, the summer 115 merely represents the addition of unavoidable quantization noise 112. The digital gain 120 controls the gain of the overall signal while it is still in a digital state. Typical signal sources for providing digital input data 110 can be via a de-serialized Inter-IC Sound (I2S) bus, SPDIF de-framed signal source, or time domain recovered signal from a compressed MP3 formatted source. The source data is typically interpolated to improve the transient signal quality. The digital gain 120 controls the gain of the overall signal while it is still in a digital state, typically through manipulation using a common digital multiplier. Excessive digital gain can cause overflow in the digital code, which would typically be clip limited, and will undesirably degrade large amplitude signals.
The gained or attenuated digital signal from digital gain block 120 is then passed to a digital to analog (DAC) 130 for conversion to an analog signal. Every DAC effectively injects additional noise into the signal, which can be input referred or output referred depending on convenience and convention. In FIG. 1, DAC input referred noise 122 is shown summed with the output of the digital gain 120. Again, no physical summer 125 exists but rather serves to represent that noise is being injected into the signal path. The output of the DAC 130 is coupled with a driver and analog gain 140, which also has some input referred noise 132. The summer 135 merely represents that even more noise is being injected into the system. It is important to note that not all prior art includes both a digital gain 120 and analog gain control 140. Some systems may include simply one or the other, or neither. It is further important to note that the signal path 100 is highly simplified, and many other components as required by specific applications can be placed along the signal path 100. For example, analog mixers are often placed between the DAC 130 and the driver and analog gain 140, and each additional component will necessarily add noise to the system. The overall gain of the signal path is controlled by a gain control 150, which may control both the digital gain 120 and the analog gain 140. The gain control 150 is controlled in turn by a user control 152. An important distinction should be made between the user of the integrated circuit and the user of an end product. The user of the integrated circuit in which this signal path can be found (for example, an audio codec or processor) is most likely a manufacturer of audio appliances, such as Apple® in making their widely popular iPod®, or any other conceivable manufacturer. Such a user designs a system in which an end user, or the user of the iPod®, for example, is able to manipulate volume as desired. In general, the manufacturer's system enables the end user to manipulate one or both of the gains with a single control input. Generally, an end user cannot manipulate the digital gain 120 and the driver and analog gain 140 separately, because end users prefer a single gain control for simplicity and convenience. When an end user manipulates the volume control on their audio device, the gain control 150 as designed by the manufacturer simply adds gain in the digital realm with the digital gain 120 and/or the analog realm with the audio gain 140. However, such a system does nothing to improve dynamic range, especially in low level signals. In the prior art solutions the noise contributions of the multiple modules in the signal path require better noise performance from each of the modules. However, greater quality and lower noise modules require greater die size and more current. Die size is the greatest component of cost in an integrated circuit, and increased current is undesirable to manufacturers of portable electronics who are concerned with battery life. Furthermore, the integrated circuit industry as a whole is extremely cost driven, and increased cost associated with larger die sizes is undesirable.

Circuit and method for optimizing dynamic range in a digital to analog signal path


In a color mode, the image quality improving liquid is set to the same rate of 20% for all input signal values. Meanwhile, in a monochrome mode, the image quality improving liquid is set to a rate of 30% in the highlight region, and the ink rate gradually decreases starting from the intermediate tones and proceeding towards the high-density region. Thus, the optimal printing method and usage rate for image quality improving liquid can be adjusted in accordance with the image quality characteristics of the color mode and the monochrome mode. As a result, it is possible to reduce color change in specular light while maintaining at least a certain level of image clarity in both modes, and thus favorably print both color images and monochrome images.

1. Field of the Invention
The present invention relates to an image processing apparatus, an inkjet printing apparatus and printing method, and more particularly, to technology that uses an image quality improving liquid, which substantially does not include color material, to suppress bronzing and interference color in a printed image, while improving glossiness and color reproduction.
2. Description of the Related Art
A technology that overcoats a print medium with yellow ink, as described in Japanese Patent Publication No. 4066338, is known as a technology that suppresses this type of bronzing. More specifically, after printing an image onto a print medium using cyan, magenta, and yellow ink, yellow ink, which produces little bronzing, is applied on the printed image with a print duty of 10% or less. This enables a reduction of bronzing for cyan hues in particular.
However, in some cases, the method disclosed in Japanese Patent Publication No. 4066338 is difficult to implement for images that use colors of many hues. More specifically, using yellow ink may cause problems that impair image quality due to changes in tint, such as lowering the saturation of certain hues and disrupting the gray balance. Also, with the method disclosed in Japanese Patent Publication No. 4066338, the phenomenon of color change in reflected light produced by thin-film interference (hereinafter also designated interference color) is not resolved.
A known technology for resolving the such problems involves printing by using ink containing ordinary color material together with clear ink which substantially does not contain color material and to which a water soluble resin that dissolve in ink is added, or ink called image quality improving liquid. This provides a certain effect of suppressing bronzing and interference color.
However, simply using such image quality improving liquid may be insufficient to improve printed image quality in some cases. First, there is room for improvement in the image quality improving liquid itself. More specifically, although the amount of the water soluble resin contained in image quality improving liquid that remains at the surface of the print medium without permeating through does control bronzing and interference color, on the other hand, the amount of image quality improving liquid also affects the glossiness and image clarity of the image. Therefore, if the amount of image quality improving liquid remaining on the print medium surface could be controlled according to the properties of the image quality improving liquid itself, it would be possible to control not only bronzing and interference color, but also glossiness and image clarity. Second, the effects of using image quality improving liquid on a print medium may differ depending on whether an inkjet printing apparatus is executing a color mode or a monochrome mode, for example. For example, in the case of applying the image quality improving liquid to the print medium during the same scan as colored ink, more irregularities are formed on the surface of the print medium compared to the case of applying the image quality improving liquid after printing an image with colored ink, and these irregularities appear themselves as differences in glossiness, image clarity, and interference color. In addition, differences in the amount of image quality improving liquid used (the amount applied per unit area) appear themselves as differences in the above bronzing.

Image processing apparatus, inkjet printing apparatus, and inkjet printing method


A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second.

In the formation of a semiconductor wafer, integrated circuit devices such as transistors are first formed at the surface of a semiconductor substrate. Interconnect structures are then formed over the integrated circuit devices. Metal bumps are formed on the surface of the semiconductor chip, so that the integrated circuit devices can be accessed.
In conventional metal bump formation processes, under-bump metallurgy (UBM) layers are first formed. The UBM layers include a titanium layer and a copper seed layer over the titanium layer. Metal bumps are then formed on UBM layers by plating. Undesired portions of UBM layers are then removed by wet etching. Conventionally, the copper seed layer was removed using ammonical (AM) etching, in which alkaline etchants including Cu(NH3)4Cl2, Cu(NH3)2Cl, NH3, and NH4Cl are used. The resulting chemicals including CuO are then cleaned using NH3 and water. The exposed portions of the titanium layer are then etched using an HF solution with a high concentration of 11 percent. It was observed that undercuts were formed under the metal bumps due to the lateral etching of the titanium layer, and the undercuts may extend under the metal bumps by as much as about 10 μm. As a result, the metal bumps may delaminate from the respective metal pads, resulting in a low yield in the metal bump formation process.

Method for reducing UBM undercut in metal bump structures

Taiwan Semiconductor Manufacturing Company, Ltd.


A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Computer systems may have a number of layers of software, and there may be several processors in one system that are linked together by these layers. Further, a computer system may be made of a number of other computer systems linked together over a network, or a computer system may be one processor with a number of layers.
Thus, computer systems utilize layering of software. Generally, a layer of software will be responsible for handling a limited set of events or provide a certain level of abstraction. A layer of software is a set of instructions that are executed on a processor. A layer may control the hardware components of a system and provide higher level functionality to another layer, and a layer may handle networking functions at the lowest level. An example of such a layer is firmware. Firmware can be designed to interface with a certain type of processor.
Layers are arranged hierarchically in computer systems with one layer on top of another. Lower level layers are layers, such as firmware, that provide lower levels of abstraction. Higher level layers are layers, such as operating systems that provide higher level of abstraction. For example, a lower level layer may have to signal the read head on a hard drive and specify which platter to read data from to access data, whereas a higher level of software may just send a command to read a file to a lower level layer to access data.
Firmware is one type of lower layer in processor systems. Firmware refers to processor routines that are stored in non-volatile memory structures such as read only memories (ROMs), flash memories, and the like. These memory structures preserve the code stored in them even when power is shut off. One of the principle uses of firmware is to provide the routines that control a computer system when it is powered up from a shut down state, before volatile memory structures have been tested and configured. The process by which a computer is brought to its operating state from a powered down or powered off state is referred to as bootstrapping. Firmware routines may also be used to reinitialize or reconfigure the computer system following various hardware event and to handle certain platform events like system interrupts.
Firmware is typically written in assembly language. This is a low level computer language that provides direct access to processor hardware and is closely tied to the processor architecture. The processor architecture is reflected in the rest of the platform, in part because of the assembly level firmware that is used to initialize, configure, and service platform level resources. For example, platform resources may transfer data through specified registers and/or memory locations defined by the Instruction Set Architecture (ISA), and platform level interrupts may be handled by referring to specified processor registers. Thus, initialization and configuration of platform level resources are tied to the ISA of the underlying processor.
Operating systems (OS) are another layer of software. Operating systems are a higher layer than firmware. Operating systems interact with firmware to provide an environment in which applications can be run. Some examples of operating systems are DOS, Microsoft Windows, Microsoft Windows NT and Unix. By utilizing firmware, OS can be designed to run on many different processing systems without re-writing the OS for each variation in platforms. As an example, Microsoft Windows NT can run on single processor systems and some dual processor systems without recompiling or rewriting the OS. Operating systems can be designed to run on a variety of architectures. An Intel Architecture 64 bit operating system (IA-64 OS) is an operating system written using IA-64 code that runs all IA-64 applications (both IA-64 and IA-32 code). Two flavors of IA-64 OS are possible: one is a 32-bit IA-64 OS that uses 32 bits for its pointer variables and 64-bit IA-64 OS that uses 64 bits for its pointer variables. Such OS as have been described, allow applications to be written without regard for the underlying architecture.
By using layers of software, upper layers such as the OS and user applications in a multiprocessor system can interact with lower layers such as firmware as if the system is a single processor system. Layering permits software to be developed for a system without regard to the hardware making up the system, including the number of processors in that system.
In computer systems, different layers are responsible for detecting and handling different errors. Some layers may detect the error and tell a higher or lower layer of the error. Other layers may detect the error and handle the error.
In single processor systems, all layers are executing on the same processor. If an error occurs, that processor handles the error by executing the appropriate error handling hardware or routines. The error handling components or routines are part of the firmware or operating system.
In multiprocessor systems, sublayers or components of the firmware and operating system are executing on different processors. If an error is encountered by one processor, the other processors may continue executing without knowledge of the error. The error may be such that continued execution by the other processors propagates the error and causes further damage such as corrupted data. In a multiprocessor system, an error is more difficult to handle because the layers may not be able to communicate effectively. Furthermore, each processor may be executing separate firmware or firmware sublayers. Thus, an error in one processor may be detected by the firmware it is executing and the rest of the processors continue operating without knowledge of the error. This may cause the error to propagate and cause further errors in the system such as corrupting data.
Multiprocessor systems may have to reboot or shutdown for errors because of a lack of proper error handling. These errors may be handled in single processor based systems without shutting down.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a microprocessor system which allows the use of multiple processors and appropriately handles system hardware and software errors.

Error correction apparatus, systems, and methods


The device for opening and emptying filled food cans comprises a conveyor path. Food cans are gripped in the conveyor path using semi-cylindrical clamping elements. In addition the cans are clamped on the end walls. Placed in the conveyor path is a knife for cutting through the can. Using the clamping elements on the end walls the can halves are turned over and emptied. The can halves are subsequently ejected into a reservoir.

The contents of food cans dented for instance by a fall are no longer suitable for human consumption because the protective inner foil for example is damaged. Equally unsuitable for human consumption are the contents of food cans wherein a determined period of time, for instance one or two years, has passed since the filling date.
Up to the present, such cans have been placed in the environment in filled state, usually with the domestic refuse at a dump-site. For environmental reasons resulting from the presence of metal, this is no longer permitted. Such food cans no longer fit for use were also destroyed in incinerators. However, the processing price has recently increased very sharply.

Device for opening and emptying filled food cans


A method for an electroplating cell which includes providing an anode chamber with at least two concentric anodes including an inner anode and an outer anode; generating a computer generated model with a simulation computer program; and selecting at least one current ratio from the computer generated model, with the computer generated model having a plurality of current ratios from which the at least one current ratio is selected and the one current ratio being a ratio of an inner electrical current to an outer electrical current. The method further includes applying the inner electrical current to the inner anode and the outer electrical current to the outer anode and adjusting the inner and outer electrical currents to incorporate the one current ratio. The generating of the computer generated model with the simulation computer program includes using a first iterative loop to determine a potential field in the anode chamber.

1. Field of the Invention
The present invention relates to the field of electroplating, and in particular to electroplating equipment.
2. Description of Related Art
The manufacture of semiconductor devices often requires the formation of electrical conductors (interconnects) on semiconductor wafers. Such interconnects may be formed by electroplating (depositing) an electrically conductive material, such as copper, onto the wafer.
The adoption of increasingly thin copper seed layers in the current wafer processing technologies leads to increasing challenges in obtaining uniform film profiles with copper (Cu) electroplating, due to increasing electrical resistance of the underlying seed layer. As the seed layer becomes thinner due to technology demands, increasing wafer resistance leads to stronger "terminal effects" (center-thin, edge-thick profile) and the film less uniform, which leads to unacceptable film profiles for subsequent processing. Hardware changes to reduce terminal effects for thin films (thicknesses of approximately 0.5 microns) often leads to worse uniformity for thick films (thicknesses approximately greater than 1 micron). More specifically, these thick films have problems with "edge roll-offs" (center-thick, edge-thin). Systematic empirical hardware optimizations to generate acceptable film profiles are prohibitively expensive in cost and time. Moreover, different types of wafers also lead to different film profiles.
Referring to FIG. 1, a cross-sectional view of a cylindrically-shaped electroplating cell of the prior art is shown, with the cross-sectional view being taken from the center axis to the outer periphery of the cell. The cell includes a plating cup with two concentric, annular or ring-like anodes 1a and 1b and an anode separator 2 which separates the two anodes. An anode chamber wall 3 defines an anode chamber for containing a plating solution. The anode chamber wall 3 includes an anode membrane outer support ring 4a and a porous anode membrane 4b attached thereto, with the anode membrane 4b traversing the anode chamber. A porous diffuser membrane 5a is affixed to the diffuser support ring 5b and traverses the anode chamber. A wafer holder 6, holding a wafer 7a, is mounted above the anode chamber wall 3. The surface of the plating solution in the anode chamber is in contact with a lower surface 7b of the wafer 7a, which forms a cathode. The lower surface 7b touches or is wetted by the plating solution during the plating process. The plating solution is provided to the anode chamber by way of a solution inlet nozzle 8 positioned on the center axis of the electroplating cell.

Apparatus having plating solution container with current applying anodes


A method for reducing time in performing an imaging function by an imaging device. The method includes receiving at least one media sheet against an image capture window of the imaging device, detecting whether a lid for covering the image capture window is closed, capturing an image of the at least one media sheet in the image capture window in response to detecting a closed lid, receiving a start signal indicative of a user request to start an image capture operation after capturing the image, and sending a final image based upon the captured image to a destination.

1. Field of the Invention
The present invention relates generally to imaging and, more particularly, to an imaging device utilizing a method for reducing time spent in performing an imaging function.
2. Description of the Related Art
Scanning is a standard imaging device feature that converts a document into digital form. Typically, scanning is utilized when performing functions that require capturing of images on media sheets. Such functions may include faxing, copying, and storing electronic copies on a computer. The imaging device may incorporate a flatbed scanner or a vertical scanner having an image capture unit utilizing a scan bar or a camera.
A user accessing the imaging device for a scan operation initially lifts a scan lid, places a document face down on an imaging window, closes the scan lid, and selects a desired function/option. The imaging device normally waits for a user to select a function before it proceeds with an image capture operation. This is typically the case as the imaging device first needs to determine the user defined options so as to properly generate an output that meets the user's approval. Only after the user presses a start button or image will the imaging device perform the selected function by first obtaining an image and then processing the image based on the options indicated by the user.
The scan operation takes time in generating image data as well as in performing image processing on the acquired image. In some practices, the scan time is reduced by capturing at one time a substantially entire image of the media sheet. This may be accomplished by utilizing, for example, a camera scan type imaging device. However, since so much data is quickly generated, image processing becomes a significant portion of the total scan time. As a result, the entire operation still takes a substantially long time to complete such that users are sometimes inconveniently required to wait. Various methods have been implemented to decrease the time required to complete such tasks by increasing hardware performance. However, such measures introduce additional cost to the product. Based upon the foregoing, there is a need to effectively reduce the completion time of an imaging function without the need to increase hardware performance or incur additional cost.

Method and system for performing an imaging function by an imaging device


In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies.

1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise strain-inducing semiconductor alloys and gate structures of increased capacitance including a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits is based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric in combination and the metal material. It is believed that the deterioration of the high-k metal gate is substantially caused by the incorporation of oxygen and a respective oxygen diffusion within the high-k dielectric material, wherein the oxygen diffusion may be fed by oxygen contained in the ambient that may come into contact with the high-k dielectric during the processing of the devices. Since, for instance, hafnium- and zirconium-based oxides grow very fast due to the high affinity to oxygen diffusion even at moderately high temperatures, a significant modification of the characteristics of the high-k dielectric material may be observed, for instance an increased layer thickness and thus a reduced dielectric constant, which may even further be pronounced at moderately high temperatures of approximately 950-1300° C., as may typically be used during activation treatments and the like.
In addition to a significant modification of the high-k dielectric material, the work function of the metal in the gate stack may be shifted towards the center of the band gap, thereby modifying the threshold voltage of respective transistors. Due to the high oxygen affinity of the high-k dielectric material and the exposure to wet chemical etch procedures and cleaning processes, usually, the gate stack is encapsulated after the patterning process in order to enhance stability of the high-k dielectric material and the respective metals in the gate stack. For this purpose, silicon nitride has proven to be a promising material due to its oxygen blocking characteristics. Hence, in typical conventional process flows, a silicon nitride liner with a thickness is the range of approximately 1-5 nm may be formed on exposed surface areas of the patterned high-k gate stack, wherein appropriate deposition techniques are used so as to not unduly affect device characteristics and/or the subsequent manufacturing steps. For example, well-established low pressure chemical vapor deposition (LPCVD) techniques may be applied for forming the silicon nitride liner.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain component in the channel region of the transistor elements, the charge carrier mobility and thus the overall conductivity of the channel may be enhanced. For a silicon material having a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, the creation of a tensile strain component in the current flow direction, may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain component in the current flow direction may increase hole mobility and thus provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past which may per se require a complex manufacturing sequence for implementing the various strain-inducing techniques. For example, one promising approach that is frequently applied is the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors. For this purpose, in an early manufacturing stage, cavities are formed selectively adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. Additionally, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose the gate electrode material to the etch ambient for forming the cavities and also providing an efficient growth mask during the selective epitaxial growth process, in which the silicon/germanium alloy may be grown on a crystalline substrate material, while a significant deposition of the alloy on dielectric surface areas may be suppressed by appropriately selecting the corresponding process parameters. After forming the strain-inducing silicon/germanium alloy, the corresponding spacer structure and a cap layer encapsulating the gate electrode of the P-channel transistor may be removed along with the spacer layer that covers the N-channel transistors. Thereafter, the further processing may be continued by forming drain and source regions so as to complete the basic transistor configuration.
A corresponding strain-inducing mechanism is a very efficient concept for improving transistor performance and thus a combination with sophisticated gate electrode structures on the basis of high-k dielectric materials and metal gate electrodes is highly desirable. However, it turns out that the combination of both complex process sequences may cause integrity issues with respect to the sensitive high-k dielectric material, since the corresponding protection liner may be unduly exposed to a reactive etch ambient, in particular when a reduced width of the offset spacer is to be used in order to enhance the strain-inducing effect of the silicon/germanium alloy.
That is, during the removal of the offset spacer element, which may frequently be combined with the removal of the cap layer and the corresponding spacer layer formed above the gate electrode structures of other transistor elements, material of the protection liner may also be removed, thereby possibly exposing corresponding sidewall portions of the sensitive high-k dielectric material and/or of the metal-containing electrode material, which may thus result in a significant variability of the finally obtained transistor characteristics, as previously discussed. Consequently, complex manufacturing sequences have been proposed so as to reduce the lateral offset of the silicon/germanium alloy on the basis of dedicated offset spacers, which have to be removed in a later stage in combination with the corresponding cap material without unduly compromising integrity of the protection liner, at least at the bottom of the gate electrode structures.
In view of the situation described above, the present disclosure relates to techniques and semiconductor devices in which a reduced lateral offset of a strain-inducing semiconductor alloy may be obtained in the context of sophisticated high-k metal gate structures while avoiding, or at least reducing, the effects of one or more of the problems identified above.

Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy


A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, a three-dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. A typical FinFET is fabricated with a thin "fin" (or fin structure) extending up from a substrate. The channel of the FET is formed in this vertical fin, and a gate is formed over (e.g., wrapping around) the channel region of the fin. While existing FinFET fabrication techniques have been generally adequate, they have not been entirely satisfactory in all aspects. Therefore, in order to continue to meet ever-increasing design requirements for FinFET devices at increased functional density and decreased geometric sizes, further advances are needed.

FinFET with dummy fins and methods of making the same

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


A clock signal generating circuit includes an oscillator portion that sustains a ramped oscillating clock signal in a memory storage device electrically connected to the oscillator portion, a switch portion that supplements electrical energy to the oscillator portion, and a cycle controller connected to the oscillator portion and the switch portion to supplement energy to the oscillator portion when a peak voltage or current level of the clock signal falls below a predetermined value.

The present invention generally relates to a clock signal generating circuit for a computing device, and more particularly, the present invention relates to a clock signal generating circuit for generating a ramped clock signal.
Conventional computing systems utilize a clock signal generating circuit to provide timing information to a plurality of flip-flops. The flip-flops store binary states, such as 1""s and 0""s contingent on the absence or presence of a voltage or charge in the flip-flop. The binary states, read or written in the flip-flops, are then used for combinational boolean logic for operation and calculation procedures in the computing system. When writing a logic state in the flip-flop by a device external to the flip flop is desired, an oscillating voltage or clock signal operates the flip-flop to cause a voltage value representative of the stored state to be stored to be written to the latching circuit in the flip-flop, latch the voltage value and hold it available for reading devices external to the flip-flop. The clock signal is commonly a square wave that drives a gate of a transistor of the flip-flop. The clock signal generating circuit, external to the flip-flops, generates the signal to effectuate read, write and timing processes in the computing device. The square or abrupt signal drives the gates of transistors in the flip-flop to turn them ON and OFF in a relatively quick manner.
While this structure effectively allows a computing system to effectuate reading of stored logic states contained within the flip-flops, drawback exists. Specifically, only a portion of a computing system""s flip-flops are actually read during any given read request. The remainder, however, still receive the clock signal. Commonly, the energy of the clock signal driving the unread flip-flops is dissipated therein, thereby creating energy inefficiencies and increased heat dissipation. When this dissipation effect is multiplied with the numerous flip-flops contained within a computing device, the overall efficiency of that computing device is compromised. The present invention was developed in light of these and other drawbacks.
A clock signal generating circuit includes an oscillator portion that sustains a ramped oscillating clock signal in a memory storage device electrically connected to the oscillator portion, a switch portion that supplements electrical energy to the oscillator portion, and a cycle controller connected to the oscillator portion and the switch portion to supplement energy to the oscillator portion when a peak voltage or current level of the clock signal falls below a predetermined value.
Other aspects of the invention will be apparent to those skilled in the art after reviewing the drawings and the detailed description below.

Method and apparatus for generating a clock signal having a driven oscillator circuit formed with energy storage characteristics of a memory storage device

The Regents of the University of Michigan


A method for improving a lifetime property and a charging rate of a lithium-sulfur secondary battery capable of both improving a lifetime property and a charging rate of the secondary battery by inducing a homogeneous reaction of the lithium-sulfur secondary battery by applying a charging rate differently for each section in a charging process of the lithium-sulfur secondary battery.

In secondary batteries of which application fields expand to electric vehicles, energy storage systems or the like, lithium-sulfur secondary batteries particularly have received attention as a next generation secondary battery technology with capability of obtaining relatively high energy storage density and the like. Such a lithium-sulfur secondary battery means a battery which uses a sulfur series material having a sulfur-sulfur bond (S—S bond) as a positive electrode active material and a lithium metal as a negative electrode active material. Particularly, sulfur used as a main material of the positive electrode active material has an advantage of being very abundant in resources, having no toxicity, and having a low atomic weight.
In the lithium-sulfur secondary battery, lithium, the negative electrode active material, is oxidized by being ionized while emitting electrons when discharged, and a sulfur series material, the positive electrode active material, is reduced by receiving the emitted electrons (an oxidation reaction of lithium is a process in which lithium metal is converted to a lithium cation form by releasing electrons, and a reduction reaction of sulfur is a process in which an S—S bond is converted to a sulfur anion form by accepting two electrons). Herein, the lithium cation produced by the oxidation reaction of the lithium is transferred to a positive electrode through an electrolyte, and forms a salt by bonding with the sulfur anion produced by the reduction reaction of the sulfur. More specifically, the sulfur has a cyclic S8 structure before discharge, and is converted to lithium polysulfide (LiPS) by the reduction reaction, and when the lithium polysulfide is completely reduced, lithium sulfide (Li2S) is produced.

Method for improving life properties and charging speed of lithium-sulfur secondary battery


An image forming apparatus has a main body and an optical device provided in the main body for producing an exposure light of an image signal. The image forming apparatus also has a media cartridge detachably mounted to the main body. The media cartridge includes a supplying shaft on which unused photosensitive and pressure sensitive sheet is rolled for continuously supplying the unused sheet, an exposure section where the supplied unused sheet is exposed by the exposure light for forming a latent image on the supplied unused sheet, a pressure developing section to which an image receiver sheet is supplied and at which the receiver sheet is superposed and pressed onto the exposed sheet for pressure-developing an image onto the receiver sheet from the latent image, and a winding-up shaft for winding up the used sensitive sheet.

1. Field of the Invention apparatus using a photosensitive and pressure sensitive sheet.
The present invention also relates to a media cartridge, which contains such a photosensitive and pressure sensitive sheet, for use in such an image forming apparatus.
2. Description of the Related Art
As one of various kinds of image forming apparatuses, there is an image forming apparatus using a photosensitive and pressure sensitive sheet.
Such a sensitive sheet is made of a resin film coated with microcapsules. The microcapsules contain photohardening resin and coloring material in its shell. The photohardening resin is polymerized by light. This sensitive sheet makes a pair with an image receiver sheet, for performing its color development.
That is to say, the receiver sheet is coated with developing material which develops the coloring material in the microcapsules when the microcapsules are ruptured and the coloring material is flown out therefrom.
The microcapsules are hardened by the polymerization of the resin caused by the illumination of the exposure light for forming a latent image such as a light reflected from the original onto the sensitive sheet. Thus, a latent image is formed on the sensitive sheet. Then, by superposing the receiver sheet onto the sensitive sheet and applying a pressure force thereon, the microcapsules which are not hardened are ruptured, thus an image is formed on the receiver sheet by the development of the coloring material of the ruptured microcapsules in cooperation with the developing material of the receiver sheet.
In the image forming apparatus using such a photosensitive and pressure sensitive sheet, the unused sensitive sheet should be guarded from light and pressure so a to maintain its photosensitive property and pressure sensitive property.
Accordingly, a media cartridge is used in this kind of image forming apparatus for accommodating the unused sensitive sheet in a rolled form so as to guard the sensitive sheet from external light and pressure. The media cartridge is provided with a supplying shaft on which the unused sensitive sheet is rolled to supply the sensitive sheet therefrom. The media cartridge is also provided with a winding-up shaft to wind up the used sensitive sheet. The media cartridge is detachably mounted to a main body of the image forming apparatus so as to allow an exchange of the sensitive sheet by exchanging the media cartridge.
When the media cartridge is mounted to the main body, the tip portion of the sensitive sheet, which is pulled out from the supplying shaft of the media cartridge, is set through various kinds of rollers and a specific transport path, which are provided in the exposure section and the pressure developing section in the main body of the image forming apparatus, to the winding-up shaft of the media cartridge. Then, the image forming operation can be performed as the unused sensitive sheet is drawn out from the media cartridge and transported through the exposure section and the pressure developing section of the main body, and then the used sensitive sheet is returned to the media cartridge.
However, in this kind of image forming apparatus, once the media cartridge is set to the main body, it is difficult to exchange the sensitive sheet in its half used condition in the media cartridge. Particularly, it is necessary to cut once the sensitive sheet in order to remove the media cartridge out of the main body, since the sensitive sheet is wound between the supplying shaft and the winding-up shaft through the exposure section and the developing section provided in the main body. Further, if the sensitive sheet, which is in a half used condition, is to be set again to the main body, the tip portion of the sensitive sheet must be set again appropriately through the exposure section and the developing section in the main body, resulting in that a length of the sensitive sheet needed for such an initial setting process is wasted. In addition, such an initial setting process is troublesome and time consuming since it should be performed in a relatively narrow space in the main body.
The pressure force needed for the pressure developing process at the developing section is relatively large, so it is also difficult to achieve a condition to apply such a pressure force and a condition to release the applied pressure force.

Image forming apparatus and media cartridge for use in the same


This invention relates to an isolated nucleic acid fragment encoding an acyltransferase, more specifically a phospholipid:diacylglycerol acyltransferase. The invention also relates to the construction of a recombinant DNA construct encoding all or a portion of the phospholipid:diacylglycerol acyltransferase, in sense or antisense orientation, wherein expression of the recombinant DNA construct results in production of altered levels of the phospholipid:diacylglycerol acyltransferase in a transformed host cell.

In eukaryotic cells triacylglycerols are quantitatively the most important storage form of energy. The main pathway for synthesis of triacylglycerol is believed to involve three sequential acyl-transfers from acyl-CoA to the glycerol backbone. Acyl-CoA:diacylglycerol acyltransferase (DAGAT, EC 22.214.171.124) uses fatty acyl-CoA (acyl donor) and 1,2-diacylglycerol (acyl acceptor) as substrates to catalyze the third and only committed step in triacylglycerol synthesis. DAGAT plays a fundamental role in the metabolism of cellular glycerolipids.
Until recently, it was believed that only DAGAT could carry out the final step in triacylglycerol biosynthesis. However, it has now been demonstrated that microsomal preparation of developing seeds from several plants (sunflower, Helianthus annus; castor bean, Ricinus communis; hawk's beard, Crepis palaestina) as well as microsomal preparations from yeast (Saccharomyces cerevisiae) catalyze triacylglycerol formation via the enzyme phospholipid:diacylglycerol acyltransferase (PDAT, EC 22.214.171.124, Registry Number 288587-47-3) (WO 2000060095; Dahlqvist et al., Proc. Natl. Acad. Sci. USA 97(12):6487-6492 (2000)). This enzyme differs from DAGAT by synthesising triacylglycerol using an acyl-CoA-independent mechanism. The specificity of the enzyme for the acyl group in the phospholipid varies with species, e.g., the enzyme from castor bean preferentially incorporates vernoloyl (12,13-epoxyoctadec-9-enoyl) groups into triacylglycerol, whereas that from the hawk's beard incorporates both ricinoleoyl (12-hydroxyoctadec-9-enoyl) and vernoloyl groups. The enzyme from the yeast Saccharomyces cerevisiae specifically transfers acyl groups from the sn-2 position of the phospholipid to diacylglycerol, thus forming an sn-1-lysophospholipid. It has also been shown that PDAT activity is present in vegetative tissues of Arabidopsis thaliana (Banaś et al., Biochem. Soc. Trans. 28:703-703 (2000)). Furthermore, the substrate specificity of PDAT varies between species and depends on the head group of the acyl donor, the acyl group transferred and the acyl chains of the acyl acceptor (1,2-diacylglycerol).


Described herein are technologies related to an in-band full-duplex wireless communication operation. More particularly, the technologies utilize a complementary pair of antennas for signal transmission and reception arranged in a new manner to be both compact (relatively to conventional approaches) and provide an extremely high (e.g., 60 dB or more) isolation.

The next generation of wireless (e.g., cellular) communication technology standards improve over the previous generation's data throughput. It is expected that the so-called fifth generation (5G) wireless communication systems and networks will dramatically (e.g., about twice as much) increase the data throughput of the previous generation.
Existing wireless communication systems and networks (including current generations) employ duplexing. Namely, either frequency division duplex (FDD) or time division duplex (TDD) has been used for separate transmission and reception. In FDD and TDD, transmitted signal does not interfere with received signal due to a separate use of frequency and time resources respectively. Therefore twice the amount of frequency and/or time are used in current duplexing systems compared to in-band full-duplex systems (IBFD). It seems possible to double data throughputs by simultaneous transmission and reception in the same frequency band at the same time.
In-band full-duplex (IBFD) operation has emerged as an attractive solution to increase the data throughput of wireless communication systems and networks. With IBFD, a wireless device (i.e., node) transmits and receives simultaneously in the same or common frequency band. However, one the biggest practical impediments to IBFD operation is the presence of self-interference (i.e., the interference caused by an IBFD node's own transmissions to its desired receptions).
The self-interference impediment to IBFD operation has been addressed by several conventional antenna designs. For example, one conventional approach is called echo cancellation. In this approach, a single antenna is used for both transmission and reception. That antenna is connected to a circulator. The circulator interconnects three different elements: antenna, transmitting (TX) radio frequency (RF) subsystem, and receiving (RX) RF subsystem.
While this arrangement accomplishes the IBFD operation, there is a signal leakage from the TX RF subsystem to the RX RF subsystem due to a relatively low isolation level (e.g., ˜20 dB) between the TX and RX port in the circulator. In addition to the TX signal leakage, the TX signal is reflected due to impedance mismatch at the antenna port. This reflection may dominate the desired RX signal at the RX RF subsystem. Furthermore, as wireless commination components go, a circulator is relatively large and heavy because of its magnets.
Another conventional approach utilizes two separate antennas. The antenna pairs have a high isolation level (e.g., ˜40 dB) with a relatively large separation and each antenna is dedicated to either signal transmission (TX) or reception (RX). While this dual-antenna approach eliminates the heavy and large circulator, it introduces new problems. The primary problems of this dual-antenna approach are space and complexity. Two separate and isolated antennas require more space because there are twice as many antennas and those antenna must be physically spaced from each other sufficiently enough to reduce interference therebetween.
The Detailed Description references the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.

In-band full-duplex complementary antenna


A microbial fuel cell includes an anode portion having an anode and a cathode portion having a cathode. The anode is configured to support an electrically conductive biofilm matrix. A cation exchange membrane is positioned between the anode and the cathode. The anode portion and the cation exchange membrane define an anode chamber having a volume of between about 1 μL and about 100 μL and configured to receive an anolyte. The cathode portion and the cation exchange membrane define a cathode chamber having a volume of between about 1 μL and about 100 μL and configured to receive a catholyte. The microbial fuel cell is configured to achieve a Coulombic efficiency of at least 30% and/or a power density of at least of 4.7 μW/cm2. The microbial fuel cell is a microelectromechanical system and can be fabricated in an automated production process.

A microbial fuel cell (MFC) is an electrochemical device that converts organic substrates into electricity through the metabolism of anode-respiring bacteria (ARB). ARB oxidize organic substrates and then complete respiration by transferring electrons to the anode via extracellular electron transfer (EET). Many MFCs are in macro-sized forms that serve as prototypes of large power sources or wastewater treatment technology. Micromachined or microelectromechanical systems (MEMS) MFCs have been explored for use as portable power sources as well as platforms for behavioral studies of ARB.

Arizona Board of Regents, a body corporated of the State of Arizona acting for and on behalf of Arizona State University


Methods and apparatus for combinatorial (i.e., high-throughput) materials research, such as catalysis research, that involves parallel apparatus for simultaneously effecting mechanical treatments such as grinding, mixing, pressing, crushing, sieving, and/or fractionating of such materials are disclosed. The methods and apparatus are useful for mechanically treating catalysis materials and other solid materials, including without limitation, electronic materials such as phosphors, colorants such as pigments, and pharmaceuticals such as crystalline drugs or drug candidates. The simultaneous protocols and parallel apparatus offer substantial improvements in overall throughput for preparing arrays of materials, such as catalysis materials.

Heterogenous catalysts have a variety of known applications, in diverse fields including commodity chemicals and fine chemicals. It has long been recognized, however, that the catalytic activity and/or selectivity of heterogeneous catalysts can vary substantially due to many factors. Factors known to have a potential effect on catalytic activity and/or selectivity are described, for example, by Wijngaarden et al., "Industrial Catalysis—Optimizing Catalysts and Processes", Wiley-VCH, Germany (1998).
Combinatorial (i.e., high-throughput) approaches for evaluation of catalysts and/or process conditions are also known in the art. See, for example, U.S. Pat. No. 5,985,356 to Schultz et al., U.S. Pat. No. 6,004,617 to Schultz et al, U.S. Pat. No. 6,030,917 to Weinberg et al., U.S. Pat. No. 5,959,297 to Weinberg et al., U.S. Pat. No. 6,149,882 to Guan et al., U.S. Pat. No. 6,087,181 to Cong, U.S. Pat. No. 6,063,633 to Willson, U.S. Pat. No. 6,175,409 to Nielsen et al., and PCT patent applications WO 00/09255, WO 00/17413, WO 00/51720, WO 00/14529, each of which U.S. patents and each of which PCT patent applications, together with its corresponding U.S. application(s), is hereby incorporated by reference in its entirety for all purposes. Considered individually and cumulatively, these references teach the synthesis and screening of arrays of diverse materials, and generally, of spatially-determinative arrays of diverse materials. Typical approaches involve primary synthesis and screening (high-throughput "discovery" screening) followed by secondary synthesis and screening (more moderate-throughput "optimization" screening), and optionally, followed by tertiary synthesis and screening (e.g., typically traditional "bench scale" screening). These references also describe screening strategies in which compositionally-varying arrays are prepared (e.g., as part of a primary or secondary screen) first with broadly-varied gradients. Subsequently, "focused" libraries comprising more narrowly-varied gradients are prepared and screened (e.g., at the same level of screen) based on the results of the first screen. Such libraries or arrays of diverse materials such as catalysts can comprise binary, ternary and higher order compositional variations. See, for example, WO 00/17413 (as well as its corresponding U.S. application, Ser. No. 09/156,827 filed Sep. 18, 1998 by Giaquinta et al.) and WO 00/51720, (as well as its corresponding U.S. application, Ser. No. 09/518,794 filed Mar. 3, 2000 by Bergh et al.), each of which U.S. and PCT applications are hereby incorporated by reference in its entirety for all purposes. High-throughput process optimization, including process optimization in parallel flow reactors has also been described. See, for example, WO 00/51720, (as well as its corresponding U.S. application, Ser. No. 09/518,794 filed Mar. 3, 2000 by Bergh et al.), and additionally, U.S. patent applications Ser. No. 60/185,566 filed Mar. 7, 2000 by Bergh et al., Ser. No. 60/229,984 filed Sep. 2, 2000 by Bergh et al., Ser. No. 09/801,390 filed Mar. 7, 2001 by Bergh et al., and Ser. No. 09/801,389 filed Mar. 7, 2001 by Bergh et al., each of which U.S. and PCT applications are hereby incorporated by reference in its entirety for all purposes.
The efficiency of a catalyst discovery program is, in general, limited by rate-limiting steps of the overall process work flow. Additionally, high throughput approaches still require substantial efforts to explore vast compositional space. As such, current approaches, while offering substantial advances over previous traditional, lower-throughput approaches, can still be improved with respect to overall efficiency. Hence, there is a need in the art for improved overall research work flows for developing and evaluating heterogeneous catalysts for a particular reaction of interest. In particular, a need exists for more efficient, meaningful approaches for identifying new heterogeneous catalysts.
More specifically, a need exists for improved preparation protocols for heterogeneous catalysts. Although substantial advances have been made with respect to parallel synthesis of catalyst candidate materials, and with respect to reaction-based screening of such catalyst candidates, relatively fewer advances have focused on pretreatment of heterogeneous catalysts—after synthesis of the catalysis material or precursor thereof and before screening thereof. Typical post-synthesis catalyst treatment can include chemical treatment (e.g., precursor decomposition, oxidation, reduction, activation), physical treatment (e.g., calcining, washing), and/or mechanical treatment (e.g., grinding, pressing, crushing, sieving, and/or shaping).
Mechanical pretreatment approaches have been effected to date for combinatorial catalysis research using conventional approaches. For example, Senkan et al. reported the preparation of a combinatorial array of shaped catalysts (pellets) using conventional, serial die-pressing. See S. Senkan et al., "High-Throughput Testing of Heterogeneous Catalyst Libraries Using Array Microreactors and Mass Spectrometry", Angew. Chem. Intl. Ed., Vol. 38, No. 18, pp. 2794-2799 (1998). Grinding approaches for catalyst preparation are also known in the art, including both serial and parallel grinding protocols. (See, for example, Obenauf et al., Catalog of SPEX CertiPrep, Inc. (Metuchen, N.J.) pp. 28-39, 90-91, 104-105 and 114-119 (1999)). Schuth et al. disclose a loading device for synthesis of an array of catalysts, where the loading device is adapted for parallel transfer of the synthesized catalysts to a parallel flow reactor through a communition device. (See EP 19809477 A1). However, such conventional pretreatment protocols, such as the conventional serial pressing approaches, are not efficient enough for preparing arrays comprising larger numbers of catalysts. Moreover, conventional grinding or communiting approaches, although parallelized, suffer from other deficiencies. Such grinding approaches, as exemplified for example by the aforementioned communition protocols of Schuth et al., result in a to-be-tested catalyst candidate that includes a broad, uncontrolled distribution of catalyst particle sizes, including catalyst particle fines. Variations in the particle size distribution of candidate catalysts—as compared between reaction vessels (or channels) of a parallel reactor—can affect catalyst performance and, additionally or alternatively, can affect the flow-characteristics when screening the catalysts in a parallel flow reactor, such that in either case, direct comparison of catalysts between reaction vessels or channels is compromised. As such, there remains a need in the art to overcome such deficiencies.

This patent is subject to a terminal disclaimer.

Methods and apparatus for mechanical treatment of materials such as catalysts


An electromagnetic shielding device for use along gaps between relatively movable surfaces of doors, access panels, drawers, and cabinets, etc., includes an electrically conductive shielding strip and a clamping element. The shielding device also includes a mechanism that secures the shielding strip to the clamping element when the shielding device is not mounted on a surface. When mounted on a surface, the shielding strip is held in position by the clamping element. The shielding strip is formed so as to avoid being exposed to excessive stress.

Electromagnetic shielding is provided at joints between removable panels of housings for electronic equipment and testing facilities to impede transmission of electromagnetic fields. Optimally, electromagnetic activity from external devices is prevented from effecting the shielded device while electromagnetic activity generated by the shielded device itself is also prevented from escaping the shielded enclosure. Electromagnetic shielding is often required for shielded enclosures such as, for example, doors of electronic laboratory rooms, casings of radio transmitters, receivers and computers and other similar facilities and equipment.
Commonly, such structures and equipment require shielding along gaps between surfaces of doors, access panels, drawers, cabinets or the like, where surfaces are repeatedly, or only possibly, moved relative to one another. For example, electrical components may be arranged individually in cases which are slid into and out of cabinets every time there arises a need to test, service or update the component. Accordingly, it is highly desirable for the casing to have electromagnetic shielding that is adapted to withstand the bi-directional shearing action induced upon it by each insertion and a removal of the casing into and from the cabinet. Similarly, electrical components may be arranged in a compartment accessible only through a pivoting door which must be opened and closed each time there arises a need to test, service or update the component. As with the casings, it is highly desirable for the mating surfaces of the door to have electromagnetic shielding that is adapted to withstand the "wiping" action induced thereon during each pivot of the door. Failing such characteristics, the electromagnetic shielding of the electrical component may become broken and the component along with the entire electrical system to which it is connected become vulnerable to or an emitter of electromagnetic interference.
Track mounted electromagnetic shielding devices such as that disclosed in U.S. Pat. No. 4,623,752 issued to Steen et al. have been previously proposed to provide acceptable electromagnetic shielding. However, track-mounted devices are not readily mountable or removable for repair or replacement since at least one part of such devices, namely the track, is separately secured to the surface by separate fasteners. Furthermore, the fastener receiving holes disposed in the track may also compromise the overall shielding effectiveness of the shielding device. For example, the carrier strip used in the Steen et al. device is mounted to a surface by separate push-in rivets and before the Steen et al. device can be fully mounted and assembled, the carrier strip must first be secured to the surface by the push-in rivets. Similarly, if the device needs to be replaced or repaired, the rivets must first be removed before the carrier strip can be removed. The extra step of having to insert or remove the rivet before the shielding device may be mounted or removed is an inconvenient step of the mounting or removal procedure. Moreover, the presence of holes for receiving the rivets is likely to reduce the overall shielding effectiveness of the Steen et al. device.
To avoid such inconveniences associated with track mounted devices while still providing acceptable electromagnetic shielding, it has been proposed to secure a shielding strip to a surface with a retaining clip. For example, in U.S. Pat. No. 4,760,214 granted to Bienia et al., an electromagnetic shielding device is disclosed having a clamping element that secures a shielding strip to a surface. The clamping element does not require a separate fastener in order to secure the clip to the mounting surface and, consequently, the shielding device may be readily mounted or removed without extensive assembly or disassembly steps.
Notable of clip mounted devices such as that disclosed in the Bienia et al. reference, however, is that the clamping element and the shielding element are only secured to each other when mounted on a surface. Consequently, when removed from the surface or prior to mounting on the surface, the clamping element and the shielding element become separated and thus each element is susceptible to becoming lost. Moreover, during the mounting procedure, care must be taken to ensure that the clamping element is situated correctly with respect to the shielding element and vice versa. Such added care causes the mounting procedure to become rather tedious.
Clip mounted devices such as that disclosed in the Bienia et al. patent may also experience undesirable stresses within the shielding element. Depending on how the shielding element is secured within the clamping element, concentrated stresses may be cyclically induced at certain locations on the shielding element. Such undesirable stresses may result in catastrophic failure of the shielding strip that would disrupt the integrity of the electromagnetic seal around the shielded item.

Clip mounted electromagnetic shielding device


A method for self-sensing, activating, and regulating thermal management for a rack-mount backup battery unit (BBU) module is disclosed. The BBU module includes a data center rack-mountable chassis, battery cells submerged in a coolant in a liquid phase in a coolant tank, the coolant extracting heat from the plurality of battery cells when at least some of the battery cells are being charged or discharged, and a cooling loop having a heat exchanger, a supply line for supplying lower-temperature coolant from the heat exchanger to the coolant tank, and a return line for returning higher-temperature or multi-phase coolant from the coolant tank to the heat exchanger, wherein the higher-temperature or multi-phase coolant is cooled and transformed into lower-temperature coolant or single phase liquid at the heat exchanger, and wherein the cooling loop is in operation when at least some of the plurality of battery cells are being charged or discharged, and is idle when none of the plurality of battery cells are being charged or discharged.

A battery pack consists of battery cells connected in series, in parallel or, a combination of both. The battery cells generate heat during discharging and charging. The speed of discharging is positively correlated with the heat generated. A cooling system for the battery pack is very important because a higher temperature or a lower temperature may negatively impact the battery performance as well as battery health conditions. Since multiple cells are connected together, a significant difference in internal temperature values can lead to different charging and discharging rates for different cells and thus cause the battery pack performance to deteriorate. Therefore, the battery thermal management system plays a vital role in the design and operation of the battery pack, and has a direct impact on the performance of the battery pack. In addition, a bad design of a thermal system may result in the BBU failed to function, such as failure to satisfy the backup time needed.
Several conventional battery thermal management systems for cooling electric vehicles exist. These include, for example, the air cooling system, the passive or active liquid system, and the thermo-electric system. However, such systems are insufficient.

Thermal management system design for battery pack


A magnetically enhanced HDP-CVD plasma source includes a hollow cathode target and an anode. The anode and cathode form a gap. A cathode target magnet assembly forms magnetic field lines that are substantially perpendicular to a cathode target surface. The gap magnet assembly forms a cusp magnetic field in the gap that is coupled with the cathode target magnetic field. The magnetic field lines cross a pole piece electrode positioned in the gap. This pole piece is isolated from ground and can be connected with a voltage power supply. The pole piece can have a negative, positive, or floating electric potential. The plasma source can be configured to generate volume discharge. The gap size prohibits generation of plasma discharge in the gap. By controlling the duration, value and a sign of the electric potential on the pole piece, the plasma ionization can be controlled. The magnetically enhanced HDP-CVD source can also be used for chemically enhanced ionized physical vapor deposition (CE-IPVD). Gas flows through the gap between hollow cathode and anode. The cathode target is inductively grounded, and the substrate is periodically inductively grounded.

Field
The disclosed embodiments generally relate to a plasma enhanced chemical vapor deposition (PE CVD) apparatus and method and, more particularly, relate to a pulse magnetically enhanced low temperature high density plasma chemical vapor deposition (LT HDP CVD) apparatus and method.
Related Art
CVD plasma sources that deposit diamond and diamond-like coatings and films use hot filament chemical vapor deposition (HFCVD) and microwave assisted chemical vapor deposition (CVD) techniques. Both methods require a high temperature on a substrate in order to form a carbon film with a high content of sp3 bonds. Accordingly, new CVD technologies are needed that will allow depositing diamond-like carbon (DLC) films at much low temperatures.

Magnetically enhanced high density plasma-chemical vapor deposition plasma source for depositing diamond and diamond-like films