The invention provides an Fe—Ni—Mo soft magnetic flaky powder having a component composition of, in percent by mass, Ni: 60 to 90%, Mo: 0.05 to 1.95%, and the balance of Fe and unavoidable impurities, and a flat surface of an average particle size of 30 to 150 μm, and an aspect ratio (average particle size /average thickness) of 5 to 500; and having a peak intensity ratio I200/I111 within a range between 0.43 and 10, where I200 is the peak height of the face index (200) and I111 is the peak height of the face index (111), in an X-ray diffraction pattern measured in such a manner that the plane including the X-ray incident direction and the diffraction direction is perpendicular to the flat surface of the soft magnetic flaky powder, and the angle between the incident direction and the flat surface is equal to the angle between the diffraction direction and the flat surface. Furthermore, the invention provides a soft magnetic flaky powder with oxide layer wherein an oxide layer of a thickness of 50 to 1000 Å is formed on the surface of this soft magnetic flaky powder.

In general, a permalloy A (Fe-70 to 80% Ni) (% denotes percent by mass, which is the same hereinunder) is known, as a high permeability soft magnetic material as an ingot material and a sintered material. After applying heat treatment to this material, if it is annealed, an FeNi3 order phase is generated and the crystalline magnetic anisotropy constant K1 becomes negative with a large absolute value. It is known that: if the crystalline magnetic anisotropy constant K1 is negative, the <111> direction becomes the easy magnetization direction and the <100> direction becomes the hard magnetization direction; if it is positive, the <100> direction becomes the easy magnetization direction and the <111> direction becomes the hard magnetization direction; and if it is zero, the crystalline material becomes magnetically isotropic. Due to the generation of this FeNi3 order phase, magnetic anisotropy is generated, resulting in a decrease in the magnetic permeability in a normal polycrystalline substance where the crystal face is not oriented, and which is isotropic in the crystal orientation. To obtain a high magnetic permeability in this material requires quenching after high temperature heat treatment, and further an aging treatment thereafter. However, such processing is not industrially used.
Moreover, there is known a Mo permalloy (Fe-79% Ni-4%-Mo) and a supermalloy (Fe-79% Ni-5% Mo), that are permalloys added with Mo. Due to the addition of Mo, even if these materials are annealed after heat treatment, generation of the FeNi3 order phase is suppressed, and even if quenching is not applied after heat treatment, the crystalline magnetic anisotropy constant K1 becomes about zero, showing a superior magnetic permeability in a polycrystalline substance which is isotropic on the crystal orientation. Therefore, these materials are widely used industrially. Moreover, in order to further improve the magnetic permeability, a high permeability soft magnetic material added with Cu, Cr, and Mn in addition to Mo is known.
Meanwhile, there is known that a soft magnetic flaky powder is obtained by flattening powder having a similar composition. For example, a soft magnetic flaky powder is known, which has the composition of Fe-70 to 83% Ni-2 to 6% Mo-3 to 6% Cu-1 to 2% Mn, an average particle size of 0.1 to 30 μm, and an average thickness of 2 μm or less. The soft magnetic flaky powder is used, for example, as a soft magnetic flaky powder for a magnetic card (refer to Japanese Unexamined Patent Application, First Application No. Hei 03-223401).
Moreover, there is known soft magnetic flaky powder having a composition of Fe-40 to 80% Ni-2 to 6% Mo. This soft magnetic flaky powder is used, for example, as a flat soft magnetic powder for magnetic marking (refer to Japanese Unexamined Patent Application, First Application No. Hei 03-232574).
Furthermore, a soft magnetic flaky powder is known, which has a composition of Fe-60 to 80% Ni—Mo or Fe-60 to 80% Ni-5% or less Mo. This soft magnetic flaky powder is used, for example, as a high frequency magnetic core (refer to Japanese Unexamined Patent Application, First Application No. Hei 04-78112).
In any of such conventional Fe—Ni—Mo soft magnetic flaky powders, it is known that the magnetic property such as the magnetic permeability in the flat surface of the powder can be further increased by flattening the Fe—Ni—Mo powder obtained by normal crushing or atomization for generating shape magnetic anisotropy due to the demagnetizing field, so as to make the easy magnetization face be within the flat surface.
Such conventional Fe—Ni—Mo soft magnetic flaky powders are all manufactured such that the Fe—Ni—Mo powder obtained by normal crushing or atomization is added with ethanol or water as a solvent, and further added with pulverizing agent as required, which is then flattened using an attritor or a ball mill.
The thus obtained Fe—Ni—Mo soft magnetic flaky powder is used to form a magnetic composite material by dispersing the flat soft magnetic powder in the resin such that the flat face is oriented in one direction. In a case that the magnetic composite material is a magnetic composite sheet, the flat surface of the Fe—Ni—Mo soft magnetic flaky powder is oriented in the right angle direction with respect to the thickness direction of the magnetic composite sheet.
However, there is a problem that the conventional Fe—Ni—Mo soft magnetic flaky powder does not exhibit sufficient properties as a high frequency magnetic material for use as a radio wave absorber having a radio wave absorption property at several tens MHz to several GHz, or for use as an antenna core for wireless communications having the magnetic property at several tens kHz to several tens MHz. Therefore, it is desired to obtain a soft magnetic flaky powder having more superior magnetic permeability in the flat surface.

Fe-Ni-Mo soft magnetic flaky powder and magnetic composite material containing soft magnetic powder


A method and an apparatus are provided for performing run-to-run control of trench profiles. At least one semiconductor wafer is processed. A trench metrology data from the processed semiconductor wafer is acquired. Data relating to at least one process chamber characteristic is acquired while processing the semiconductor wafer. A chamber characteristic adjustment process is performed in response to the trench metrology data and the data relating to the processing chamber characteristic. A feedback adjustment of the processing chamber characteristic is performed in response to the chamber characteristic adjustment process.

1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for performing process control adjustments based upon trench profiles.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed above a wafer. Thereafter, a patterned layer of photoresist may be formed above the process layer using known photolithography techniques. Typically, an etch process is then performed on the process layer using the patterned layer of photoresist as a mask. This etching process results in formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Typically, shallow trench isolation (STI) structures formed on the semiconductor wafers are filled by forming silicon dioxide using tetraethoxysilane (TEOS), over the wafer and in the STI structures. The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a silicon substrate 210 that contains a plurality of layers 220, 230, is shown. In one embodiment, a layer of silicon nitride is added on the surface 215 of the silicon substrate 210, producing the layer 220. Trenches 240 are formed that extend through layer 220 of silicon nitride and into the silicon substrate 210. Any of a variety of etching processes may be employed to create the trench 240. The trenches 240 in the silicon substrate 210 generally have a finite trench depth 250. The trench depth 250 extends from the bottom of the trench 240 to a top surface of the semiconductor wafer. Generally, the silicon nitride layers 220 are removed in the finished product.
FIG. 2 also illustrates a pre-polished layer of silicon dioxide material deposited on the silicon substrate 210, which is represented by layer 230. Generally, TEOS, which is a source gas, is used in the deposition process. Ideally, the silicon dioxide completely fills the trench depth 250.
Maintaining predetermined trench profile characteristics, such as trench depth 250, is important in semiconductor wafer manufacturing. Trench characteristics can affect the performance of a device manufactured from a processed semiconductor wafer. For example, variations in STI structures formed on a semiconductor wafer can affect the electrical characteristics of the semiconductor wafer. This, in turn, can affect the quality of devices produced from the processed semiconductor wafers.
Controlling trench profile characteristics during semiconductor wafer processing is generally difficult. Many times, loss of control of processing of trench structures on layers of semiconductor wafers can cause excessive variations among trench structures on the semiconductor wafers 105. These variations can cause undesirable electrical characteristics associated with the operation of devices manufactured from the semiconductor wafers.
Turning now to FIG. 3, trenches 240 formed in a process layer 210 is illustrated. During processing of trench structures, loss of control can result in a trench depth 250 that is larger or smaller than a predetermined target value, or a range of values. A trench 240 with incorrect trench depth 250 can result in defective semiconductor wafers 105. Furthermore, loss of control of processing of trench structures can result in diminished ability to form trench structures that contain sidewalls 305 at the appropriate angles. The sidewall angle, xcex8, 320 can be greater or smaller than a predetermined target value, or a range of values. Variations in the sidewall angle 320 can cause undesirable fluctuations in the electrical characteristics of structures associated with the trenches 240, resulting in defective semiconductor wafers 105.
Generally, when loss of control of processing of trench structures occurs, many actions may be taken. For example, the processing chamber, e.g., etch chamber, in which the trench structures are formed, may be shut down and cleaned in an effort to return the chamber to a known steady state condition. The control of processing of trench structures is then re-initiated. However, the shutting down of a process chamber is inefficient and delays manufacturing of semiconductor wafers. Furthermore, frequent cleaning of process chambers requires a manufacturing system to constantly re-establish control of processing of trench structures from an initial state, resulting in additional delays and expenses.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for performing run-to-run control of trench profiles. At least one semiconductor wafer is processed. A trench metrology data from the processed semiconductor wafer is acquired. Data relating to at least one process chamber characteristic, the data acquired while processing the semiconductor wafer is acquired. A chamber characteristic adjustment process is performed in response to the trench metrology data and the data relating to the processing chamber characteristic. A feedback adjustment of the processing chamber characteristic is performed in response to the chamber characteristic adjustment process.
In another aspect of the present invention, a system is provided for performing run-to-run control of trench profiles. The system of the present invention comprises: a metrology data storage unit to receive trench metrology data; a chamber data storage to receive chamber characteristic data relating to a processing of a semiconductor wafer; a chamber characteristic/metrology data correlation unit operatively coupled with the metrology data storage unit and the chamber data storage unit, the chamber characteristic/metrology data correlation unit to correlate the trench metrology data with corresponding chamber characteristic data; and a chamber control model to modify a chamber characteristic during a time period of processing of a semiconductor wafer based upon the correlated trench metrology data and corresponding chamber characteristic data.

Method and apparatus for run-to-run control of trench profiles


A method and system for providing up-to-date monitoring results in a virtual machine environment are described. In one embodiment, a control server executes a query pertaining to one or more objects in a virtual machine system, and provides a result of the query to a client for presentation to a user in a graphical user interface (GUI). The control server then periodically re-executes the query to obtain up-to-date information for the objects in the virtual machine system. Upon each re-execution of the query, the control server compares a new result of the query with a previous result of the query to determine whether the up-to-date information for the objects in the virtual machine system has changed. If so, the control server provides the new result of the query to the client. If not, the control server refrains from providing the new result of the query to the client.

Virtualization allows multiplexing of the underlying host machine between different virtual machines. The host computer allocates a certain amount of its resources to each of the virtual machines. Each virtual machine is then able to use the allocated resources to execute applications, including operating systems (referred to as guest operating systems). The software layer providing the virtualization is commonly referred to as a hypervisor and is also known as a virtual machine monitor (VMM), a kernel-based hypervisor or a host operating system. The hypervisor emulates the underlying hardware of the host computer, making the use of the virtual machine transparent to the guest operating system and the user of the computer.
The virtualization technologies have wide applications in the computer field with the development of computer systems. For example, such virtualization technologies can be used to implement a virtual desktop application which runs within a virtual machine of a host and accessed from a client over a network.
In a large organization, thousands of virtual machines can be run on one or more hosts, making it very difficult for a system administrator to manage the virtual machines. One existing solution employs a host controller that monitors the operation of the virtual machines and allows an IT administrator to add a new virtual machine, delete an existing virtual machine, migrate a virtual machine to a different host, or perform any other action based on up-to-date information provided by the host controller. The up-to-date information for the virtual machine system can be displayed to a user (e.g., an IT administrator) on the user's client machine via a graphical user interface (GUI). Usually, the information in the GUI is updated in response to frequent requests sent from the client to the host controller. However, this approach creates network-related problems in a system with a limited bandwidth such as a virtual desktop system or the like.

Interactive search monitoring in a virtual machine environment


The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. Such subsystems are commonly implemented as either removable memory cards that can be inserted into multiple host systems or as non-removable embedded storage within the host system. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash EEPROM devices are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. A typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks, wherein a block contains the smallest number of cells (unit of erase) that are erasable at one time.
In one commercial form, each block contains enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it is stored. The amount of user data included in a sector is the standard 512 bytes in one class of such memory systems but can be of some other size. Because the isolation of individual blocks of cells from one another that is required to make them individually erasable takes space on the integrated circuit chip, another class of flash memories makes the blocks significantly larger so there is less space required for such isolation. But since it is also desired to handle user data in much smaller sectors, each large block is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data. Each page usually stores one sector of user data, but a page may store a partial sector or multiple sectors. A "sector" is used herein to refer to an amount of user data that is transferred to and from the host as a unit.
The subsystem controller in a large block system performs a number of functions including the translation between logical addresses received by the memory sub-system from a host, and physical addresses within the memory cell array. This translation often involves use of intermediate terms for a logical block number (LBN) and logical page. The controller also manages the low-level flash circuit operation through a series of commands that it issues to the flash memory devices via an interface bus. Another function the controller performs is to maintain the integrity of data stored to the subsystem through various means, such as by using an error correction code (ECC).
In case of a power outage during operation of such a memory circuit, for example if a memory card is removed from a host or a power is lost to a device with an integrated memory, the memory may be caught in the middle of a write or erase operation, resulting in an incomplete operation. For example, if a memory system loses power during a programming process when most, but not all, of the cells in a group being written have reached their target state, the write group may contain a large number of errors. As is familiar in the art, it is common to incorporate error correction code (ECC) into memory systems to determine and correct data errors. A power outage before completion of a programming operation can cause the write group to be in three situations when the interrupted write group is read: (1) it is correctable by ECC; (2) it is uncorrectable by ECC; and (3) an ECC mis-detect can occur. In the first case, the extent of the error is minor enough where the error correction code can salvage the data. In the second case, the data will be incorrect, but the system will determine this condition. In the third case, the data will again be incorrect, but, due to an ECC mis-detect, the system is unaware of the situation.
This last case, the ECC mis-detect, can occur if, for example, the ECC has the capacity to correct up to, say, 4 bits of error, but 7 bits of data in the write group were not correctly written. The system will then unaware of the incorrectly written data and operate as if it has corrected any error in the write group, but the data will still be wrong. A similar situation can occur if power loss occurs during an erase process. These scenarios make ECC write and erase abort detection far from perfect and are particularly troublesome for mission critical situations where it is important to know if the data has been correctly entered. Consequently, there is room for improvement in this aspect of memory systems.

Flash storage system with write/erase abort detection mechanism


Disclosed are a CSI-RS configuration and CSI feedback method and apparatus, and a relevant device, which are used for implementing 16-port CSI-RS configuration and performing CSI feedback based on a 16-port CSI-RS. The CSI-RS configuration method comprises: determining 16-port channel state information-reference signal (CSI-RS) configuration information configured to a user equipment (UE), wherein the CSI-RS configuration information comprises information about a resource element (RE) occupied by a 16-port CSI-RS configured to the UE, and the RE occupied by the 16-port CSI-RS comprises an RE other than REs occupied by a physical downlink control channel (PDCCH), a cell-dedicated reference signal (RS) and a UE-dedicated RS; and sending, to the UE, the 16-port CSI-RS configuration information configured to the UE.

In a Long Term Evolution-Advanced (LTE-Advanced) system, a CSI-RS is defined. The CSI-RS is a downlink pilot signal, and is an existing signal provided by a sender to a receiver and configured for useful signal channel measurement. CSI feedback may be divided into a periodic feedback mode and a nonperiodic feedback mode. The CSI is formed by a Rank Indicator (RI), a Precoding Matrix Indicator (PMI) and a Channel Quality Indicator (CQI). For nonperiodic CSI feedback, a system working flow is as follows.
1. A base station triggers CSI-RS measurement performed by a user on a certain downlink subframe, and sends a CSI-RS.
2. A terminal obtains a triggering message, measures the CSI-RS on the corresponding subframe, and estimates useful signal quality.
3. The terminal determines CSI according to the useful signal quality.
4. The terminal delays for at least K subframes, and feeds back the CSI on an available uplink subframe (where K refers to a processing time for CSI calculation of the terminal).
5: The base station receives the CSI fed back by the terminal on the corresponding uplink subframe.
A three Dimensions Multiple-Input Multiple-Out-put (3D-MIMO) technology is a topic under discussion of the 3rd Generation Partnership Project Radio Access Network 1 (3GPP RAN1), and 3D-MIMO mainly adopts a two-dimensional array antenna, and may be described with the following parameters (M, N, P, Q), where M represents a number of elements of a column of polarized antennae, N represents a column number of an antenna array, P=2 represents adoption of dual-polarized antennae, MTXRU represents a number of transceiver channels corresponding to the same column of antennae, a transceiver channel may correspond to a plurality of antenna elements, and Q=2N*MTXRU represents a total number of Transceiver Units (TXRUs) included in a TXRU array corresponding to the antenna array. For example, an antenna array corresponding to (M, N, P, MTXRU)=(8,4,2,4) may be represented by FIG. 1 (left), and a TXRU array corresponding to Q=32 may be represented by FIG. 1 (right), TXRU # (mTXRU, nTXRU) representing a certain TXRU.
CSI feedback enhancement is an important topic in 3D-MIMO, and at present, three main solutions are adopted.
A first solution: Full port CSI-RS (all CSI-RS ports)-based CSI feedback, where, in the solution, a number of CSI-RS ports is equal to a number of TXRUs, and they are in a one-to-one mapping relationship, as shown in FIG. 2.
A second solution: Partial port CSI-RS (part of CSI-RS ports)-based CSI feedback, where the solution adopts two sets of independent CSI-RSs, where 2N ports are involved in one set of CSI-RSs, and are mapped to 2N TXRUs in a certain row of a TXRU array one to one, and MTXRU ports are involved in the other set of CSI-RSs, and are mapped to MTXRU TXRUs in a certain column of the TXRU array one to one, as shown in FIG. 3.
A third solution: Beamformed CSI-RS (beamformed CSI-RSs)-based CSI feedback, where, in the solution, the CSI-RSs are beamformed in a vertical dimension, MTXRU TXRUs in the same column are mapped onto B vertical-dimension beams through B groups of different vertical-dimension forming weights, and each vertical-dimension beam corresponds to a set of CSI-RSs (2N ports are involved in each set), so that there are totally B sets of CSI-RSs, as shown in FIG. 4.
The first solution is a method adopted by a current LTE system, and its advantage is that User Equipment (UE) may estimate most comprehensive channel information, that is, the UE may obtain channel information between the UE and all sending antenna ports. However, when the solution is adopted, if a number of ports is relatively large, on one hand, CSI-RS overhead is high, and it is overhead corresponding to different CSI-RS ports. In present LTE, overhead of 8 CSI-RS ports is about 1.5%, overhead of 16 CSI-RS ports is 3%, and overhead of 32 CSI-RS ports and 64 ports is relatively high.
It is widely believed in the industry that: CSI-RS overhead is acceptable when a number of ports is relatively small (for example, smaller than 20), so that the first solution may be adopted; and when the number of the ports is relatively large (for example, larger than 20), CSI-RS overhead of Full port CSI-RS-based CSI feedback is too high, so that the second solution and the third solution are required to be considered.
A system in a related technology supports 1, 2, 4 and 8 CSI-RS ports. CSI-RS pattern designs in FIG. 5a-FIG. 5c may be applied to a frame structure type 1 (Frequency Division Duplex (FDD)) and a frame structure type 2 (Time Division Duplex (TDD)), a Resource Element (RE) configured for CSI-RSs is represented by two letters, the first letter represents a cell index, and the second letter represents antenna ports transmitted on the RE. These patterns adopt a nested structure, that is, 2-port CSI-RS antenna ports are subsets of 4-port and 8-port CSI-RS antenna ports, and such a design is favorable for reducing complexity in implementation. There are totally 40 antenna ports, and it is supported that an intercell frequency multiplexing factor is 5 and each cell adopts 8 CSI-RS antenna ports or the intercell frequency multiplexing factor is 20 and each cell adopts 2 CSI-RS antenna ports. From FIG. 5a-FIG. 5c, it can be seen that a Demodulation Reference Signal (DMRS) (Port 5 is configured to send the DMRS) configured for a Transmission Mode 7 (TM7) in Release 8 (R8) may collide with a CSI-RS, so that it is necessary to avoid scheduling a user of the TM7 in a subframe where the CSI-RS is sent. CSI-RS pattern designs in FIG. 5d-FIG. 5f are only applied to the frame structure type 2 (TDD), mainly for avoiding the DMRS (Port 5) configured for the TM7 in R8 to collide with the CSI-RS. A CSI-RS design in the system of the related technology adopts an orthogonal code division design with a length of 2 in a time domain, so that CSI-RSs of two antenna ports share 2 REs on the same subcarrier.
Configuration of a CSI-RS of up to 8 ports is supported only in the related technology, and how to implement configuration of a 16-port CSI-RS and perform CSI feedback on the basis of the 16-port CSI-RS becomes one of technical problems urgent to be solved.

CSI-RS configuration and CSI feedback method and apparatus, base station and user equipment

China Mobile Communications Group Co., Ltd.


A pipetting device comprising a probe for dipping into a reservoir, reaction vessel or the like, a metering pump connected to the probe and a shutoff valve disposed between the probe and the pump are provided. In the intake phase of the pump with the valve open, first air and then a predetermined quantity of liquid is intaken. For at least some of the delivery phase of the pump the valve is in the closed state so that a pressure builds up in the pump. At the end of the delivery phase the valve opens whereby due to the high pressure any adhering liquid particles are expelled.

A particular difficulty in the dispensing or pipetting of very small quantities of liquid concerns errors caused because parts of the liquid to be dosed or metered stick to the pipette probe and are not ejected. Errors of this kind are negligible when quantities are fairly large but become more serious in proportion as the quantities to be dosed or metered are smaller. Tiny drops sticking to the tip of the pipette probe cause considerable difficulties in modern analysis systems working with quantities of liquid of less than 30 .mu.l.
This is a familiar problem and many endeavars have been made to exclude this source of errors in the pipetting of very small quantities of liquid.
Unfortunately, all the proposed solutions are either insufficiently reliable or need very costly apparatus and in some cases there are contamination problems too.


A method for estimating restoration capacity for a communication network includes a specified number of restoration paths, which can be maximally diverse from each other.

Communication networks having some level of restoration capability to overcome failures and fiber cuts are well known in the art. One challenge with such networks is estimating the amount of restoration capacity needed which, in turn, requires a selection of restoration paths for all circuits. The choice of restoration paths balances the speed of restoration and the amount of restoration capacity deployed.
A failed circuit restores in the fastest amount of time if it finds sufficient capacity on the pre-stored protect path used by the switches. The protect path is typically the shortest path maximally diverse from the service path. If not, it has to crankback and repeatedly attempt to restore on newly calculated paths until one is successful. On the other hand, restoration capacity needs to be shared between unrelated failures or an excess amount of restoration capacity will be needed. Sharing may require that restoration paths other than the pre-stored protect path be used.
There are often multiple choices available for restoration paths for each circuit. In one known technique, the system allocates all capacity on the shortest maximally diverse path and essentially optimizes restoration performance at the expense of capacity. In another known technique, an integer programming formulation minimizes the amount of restoration capacity needed. This method essentially optimizes the cost of capacity and sacrifices restoration performance.
In addition, for any given service path, there can be numerous restoration paths available in the network. The system needs to select one of these multiple choices, and deal with the dimensionality explosion when there are hundreds of service paths. Thus, planning restoration capacity is challenging. Known methods can come up with widely varying estimates of restoration capacity and also propose capacity in different places in the network. The difficulty in estimating restoration capacity further increases if the network is evolving and new (better) restoration paths become available as more nodes and links are added.
It would, therefore, be desirable to overcome the aforesaid and other disadvantages.

Method of estimating restoration capacity in a network


A wireless communication device of the present invention receives a signal on a channel that another wireless communication device allocates to the wireless communication device from a plurality of channels. The wireless communication device includes: an update channel selector that selects a plurality of request channels that are candidates to be allocated to the wireless communication device from the channels, calculates a difference between a group of the request channels and a group of predetermined channels, and generates difference information indicative of the difference; and a multiplexer that multiplexes the difference information to a signal to be transmitted to the other wireless communication device.

Currently, demand for data communication is increasing in a mobile communication system. Various technologies achieving the high frequency utilization efficiency have been proposed with the increase in data communication.
One of the technologies capable of enhancing the frequency utilization efficiency is OFDMA (Orthogonal Frequency Division Multiple Access) in which a modulation scheme for communication is OFDM (Orthogonal Frequency Division Multiplexing) and an access scheme is TDMA (Time Division Multiple Access) or FDMA (Frequency Division Multiple Access). OFDMA is a communication scheme achieving higher-speed data communication while a common radio interface is used in both an isolated cell and a cell area.
In HSDPA (High Speed Downlink Packet Access) of a W-CDMA (Wideband-Code Division Multiple Access) mobile communication system, a scheduling method for an OFDMA system has been proposed in which a communication terminal device indicates a CQI (Channel Quality Indicator) for every subcarrier indicative of a downlink channel condition to a base station device so that the base station device performs packet scheduling based on the CQI for every subcarrier indicated by each communication terminal device (see, for example, Non-patent Document 1).
Similarly, an invention is disclosed in which a communication terminal device evaluates each downlink channel condition (frequency characteristics) upon scheduling of transmission data in an OFDMA system using multiple subcarriers and indicates the channel condition that is quantized to a base station device using an uplink feedback channel so that the base station device determines subcarriers to be allocated to each communication terminal device based on the indicated information (see, for example, Patent Document 1).
As a channel-quality feedback method for an OFDMA system, a method has been proposed in which a receiver selects multiple subcarriers having high channel qualities and indicates information indicative of the subcarriers and an averaged value of the channel qualities of the subcarriers to a transmitter so that the amount of feedback information is reduced to prevent overhead in reverse link from a communication terminal device to a base station device (see, for example, Patent Document 2).
Additionally, another method for an OFDM system has been proposed in which a receiver specifies carriers having bad channel qualities and indicates frequency information concerning the specified carriers or the numbers of the specified carriers to a base station so that the carriers having the bad channel qualities are not used (see, for example, Patent Documents 3 and 4).
Patent Document 1: Japanese Unexamined Patent Application, Fast Publication No. 2005-130491
Patent Document 2: Japanese Unexamined Patent Application, Fast Publication No. 2004-208234
Patent Document 3: Japanese Unexamined Patent Application, Fast Publication No. 2001-148682
Patent Document 4: Japanese Unexamined Patent Application, Fast Publication No. 2004-147068
Non-patent Document 1: "Comments on frequency scheduling and joint power and rate optimization for OFDM", 3GPP, TSG RAN WG1 Meeting #29, R-02-1321, November, 2002

Wireless communication device and wireless communication system


Embodiments of the present invention provide a method, system and computer program product for multi-variable challenge-response. In an embodiment of the invention, a method for multi-variable challenge-response can include receiving a request to access content from an end user computing device from over a computer communications network. The method also can include selecting different objects for inclusion in an object set and applying a different characteristic to each of the different objects in the object set. A question and answer can be generated based upon each of the different characteristics. Further, a challenge-response prompt can be transmitted to the end user computing device such that the prompt includes the different objects with different characteristics applied, and also the generated question. A response to the challenge-response prompt can be received and compared the response to the computed answer. Finally, access to the content can be granted if the response and computed answer match, but otherwise access to the content can be denied.

1. Field of the Invention
The present invention relates to the field of secure computing and more particularly to computer-human differentiation in secure computing.
2. Description of the Related Art
The advent of network computing and the global Internet has provided vast new opportunities for information sharing not previously possible. The global Internet in particular provides a vehicle through which unimaginable volumes of content can be shared with the public without regard to the geographic distance separating content publisher from content consumer. Notwithstanding, the availability of the widespread dissemination of content over the global Internet is not without consequence. In this regard, the use of the global Internet to distribute content often relies upon the good faith of content consumers that all will consume content on a fair and equal basis. Automated logic, however, can skew content consumption in favor of automated mechanisms at the expense of human consumers.
Specifically, bot technology permits rapid and repeated access to content at a pace orders of magnitude greater than a human end-user. In consequence, malicious agents can defeat the intent of content publishers publishing content intended for consumption by human end-users at a pace expected only of a human end user. The net result can include the over consumption of resources of the content provider and the unauthorized mining of content for purposes not authorized by the content provider.
To defeat the operation of bot technology accessing content intended for direct human consumption, various forms of reverse Turing tests have been contrived including tailored challenge-response tests. "CAPTCHA" is one such well-known challenge-response test in which the content publisher (or its proxy) challenges an end-user to state text rendered in a distorted manner within an image. Presumably, an automated process cannot recognize the text due to its distortion. Yet, a human end user can adequately recognize the text and respond in kin in a minimally burdensome manner. Thus, CAPTCHA aids in differentiating a computer response from a human response.
CAPTCHA technologies such as that described in U.S. Patent Application Publication US 2007/0124595 by Carter et al. (Carter) for METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ACCESS CONTROL, provide for the advanced ability of dynamically selecting CAPTHCA images for display during an access control process to add a layer of complexity in the CAPTCHA process. For example, as described in Carter, an image for CAPTCHA can be generated according to provided meta-data—namely image attributes—such as a gender of an image of a person, or a dimensionality of a shape. Using the meta-data, the CAPTCHA image can be produced and used during the access control process.
Of note, alternatives to CAPTCHA include prompting end users to engage in manually interactive processes such as drawing with a pointing device about a designated region of a display screen or display element. A well-known alternative common to the financial services industry includes presenting to an end user a series of pictures that are to be selected in accordance with an associated keyword. In all circumstances, however, a reasonable probability remains that an automated bot can correctly "guess" a response to a challenge to defeat the intent of the challenge-response exercise. Even still, to reduce the probability of a correct guess to a challenge-response exercise can frustrate the end user with an overly complicated process.

Multi-variable challenge and response for content security

International Business Machines Corporation


Provided are binuclear organometallic complexes enabling highly efficient phospholuminescence and an organic electroluminescent device using the same. The binuclear organometallic complexes, which are suitably used for forming an organic layer of the organic electroluminescent device, provides maximum luminescence emission in the wavelength range of 400-650 nm, and induces white electroluminescence when combined with green or red luminescent materials.

1. Field of the Invention
The present invention relates to the binuclear organometallic complexes and organic electroluminescence devices using the same, and more particularly, to binuclear organometallic complexes capable of emitting light of wavelengths from the blue range to the red range from the triplet metal-to-ligand charge transfer (MLCT) state and an organic electroluminescence device using the same as the emitting layer forming material.
2. Description of the Related Art
Generally, an organic electroluminescent device (hereinafter referred to as EL) may include an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode. These layers may be sequentially formed on a substrate. The hole transport layer, the light-emitting layer, and the electron transport layer may be organic layers made of organic compounds. The organic electroluminescence device having the above-described configuration may be driven as follows.
When a voltage is applied between the anode and the cathode, holes injected from the anode migrate to the light-emitting layer via the hole transport layer. Electrons emitted from the cathode are injected into the light-emitting layer via the electron transport layer. The electrons and the holes recombine in the light-emitting layer to generate excitons. As the excitons transition from an excited state to a base state, energy is transferred to luminescent molecules in the light-emitting layer, enabling the molecules to emit light and display images.
Materials for forming the light-emitting layer of the organic EL device may be classified as fluorescent materials that use a singlet or phosphorescent materials which use a triplet. The fluorescent material or the phosphorescent material or the material in combination with an appropriate host material may form a light-emitting layer. As a result of electron excitation, singlet excitons and triplet excitons are produced in the host. Statistically, the singlet excitons and the triplet excitons in an OLED are created in a ratio of about 1:3.
Conventional organic EL devices that us a fluorescent material as a material for forming a light-emitting layer may be disadvantageous in that triplets from the host may be wasted. However, organic EL devices using a phosphorescent material as a material for forming a light-emitting layer are advantageous in that singlet excitons and triplet excitons are both utilized. Such phosphorescent materials can use all of the 75% triplet excitons for emission and offers higher luminescent efficiency compared to fluorescent materials using only 25% singlet excitons for emission.
Various phosphorescent materials employing metallic complexes of Iridium or platinum as luminescent materials using triplet excitons have been discussed. However, materials satisfying requirements for realizing a full-color display of high emission efficiency or white electroluminescence with low power consumption have been restricted to ones emitting in the green and red ranges. Blue phosphorescent materials, however, have not been reported, making it difficult to achieve a full-color display, which is, in turn, becoming a barrier to the development of phospholuminescent full-color display devices.
To address the above-described problems, intensive development of blue luminescent materials is under way (See, for example, WO 02/15645 and U.S. Patent Pub. No. 2002/0064681). Also, there have been proposed organometallic complexes having a bulky functional group, e.g., a phosphine group, or a functional group having a high ligand field intensity, e.g., a cyano group, introduced thereto to increase a difference between HOMO-LUMO energy levels by transforming the molecular geometry. Specific examples of the organometallic complexes include iridium (III) complexes having cyclometalating phenyl pyridine and a phosphine group. The iridium (III) complexes are mononuclear complexes having the general formula of Ir(ppy)2P(X)3Y (X=phenyl, phenoxy or n-butyl, Y=Cl or CN.), as described in US2002/0048689 A1.

Binuclear organometallic complexes and organic electroluminescence device using the same


Methods and systems for determining extracellular concentration data of an analyte are disclosed. A method for determining extracellular concentration data of an analyte includes receiving sensor data from one or more arrays of functionalized plasmonic nanostructures on a localized surface plasmon resonance imaging chip in contact with a fluid containing at least one living cell for a plurality of times, determining intensity data for the one or more arrays, determining fractional occupancy based on the intensity data, and determining extracellular concentration data based on the fractional occupancy data. A system for determining extracellular concentration data of an analyte includes a LSPRi chip, a sensor component, an intensity component, a fractional occupancy component, a concentration component, and a processor to implement the components.

Aspects of the exemplary embodiment relate to detection of analytes in a fluid and find particular application in connection with the detection of extracellular proteins using nanoplasmonic sensors.
From bacterium to eukaryote, a cell's fate is directly tied to its local chemical environment. The measurement of external protein concentrations and gradients by membrane bound receptors is useful in the study of cell differentiation, motility and proliferation. Such dependencies have been deduced by introducing artificial gradients to cell cultures. However, direct measurements of the spatio-temporal concentrations of analytes, which cells themselves produce via secretion, have remained elusive.
One roadblock has been the lack of an assay that can measure extracellular protein concentrations in real time without disrupting the signaling pathways of interest. This real time, non-invasive requirement severely limits the techniques that can be employed, including common fluorescent labeling methods. For example, while fluorescent fusion proteins have been useful in the study of intracellular protein measurements, the technique does not lend itself to extracellular signaling. A tag, such as green fluorescent protein (GFP) tag of about 27 kDa, for example, may compromise the labeled protein's ability to navigate the complexities of the secretory pathway (Wiedenmann et al., "Fluorescent Proteins for Live Cell Imaging: Opportunities, Limitations, and Challenges," lubmb Life 61(11):1029-1042 (2009); Costantini, et al., "Fluorescent Proteins in Cellular Organelles: Serious Pitfalls and Some Solutions," DNA Cell Biol. 32(11):622-627 (2013)).
Even if the proteins are successfully secreted, the result is a diffuse fluorescent glow outside the cell which is difficult to quantify. Fluorescently-labeled antibodies used for immunosandwich assays have been successfully introduced outside of live cells to measure secretions (Bailey, et al., "DNA-encoded antibody libraries: A unified platform for multiplexed cell sorting and detection of genes and proteins," J. Am. Chem. Soc. 129(7):1959-1967 (2007); Han, et al., "Polyfunctional responses by human T cells result from sequential release of cytokines," Proc. Natl. Acad. Sci. U.S.A. 109(5):1607-1612 (2012); Shirasaki, et al., "Real-time single-cell imaging of protein secretion," Scientific Reports 4 (2014)). However, the addition of these relatively large probes (typically 150 kDa) is an impediment to downstream signaling and the techniques typically involve isolating individual cells. In both examples, the ability to establish causal relationships between secreted protein concentrations and cell fate, whether the signaling be autocrine, paracrine or endocrine in nature, is hampered by the probes themselves.
Solid-state nanosensors have the potential to overcome this impasse. Probes such as nanodiamonds and metallic nanostructures are biocompatible, do not suffer from photobleaching and, advantageous from the protein secretion perspective, are label-free techniques. Nanodiamond sensors are highly sensitive magnetic field detectors resulting from nitrogen vacancies, which makes the technique particularly applicable to detecting metalloproteins (Horowitz, et al., "Electron spin resonance of nitrogen-vacancy centers in optically trapped nanodiamonds," Proc. Natl. Acad. Sci. USA. 109(34):13493-13497 (2012); Ermakova, et al., "Detection of a Few Metallo-Protein Molecules Using Color Centers in Nanodiamonds," Nano Lett. 13(7):3305-3309 (2013)). Metallic nanoparticles exhibit a localized surface plasmon resonance (LSPR) which is sensitive to changes in the local refractive index of the surrounding medium. Their surfaces can be biofunctionalized for the detection of proteins, lipids, and DNA in cell-free environments (Sepulveda, et al., "LSPR-based nanobiosensors," Nano Today 4(3):244-251 (2009); Mayer, et al., "A single molecule immunoassay by localized surface plasmon resonance," Nanotechnology 21(25) (2010); Haes, et al., "A nanoscale optical blosensor: Sensitivity and selectivity of an approach based on the localized surface plasmon resonance spectroscopy of triangular silver nanoparticles," J. Am. Chem. Soc. 124(35):10596-10604 (2002); Nusz, et al., "Label-free plasmonic detection of biomolecular binding by a single gold nanorod," Anal. Chem. 80(4):984-989 (2008); Jonsson et al., "Supported lipid bilayer formation and lipid-membrane-mediated biorecognition reactions studied with a new nanoplasmonic sensor template," Nano Lett. 7(11):3462-3468 (2007); Dahlin, et al., "Specific self-assembly of single lipid vesicles in nanoplasmonic apertures in gold," Adv. Mater. 20(8):1436-1422 (2008); Endo, et al., "Label-free detection of peptide nucleic acid-DNA hybridization using localized surface plasmon resonance based optical biosensor," Anal. Chem. 77(21):6976-6984 (2005); Lo, et al., "Monitoring of DNA-protein interaction with single gold nanoparticles by localized scattering plasmon resonance spectroscopy," Methods 64(3):331-337 (2013)). In addition, LSPR optical configurations are readily integrated with standard wide-field microscopy setups which have enabled the detection of protein secretions in the presence of thousands of cells, as well as real-time single cell secretions (Oh, et al. "Integrated Nanoplasmonic Sensing for Cellular Functional Immunoanalysis Using Human Blood," ACS Nano 8(3):2667-2676 (2014); Endo et al., "Label-free cell-based assay using localized surface plasmon resonance biosensor," Anal. Chim. Acta 614(2):182-189 (2008); Raphael et al., Quantitative Imaging of Protein Secretions from Single Cells in Real Time. Biophys. J. 105(3):602-608 (2013)). However, measuring extracellular protein concentrations in both space and time, for modeling and quantifying of signaling pathways, has remained a challenge (Kolitz, et al., "Measurement and Modeling of Signaling at the Single-Cell Level," Biochemistry 51(38):7433-7443 (2012)).
Additionally, methods using spectrometry-based techniques are severely restrictive in that they only allow for a single array's response to be quantified, and the spectrometer requires a lot of light and significant exposure time, which could be harmful to live cells.
Thus, it would be desirable to have a method and system for measuring extracellular analyte concentrations in space and time, without the need for use of fluorescent tagging and without the need to use a spectrometer.

Determining extracellular analyte concentration with nanoplasmonic sensors

The Government of the United States of America, as represented by the Secretary of the Navy


The instant invention refers to an antibacterial peptide with all amino acids in D-configuration, possessing strong antimicrobial activity against Gram-negative and Gram-positive bacteria and Candida strains. The peptide can be in linear form multimerised on a skeleton of polyacrylamide, of dextrane units or on a skeleton of ethylene glycol units. The peptide is resistant proteolysis especially when synthesized in the tetra-branched form where identical peptide sequences are linked together by an appropriate molecular scaffold.

The growing emergency of multi-drug resistant-bacteria is a global concern, mostly in those countries where antibiotics are widely used in clinics. A number of pathogens like Staphylococcus aureus, Staphylococcus epidermidis, Mycobacterium tuberculosis, some enterococci, Pseudomonas aeruginosa and many other bacteria have developed resistance against most traditional antibiotics as well as against those of new generation (Wenzel and Edmond 2000). It has therefore become increasingly important to develop new antibiotics. This demand urges the community of researchers and the pharmaceutical companies to consider new antimicrobial agents. Antimicrobial peptides are considered one of the best alternative to traditional antibiotics which generally cause the selection of resistant bacteria (Hancock and Sahl, 2006). Most antibacterial peptides are components of the innate immunity of animals, including humans, plants and fungi (Zasloff, 2002). They usually consist of 6-50 amino acid residues and have a positive net charge. Cationic peptides interact selectively with anionic bacterial membranes and with other negatively charged structures such as LPS and DNA. Eukaryotic membranes, in their external layer, are normally less negatively charged than bacteria's, and, differently from bacterial membrane, they are also stabilized by cholesterol molecules. These differences are the basis of cationic peptides' specificity. The mechanism of action of cationic antimicrobial peptides is consequently due to their specific binding to bacterial membranes, which provokes cell permeation and, in some cases, metabolic pathways inhibition.
Many studies then, aimed to the identification and characterization of antimicrobial peptide sequences by studying their mechanism of action, their toxicity for eukaryotic cells and their therapeutic efficacy when administered topically or systemically. Unfortunately, two main problems hindered the development of antimicrobial peptide drugs so far. The first is that selectivity of natural antimicrobial peptides for bacteria is generally too low and they appear to be very toxic for eukaryotic cells, particularly erythrocytes, generating a high level of haemolysis. The second is linked to the generally short half-life of peptides in vivo. These are the main reasons for which only few cationic peptides reached the market in the last 10 years (polymyxin and daptomycin are two successful examples).
A few years ago, researchers began to concentrate on the identification of novel peptide sequences of non-natural origin, selected in the laboratory by rational design or screening of combinatorial libraries. The aim was to find peptides with better biological properties in terms of general toxicity and specificity for bacteria and improved half-life for drug development.
In the inventors' laboratory, non-natural peptide sequences were identified, which showed a strong antimicrobial activity especially against Gram-negative bacteria (Pini et al, 2005; Pini et al., 2007; Pini et al., 2010). The last improved version of these peptides was called M33 (sequence KKIRVIRLSA, SEQ ID NO: 1; WO 2010/038220 A1) and it was tested in vitro for its capability to neutralize bacterial LPS and in vivo for its antibacterial and anti-inflammatory activity in sepsis animal models (Pini et al., 2010). Peptide M33 appeared selective for Gram-negative bacteria with a slight activity against only two strains of the Gram-positive Staphylococcus aureus. The peptide M33 was used and described in Pini et al., 2010 and in WO2010/038220A1 always with amino acids in L configuration (L-M33). Surprisingly, the synthesis of the same peptide sequence wide all the amino acids in D-configuration (D-M33) produced not only a better activity for some Gram-negative bacteria but also a strong activity against a panel of Gram-positive bacteria and fungi for which the L-M33 was not active at all. This result is completely unexpected, in that substitution of L-amino acids with their D configuration is known to increase peptide stability but the effect on peptide selectivity was not predictable.

Antimicrobial peptide, branched forms thereof and their use in the treatment of bacteria infections


A switched node for use in a multi-dimensional switched fabric network is disclosed. The switched node comprises adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data, and each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchronous-to-isochronous converter converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets.

1. Field of the Invention
The present invention relates to computer networks. More particularly, the present invention converts asynchronous packets into isochronous packets for transmission through a multi-dimensional switched fabric network.
2. Description of the Prior Art
Data transmitted through a computer network includes asynchronous or xe2x80x9cbest-effortxe2x80x9d data and isochronous or xe2x80x9ctime-constrainedxe2x80x9d data. Asynchronous data is injected into the network at arbitrary intervals and forwarded to a destination node within an unconstrained (best-effort) time interval. An example of asynchronous data is transaction data transmitted between an end user and a service provider (e.g., a web site). Isochronous data, in contrast, is typically injected into the network at a periodic interval and forwarded to a destination node within a predetermined time-constrained interval. An example of isochronous data is a video stream which must be transmitted to an end user at a guaranteed periodic interval to facilitate uninterrupted viewing.
Details of a prior art method for transmitting best-effort and time-constrained data through a multi-dimensional switched fabric network are disclosed by Jennifer Rexford, et al. in xe2x80x9cA Router Architecture for Real-Time Communication in Multicomputer Networksxe2x80x9d, IEEE Transactions on Computers, Vol. 47, No. 10, October 1998, which is incorporated herein by reference. Rexford suggests to implement a switched node using a data structure (a queue or virtual cache) for best-effort data and a separate data structure (another queue or virtual cache) for time-constrained data. Rexford also suggests to prioritize virtual lanes so that on-time time-constrained data is transmitted through the switch ahead of any pending best-effort data. However, the additional hardware support needed to handle best-effort data using a separate data structure increases the complexity and cost of the switch. In addition, giving absolute priority to time-constrained data can degrade the performance of the network with respect to best-effort data, which may be undesirable. Further, it is not possible to control the variance in transmitting best-effort data if it is always transmitted subordinate to time-constrained data. Best-effort data may also subject the network to deadlock, a condition where a packet cannot advance toward the destination node because the buffers (or other resources) in the path cannot be allocated to transmit the packet.
There is, therefore, a need to improve performance of a multi-dimensional switched fabric network for both isochronous (time-constrained) as well as asynchronous (best-effort) data. In particular, there is a need to simplify the circuitry within each switched node, to mitigate blocking of asynchronous data by isochronous data, to control transmission variance, and to mitigate deadlock.
The present invention may be regarded as a switched node for use in a multi-dimensional switched fabric network. The switched node comprises adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data, and each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchronous-to-isochronous converter converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets. A plurality of bi-directional ports receive isochronous packets from other switched nodes and transmit isochronous packets to other switched nodes. A data buffer stores the isochronous packets received from the bi-directional ports, the isochronous packets received from the adapter circuitry, and the isochronous packets comprising the asynchronous data. Routing circuitry selects at least one of the bi-directional ports to output the stored isochronous packets, and assigns a departure time parameter to each of the stored isochronous packets. A scheduler, responsive to the target arrival times and the departure times, schedules the transmission of the stored isochronous packets through at least one of the bi-directional ports
In one embodiment, the asynchronous-to-isochronous converter comprises a microprocessor for reserving a path through the network for transmitting the isochronous packets comprising the data from the asynchronous packets. In one embodiment, the path is reserved by routing a request packet through the switched fabric between the source and destination nodes, wherein resources are reserved along the path of the request packet. In another embodiment, the microprocessor schedules the transmission of the isochronous packets comprising the data from the asynchronous packets. In yet another embodiment, the switched node further comprises an isochronous-to-asynchronous converter for converting isochronous packets comprising asynchronous data into asynchronous packets for transmission by the adapter circuitry to the external entity.
The present invention may also be regarded as a multi-dimensional switched fabric network comprising a plurality of interconnected switched nodes. A select number of the switched nodes comprise adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data. Each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchrbnous-to-isochronous converter within the switched nodes converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets. The switched nodes comprise a plurality of bi-directional ports for receiving isochronous packets from other switched nodes and for transmitting isochronous packets to other switched nodes. A data buffer within the switched nodes stores the isochronous packets received from the bi-directional ports, the isochronous packets received from the adapter circuitry, and the isochronous packets comprising the asynchronous data. Routing circuitry within the switched nodes selects at least one of the bi-directional ports to output the stored isochronous packets, and stores a departure time parameter for each of the stored isochronous packets. A scheduler within the switched nodes, responsive to the target arrival times and the departure times, schedules the transmission of the stored isochronous packets through at least one of the bi-directional ports.
The present invention may also be regarded as a multi-dimensional switched fabric network comprising a plurality of interconnected switched nodes and an input for receiving asynchronous and isochronous packets from host initiators. Each asynchronous packet comprises destination node routing information and data. Each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into each switched node, and data. A central microprocessor converts the received asynchronous packets into isochronous packets comprising the data from the asynchronous packets. Each switched node comprises a plurality of bi-directional ports for transmitting the received isochronous packets and the isochronous packets comprising the data from the asynchronous packets through the network. A data buffer stores the received isochronous packets and the isochronous packets comprising the data from the asynchronous packets. Routing circuitry selects at least one of the bi-directional ports to output the stored isochronous packets. The routing circuitry also stores a departure time parameter for each of the stored isochronous packets. A scheduler schedules, responsive to the target arrival times and the departure times, schedules the transmission of the stored isochronous packets through at least one of the bi-directional ports.
In one embodiment, the central microprocessor reserves a path through the network for transmitting the isochronous packets comprising the data from the asynchronous packets. In one embodiment, the path is reserved by routing a request packet through the switched fabric between the source and destination nodes, wherein resources are reserved along the path of the request packet. In another embodiment, the central microprocessor schedules the transmission of the isochronous packets comprising the data from the asynchronous packets. In yet another embodiment, the central microprocessor converts isochronous packets comprising asynchronous data received from the switched nodes into asynchronous packets transmitted to the host initiators.
The present invention may also be regarded as a method of transmitting asynchronous and isochronous packets through a multi-dimensional switched fabric network comprising a plurality of switched nodes. An asynchronous packet is injected into the switched fabric network, wherein the asynchronous packet comprises destination routing information. An isochronous packet is also injected in to the switched fabric network, wherein the isochronous packet comprises a path ID corresponding to a reserved path through the network, and a target arrival time parameter identifying a target arrival time of the isochronous packet into a selected one of the switched nodes. The asynchronous packet is converted into an isochronous packet comprising the data from the asynchronous packet, and the injected isochronous packet and the isochronous packet comprising the data from the asynchronous packet are stored in a data buffer. Departure time and routing information is stored within each switched storage node corresponding to the injected isochronous packet and the isochronous packet comprising the data from the asynchronous packet. The transmission of the stored isochronous packets through the switched nodes is scheduled based on the target arrival times and the departure times.
In one embodiment, the method further comprises the step of reserving a path through the switched fabric network for the isochronous packet comprising the data from the asynchronous packet. In another embodiment, the method further comprises the step of converting the isochronous packet comprising the data from the asynchronous into an asynchronous packet.

Converting asynchronous packets into isochronous packets for transmission through a multi-dimensional switched fabric network


The present disclosure relates to piezoelectric compositions of Formula I comprising Lead Zirconate—Lead Titanate solid solution. The disclosure further relates to a method of obtaining said composition, method of preparing/fabricating piezoelectric component(s) and piezoelectric component(s)/article(s) obtained thereof. The piezoelectric composition and articles of the present disclosure show excellent electromechanical characteristics along with very large insulation resistance (IR).

Piezoelectricity is referred as the electric charge that accumulates in certain solid materials (such as crystals, certain ceramics etc.) in response to applied mechanical stress. In general, 'piezoelectricity' means electricity resulting from application of pressure and vice-versa and has useful applications such as in the production and detection of sound, generation of high voltages, electronic frequency generation, microbalances, to drive an ultrasonic nozzle, and ultrafine focusing of optical assemblies.
Piezoelectric compositions have been widely investigated and used in a variety of piezoelectric components like transducers, ultrasonic receivers, generators etc. Consequently, the use of piezoelectric ceramic compositions to form piezocomponents is increasing. Piezoelectric compositions having higher electromechanical coupling efficiency (kp>0.56), mechanical quality factor (Qm>500) and low dielectric loss (tan δ≤0.004) are in great demand for high power applications. Piezoelectric components for transducers demand piezoelectric compositions that can also yield enhanced insulation resistance, IR≥10 GΩ. Existing high power piezoelectric ceramics do not simultaneously exhibit suitable electromechanical properties and high insulation resistance. In the current state of art, the existing piezoelectric components that exhibit sufficiently high electromechanical characteristics have low insulation resistance, usually ≤10 GΩ, which is not adequate especially for high power transducer applications.
The piezoelectric properties of piezoelectric elements can be varied by addition of certain foreign constituents. Sintering cycles and poling process have an effect on fabrication of piezoelement of desired physical properties and electromechanical characteristics. However, it is difficult to optimise these processes to fabricate specific piezoceramic components having desired electromechanical characteristics as well as high IR. In other words, it is technically very difficult to prepare a piezoelectric component through a known set of process parameters. Therefore, the development of new piezoceramic composition and its intended application often demand practising of a different fabrication method because processing methods can have influence on the physical and electromechanical characteristics of piezoceramics.
As piezoelements are sought after in various applications, the demand for new piezoelectric compositions and piezoelectric components derived from them is very important. However, the need of the hour is that the piezoelectric compositions and the corresponding piezocomponents must possess improved insulation resistance along with high electromechanical characteristics.
U.S. Pat. No. 3,376,226 claims piezoelectric ceramic composition having a solid solution of lead-zirconate titanate-stannate modified by adding thorium oxide and chromium oxide improving electro mechanical coupling factor(kp˜0.59) and providing mechanical quality factor (Qm˜400).
U.S. Pat. No. 3,268,453 relates to piezoelectric ceramic compositions of ternary and binary systems containing solid solutions of PMN-PT-PZ modified by additional constituents and articles of manufacture fabricated therefrom. In addition, several patents such as U.S. Pat. Nos. 3,546,120, 3,649,540, 3,890,241 relate to piezoceramic compositions having piezoelectric properties meeting the specific application fields of transducers, sensors etc.
It is clear from the above discussion that piezoceramic compositions are known in the art for various applications. However, the simultaneous requirements of high insulation resistance and improved electromechanical characteristicsare not met by the piezocomponents of the prior art. Accordingly, there has been a continuing need in the art to provide better and significantly improved piezoceramic systems having high values of electromechanical coupling efficiency and mechanical quality factor along with very large insulation resistance in component form. The present disclosure aims at overcoming the aforesaid drawbacks of the prior art.

Piezoelectric composition, methods and applications thereof

Department of Electronics and Information Technology

Centre for Materials for Electronics Technology


Devices and methods to assist wire arc additive manufacturing (WAAM) are provided. A non-contact, multidirectional synchronized ultrasonic device can include multiple ultrasonic probes mounted on a nozzle of a WAAM robotic arm. The probes can include one normal probe and a plurality of lateral probes configured to rotate on a parabolic frame. The ultrasonic probe in the normal direction can act by its continual high-frequency oscillation in the arc plasma to enhance the arc push force, while the lateral probes can act on the shape of both sides of the deposit. The combined effect of the probes can generate ultrasonic waves and cavitation in the molten pool.

Wire arc additive manufacturing (WAAM) is a technique used to produce metal components by melting and depositing a wire layer by layer, maneuvered by a controlled robotic arm. This process leads to an inherent buildup of heat and a slow cooling rate, resulting in the formation of large, millimeter-sized grains in the component. In order to manufacture parts with high strength, it is necessary to refine the grain size such that higher grain boundary area or volume can resist deformation.

Multidirectional synchronized ultrasonic devices and methods for assisting wire arc additive manufacturing

THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES


The invention concerns a method of providing resource admission control to packet flows (11, 12, 50) associated with sessions in a communication network (2), and an access controller (21, 22) to execute this method. The communication network (2) handles packets according to priority levels assigned to the packets. The priority levels comprise at least a first and a second priority level wherein the first priority level is higher than the second priority level. First, a packet flow (12) associated with the new session is identified when packets of the packet flow (12) enter the communication network (2). Preferably, the new session is a real-time session. The second priority level is assigned to the identified packet flow and the packet flow (12) is handled according to the second priority level within the communication network (2). A congestion level is measured in the communication network (2). If the measured congestion level stays below a predefined threshold, the priority level of the packet flow (12) associated with the new session is upgraded from the second priority to the first priority within the communication network (2). Once upgraded, the packet flow (12) is handled according to the first priority level within the communication network (2) until the packet flow (12) is terminated.

The present invention is based on a priority application EP 06 291 097.1 which is hereby incorporated by reference.
The present invention relates to a method of providing resource admission control to a packet flow in a communication network, and an access controller to execute said method.
As IP networks are increasingly used to transport real-time, in-elastic traffic with hard QoS (=Quality of Service) guarantees, appropriate traffic management becomes increasingly challenging (IP=Internet Protocol). Proactive traffic management schemes rely on RAC (=Resource Admission Control) for new sessions that have to be set up. The aim of RAC is to determine if the network can carry the new session at the appropriate QoS without impacting the QoS specifications of already ongoing real-time sessions. Especially the latter is of extreme importance in IP networks as in the (pre-dominantly used) diffserv-like model, a new session that is admitted to run at the highest QoS class level while there are not sufficient resources in the network to sustain that session, will not only be adversely affected by that lack of resources, but will also impact the other sessions running at the same QoS class level.
Current envisaged solutions either assume that the network is dimensioned in a way that no problems can arise, or rely on a central resource manager having a (theoretical) model of the available resources in the network, and which is queried for acceptance on each new session set-up, e.g. TISPAN RAC Functions and Architecture (TISPAN=Telecoms & Internet converged Services & Protocols for Advanced Networks).
The assumption of over-dimensioning the network is not realistic for a variety of reasons, such as: with the ever growing amount of traffic, it is not trivial to assure that there will be always enough resources in the network to avoid any congestion problems. Even if the average traffic would be predictable, mass events such as tele-voting will cause peaks of traffic in which problems will occur. For economical reasons, access and aggregation networks are not non-blocking and will cause traffic congestion if no measures are taken.
In the model with a central resource controller, the central entity has to be queried to accept or deny each new session request. This leads to the following drawbacks. Increased complexity and increased latency in session set-up: the signalling flow for setting up the session must be interleaved with the resource queries to the resource controller, adding to the end-to-end set-up delay (Multiple round-trip signalling plane interactions).
Another drawback is that a failure of access to the central resource controller services leads to unavailability of the service. As no resources can be granted, all new sessions will be rejected.
Still another drawback is that the resource controller uses a (pre-configured) model of the network resources upon which it grants or refuses new session requests (resource counting). A change in network topology, maintenance activities, or network link failures require a change to the model, which is not updated in real-time. This makes the network resource controller work with a model that does not fit reality for a certain amount of time.
Another drawback is that RAC-based solutions can lead to underutilization of available network capacity as an application will tend to reserve more resources than effectively needed, as, e.g. with non-CBR traffic based services (CBR=Constant Bit Rate).

Method of providing resource admission control


A method of asynchronously transmitting data from a first clock domain to a second clock domain by transmitting the data from the first domain to a first register; after a first period of time, transmitting the data from the first register to a second register; after a second period of time, transmitting the data from the second register to a third register; and after a third period of time, transmitting the data from the third register to the second clock domain, where the first clock domain operates at a first frequency C1, and the second clock domain operates at a second frequency C2, C1 being faster than C2; and where: the first period of time is determined by C1; and the second and third periods of time are determined by a third frequency C3 that is greater than and a whole number multiple of C2.

1. Field of the Invention
This invention generally relates to data transfer between asynchronous clock domains, and more specifically, to reducing the latency in such data transfers.
2. Background Art
Asynchronous data transfers have become very common in many integrated circuit devices, such as ASICs and SoCs, today. In particular, various components or subsystems utilized for the construction of an integrated circuit may independently operate at different frequencies, such as in microprocessors and micro-controllers, where certain components or subsystems have a faster rate of operation than the operating frequencies of other system components or subsystems. Therefore, typically, it is desirable to devise integrated circuits with the ability to support multiple domains, which may operate at different frequencies.
For instance, many integrated circuits include a number of electronic circuits referred to as "clocked logic domains" that operate independently based on electrical "timing" or "clock" signals. Such clock signals are used to control and coordinate the activities of various components or subsystems.
A particular device interface, or bus operating at a specific frequency, may define a distinct clocked logic domain. A variety of clocked systems may include one or more clock synthesizers, clock controllers or timers, such as a real time clock generator, an operating system timer, or an analog to digital converter controller that may require synchronizing transfer of multiple bits of data between asynchronous clock domains. However, synchronization of data transfer, particularly between various clocked logic domains, presents a number of problems.
While transferring digital data or signals between multiple clocked logic domains in a clocked system, one problem involves synchronization, such as by using storage elements or other hardware so that the timing of the digital data or signals transmitted is properly aligned at the receiving end. In doing so, the data or signals being transferred from one clocked logic domain may be delayed by one or more clock cycles so that the data or signals may be synchronized with the clock signals in another clocked logic domain, as an example. However, providing such synchronization may cause undesirable and sometimes unpredictable delays in the communications path or the data path. This may result in significant performance degradation and/or lack of data or signal integrity.
Since there will not be a fixed relationship between the active edge of the launch clock and the capture clock, there is a possibility of having setup or hold violations in the capture flip-flop, causing meta-stability. To avoid meta-stability in asynchronous data transfer, a commonly adopted technique is to double latch (also called double stage synchronization, or double flopping) the clock domain crossing signal at the receive domain clock frequency. Double flopping involves passing an asynchronous signal(s) through a pair of edge triggered D-Flip-flops or some equivalent storage element. If the receiving clock frequency is considerably less than the transmitting clock frequency, there is a huge latency involved in the double flopping process, often up to 20 or more clock cycles in the higher frequency domain. This situation frequently arises with slower devices, like a Flash Memory controller, being used in ASICs that have a majority of the components running at a much higher clock frequency.
Any reduction in the clock domain-crossing overhead tremendously reduces the data transfer latencies and increases the overall system performance.

Method of asynchronously transmitting data between clock domains


A backrest for a motor vehicle seat has a head restraint that is height adjustable with the aid of a guide. A transverse strut connected fixedly at an upper region of the backrest. The guide has a guiding device that is attached fixedly to the transverse strut and guides a guiding element that is attached to and integrated in the head restraint. The guide (22) is assigned a locking unit (50), with a first locking part (51) that is fastened to the transverse strut (18), and a second locking part (52) that is fastened to the head restraint (4). The two locking parts (51, 52) interact according to a latch and hole principle.

1. Field of the Invention
The invention relates to a backrest for a motor vehicle seat with a head restraint that is height adjustable.
2. Description of the Related Art
DE 20 2009 013 635 U1 discloses a head restraint that is height adjustable manually by means of a latching rod that interacts with an adjustable catch. The backrest of the vehicle seat that supports the head restraint has two guide rods. One end of each guide rod is fixed in the backrest and the other ends are connected to each other by a yoke. The head restraint slides along the guide rods when the head restraint is adjusted in height manually. However, there is the problem in that the lower region of the head restraint has two holes from which the guide rods emerge. In addition, depending on the latching position of the head restraint, guide rod sections that differ in length are visible. An esthetically satisfactory solution therefore is not produced.
DE 32 23 649 C2 discloses a head restraint with additional arms. Each arm holds a rod on which bearings are provided and the bearings slide along the rods during displacement of the head restraint. This constitutes a structurally complicated solution.
The assignee of the subject invention also is the assignee of DE 10 2010 060 076.8. This earlier application is not prior art, but discloses a backrest with an aesthetically satisfactory solution to the height adjustment of the head restraint. However, only motorized adjustment possibilities are provided here.
It is therefore the object of the invention to provide the backrest an aesthetically attractive, functional, manually adjustable head restraint.

Dr. Ing. h.c. F. Porsche Aktiengesellschaft


A dark box which has at least one sealable opening and whose internal chamber can be divided into a desired number of compartments for stacks of identical or differently dimensioned and/or shaped sheets of exposed radiation sensitive material such as X-ray films, photographic paper, photographic film or others. The dark box can be inserted into the dark room of an apparatus which is designed to simultaneously withdraw two or more sheets from the inserted dark box and to transport the withdrawn sheets toward or into a developing machine of the type capable of simultaneously processing two or more rows of sheets. If the machine must be confined in a dark chamber, the apparatus is equipped or combined with an adapter which prepares simultaneously withdrawn sheets for admission into the developing machine.

The invention relates to improvements in so-called dark boxes, namely to improvements in receptacles or containers from which light or certain other radiation (hereinafter referred to as light) is wholly excluded and which are used to store radiation sensitive photographic and analogous equipment, for example, films, plates and/or paper (hereinafter called light sensitive sheets). Such dark boxes are also called cassettes or magazines.
X-ray equipment is used in many fields including medicine as well as various industries, particularly for nondestructive testing of materials and/or products. Such equipment employs sheets which carry coatings of photosensitive material. When the exposure of a sheet to a required amount of radiation is completed, the thus obtained latent image must be developed in a suitable developing machine. To this end, the exposed but undeveloped sheets are inserted into a dark box within the confines of a darkroom and the dark box is closed and sealed when it receives a desired (e.g., maximum) number of exposed sheets so that the thus closed and sealed dark box can he transported to a developing machine. A dark box which is ready to be relieved of its contents is coupled with a so-called feeder which withdraws discrete sheets, one after the other, and introduces them into the developing machine.
A drawback of presently known dark boxes is that each such receptacle or container is designed to accept exposed sheets of a particular size and shape. Thus, it is necessary to maintain a supply of dark boxes each of which can he used to store exposed sheets of a given size and shape. This contributes to the cost and to space requirements of the equipment, irrespective of whether the sheets are used to receive latent images of parts of human or animal bodies or latent images of inanimate objects in a manufacturing plant or the like. Dark boxes of different sizes are provided with discrete codes which are read by the feeder in order to avoid introduction of sheets into wrong developing machines. In spite of the provision of coded dark boxes, the feeder is likely to make mistakes and to introduce exposed but undeveloped light sensitive sheets into wrong developing machines. Each such error must be corrected (if possible) in a dark room with attendant loses in time, or the sheet which was withdrawn from a dark box is likely to be exposed to light on its way to the developing machine with attendant damage to or total eradication of the latent image. On the other hand, it is normally desirable to rapidly develop the latent images, e.g., in a hospital or in a similar establishment so that the physician or another person in charge can receive an exposed latent image as expeditiously as possible. The same holds true for nondestructive testing of objects in various plants, especially if the results of testing are utilized to modify the operation of various machines in response to detection of unsatisfactory objects.

Dark box for storage of exposed light sensitive sheets


The present invention provides an image forming method including jetting an ink composition containing a pigment, a volatile water-soluble organic solvent, polymer particles and water, from a heated nozzle plate of an inkjet head onto a recording medium; and applying a maintenance liquid on a nozzle surface of the nozzle plate after jetting.

1. Field of the Invention
The invention relates to an image forming method for forming an image by jetting ink from an inkjet head equipped with a nozzle plate having ejection orifices (nozzles) for ink provided therein.
2. Related Art
Various information processing systems have been developed concomitantly with the rapid progress in the information technology industry of recent years, and in addition, recording methods and recording apparatuses appropriate for the respective information processing systems are being put to practical use.
Among these, inkjet recording methods have been widely used because of their advantages that recording can be carried out in a variety of materials, that the hardware (apparatus) is relatively inexpensive and compact, that the method is excellently quiet, and the like. Recording performed by using an inkjet recording method also makes it possible to obtain so-called photograph-like high quality recorded matters. Furthermore, inkjet recording methods making use of pigment inks are generally considered to have better keeping qualities than inkjet recording methods making use of dye inks.
Accordingly, a method for forming an image on a non-porous substrate other than paper substrate, for example, a plastic substrate, using an inkjet method has been recently proposed. For example, an inkjet ink containing a pigment colorant bound to a polymer, and a water-based liquid vehicle containing acid-functionalized polymer colloidal particles and a volatile co-solvent having a boiling point of 285° C. or lower have been disclosed, and this inkjet ink is considered to have excellent adherence to non-porous substrates (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2005-220352).


A hingedly adjustable two-sided storage system and device having a front and back portion that may be secured to a fixed structure through a plurality of adjustable attachment mechanisms to allow a user to access both portions during operation and configure the storage device with a plurality of attachment hangers and components.

1. Field of the Invention
This invention relates generally to storage devices and more particularly to a hingedly adjustable two sided storage system and device that may be secured to a fixed structure through the use of adjustable attachment mechanisms.
2. Description of the Related Art
Currently, systems for closet door storage or other fixed surfaces only use one side for storage and are door or wall attached or door hanging. Usual door openings, specifically wall and wood trim allow for approximately four inches of "free space", adequate for limited two sided use. However, as known in the art, closets differ in both depth and usage, thereby allowing for the possibility of greater "free space". As such, adjustable hinges and latches would further expand two sided storage capabilities.

Hingedly adjustable two sided storage device


A method for autonomous mower navigation includes performing a training operation for an area including identifying a GPS signal associated with a training apparatus, iteratively recording data associated geolocations of the training apparatus as the training apparatus moves along a trajectory through the area, smoothing the geolocation data associated with the trajectory, and storing the smoothed geolocation data. The method can include subsequent to the training operation, performing a greens association process including establishing a link between the autonomous mower and an RTK-GPS base, receiving by the autonomous mower correction data from the RTK-GPS base, and determining an approach angle to a work area, wherein the path the autonomous mower travels to the work zone is defined by the approach angle.

Conventional systems for robotic greens mowers utilize a local positioning system (LPS) which includes four beacons, and uses the system to localize the robot's pose. By driving the robot and recording the trajectory, an operator can train the greens' perimeter shapes and keep-out zones. This approach, however, requires beacons and is susceptible to ambiguities with regards to location. A beacon-base system uses the geometry pattern formed by the 4 beacons to perform the greens association, it has been identified that a symmetric shape or similar beacon patterns among other greens would lead to greens-association difficulties.
Thus, there remains a need for an accurate, efficient and cost-effective solution for autonomous mower navigation that does not require beacons, reduces ambiguities, and is easier to deploy and install.

Autonomous mower navigation system and method