Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.- central epi region of well controlled thickness and a smooth outer surface suitable for device formation. Bipolar transistors of excellent properties are formed by providing a nested base and emitter within the central region. Other types of devices may also be formed. The surrounding N.sup.+ periphery automatically provides a buried layer and buried layer contact.

Dielectric isolated devices and circuits, generally denoted by "DIC", have long been known in the semiconductor art. They comprise devices and circuits in which the components (transistors, diodes, resistors, etc.) are formed in single crystal semiconductor tubs or islands embedded in an insulated supporting matrix, for example, a polycrystalline semiconductor such as polysilicon with a dielectric liner between the poly and the single crystal island. Each island of single crystal semiconductor material is separated from the supporting matrix and the adjacent islands by the dielectric liner. Hence, there is excellent electrical isolation between the individual islands and low parasitic capacitance. However, the packing density is comparatively low since, generally, only one device is placed in each island and space must be left between the islands for the dielectric liner and separating poly support matrix. Typical DIC methods and structures are described in U.S. Pat. Nos. 3,407,479, 3,431,468, 3,457,123, 3,461,003, 3,508,980, 3,876,480, 3,902,936, 3,929,528, and 4,649,630 which are incorporated herein by reference.
The process by which DIC structures are made is much more arduous than the processes conventionally used for most other types of semiconductor devices and circuits This is because great effort must be expended in obtaining the basic DIC wafer with the isolated single crystal islands before the conventional device formation process may begin. Further, dimensional tolerance control is vastly more difficult with DIC wafers because of the need to remove the bulk of the original substrate from which the islands are obtained. In particular, it is very difficult to control the precise thickness of the isolated single crystal islands across the DIC wafer There is an ongoing and long felt need for improved DIC structures and fabrication processes in which critical device dimensions are less susceptible to process variations. Accordingly, it is an object of the present invention to provide an improved configuration and process for DIC structures which are less susceptible to process variations. It is a further object of the present invention to provide an improved configuration and process for DIC structures wherein a buried layer and buried layer contact, and an epi region of well controlled thickness, are provided in selected islands, even though the island thickness varies substantially.

Fabrication of dielectrically isolated semiconductor device


The helicopter drizzle pipe allows for aerial wildfire suppression efforts in otherwise inaccessible areas. The pipe is balanced between the bottom legs of the helicopter as to prevent an imbalance or obstruction to the helicopter rotor blades. Along the bottom of the pipe are strategically placed holes to allow the liquid in the pipe to drizzle out at a constant speed over the whole length of the pipe, simulating rainfall. Due to the pipe's positioning, it is also very easy to remove from the helicopter for refilling or cleaning. Furthermore, the method by which the liquid drizzles from the pipe does not necessitate aircraft movement, thus functioning even when the helicopter hovers to thoroughly cover a specific area.

A wildfire is an uncontrolled fire in an area of combustible dry vegetation occurring in rural areas. Wildfires can be characterized in terms of the cause of ignition, their physical properties, the combustible material present, and the effect of weather on the fire. Wildfires can cause damage to property and human life, although naturally occurring wildfires may have beneficial effects on native vegetation, animals, and ecosystems that have evolved with fire. There have been no products available as original equipment or as an aftermarket to prevent and address this problem.
Wildfire suppression depends on irrigation and technologies available in the area in which the wildfire occurs. Silver iodide can be used to encourage snow fall, while fire retardants and water can be dropped onto fires by unmanned aerial vehicles, planes, and helicopters. Complete fire suppression is no longer an expectation, but the majority of wildfires are often preventable or extinguished before they grow out of control. There have been no products available as original equipment or as an aftermarket to address this problem either.
There exists a need for an aircraft delivered irrigation and fire suppression that is not being met by any known or disclosed device or system of present.


A method for determining misalignment between two semiconductor dies is described in which signals are transmitted through a first subset of an array of proximity connectors that are proximate to a surface of one of the semiconductor dies and received through a second subset of an array of proximity connectors that are proximate to a surface of the other semiconductor die. A spatial beat frequency is determined from the received signals. This spatial beat frequency corresponds to misalignment-induced aliasing of spatial frequencies associated with the first subset of the array of proximity connectors and the second subset of the array of proximity connectors. The misalignment is then determined using the spatial beat frequency.

1. Field of the Invention
The present invention relates to techniques for communicating signals between semiconductor dies. More specifically, the present invention relates to a method and an apparatus for determining misalignment between semiconductor dies based on spatial interference patterns.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, which can include tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem has created a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, the first chip can directly transmit signals to the second chip without having to route the signals through intervening signal lines within a printed circuit board.
Capacitive coupling requires proper alignment between the transmitter pads and the receiver pads, both in a plane defined by the pads and in a direction perpendicular to the plane. Misalignment between the transmitter pads and the receiver pads may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, satisfactory communication requires alignment such that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, limiting overall misalignment may improve communication performance between the chips and reduce power consumption.
Unfortunately, it can be very challenging to align the chips properly. Existing approaches include mechanical mounting structures that incorporate self-alignment and/or self-adjustment of pad positions. However, due to thermal expansion and mechanical vibrations, as well as manufacturing and assembly perturbations, even with very careful mechanical assembly the chips often still have some residual misalignment. Other techniques such as electronic steering, in which data signals are routed to particular pads in an array of pads, may be used to further reduce the effects of misalignment. Implicit to many of these solutions, however, is the ability to measure the alignment of the chips.
One existing alignment measurement technique assigns a charge to conducting pads on one chip, and detects a pattern of charges that are induced in the pads on a facing chip. Another existing system improves upon this technique by providing an array of conductive pads on the first chip and an array of conductive pads on the second chip with a different spacing than the conductive pads on the first chip. When the conductive pads on the first chip overlap with the conductive pads on the second chip, a vernier is created, allowing the alignment between the chips to be determined.
These existing approaches, however, have limitations. Measurements using such techniques are often complex and slow. The results may also be inaccurate, especially for small misalignment values, since these approaches rely on being able to detect very small differences in capacitances for each pad. Unfortunately, due to noise and other instrument limitations, accurately detecting such small differences in capacitances is often not possible.
Hence, what is needed is a method and an apparatus to determine misalignment and facilitate capacitive inter-chip communications without the problems listed above.

Measuring rotational misalignment using spatial interference patterns


An engine control module having an environmentally-sealed housing includes a housing-mounted air pressure sensor for providing a reliable measure of atmospheric air pressure to a control circuit mounted within the housing. The sensor is mounted on an inboard face of the housing, and includes a sensor element, a body portion and a riser portion. The sensor element is mounted in the body portion, and the riser portion protrudes through an opening in the housing to couple the sensor element to atmospheric pressure outside the housing. The body portion is sealingly secured to the inboard face of the housing, and a set of conductor pins molded into the body portion extend inward to engage a circuit board enclosed by the housing, and thereby directly couple the sensor element to the ECM's control circuit. The top of the riser portion is capped by a splash-proof lid to prevent water intrusion.

A modern motor vehicle powered by an internal combustion engine is equipped with an engine control module (ECM) for controlling various engine operational parameters such as spark timing, fuel injection, valve timing, emission controls, and so on. The algorithms for carrying out these control functions are based in part on current atmospheric conditions such as ambient air pressure and temperature, and measures of these and other parameters are ordinarily obtained from discrete sensors. In certain instances, the sensors can be mounted on a circuit board within the ECM to minimize system cost, but parameters such as ambient air pressure cannot be reliably sensed inside the ECM, particularly in applications where the housing of the ECM is environmentally-sealed. Accordingly, the ambient air pressure is ordinarily measured with a wired external sensor coupled to the ECM via its wiring harness. For reduced system cost, however, it would be desirable to obtain a reliable measure of ambient air pressure while avoiding the increased expense associated with a wired external sensor.

Sealed engine control module with integral ambient air pressure sensor


A process for producing powders of metal compound containing oxygen including the steps of: feeding at least one material selected from a liquid material and a solution material obtained by dissolving solid ingredient in organic solvent via a liquid flow controller into a vaporizer; vaporizing the materials in the vaporizer; adding oxygen; heating; cooling; and crystallizing. Also disclosed is the product formed by this process, and apparatus used in performing the process. The process and the apparatus enable easily mass-producing fine powders of metal compound containing oxygen used as materials for optical crystals, nonlinear crystals or magneto-optical crystals with reasonable production cost.

In the field of semi-conductive crystal, powders of metal compound containing oxygen such as lithium niobate, niobic acid tantalum or barium titanate is employed as material of optical crystal; powders of metal compound containing oxygen such as bismuthic acid barium, bismuthic acid silicon or bismuthic acid germanium is employed as material of nonlinear crystal; and powders of metal compound containing oxygen such as lithium niobate or lithium tantalate is employed as material of magneto-optical crystal. For example, lithium niobate is known as a transparent crystal without rendering color or tinted with pale yellow, and as revealing ferroelectricity. Also, surface acoustic wave devices, Q-switches, optical modulators, optical switches and so on that took advantages of electro-optic effect, nonlinear optical effect, ultrasonic propagation, piezoelectric effect, etc. as the characteristics of lithium niobates are put into practical use.
Conventionally, the powders of metal compound containing oxygen are produced in general by sol gel method, sintering method or sputtering method. Japanese Unexamined Patent Application Laid-Open Nos. Hei 5-9023, Hei 7-21831, Hei 9-208227, 2000-113898 and 2002-356326 disclose the sol-gel method, in which, for example, the powders of metal compound containing oxygen are obtained by dissolving several kinds of metal alkoxide in amine, hydrolyzing and adding a precipitant, thereafter drying precipitation. Japanese Unexamined Patent Application Laid-Open No. Hei 10-338524, for example, discloses the sintering method, in which the powders of metal compound containing oxygen are obtained by mixing several kinds of metal oxide and sintering the resultant mixture. Further, Japanese Unexamined Patent Application Laid-Open No. Hei 8-277467 discloses the sputtering method, in which the powders of metal compound containing oxygen are obtained after repeating the sintering and crushing the sintered objects several times, hot pressing and sputtering the sintered objects with aiming them as a target.

Process and apparatus for producing powders of metal compound containing oxygen, and the powders produced by the process


A technique is disclosed for optically trimming a sensor (10) to account for manufacturing variations in the losses of the sensor. As a result, the sensor can be used interchangeably, without requiring adjustment of the processing system (12) the sensor is used with. More particularly, in one embodiment, variably transmissive optical filters 72 and 74 are positioned inside the sensor to effectively alter or standardize the losses of the sensor. Various other arrangements, including the use of variably reflective mirrors, wavelength selective elements, blocking elements, and path adjustment elements, are also described in which the characteristics of the sensor's optical paths are altered.

Sensors are used to monitor parameters of interest in a variety of different applications. For example, in avionic applications, the parameter of interest may be the position of an aircraft's landing gear, flaps, or ailerons. Alternatively, the parameter of interest may be the temperature, pressure, or flow rate of some fluid involved in an industrial process. In a medical application, the parameter of interest may be a patient's temperature, pulse rate, or blood pressure.
Regardless of the application involved, a sensor produces an output that is representative of the parameter of interest. In one class of sensors, referred to herein as optical sensors, the sensor output is based at least partially upon the processing of an optical beam.
More particularly, in a "passive" optical sensor, the sensor modulates an optical input beam to produce an optical output beam that is representative of the parameter of interest. A "hybrid" optical sensor, on the other hand, receives an electrical input signal and produces an optical output beam that is representative of the parameter, or receives an optical input beam and produces an electrical output signal representative of the parameter. Finally, a "self-generating" optical sensor produces an optical output beam in direct response to the parameter, without receiving either an optical or electrical input.
Optical sensors have several advantages over more traditional electrical sensors. For example, the optical beams employed by such sensors are typically not disrupted by electromagnetic fields. Optical sensors are also preferred for use in flammable environments because of their reduced risk of sparking or heating. Further, optical sensors are often relatively compact and lightweight.
Conventional optical sensors do, however, have some limitations. In that regard, the losses involved in the transmission of optical beams used by such a sensor may significantly affect the interpretation of the sensor's output. As will be appreciated, external losses may occur as the result of the absorptive, reflective, and refractive nature of the components used to transmit optical beams to and from the sensor. Similarly, internal losses may be introduced by the components that transmit optical beams within the sensor.
In the past, attempts have been made to limit the influence that optical losses have on the operation of optical sensors. For example, one approach that has been used involves the measurement of the internal losses associated with a particular sensor and the external losses associated with the system the sensor is used in. The measured optical losses are then taken into account when the sensor output is interpreted.
In that regard, the measured losses alter the relationship that would otherwise exist between the sensor output and the parameter of interest. Thus, if the sensor output is normally applied to an equation to compute, for example, the position of an object, the equation must be altered to account for the measured losses. Similarly, if a look-up table is used to determine the position of the object corresponding to a particular sensor output, the look-up table must be altered to account for the losses.
Along with the initial calibration of the sensor and system, another approach has been developed to remove the influence of losses on the sensor's output, without requiring the losses to be measured. More particularly, an optical beam including components having more than one wavelength is transmitted through the elements whose losses are to be accounted for. As will be appreciated, the losses associated with these elements, which form a common path for the beam, affect each of the different wavelength components the same. For that reason, these losses are referred to as "common-mode" losses.
After traversing the common path elements, the beam is split into its different wavelength components. One of the wavelength components is not modulated and is used as a reference. The sensor typically modulates the remaining wavelength components, however, to include information representative of the parameter of interest.
Thus, each modulated wavelength component is proportional to the parameter of interest. Because the modulated components are subject to the common mode losses, however, the losses will also influence the determination of the parameter of interest if a modulated component is used, by itself, to monitor the parameter.
Fortunately, the ratio of each modulated wavelength component over the unmodulated or reference wavelength component is also proportional to the parameter of interest. Because the modulated and reference wavelength components of the beam each traverse the common path elements whose losses are to be accounted for, the optical losses introduced by the elements are the same for each wavelength component. As a result, if the ratio of the modulated and reference wavelengths is used to evaluate the parameter of interest, the losses effectively cancel and do not influence the evaluation.
While the use of multiple wavelengths does allow common mode losses to be removed, the operation of the sensor may still be subject to "differential-mode" losses attributable to variations in the optical paths traversed by the different wavelength components once the input beam is split. Because the optical losses associated with these differential paths typically are not the same, the losses do not cancel when the ratio of modulated to reference wavelength components is used to monitor the parameter of interest. These differential-mode losses can be measured and accounted for electronically, as described above, but the process is expensive and time-consuming.
Another type of optical sensor in which some form of initial calibration may be important is a multiple-phase optical sensor. Such a sensor typically responds to a parameter of interest, like position, by producing two outputs exhibiting a relative phase difference. The analysis of this phase difference allows, for example, the direction of motion to be determined and position to be determined with higher resolution via interpolation.
To produce meaningful relative phase information, however, the various components of the sensor must be constructed and aligned to exacting tolerances. As a result, conventional multiple-phase sensors have been relatively difficult and expensive to produce. The prior art has suggested the use of adjustable lenses, mirrors and apertures to alter the optical paths within the sensor to introduce the desired relative phasing between the paths and otherwise eliminate the need for initial phase calibration.
One particular scenario of interest in which sensor losses and constructional variations present a problem relates to sensor interchangeability. In many applications, it is sometimes necessary to replace a damaged, inoperative, or outdated sensor. As will be appreciated, if the various optical components of a sensor are constructed and assembled to extremely close tolerances, the optical characteristics of the sensor will also fall within a relatively narrow range. As a result, an old sensor can be replaced with a new sensor, without significantly altering the operation of the sensor. The parameter of interest can then be evaluated by applying the new sensor's output to the same formula or look-up table used with the replaced sensor.
Unfortunately, it is often prohibitively expensive to produce optical sensors within such close tolerances. As a result, the performance of a new sensor may be considerably different than the that of the old sensor. As will be appreciated, these sensor-to-sensor variations can be accounted for by actually measuring the characteristics of the new sensor and altering the formula or look-up table used to compute the parameter of interest. Unfortunately, such a recalibration procedure is time-consuming, inconvenient, and expensive.
The problems presented by the recalibration of a system for use with a new sensor are particularly acute when only a portion of a complete sensing system is replaced. For example, some sensors do not include light sources or detectors and, instead, modulate optical beams received from remote sources and transmit the modulated beams back to remote detectors. The recalibration performed if such a sensor is replaced in a system is complicated by the need for information about both the sensor and the remote sources and detectors.
Reviewing now one particular prior an arrangement, U.S. Pat. No. 4,672,201 (Welker) discloses a multiple-phase, distance-measurement sensor that includes a plurality of light source and light detector pairs. An opaque scale and grating with transparent graduations are positioned between the sources and detectors and are movable relative to each other. Light directing lenses, positioned adjacent the light sources, can be adjusted in one direction to control the relative phase of the various detector outputs and in another direction to control the relative gain of the outputs. Thus, independent control over phase and gain is provided.
The Welker patent, however, nowhere addresses the problem of sensor interchangeability. The adjustments to gain are made simply to control the relative response of the different source/detector pairs in the sensor. In addition, because the Welker sensor includes light sources and detectors, the potential problems that might be presented by the replacement of a sensor used with remote sources and detectors are reduced.
In view of these observations, it would be desirable to provide a relatively low-cost sensor that can be used to quickly replace an existing sensor, without altering the way in which the sensor's output is processed.

Optically trimmed sensor for reducing influence of differential node losses


In a method of producing a micro-electromechanical element a first intermediate layer, which is applied to a first main surface of a first semiconductor wafer, is structured in a first step so as to produce a recess. The first semiconductor wafer is connected via the first intermediate layer to a second semiconductor wafer in such a way that a hermetically sealed cavity is defined by the recess. When one of the wafers has been thinned from a surface facing away from said first intermediate layer so as to produce a diaphragm-like structure on top of the cavity, electronic components are produced in said thinned semiconductor wafer making use of standard semiconductor processes. At least one further intermediate layer between the two semiconductor wafers is provided, which, prior to the connection of the two semiconductor wafers, is structured in such a way that the structure formed in said at least one further intermediate layer and the recess in said first intermediate layer define the cavity. Finally at least one defined opening is produced so as to provide access to the hermetically sealed cavity.

1. Field of the Invention
The present invention relates to a method of producing a micro-electromechanical element, and, more specifically, to a micro-electromechanical element which is implemented such that a micromechanical structure and electronic components are arranged in the same semiconductor wafer.
2. Description of Prior Art
Due to the fast development in the field of semiconductor industry and microelectronics, micromechanical elements, e.g. silicon-based micromechanical pressure measurement cells, replace classical mechanical pressure transducers more and more. Micromechanical elements are used in great amounts e.g. in the fields of automation technology and medical engineering as well as in automotive vehicles. The systems preferably used in this connection are micro-electromechanical integrated systems which realize the combination of mechanical and electronic functions on one substrate. In addition to the electronic components produced in CMOS or similar technologies, which are e.g. measuring transducers, amplifiers, storage means, microcontrollers, etc., mechanical components exist in the same layers. These mechanical components may e.g. be diaphragms of pressure sensors, elastic sheets of valves or pumps, oscillating masses of acceleration sensors, movable fingers or cantilevered arms of switches and the like. In addition to the more or less smooth surface which normally exists in the field of planar technology, these mechanical structures have a three-dimensional structural design and comprise cantilevered structures and buried cavities.
Up to now, it has been known to produce such cavities by wet-chemical etching or by connecting two disks which have been fully processed individually in advance. The techniques which may be used as a connection technique for connecting the individually processed disks are wafer bonding (silicon fusion bonding), anodic bonding or glueing. In any case, the individual disks are fully processed before they are connected in accordance with conventional methods, so that processing steps which may impair the mechanical structures need not be carried out afterwards.
When a wet-chemical undercutting of structures is carried out, the so-called "sticking" problem arises in the case of which the cantilevered structure will adhere to the neighbouring surface due to capillary forces occurring when the liquid dries; hence, the cantilevered structure will lose its movability. Small ditches, holes and gaps additionally cause problems when the structure in question is to be wetted with liquids (e.g. etching solutions, cleaning water, photoresist) and during the removal of these liquids, the problems being then caused e.g. by bubbles which may adhere to the structure in corners thereof. In the case of spinning, drops may remain, which will cause marks when they dry up. Cleaning by means of brushes is problematic as well, since the movable structures may break off during such cleaning processes. A clean surface of the structures is, however, necessary so that the production methods for producing the evaluation structures, such as a CMOS method, can be applied. Due to the risk of carrying over particles and contaminations, the CMOS ability may no longer be given in the case of open structures, i.e. certain sequences of process steps are not allowed in an CMOS line. In addition, when the chips comprised in the wafer are diced by means of a wafer saw, water is used as a rinsing liquid, which may penetrate into open cavities thus aggravating the particle and contamination problem.
It is additionally known to produce diaphragm-like structures making use of KOH back etching, when the electronic components on the front surface of a wafer have been finished. Due to the oblique etch edges occurring in the case of KOH etching, the integration level will, however, decrease substantially when this method is used, especially when a high number of micro-electromechanical components is produced from one wafer.
Various methods of producing semiconductor pressure sensors are additionally described in DE 3743080 A1.
DE-C-19543893 describes a method of aligning structures which are to be produced in a substrate, in the case of which a diaphragm-like structure is formed on top of a cavity. For this purpose, a closed cavity is first produced between two substrates by forming a recess in a masking layer on one of the substrates, whereupon the two substrates are interconnected via the masking layer and one of the substrates is thinned in a final step.
U.S. Pat. No. 4,586,109 describes a method of producing a capacitive pressure sensor. For this purpose, a layer arranged on a substrate is first structured so that a closed cavity will be formed, when the substrate has been connected via this layer to a further substrate. This cavity can then be opened through one of the substrates for producing a relative pressure sensor.
EP-A-639761 discloses a method of producing a differential pressure sensor in the case of which a substrate structure, in which a micromechanical element is formed, is connected to a glass substrate.

Method of producing a micro-electromechanical element

Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.


System and methods are described to create successive abstractions of real and virtual environments and objects. A common framework is provided to define abstractions for a large collection of various input data feeds. It is assumed that environments are either instrumented to produce such messages or that they may contain sensors or smart devices that generate such messages. Incoming messages are analyzed preserving latency requirements and without imposing unduly heavy procedures. The analysis yields various abstractions at several scales that can be utilized by application programs. A system architecture using specialized storage mechanisms is proposed that preserves the latency requirements of the incoming data messages and the generated abstractions.

Various kinds of sensors or information-transmitting devices containing sensors (sometimes also called smart devices) continue to be installed in physical environments leading to a merger of the online and physical worlds. Mobile phones also contain several sensors that may provide data to applications installed on the mobile phone or to servers connected to the mobile phone via data networks. Software systems that create virtual environments are being instrumented to capture events in data sets (also called log files). Data sets of online and physical environments are being made available for computational purposes.

System and method of creating abstractions of real and virtual environments and objects subject to latency constraints


An image generation method, image generation device, and image synthesis device include generating at least two images at different exposure times. Intensities of pixels in the images at different exposure times are respectively obtained. Reliabilities of the pixels in the images at different exposure times are respectively obtained. The intensities of the corresponding pixels in the images at different exposure times are respectively multiplied by the corresponding reliabilities, and then the products are summed, so as to obtain intensities of pixels in a synthesized image and thus generate the synthesized image. By using the technical schemes of the present disclosure, an image with abundant details can be generated in real time.

This section provides background information related to the present disclosure which is not necessarily prior art.
In reality scene, the dynamic range perceived by human eyes is quite large. The human eyes may sense starlight with a brightness of 10−3 cd/m2 and sunlight with a brightness of 105 cd/m2, and may even sense details in a reality scene under a very dark or bright circumstance. With a relatively small brightness dynamic range, the current image capturing equipment cannot perceive bright details in an extremely bright scene, nor perceive dark details in an extremely dark scene. Therefore, the brightness dynamic range perceived by the image capturing equipment is much smaller than the brightness dynamic range in an actual scene perceived by the human eyes.
During the research and practice of the prior art, the inventor finds out it is highly desirable to simplify and improve the image synthesizing process and generate a video image in real time.

Image generation method, device, and image synthesis equipment


One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods that involve the use of pattern matching techniques to identify and resolve potential non-double-patterning-compliant (NDPC) patterns or layouts that are encountered when using double patterning techniques to manufacture integrated circuit products.
2. Description of the Related Art
Integrated circuit products, or ICs, are generally created by patterning several layers of material so as to define the various devices and components, e.g., transistors, resistors, capacitors, etc., that are used to make the product. Generally, the process starts with the design of the integrated circuit using an electronic design automation (EDA) tool that allows a designer to interactively position and connect various components of the circuit. This design, in turn, is generated into a circuit layout by the electronic design automation tool. The circuit layout, also known simply as a layout, contains the physical locations and dimensions of the circuit's components, interconnections and various layers. The components, interconnections and various layers of the circuit form the features of the integrated circuit. As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the layout must take place.
Design Rule Checking (DRC) is the area of electronic design automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rule checking is a major step during physical verification of the chip design. Design rules are a series of parameters provided by semiconductor manufacturers that enable the chip designer to verify the correctness of a product layout and the mask sets (reticle) used in manufacturing the product. Advanced processes and products may involve the use of more restrictive design rules in an effort to improve product yield.
Design rules may be specific to a particular semiconductor manufacturing process and/or product. In general, a design rule set specifies certain geometric and connectivity restrictions between features of the layout to ensure sufficient margins to account for variability in semiconductor manufacturing processes and to ensure that the circuits work as intended. Typically, there are several basic types of design rules that semiconductor manufacturers employ. The first are single layer rules, such as, for example, width rules, spacing rules and pitch rules. A width rule specifies the smallest allowable width of any shape in the design, i.e., the width of a metal line or a gate electrode structure. A spacing rule specifies the minimum distance between two adjacent features, like the spacing between two adjacent metal lines. Spacing rules can vary depending upon the nature of the relationship between the two adjacent features, e.g., corner-to-corner spacing, tip-to-side spacing, side-to-side spacing, tip-to-tip spacing, etc. The magnitude of the space allowed by these various spacing rules will likely not be the same in all situations, e.g., the allowable tip-to-tip spacing may be different from the allowable side-to-side spacing. Additionally, the magnitude of the allowed spacing will likely be tighter (smaller) for more advanced products and processes as compared to older product generations. These single layer rules will exist for each layer of a semiconductor product, with the lowest levels typically having the tightest or most restrictive design rules and the highest metal layers on the product typically having larger, less restrictive design rules. There is also what is known as two layer design rules. A two layer design rule specifies a relationship that must exist between features on two separate layers of the product. For example, an enclosure design rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin of error, by a metal layer. There are many other design rules that are not discussed herein.
Typically, the design validation process is handled by a verification tool, which processes a circuit layout and verifies that the layout adheres to a set of specified design rules. One such verification tool is sometimes referred to as a design rule checker. Often times the design rule checker is implemented as a stand-alone software program, such as Cadence Assura®DRC, or as a part of an electronic design automation tool, such as Cadence Virtuoso®. The design rule checker examines a layout for violations of a set of specified design rules. The layout is usually received by the design rule checker in the form of a file that digitally represents the layout of the circuit. Current formats for layout files include, but are not limited to, GDS II and OASIS. When a design rule checker observes a circuit feature within the layout that violates a particular design rule, the violation is flagged by the design rule checker. Examples of how this flagged violation can be brought to the designer's attention include, but are not limited to, marking the violation directly in a resulting output layout file or graphically bringing attention to the violation within the electronic design automation tool.
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as a photoresist material, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the final circuit layout (design) on the integrated circuit product. Historically, the pitches employed in integrated circuit products were large enough such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced in size to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning or double patterning technology (DPT). In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively enables the printing of even smaller features than would otherwise be possible using a single mask using existing photolithography tools. There are several double patterning techniques employed by semiconductor manufacturers.
One illustrative double patterning technique involves exposing the same layer of photoresist material to two separate exposure steps using two different reticles. After the second exposure, the double-exposed photoresist layer is then developed so as to define a patterned photoresist mask that may be used, for example, as an etch mask to transfer the pattern defined in the patterned photoresist mask to an underlying layer of material.
Another illustrative double patterning technique is more involved and generally involves creating the ultimate or desired target pattern in a hard mask material by performing two lithography and two etch processes—this process is sometimes referred to as an LELE (Litho-Etch-Litho-Etch) process. In an LELE double patterning process, a first photoresist layer is formed above a hard mask layer. Thereafter, the first photoresist layer is exposed during a first exposure process and subsequently developed to define a first patterned photoresist mask. Next, an etching process is performed through the first patterned photoresist mask on the hard mask layer to transfer the pattern in the first patterned photoresist mask to the hard mask layer. The first patterned photoresist mask is then removed from the now partially patterned hard mask layer. Next, a second photoresist layer is formed above the partially patterned hard mask layer. The second photoresist layer is then exposed during a second exposure process (using a different reticle) and subsequently developed to define a second patterned photoresist mask. An etching process is then performed through the second patterned photoresist mask on the partially patterned hard mask layer to transfer the pattern in the second patterned photoresist mask to the partially patterned hard mask layer. This latter etching process results in a final patterned hard mask layer having the desired target pattern. The second patterned photoresist mask is then removed. The final patterned hard mask layer may then be used to pattern an underlying layer of material.
To use double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometime speak of such patterns with reference to "colors," wherein the first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a "coloring conflict" between the two masks. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too closely to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent an overall target pattern has an even number of such features, such a pattern is sometimes referred to as an "even cycle" pattern, while an overall target pattern that has an odd number of such features is sometimes referred to as an "odd cycle" pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques.
If a layout cannot be separated or "decomposed" into two masks, the problem can be addressed by changing the circuit layout. The circuit layout is usually changed manually by a designer reviewing the output from design rule checking software. Changing a circuit layout is time-consuming and expensive because a designer aims to minimize the total volume of a circuit layout and a change to a portion of a circuit layout often affects structures in other layers or regions of the circuit layout. A designer must evaluate many alternate fixes before determining the best solution. Additionally, some fixes do not necessarily resolve certain odd cycle situations. Therefore, improved methods for efficiently resolving double patterning constraint violations are desired.
FIGS. 1A-1D depict a very simplistic circuit layout that will be helpful in understanding the concepts mentioned above. FIG. 1A depicts a very simplistic circuit layout 11. The circuit layout 11 is comprised of line-type features 13 and 15A-15C. The "X" in FIGS. 1A-1D indicates where a design rule violation exists, i.e., the features are positioned too closely to one another. Thus, the circuit layout 11 in FIG. 1A cannot be formed using a single patterned photoresist mask. The initial task is to determine whether or not the circuit layout 11 can be formed using double patterning techniques.
To that end, FIG. 1B depicts one possible arrangement 11A or so-called "coloring" in which the circuit layout 11 can be "decomposed" into two separate mask layers. Layout designers sometime speak of such patterns with reference to "colors," wherein the first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a "coloring conflict" between the two masks. Layout designers also use the phrase "coloring solution" in describing various situations. For example, a potential non-double-patterning-compliant (NDPC) pattern may be referred to as a pattern that is perceived to have "no coloring solution." In FIG. 1B, one mask is depicted in dashed lines while the other mask is depicted in solid lines. More specifically, a first mask is comprised of only the feature 13, while a second mask is comprised of the three features 15A-15C. While the first mask does not violate any design rules, the second mask still violates the spacing design rules as indicated by the two "Xs" in FIG. 1B. Thus, the possible arrangement 11A, i.e., the first possible coloring solution, is not double-patterning-compliant.
FIG. 1C depicts another possible arrangement 11B, i.e., another possible coloring solution, in which the circuit layout 11 can be "decomposed" into two separate mask layers. In FIG. 1C, one mask is depicted in dashed lines while the other mask is depicted in solid lines. More specifically, a first mask is comprised of the features 13 and 15B, while a second mask is comprised of the features 15A and 15C. While the second mask does not violate any design rules, the first mask still violates the spacing design rules as indicated by the "X" in FIG. 1C between the features 13 and 15B. Thus, the possible arrangement 11B, i.e., the second coloring solution, is not double-patterning-compliant.
From the foregoing, it is clear that the circuit layout 11 is a layout that is an impossible-to-decompose (ITD) pattern that cannot be formed using double patterning techniques. Accordingly, the designer must modify or "fix" the circuit layout 11 such that it may be formed using double patterning techniques. To that end, FIG. 1D depicts an illustrative fixed arrangement 11F that is double-patterning-compliant. In this example, the fix involves reducing the axial length of the feature 15B in the region 17. This results in a new feature 15B1 that is spaced farther away from the side surface of the feature 13. This change effectively eliminates the design rule violation depicted in FIG. 1C. More specifically, as shown in FIG. 1D, a first mask is comprised of the features 13 and 15B1, while a second mask is comprised of the features 15A and 15C. Neither the first nor second mask violates any design rules, as indicated by the absence of any "Xs" in FIG. 1D. Thus, the fixed arrangement 11F is double-patterning-compliant.
FIG. 2 depicts one illustrative example of a prior art electronic design automation process that is performed for checking a layout to insure that the layout is both design-rule-compliant and double-patterning-compliant. As shown in FIG. 2, the software 10 is comprised of several functional modules that perform various activities. In general, an initial drawn circuit layout 12, in digital form, is subjected to analysis by the software 10 to determine whether or not the layout 12 is both design-rule-compliant (DRC) and double-patterning-compliant (DPT), as reflected in block 14. To the extent the initial layout 12 passes both the design rule checking and double patterning checking (PASS), the initial layout 12 is declared to be both design-rule-compliant and double-patterning-compliant, as indicated in block 16. To the extent that the initial layout 12 fails the design rule and/or double patterning checking (FAIL) in block 14, the entire initial layout 12 is subjected to decomposition in block 18. At that point, the initial layout 12 is decomposed in block 20 to produce a new post-decomposition layout 12A. The new post-decomposition layout 12A is then subjected to design rule checking and double patterning checking in block 22. To the extent the new post-decomposition layout 12A passes both the design rule checking and double patterning checking in block 22 (PASS), the new post-decomposition layout 12A is declared to be both design-rule-compliant and double-patterning-compliant, as indicated in block 24. To the extent that the new post-decomposition layout 12A fails the design rule and/or double patterning checking (FAIL) in block 22, the new post-decomposition layout 12A is determined to have one or more potential non-double-patterning-compliant (NDPC) patterns or layouts that must be fixed to eliminate the situations that are causing the new post-decomposition layout 12A to fail the design rule and double patterning checks, as indicated in block 26. Such fixes may involve adjusting the spacing, position and/or location of one or more features of the NDPC patterns. Determining which fixes to make is a very complex problem as movement or re-sizing of one feature on an integrated circuit product may necessitate changing the location, position or size of another feature. Moreover, there are typically several possible fixes to a particular problem. Thus, the designer must evaluate which solution is best for the particular problem at issue. As a result of fixing the NDPC patterns in the new post-decomposition layout 12A, a modified circuit layout is produced, as indicated in block 28. This modified circuit layout is then processed through the software 10 beginning with design rule checking and double patterning checking in block 14, as indicated in FIG. 2. This process is then repeated until a final circuit layout is determined to be both design-rule-compliant and double-patterning-compliant.
Design rule checking and double patterning checking are very computationally intense tasks. Usually, design rule checks will be run on each sub-section of a product to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a design rule check for modern integrated circuit designs. Most design companies need to or would like to reduce the time involved in performing design rule checking/double patterning checking operations, i.e., it is desirable to achieve reasonable cycle times since design rule checking/double patterning checking operations will likely be performed several times prior to producing a final circuit layout that is both design-rule and double-patterning-compliant. With today's processing power, full-chip design rule checking/double patterning checking operations may be performed more quickly. Nevertheless, reducing the time involved in validating and correcting errors in a product layer such that the final product layout is design-rule-compliant and double-patterning-compliant is a highly desirable goal.
State-of-the-art software for checking for double patterning compliance identifies potential non-double-patterning-compliant (NDPC) patterns through the use of automated decomposition algorithms. Importantly, such software identifies so-called coloring conflicts, but only after the circuit layout has been decomposed. This basic strategy may present several problems. First, since there is, by definition, no coloring solution for a potential non-double-patterning-compliant (NDPC) pattern, the state-of-the-art software uses an arbitrary coloring or masking arrangement as a starting point to decompose the rest of the circuit layout. Such an approach tends to result in a sub-optimal decomposed layout. Second, when using the state-of-the-art methodology, identifying and generating error markers for the features that cause coloring conflicts, i.e., the features that cause the layout to be non-decomposition-friendly, increases the run-time of the software tool, thereby slowing down the design process. Third, the state-of-the-art systems do not provide any localized guidance for fixing the coloring conflict. Unlike traditional rule-based checks and violations, layouts that are determined by the software to be potential non-double-patterning-compliant (NDPC) patterns are typically caused by the interactions among a chain of several features. Even with the error markers provided by the state-of-the-art systems, it is extremely difficult for a layout designer to readily understand the information presented and to devise a timely proposed solution.
The present disclosure is directed to various methods that involve use of pattern matching techniques to identify and resolve potential non-double-patterning-compliant (NDPC) patterns that are encountered when using double patterning techniques to manufacture integrated circuit products which may solve or at least reduce one or more of the problems identified above.

Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications


An ice scraper with brush and the glove, which has an anatomically designed handle grip. The ice scraper and the brush are mounted into the glove to protect the user""s hand from snow, ice, water, and cold. The ice scraper blade and the brush are inserted into a fork branched handle, which is designed with a comfortable and firm grip to maximize the scraping force when applied to an ice covered windshield of a car. Glove is made out of waterproof fabric and internally can be insulated with any thermo-insulating fabric. The glove is provided with Velcro fasteners that are placed at the end of the glove. This prevents entering of the snow and ice into the glove.

This invention relates to an ice scraper and brush with the glove for removing ice and snow from a windshield of the car, and is an improvement over the conventional ice scrapers. One of the more common scrapers have an ice scraper and the brush, which does not protect user""s hand and their garment/sleeve from snow, ice, water and similar. Because of the lack of a sturdy grip on the conventional ice scrapers it is also hard to remove thick sheets of ice from the windshields. For example in U.S. Pat. No. 4,922,569 to Brinker, patent does not disclose any gloves attached to the ice scraping tool. In addition U.S. Pat. No. 378,322 to Young shows extendible ice scraper and snow brush but also without any glove attached to the ice scraping tool. His invention also lacks the ability to act sturdy on the frozen surfaces.
Finally, object of the present invention, ice scraper and brush with the Glove, is to provide a ridged support to the user""s hand that will allow him/her to use the ice scraping tool with ease by having an extra support of an anatomically designed handle grip, which may be either in the form of a gun barrel like, spherically shaped or T-shaped handle grip. This invention is also designed to protect users garment and hands from the snow, ice, water and cold. Other objective is to provide an easily fabricated and inexpensive product. The above mentioned objects will become more apparent when the following drawings and descriptions are read.
The ice scraper and brush with the glove includes three different anatomically designed handles. These include gun barrel like handle, spherically shaped handle, and the T-shaped handle. Another important feature of the invention is the waterproof glove that has an extended sleeve. Further, glove also comprises velcro fasteners that are located on the sleeve portion of the glove. In addition brush as well as the fork branched extension of the ice scraper and brush with the glove is provided with a gusset.


Methods for determining a focus position of a lens system based on astigmatism. The methods can be used to monitor the focus of the lens system or to determine the flatness of a surface.

This disclosure is related to imaging systems that use a lens system to project images, and more specifically, to monitoring focus errors of imaging systems.
An imaging system can be configured to use an optical lens system to project an image of an object onto an imaging surface. The lens system may include one or more lenses depending on the imaging requirements for the system. In many applications, the distances from the object to the lens system and from the lens system to the imaging surface are carefully selected so that the image is well focused onto the imaging surface to form a sharp image. An imaging system may use a focus module to control the focus of the lens system. A photolithographic imaging system in wafer processing is an example of such an imaging system. Any focus error may cause blurring of the image and can be undesirable. For example, a focus error can adversely reduce the resolution in image sensing devices or undesirably change the minimum feature size in photolithography.
An optical lens system may be characterized by a number of parameters, including its numerical aperture ("NA"), depth of focus ("DOF"), and minimum feature size ("W") at its imaging surface. Under illumination of radiation at a wavelength (.lambda.), the minimum feature size due to the limit of diffraction is ##EQU1##
The depth of focus of this lens system can be expressed as ##EQU2##
It is desirable to make the minimum feature W as small as possible while maintaining a robust image fidelity. In a photolithographic process, a line feature in a photomask for a positive photoresist is in its best focus when its imaged linewidth is as large as possible. The image of the same line feature in a photomask for a negative photoresist is in its best focus when the imaged linewidth is as small as possible. High imaging resolution is achieved by either increasing the numerical aperture NA or using a shorter wavelength .lambda.. However, a large numerical aperture NA or a shorter wavelength .lambda. reduces the depth of focus so that any focus error is likely to cause significant blurring of the image. This therefore degrades the imaging resolution. Hence, a lens system may be optimized for the specific requirements of an application by selecting proper minimum feature size W and the depth of focus DOF.
The focus errors of an imaging system may be caused by various contributors which include, among others, the relative spacing between the lens system and the imaging surface, the relative spacing between the object and the lens system, and the non-flatness of the imaging surface. For example, in the exposure process of one type of photolithographic imaging systems such as a scanner lens system, the relative scanning motion between the wafer and the lens imaging system from one exposure to another may cause a variation or shift in the focus.

Monitoring focus of a lens imaging system based on astigmatism


The present invention provides a mechanism for reorganization of the brain through tactile stimulation. A board is provided that has a dual contact path for tracing by the user's fingers. The contact can be continuous or intermittent and the paths can be mazes, labyrinths, spirals or any other design to stimulate the brain.

1. Field of the Invention
The present invention relates generally to reorganizing the brain synapses, and more particularly, reorganization of the brain by using the nerve receptors on fingertips.
2. Related Art
Johnson '897 discloses a programmable tactile stimulation array system.
In the past few years, an enormous amount of research has revealed that the brain never stops changing and adjusting. Brain plasticity is the ability of the nervous system to adapt to changed circumstances and find new ways of learning, sometimes after an injury or a stroke, but more commonly when acquiring a skill. Professor Thomas Elbert, Professor of Psychology at the University of Konstanz in Germany, conducted experiments with individuals who used Braille. The experiments were conducted to determine whether adult brains have plasticity. The findings showed a super highway from the fingertips to the brain. The fingertips provided a means for the brain to adapt and find new ways of learning (Brain Plasticity, Thomas Elbert, January 1998, Radio National, the Health Report)
Research has found that there appear to be at least two types of modifications that occur in the brain with learning. The first is a change in the internal structure of the neurons, the most notable being in the area of synapses, and the second is an increase in the number of synapses between neurons.
The effects of tactile stimulation on the structure of the brain can be appreciated by understanding that the skin is almost an extension of the brain, formed as it is from the same layer of tissue during the embryonic stage of life (Taylor, 1979: 136). (Biosociology: An Emerging Paradigm, Anthony Walsh, 1995)
As with muscle tone and cardiovascular fitness, a new study suggests that use of the brain is required to prevent loss. The cells and connections that are used will survive and flourish, while cells and connections that are not used will wither and die (Dr. Jay Giedd MD, frontline interviews, PBS)
Scientists theorize that cognitive activities are protective in some way. Some speculate that repetition may improve the efficiency of certain cognitive skills and make them less vulnerable to the brain damage associated with Attention Deficit ("AD") Repetition provides mechanisms that may strengthen information processing skills to help compensate for age-related declines in other cognitive areas.
It is known that repetition forms connections and that with proper stimulation, the synapses become stronger. During use electrical chemicals are sent out that make the connections stronger and more permanent. (Brain Development, Karen DeBord, North Carolina cooperative Extension Service). Wiring the brain: "Synapse additions" are not only sensitive to experience, but are actually driven by experience. The role of experience is essential for not only increasing the initial wiring of the brain during childhood but continues to increases the overall quality of functioning of the brain during an entire lifetime. As cardiovascular exercise increases the channels of flow to and from the heart, learning serves to add synapses throughout the brain. (How People Learn, Brain, Mind, Experience and School, Expanded Edition, 2000, Commission on Behavioral and Social Sciences and Education, Mind and Brain)

Method and apparatus to rewire the brain with finger movements


A mobile device, and a method and computer program product for displaying a streaming video image at the mobile device during a packet based video call via a channel established over a wireless communication network, the method includes receiving a speed indication of the mobile device and sending said indication to a communication client application; and responsive to receiving said indication, the communication client application is configured to limit the amount of information in the streaming video image that is supplied for display on a display of the mobile device during the video call when the speed of the mobile device is greater than, or equal to, a first predetermined speed threshold.

Some communication systems allow the user of a device, such as a personal computer, to conduct voice or video calls over a packet-based computer network such as the Internet. Such communication systems include voice or video over internet protocol (VoIP) systems. These systems are beneficial to the user as they are often of significantly lower cost than conventional fixed line or mobile cellular networks. This may particularly be the case for long-distance communication. To use a VoIP system, the user installs and executes client software on their device. The client software sets up the VoIP connections as well as providing other functions such as registration and authentication. In addition to voice communication, the client may also set up connections for other communication media such as instant messaging ("IM"), SMS messaging, file transfer and voicemail.
Mobile devices are commonly used to place voice over IP calls when a user of the device is driving. Such communication is aided by use of a hands free device which enables the user to concentrate on driving whilst a voice over IP call takes place.
With increasing mobile bandwidths, there is increasing interest in providing packet-based video calls via client applications running on mobile devices such as Internet-enabled mobile phones. These mobile devices comprise transceivers such as short-range RF transceivers operating on one or more unlicensed bands for accessing the Internet via wireless access points (e.g. of Wi-Fi access points of WLAN networks), and/or cellular transceivers operating on one or more licensed bands for accessing the Internet via a packet-based service of a cellular network such as GPRS (General Packet Radio Service) or HSPA (High Speed Packet Access).
Video calls take up a large amount of device and network resource, and it is not uncommon for video calls to fail or suffer reduced quality due to insufficient resource. To date attempts to solve this problem have focused on trying to hide such issues from a user as far as possible.


A method, medium, and system providing an updating traveling route to a user. The navigation system includes a route selecting unit to select an optimal route for an item to traverse based on calculated performance indexes of a plurality of alternative routes for the traversal, a performance index calculating unit to recalculate the performance indexes of the alternative routes during a current traversal of the selected optimal route based on received external information regarding sections of available traversals after a predetermined point in each alternative route beyond a current point of the current traversal, and a route changing unit to selectively update the optimal route during the current traversal based on the recalculated performance indexes.

1. Field
Embodiments of the present invention relate to a navigation method, medium, and system, and more particularly, to a navigation method, medium, and system capable of providing information regarding an optimal traveling route and effectively transmitting the information.
2. Description of the Related Art
With the development of GPS (global positioning systems), and like positioning techniques, navigation services providing information on the positions of persons or objects and information on traveling routes have drawn attention. Such navigation systems receive destination information from a user, determine the optimal route from a current user position to a destination, and provide the determined optimal route to the user. These navigation systems determine the optimal route based on traffic information obtained or known at the start point of the user's travel.
However, when the start point to destination route guidance is performed based on the traffic information obtained or known at the start point, it is difficult to obtain real-time traffic information after the starting time. In addition, it is difficult to appropriately reflect real-time traffic conditions because traffic conditions can change while the user or vehicle is traveling. Here, such real-time traffic information could include information on accidents and weather, or other traffic increasing/decreasing occurrences, for example.
In order to overcome such drawbacks, techniques have been proposed for receiving updated traffic information from a navigation server in real time and determining the route of the vehicle based on the received traffic information.
However, even though such real-time traffic information may be received from a navigation server, the traffic information used to determine the route of the vehicle may be unavailable during the travel of the route before the user reaches the destination. For example, when the vehicle encounters traffic congestion at a point A of a first route, conventional navigation system select a second route capable of avoiding traffic congestion and provide the second route to the user. However, for example, even though traffic congestion occurs at point A, the traffic congestion may be reduced before the vehicle actually reaches point A. In this case, the second route provided to the user may actually not be the optimal route.
In addition, when the navigation system periodically receives such updated information from the navigation server, the overall amount of data transmitted therebetween increases.


A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, one area of manufacturing with room for improvement is wafer testing, a mechanism for determining device performance and manufacturing defects. Prior to dicing (the removal of circuit elements such as chips from a semiconductor wafer), test structures as well as functional devices on the wafer are evaluated for electrical performance. Wafer test systems typically utilize a probe card, which includes hundreds to thousands probe tips for making secure electrical connections to test pads on the wafer. Probe tips are either needle tips (or radius tips) or flat tips. Needle tips are more expensive to manufacture and more difficult to maintain than flat tips and have shorter useable life than flat tips. In addition, using needle tips typically leaves marks on test pads after testing, which is undesirable for subsequent processing. Flat tips can be used in large test areas and are more economically feasible than needle tips but can be used only to contact soft materials.

Integrated circuit test method and structure thereof

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


A computer simulation method is provided for modeling the behavioral expression of one or more computerized agents for running a simulation against real-world input data, and providing a visual display identifying elements in the input data corresponding to the modeled agent(s) response(s). Simulations can be run on sources of input data on global networks for agent types of different cultures, societies, and behaviors, such as news feeds, text communications, and reports, in order to identify keywords or phrases therein that correspond to agent behavioral expressions being monitored. Robust new visual tools are provided for discerning patterns and trends in the simulation data, including waveform charts, star charts, grid charts, and pole charts.

During the Industrial Age, the preferred models of human organization were vertically structured, hierarchical, and monolithic. Hierarchical organizational structures promoted efficient economies of scale and the effective command and control of participants within organizations. However, these organizational models have changed in the so-called Information Age, in which worldwide information networks have made, and are increasingly making, vast amounts of information available to all participants in real time, enabling them to make decisions and take actions far more quickly and adaptively than decision-making by top-down management in hierarchical organizations. The preferred models of organization in the information economy are horizontal, networked, and widely distributed. They are requiring a fundamental re-thinking and re-structuring of business, political, and societal organizations in the post-industrial era.
Networked organizations can be viewed as complex, non-linear, adaptive systems that operate by totally different assumptions and rules than hierarchical organizations. With relevant information being available simultaneously to all participants through all-pervasive channels (e.g., broadcast or publication media channels), decision making and taking action can occur locally at any point (node) of a network without having to traverse through the established levels or protocols of a hierarchical organization. A network can accommodate rapid growth in the addition of new participants simply by association with new nodes or to the nearest available contacts (connectors, pathways, qualitative state or hubs) in common or by exclusion, compare, or qualitative descriptor with other nodes. Participants who share common values, beliefs, or goals will prefer to aggregate in communities (clusters) and can link to the nodes of other communities having shared interests or desired or appropriate qualitative state. The preferential attachments of participants to common nodes, in clusters, and bylinks to other clusters allow information flow and decision making to traverse the network quickly by a relatively few number of links. If some clusters cease activity or are rendered inoperative, the pervasiveness of networked linages ensures that other pathways for information and decision making through the network can be found. This provides the robustness of a network to adapt to changing conditions and circumstances.
However, obtaining relevant information about a network or other complex adaptive system has correspondingly become more difficult. Information is widely dispersed among a large number of nodes and clusters, and information from one node or cluster does not necessarily apply to or represent other nodes and clusters. In contrast to a top-down organization, it is also difficult to predict how the nodes and clusters of a network will react to new information or to changing conditions and circumstances. Informants linked to specific communities can better characterize the features of the linked participants of a community than external attempts to characterize the network in aggregate. Without being able to extract relevant information, the status, intentions, and future actions of a network or other complex adaptive system can be difficult to assess.
As an example, the information economy is having a fundamental impact worldwide on the ways that businesses market, distribute and sell products to consumers. Whereas businesses in the industrial era sought to dominate markets by amassing capital, resources, and distribution channels to sell standardized products to consumers, businesses today face a much more competitive environment in which real time information enables many new businesses to continually enter with new or customized products, and consumers to demand with ever increasing specificity the product features or services they want to purchase. This is fueled by vast amounts of financial, marketing, news, and other information made available simultaneously to businesses and consumers alike. Businesses must make quick decisions when to launch new products or customize existing products to changing consumer tastes, and consumers are become ever more informed about product features they want and comparison pricing for product offerings.
In a competitive market environment, the marketing director in each of the many competitor companies must decide whether, when, and what kind of product to bring to market based upon trying to assess what will succeed with consumers in relation to what products other companies will offer. His/her company's ultimate goal is to succeed by increasing sales for its products, yet must be careful not to launch the wrong product and lose consumer confidence, or to take on the market leader or other competitors too directly or too soon and risk being squashed. Their assessments must be made against a vast background of real-world data reflecting historical economic trends, product development timelines, consumers' changing attitudes, and ever shifting tactics and product releases by competitors. As a result, powerful computerized analysis tools have been very much in demand to assist and inform marketing decision making.
Prior attempts to use computer simulation to model complex systems like competitive markets have relied on modeling aggregate parameters of the modeled environment, such as cost of capital, interest rates, consumer spending, sales histories, seasonal adjustments, etc., then the probable responses of other companies, distributor intermediaries, and end users (purchasers) are deductively predicted using market rules culled from market informants. However, the use of deductive methods to forecast the actions of participants from aggregate parameters is, at best, an academic fiction because the participants do not all behave the same way over any extended length of time and with a plethora of diverse sources of market and product information.
Under real conditions, participants in a given environment can be expected to interpret real-world information available to them in different ways, and they will continually adapt and evolve new rules of decision making, showing no evidence of settling down to a single set of commonly observed rules for all participants in that environment. Moreover, complex systems have shown a tendency to coalesce toward unexpected "emergent" behavior that arises out of the chaotic ecology of the multitude of individual decisions and interactions, rather than a predictable behavior that can be deduced from the sum of their individual parts. New methods of modeling have had to be developed to take into account the individual behaviors and interactions of participants in order to derive inductively relevant information about the environment being modeled.
Recent attempts have been made to model complex systems by modeling the expected behavior of the individual participants (agents) in the environment, and running simulations based upon the chaotic ecology of their interactions. For example, the SWARM simulation system developed at the Santa Fe Institute provides general purpose tools for modeling multiple agents and running simulations of anything from artificial life to traffic patterns. See, "The SWARM Simulation System: A Tool for Studying Complex Systems", by C. Langton, N. Minar, and R. Burkhart, Santa Fe Institute, March 1995. While such multiagent modeling systems are better at approximating the behavior of complex systems, they have still relied on modeling individual agents according to an assumed set of behaviors or rules of interaction in response to predefined initial conditions. These existing multi-agent simulation models thus do not take into account the diverse cultural interactions, values and belief bases of perception, and the unexpected responses of participants to diverse sources of real-world information under changing conditions.

Cultural simulation model for modeling of agent behavioral expression and simulation data visualization methods


Provided is an optical apparatus and method wherein power transfer coefficients arising from SRS are measured at a designated co-location point and the power of dithers, which are impressed on the channels of a multiplexed optical signal propagating through the optical apparatus, is measured at each co-location point. Within the optical apparatus distances between co-location points are short and the power transfer coefficients are effectively constant. Consequently, the power of each channel of the multiplexed optical signal at the co-location points is obtained from the power of the dithers at a respective one of the co-location points and the power transfer coefficients measured at the designated co-location point. In some embodiments, information on the channel power at the co-location points is used to provide instructions for compensating for fluctuations in channel power and/or channel count at an input and/or channel count within the optical apparatus.

Performance monitoring to determine channel presence and per-channel power has been employed using detection of an entire spectrum of channels of an optical signal wherein each channel has had impressed upon it a known dither. The dither can be implemented in many ways, such as amplitude modulation (AM) of a tone or set of tones or a code division multiple access (CDMA) modulation scheme, etc.
In an example using AM detection each channel of a multiplexed optical signal has impressed upon it a unique AM tone and power of each channel of the optical signal is measured through differentiation of the unique AM tones and knowledge of a fixed modulation depth and total optical power. This technique has the benefit of being easy to implement and requires a broadband optical tap and a PIN detector to perform the monitoring function. In addition, one can uniquely identify the source of an optical signal by modulating AMs with wave identification (WID) information. The accuracy of this method in estimating per channel power is limited by effects such as stimulated Raman scattering (SRS) which limits its usage to systems with a small number of spans, small channel counts and low per channel powers.
Modern systems are striving to achieve greater span, higher channel count and require higher channel power, thus limiting the applicability of this approach. Another method is to use an optical spectrum analyzer (OSA) at each monitoring point or a single OSA with an optical switch for all points that are co-located (along the path of the optical signal). This approach provides accurate per-channel power measurements that are not affected by SRS. However, in the past, OSAs have not been equipped with the capability of discerning WID information. In addition, it is usually much more expensive to implement, slower in taking measurements and the optical switch can limit the overall reliability of the OSA function. Furthermore, an OSA takes up more space than a PIN detector and measurements at a plurality of co-location points using one or more OSAs causes fiber routing and handling issues.
Finally, SRS can affect system performance. Consequently, a measurement of the SRS present in a system is therefore needed so that it can be used to control the system to minimize the impact of the SRS.

Method of WDM channel tagging and monitoring, and apparatus


A conductive substrate is provided that is arranged on an image display surface of a liquid crystal panel. The conductive substrate includes a transparent base material, a metal layer formed on at least one surface of the transparent base material, and a blackened layer formed on at least one surface of the transparent base material. Provided the color of the image display surface of the liquid crystal panel during backlight-off time, when converted into the CIE (L*a*b*) color space, has a b* value denoted as “b*panel”, the color of the blackened layer, when converted into the CIE (L*a*b*) color space, has a b* value that satisfies the following Formula 1:(b*panel+1)≥b*≥(b*panel−3.5)   Formula 1.

Capacitive liquid crystal touch panels that are recently used in various applications detect a change in electrostatic capacitance caused by an object coming close to the panel surface and convert position information of the object coming close to the panel surface into an electric signal.
A conductive substrate used in a capacitive liquid crystal touch panel is arranged on the surface of the liquid crystal panel, and as such, the material of a conductive layer of the conductive substrate is required to have low reflectance and low visibility.
Thus, a material with low reflectance and low visibility is used as the material of the conductive layer of a conductive substrate used in a capacitive touch panel, and the conductive layer is formed on a transparent substrate or a transparent film. For example, Patent Document 1 discloses a transparent conductive film for a touch panel including an ITO (indium oxide-tin) film formed as a transparent conductive film on a polymer film.
In recent years, the screens of displays provided with touch panels are becoming increasingly larger, and as such, there is a demand for increasing the size of conductive substrates, such as transparent conductive films for touch panels. However, because ITO has high electrical resistance and is susceptible to signal degradation, it is not suitable for use in a large panel.
In this respect, use of a metal foil made of copper or the like instead of an ITO film has been contemplated as described in Patent Documents 2 and 3, for example. However, when a metal foil made of copper or the like is used in place of an ITO film, for example, because a metal foil made of copper or the like has metallic luster, visibility of the liquid display panel may be degraded due to light reflection.
Accordingly, a conductive substrate having a metal layer made of copper or the like and a blackened layer made of a material that can restrict light reflection at the surface of the metal foil made of copper or the like is being contemplated. By forming such a blackened layer, light reflectance of the conductive substrate can be reduced and wiring formed by patterning a metal layer may be less visible such that visibility of the liquid crystal panel may be improved, for example.

Conductive substrate and liquid crystal touch panel


An entry adapter for a cable television (CATV) network includes a first signal separation device configured to separate downstream CATV signals into a first downstream high-frequency signal and a first downstream low-frequency signal based on a first cutoff frequency, a second signal separation device configured to separate the downstream CATV signals into a second downstream high-frequency signal and a second downstream low-frequency signal based on a second cutoff frequency, and a signal frequency sensor and selector device in selective communication with the first and second signal separation devices.

In cable television networks, bidirectional communication is generally provided by constraining the signals in different directions to different frequency bands. Commonly, low-frequency signals are used for upstream communication, while high-frequency signals are used for downstream communication. For example, the upstream communication band may be between 5 MHz and 42 MHz, while the downstream communication band may be between 54 MHz and 1218 MHz.
Entry devices may be used to receive upstream and downstream signals, split the signals, mitigate noise, or otherwise condition signals at or near a subscriber premises. Thus, the entry devices may include an upstream path and a downstream path. The upstream and downstream paths may be active or passive, and may be segregated based on the frequency of the signals, in a variety of ways.
Recently, there has been interest in higher-frequency signal communication with subscriber devices, in either or both of the upstream and/or downstream directions. However, many network devices may operate under the assumption that the frequency distinction between the upstream and downstream signals is in the traditional range noted above. Accordingly, such devices may not be configured for operation at such higher frequencies.


A pitch changing apparatus, providing bi-stable operation within a tremolo system which produces two distinct pitches for selected strings. The apparatus includes a shifting element 56, which is engagable to introduce or remove a pre-determined thickness within a tremolo system, creating string tensions relative to chosen, distinct pitches. An established ratio of total string tension and opposing spring counter-tension acting upon a tremolo is maintained by a tension correcting mechanism 73. The tension correcting mechanism is manually rotated to adjustable stop positions of required spring counter-tension, thereby keeping all strings in tune under conditions of changed total string tension.

This invention relates generally to tremolo devices for stringed instruments, and more particularly with a novel apparatus which complements both tremolo systems and fine tuning mechanisms therein, making possible rapid tuning changes, and adapting for the resulting change in tensions, maintaining a ratio of forces acting upon the tremolo to insure proper pitch for all strings of the instrument.

Pitch changing apparatus for stringed instrument tremolo


A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.

1. Field of the Invention
The present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of chips stacked so as to implement a three-dimensional (3-D) configuration and a method of assembling the semiconductor device.
2. Description of the Related Art
With movement toward higher levels of integration and improved functions of electric devices in recent years, various assembling methods for 3-D chip stacking technology have been developed.
As a commonly used method for assembling a semiconductor device, a core board, which serves as an intermediate layer, is sandwiched between a lower-layer semiconductor package and an upper-layer semiconductor package. Then, the core board and the lower-layer and upper-layer semiconductor packages are fixed by use of thermo compression. The lower-layer and upper-layer semiconductor packages can be connected with a plurality of vias buried in the core board.
To improve electrical connection between the upper-layer and lower-layer semiconductor packages, a fluctuation of the height of the vias buried in the core board have to be suppressed. However, since the vias are formed by plating, a number of platings have to be processed to control the height of vias. This as a result, complicates manufacturing process and decreases manufacturability.
As another assembling method for the semiconductor device, the upper-layer and the lower-layer semiconductor packages are stacked and connected directly with a plurality of bumps without using the intermediate layer. However, since an alignment between the lower-layer and upper-layer semiconductor packages is difficult, a misalignment between the lower-layer and upper-layer semiconductor packages occurs.

Semiconductor device and a method of assembling a semiconductor device