text:
|Publication number
|Publication type
|Application number
|Publication date
|Jan 31, 1978
|Filing date
|Oct 30, 1975
|Priority date
|Oct 30, 1975
|Also published as
|Publication number
|Thomas C. Daly, Edward C. Hepworth, Rodney J. Means
|Original Assignee
|Motorola, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (10), Referenced by (107), Classifications (15)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to assignees copending U.S. patent application Ser. No. 519,138 "INTERFACE ADAPTOR ARCHITECTURE" (now abandoned), Ser. No. 519,150 "MICROPROCESSOR ARCHITECTURE" (now abandoned), and Ser. No. 519,149 "MICROPROCESSOR SYSTEM" by Bennett et al, all filed on Oct. 30, 1974 and to assignee's issued U.S. Pat. No. 3,975,712 by Hepworth et al.
A large number of microprocessor systems are presently available. More recently, microprocessor systems utilizing bidirectional data buses have become available. A variety of digital circuits have been utilized to form the interface between such bidirectional data buses and the various peripheral devices controlled by and interacting with the microprocessor in the system. A particular category of peripheral devices incorporated in such systems are control and data storage devices which normally require the interchange of long serial blocks of data. In order to achieve maximum efficiency in such serial data transmission, synchronous transfer methods are often employed. In synchronous transmission, special characters or codes are transmitted and received as a preamble to a data message comprising a continuous stream of data characters with no delineation indicating the end of one character and the beginning of the next.
The overall area of application of serial synchronous data transmission can be generally divided into three subcategories;
1. Process control or numeric control applications within a local facility where a device in control by a microprocessor has a need to transmit or receive a stream of serial data. The most efficient way to accomplish this data transfer is to transmit and receive a long block of continuous characters. Typically this type of application makes use of signals transmitted over separate control channels to synchronize the transfer of the block of continuous characters.
2. Standard data communications involving transmission and reception over a MODEM (modulator-demodulator) arrangement which might be coupled to a telephone line. In this application dedicated lines or channels for control signals are impractical and synchronous transmission makes use of synchronization codes in the data stream to notify the destination of the data that a serial block of continuous characters is about to be transmitted.
3. Serial peripheral memory units such as tapes, disks or cassettes which have a relatively higher speed data transfer requirement. This category is a hybrid of (1) and (2) above in that it represents a data requirement within a local environment, for example, within a computer facility but it does not use special control lines per se to signal when blocks of data are being transmitted or received. Instead, these systems revert to the use of synchronization codes transmitted as a preamble to the actual block of data characters in order to synchronize the transmission data.
Accordingly, it is an object of the present invention to provide low cost integrated circuit for synchronous serial data communication with a bidirectional data bus of a digital system.
It is another object of this invention to provide a synchronous serial data adaptor which incorporates first-in-first-out buffer memory to facilitate a higher speed data operation.
It is another object of this invention to provide a synchronous serial data adaptor which includes control registers for selecting the internal operating mode of the adaptor under program control.
It is another object of this invention to provide a synchronous serial data adaptor for data communication with a bidirectional data bus which includes a first control register for receiving data from the data bus in response to direct address selection and which contains additional registers for receiving data from the data bus in response to direct address selection combined with supplementary address code contained in the first control register.
It is another object of this invention to provide a synchronous serial data adaptor having a control section which detects synchronization codes defining the beginning of a serial data message which, under program control, will automatically strip the synchronization codes from the serial data message.
Briefly described, the present invention is a digital system for the synchronous transfer of data between serial data channels in a mircoprocessor system having a bidirectional parallel data bus. The invention includes a transmitting section which incorporates a first-in-first-out memory by which parallel data is reformatted and transmitted in serial form. The invention also includes a receiver section incorporating a first-in-first-out memory which receives serial data and reformats this data in parallel form. Additional control logic inserts or deletes synchronization codes and performs error checking under program control.
FIG. 1A and FIG. 1B show block diagram of a synchronous serial data adaptor according to a presently preferred embodiment of the invention partitioned along a section line X-X'. For convenience of discussion, this block diagram is called FIG. 1 in the detailed description which follows.
FIG. 2 is a block diagram of a microprocessor system in which the synchronous serial data adaptor of FIG. 1 may be utilized.
FIG. 3 is a diagram of a sequence of serial data words including synchronization codes as are used in synchronous data transmission and is useful in explaining the invention.
FIG. 1 is a block diagram of a synchronous serial data adaptor (SSDA) 10 according to the invention which in the preferred embodiment is implemented as a single integrated circuit chip. SSDA 10 has 8 bidirectional data input/output lines forming a bidirectional data bus 14 connected to multiplexer (MPXR) bus driver circuitry 12. Enable (E) input 16, read/write (R/W) input 18, chip select (CS) input 20 and register select (RS) input 22 are all connected to address logic circuitry 24 which is coupled to multiplexer bus driver circuitry 12 (referred to hereinafter as buffer circuitry 12) by means of one or more connections 26. In FIG. 1 the arrows indicate the direction of signal or data flow to or from a particular block of circuitry. Some of the solid lines are to be understood to represent a single conductor while others may represent a plurality of separate conductors. The wide coupling elements such as 28, 34, 38, 66, etc. represent buses which may include, for example, eight conductors for a one byte word system. The pointed ends of the buses indicate the direction of data flow and the same general format exists as when data is received or driven by bidirectional data bus 14.
Data to be transmitted from the SSDA 10 to an associated peripheral is transmitted via internal bus 28 which couples to transmitting data FIFO register 30 (hereafter referred to as TX FIFO 30). TX FIFO 30 provides storage for three eight bit data words for three "bytes" of data. The output of TX FIFO 30 couples to transmitting (TX) shift register 32 via internal bus 34. TX shift register 32 formats data words received in parallel in accordance with control information received from TX control circuit 36 via internal bus 38. Even or odd parity is generated by parity generator circuit 40 which couples to TX shift register 32 via conductor 42 and the resulting serial data word is transmitted via TX data output 44. The formatting and transmission of the serial data word is performed in synchronization with the transmitting clock signal (CTX) applied via input 46.
Received data is coupled to receiving (RX) shift register 48 via RX data conductor 50 which also couples to parity check circuit 52. RX clock conductor 54 which couples to RX shift register circuit 48 and RX control circuit 56 provides the basic timing for data reception. The output of RX control 56 couples to RX shift register 48 via internal bus 58 and to an input to parity check 52 via conductor 60. The output of RX shift register 48 couples to receiving data FIFO register 62 via (hereafter referred to as RX FIFO 62) internal bus 64. The output of RX FIFO 62 couples to buffer circuitry 12 via internal bus 66 which thus allows transmission of received data to the associated MPU via bidirectional data bus 14.
SSDA 10 contains three write only control registers which define modes of operation for the circuit. Internal bus 68 which couples to buffer circuit 12 provides the data inputs to control register #1, 70. Control register #1, 70, also has a RESET input applied via conductor 72 and an input from address logic 24 applied via conductor 74. One output of control register #1, 70, couples to control register #2, 76, control register #3, 78, TX FIFO 30 and synchronization code register 80 via conductor 82. Another output of control register #1, 70, connects to TX control circuit 36 and RX control circuit 56 via conductor 84. Control register #2, 76, control register #3, 78, and sync code register 80 all have data inputs via internal bus 28 and address inputs via conductor 29. The output of control register #2 connects to RX control circuit 56 and TX control circuit 36 via conductor 86. The output of control register #3, 78, connects to TX control circuit 36 and RX control circuit 56 via conductor 88 which also couples to an input of compare logic 90. Compare logic 90 as additional input via conductor 84 from control register #1 and an input from comparator 92 via conductor 94. Comparator 92 compares the contents of sync code register 80 via data inputs on internal bus 34 and the contents of RX shift register circuit 48 via data on internal bus 96. The output of compare logic circuit 90 is transmitted via conductor 98 which is the synchronization match/data terminal ready (SM/DTR) output of SSDA circuit 10. Compare logic 90 also has an input from control register #1 via conductor 84 and an input coupled to control register #3, 78, via conductor 88. Status register 100 has an input from TX FIFO 30 via conductor 102, an input from address logic 24 via conductor 104, an input from TX control logic 36 via conductor 106, an input from conductor 108 which is the receiver enable (DCD) input to SSDA 10, and an input from interrupt logic 110 via conductor 112. Status register circuit 100 also has an input from compare logic 90 via conductor 114 which also connects to RX control circuit 56, an input from parity check circuit 52 via conductor 116 and an input from RX FIFO 62 via conductor 118. The output of status register 100 is internal bus 120 which couples to buffer circuit 12. Interrupt logic 110 has an input from status register 100 via conductor 122 and produces an output via output conductor 124 which is the interrupt request via output conductor 124 which is the interrupt request output (IRQ) output of SSDA 10. TX control circuit 36 has a transmit inhibit (CTS) input via conductor 106 which also couples to status register 100 as well as inputs from control register #1, 70, via conductor 84, control register #2, 76, via conductor 86 and control register #3, 78, via conductor 88. The output of transmitting control circuit 36 couples to transmitting shift register circuit 32 via internal bus 38 and to the transmitter underflow (TUF) output of SSDA 10 via conductor 126.
FIG. 2 is a block diagram of a typical microcomputer system in which the presently preferred embodiment of the serial synchronous data adaptor may be utilized. Microcomputer system 200 includes microprocessor chip 202, which may be described in the above mentioned patent application Ser. No. 519,150. Microprocessor circuit 202 is connected to a bidirection data bus 14'. Random access memory (RAM) 204 and read only memory (ROM) 206 are connected, respectively, by means of their data bus lines to the data conductors which constitute bidirectional data bus 14'. A plurality of peripheral interface adaptor (PIA) circuits such as 207 and 208 in FIG. 2 are connected by means of their bidirectional data input output conductors to their respective conductors of data bus 14'. An exemplary PIA circuit is described in detail in copending patent application Ser. No. 519,138 mentioned above. A PIA circuit such as circuit 208 may be utilized to couple peripheral devices such as keyboard 210 to data bus 14' to allow microprocessor 202 to communicate therewith. PIA circuits may also be used to couple other peripheral devices such as teletypes, cathode ray tubes, control panels, cassettes, etc. designated in FIG. 2 by reference number 209 to bidirectional bus 14'.
FIG. 2 also includes an asynchronous communications interface adaptor (ACIA) chip 10' of the type described in U.S. Pat. No. 3,975,712 mentioned above. ACIA chip 10' couples to modem 212 via bidirectional data coupling 209 to provide asynchronous communications with data system 214.
FIG. 2 also shows that SSDA 10, may be connected by means of data bus 14 to microcomputer data bus 14'. SSDA 10 couples to modem 218 via conductors 216 with modem 218 coupling in turn to a peripheral data system 220 thus allowing SSDA 10 to perform the functions of receiving data, transmitting data and performing modem control.
The operation of SSDA 10 will now be described in terms of the functional interrelationship of the elements shown in the block diagram of FIG. 1. At the interface of data bus 14, the SSDA 10 appears as two addressable memory locations. Internally, SSDA 10 comprises 7 registers, two of which are read only and 5 of which are write only registers. The read only registers are status register 100 and receive data register 62 which is a FIFO register of three data byte capacity. The write only registers are control register #1, 70, control register #2, 76, control register #3, 78, sync code register 80 and TX data register 30. TX data register 30 is a FIFO register with a three byte data capacity. The serial interface of SSDA 10 comprises TX shift register 32, RX shift register 48, serial input and output lines with independent clocks, peripheral and modem control lines and associated logic. Additional information on FIFO registers is provided in Assignee's copending U.S. patent application Ser. No. 580,634 "FIRST-IN-FIRST-OUT REGISTER IMPLEMENTED WITH SINGLE RANK STORAGE ELEMENTS" By Hepworth et al filed on May 27, 1975.
During the power on sequence, SSDA 10 is reset by means of RESET input 72 and is internally latched in the reset condition via bits 0 and 1 of control register #1 to prevent erroneous output transitions. The sync code register, control register #2 and control register #3 should be programmed prior to the release of reset. The reset is released by clearing the control bits in control register #1.
Data is transferred to the transmitter section of SSDA 10 in parallel form by means of TX data FIFO register 30. The Tx data FIFO is a three byte register whose status is indicated by the transmitter data available (TDRA) status bit of status register 100 and its associated interrupt. Two data transfer modes are provided in SSDA chip 10, "one byte transfer mode" provides data to the transmitter section (and reading data from the receiver section) one byte at a time. The operating procedure is to determine that TDRA is high and then write a data character into the TX data FIFO 30. This process is repeated until status bit TDRA no longer returns high. The "two byte transfer mode" provides for writing two data characters in succession without a second status read. The second character can be written into the FIFO after one clock pulse on the E clock input has occurred to cause the FIFO data to shift. The data moves through the FIFO to the last empty register location being clocked by the pulse on E input 16.
Data will automatically transfer from the last register location in TX data FIFO 30 (when it contains data) to the TX shift register 32 during the second half phase of the clock cycle of the previous character. The character being transferred to the transmitter for transmission is clocked into Tx shift register 32 by the transmitter clock (CTX). Parity (odd or even) can optionally be automatically appended to the character being transmitted. The number of bytes in a character being transmitted is defined by bits 3, 4 and 5 of control register #2 as discussed below. The unused bit positions in short word length characters (including parity if applicable) are "don't cares." When the TX shift register becomes empty and data is not available for transfer from the TX data FIFO, an "under flow" is said to occur, and a character length of delay (an underflow character) is inserted into the transmitter data stream to maintain character synchronization. This is illustrated in schematic form in FIG. 3 where a synchronization character 308 has been inserted in data stream 300 to maintain synchronization. The "underflow" character (which is also called a "fill" character) to be transmitted will either be a "mark" (all bits equal logical "1") character or the contents of the sync code register depending upon the state of the "transmit sync code on underflow bit" in control register #2 as discussed below. Internal parity generation is inhibited during underflow except for sync code fill character transmission in the case of 8-bit plus parity word lengths. The underflow condition is indicated by a pulse on the TUF output conductor 126. This underflow output occurs coincident with transfer during the second half phase of the clock cycle of the last bit preceding the underflow character. In addition, the underflow status bit is set and remains set until cleared by means of the "clear underflow" control bit of control register #3.
Transmission is initiated by releasing the bus controlled transmitter reset bit (TXRs) in control register #1. When the TXRs bit is released, the first full positive half cycle of the transmitter clock (CTX) will initiate a transfer cycle. The transferred character will begin to be transmitted on the negative CTX transition which causes the transfer. If the Tx data FIFO 30 was not loaded during the Tx reset condition and two additional E clocks have not occurred, an underflow character will be transmitted.
The clear-to-send (CTS) input 106 provides for automatic control of serial character transmission in a system configuration such as the system embodiment of FIG. 12. In FIG. 2, data and control interconnections 216 would include a "clear-to-send" output from modem 218 which would connect to the CTS input 106 of SSDA 10. The CTS input at logical "1" would indicate that the modem 218 was not available for data transmission. The CTS input resets the transmitter section when high but does not reset the TX data FIFO. The TDRA status bit is inhibited by CTS being high in either the one sync code or two sync code modes of operation. In the parallel-to-serial mode (the operating mode which utilizes no internal synchronization), TDRA is unaffected by CTS in order to provide TX data FIFO status for preloading the transmitter and to operate under the control of the CTS input. When the TX reset bit of control register #1 is set, the TX data FIFO is cleared and the TDRA status bit is inhibited. After one E clock has occurred, the TX data FIFO becomes available for new data but TDRA remains inhibited. This feature allows for preloading transmit data (such as with sync codes) when the TX data FIFO status is known.
Referring to FIG. 1, data and a presynchronized clock are provided to the receiving section of SSDA 10 by means of the RX data input 50 and the RX clock input 54. Data is in a homogenous form (a continuous stream of binary data bits) without means for identifying characters within the stream. It is therefore necessary to achieve character synchronization at the beginning of the message block. FIG. 3 illustrates schematically a continuous stream of data characters 300 with synchronization characters 302 and 304 defining the beginning of a message block. When synchronization is achieved, it is assumed to be retained for all successive characters within the message block. Digital communication systems utilize the detection of predetermined reference characters known as "synchronization codes" during the initial portion of the preamble to establish character synchronization. This synchronization generally requires the detection of one synchronization code or of two successive synchronization codes. The schematic data stream 300 shown in FIG. 3 illustrates two successive synchronization codes 302 and 304.
The SSDA 10 provides three operating modes with respect to character synchronization. These are the one synchronization character mode and two synchronization character mode discussed previously and the parallel-to-serial mode. The parallel-to-serial mode requires external synchronization and control of the receiving section through the DCD input 108 (FIG. 1). This external synchronization could consist of direct line control from associated peripheral unit or from external detection of the occurrence of the beginning of the message block of data. In the one synchronization character mode of operation, internal logic of SSDA 10 compares on a bit by bit basis until a match is achieved between the data in RX shift register 48 and in synchronization code register 80. This match, as determined by comparator 92 which couples to compare logic 90, indicates that character synchronization is complete and the character reference will be retained for the message block. In the two synchronization character mode of operation the receiver searches for a first synchronization match on a bit by bit basis and then looks for a second successive synchronization code character prior to establishing character synchronization. If the second synchronization code character is not received, the bit by bit search is resumed from the first bit of the second character. In another mode of operation the synchronization code register 80 (FIG. 1) can be reloaded after the first code is detected to provide matching of a unique synchronization "code" which is two characters long (16 bits for the particular embodiment of FIG. 1). Timing for the loading of the second character can be derived from the SM/DTR output 98. Synchronization codes received prior to the completion of synchronization are not transferred to the RX data FIFO 62. Redundant synchronization codes during the preamble or synchronization codes which occur as "fill characters" within a sequence of data characters can be optionally stripped from the data using the "strip sync control bit" in control register #1 as described below. This option tends to minimize system loading. The character synchronization mode of operation will be retained until cleared by means of the "clear sync" bit in control register #1.
When synchronization has been achieved subsequent characters will automatically transfer to the RX data FIFO 62. The RX data FIFO 62 is clocked to give the timing pulse on E input 16 to cause received data to move through the FIFO to the last empty register location. Data will be transferred from RX data FIFO 62 to the system data bus 14 utilizing either the "1 byte transfer" or the "2 byte transfer" mode depending on the programming of control register #2. This transfer mode combined with the buffering action of RX data FIFO 62 provide one of the major advantages of the invention since a much higher note of data reception can be achieved. TX data FIFO 30 provides an analogous advantage for data transmission. The receiver data available status bit (RDA) indicates when data is present either in the last FIFO register location or in the last two FIFO register locations depending on the transfer mode programmed. Data being available in RX data FIFO 62 causes an interrupt to be initiated (assuming the receiver interrupt is enabled, RIE = logical "1" and the MPU chip 202 (FIG. 2) will then read the status register 100 of SSDA 10 as a result of the interrupt or in its turn in a polling sequence. The RDA status bit will indicate that receiver data is available and the MPU will subsequently read the RX data FIFO register 62. The interrupt and the RDA status bit will then be reset automatically. If more than one character had been received and was resident in RX data FIFO 62, subsequent clocks (Input 16) will cause the FIFO to update and the RDA status bit and interrupt will again be set. Parity is automatically checked as characters are received and parity errors are optionally available in status register 100 until the RX data FIFO 62 has been read. Parity errors will cause an interrupt on IRQ output 124 if the error interrupt enable bit has been set in control register #2. The parity bit is automatically set to 0 for short word length data being transferred to the MPU via the data bus.
Other status bits which pertain to the receiver section of SSDA 10 are overrun bit and the receiver inhibit bit (DCD). The overrun status bit is automatically set when a transfer of a character to the RX data FIFO 62 occurs and the first word location of the FIFO is full. Overrun causes an interrupt if EIE has been set. The transfer of the overrunning character into the FIFO causes the previous character stored in the FIFO input register to be lost. Overrun is cleared by reading the status register 100 (when the overrun condition is present) and subsequently reading RX data FIFO 62. Overrun cannot occur and be cleared without providing opportunity to detect its occurrence via the status register 100. The DCD input going high causes an interrupt if the EIE control bit of control register number 2 has been set. The interrupt caused by DCD is cleared by reading the status register when the DCD status bit is high followed by an RX data FIFO read. The DCD status bit will subsequently follow the state of the DCD input until it goes high a second time.
The operation of the SSDA and in particular its operation in a microprocessor system environment such as shown in FIG. 2, is further explained by briefly summarizing the functions performed by each of the input and output connections to the SSDA as shown in FIG. 1.
SSDA bidirectional data bus 14--these bidirectional data lines allow for data transfer between the SSDA and the MPU. In the preferred embodiment data bus output drivers are three state devices which can transmit logical 0, transmit logical 1, or remain in a high impedance (off) state which prevents interference with other MPU operations on the bus.
SSDA enable (E) 16--this input provides basic timing which enables the bus input/output data buffers and provides basic timing to clock data to and from the SSDA.
Read/write (R/W) 18--this input is used to control the direction of data flow to the SSDA. When R/W is high (MPU read cycle), SSDA output drivers 12 (FIG. 1) are turned on and a selected register is read. When R/W is low the SSDA output drivers are turned off and the MPU writes into a selected register. Therefore the R/W signal is used to select read-only or write-only registers within the SSDA.
Chip select (CS) 20--this input is used to address the SSDA. The SSDA is selected when CS is low. Transfers of data to and from the SSDA chip are then performed on control of the E input, R/W input and register select.
Register select (RS) 22--a logic "1" on this input is used to select the TX data FIFO register 30 or the RX data FIFO register 62. A logic 0 on this input is used to select the control registers 70, 76, and 78, the status register 100 and the synchronization code register 80. The R/W input is used in conjunction with register select to select the read-only or write-only register in each register pair.
Interrupt request (IRQ) 124--this output interrupts the MPU when at the logic 0 state and is arranged so that it may be connected in a "wire OR" configuration with similar request outputs from other chips in an MPU system. The IRQ output remains at a logic "0" as long as the cause of interrupt is present and the appropriate interrupt enable control bit within the SSDA chip is set.
Separate inputs are provided to the SSDA chip for the clocking of transmitted and received data:
Transmit clock (CTX) 46--the transmit clock input is used for the clocking of transmitter data. The transmitter initiates data on a negative transition of the clock.
Receive clock (CRX) 54--a receive clock input is used for the synchronization of receive data. The clock and the data (RX data input 50) must be synchronized externally. The receiver samples the data on the positive transition of the clock.
Receive data (RX data) 50--the receive data input provides the path through which data is received in serial format.
Transmit data (TX data) 44--the transmit data output transfers serial data to a modem or peripheral associated with the SSDA.
The SSDA includes several inputs and outputs that function to permit limited control of associated peripherals or modems.
Clear to send (CTS) 106--the CTS input 106 provides a real time inhibit of the transmitter section which functions without disturbing the contents of the TX data FIFO 30. When the CTS input 106 is a logic "1," it inhibits the TDRA status and its associated interrupt in both synchronization modes of operation. TDRA bit of status register 100 is not affected by the CTS input 106 in the parallel to serial mode.
Data carrier detect (DCD) 108--the DCD input also referred to as receiver enable, provides automatic control of the receiving end of the serial data system by means of system hardware. DCD input 108 at logic "1" inhibits the receiver section except for the RX data FIFO register 62 and its associated RDA status bit. The DCD input 108 going to logic "1" results in the storage of the event within the SSDA to insure the system recognizes its occurrence as a transient. The DCD input provides character synchronization timing for receiver data during parallel-to-serial operation. The receiver will be initialized and data will be sampled on a positive transition of the first full clock cycle of the receiver clock one bit time after the release of DCD.
Sync Match/Data Terminal Ready (SM/DTR) 98--The SM/DTR output 98 provides two additional functions which depend on the state of the PC1 and PC2 control bits (control register #2). When the sync match mode is selected, the output provides a one bit wide pulse when a sync code is detected.
Transmitter underflow (TUF) 126--the TUF output indicates the occurrence of a transfer of a "fill character" to the transmitter shift register 32 when the last register in TX data FIFO 30 is empty. RESET 72--RESET input provides a means of resetting the SSDA from a hardware source. In the logic "0" (active) state the RESET input causes the following:
1. RX reset and TX reset (control register #1) are set causing both the receiver and transmitter section to be held in a reset condition.
2. PC Mode (control register #2) is selected and PC output is at logic "1."
3. A synchronization mode is selected (control register #3).
4. The TDRA status bit is inhibited (TDRA = logic "0").
When RESET returns to a logic "1" (the inactive state), the transmitter and receiver section will remain in the reset state until RX reset and TX reset are cleared via the bus under software control.
Seven registers in the SSDA can be accessed by means of the data bus 14 (FIG. 1). The registers are defined as read-only or write-only according to the direction of information available. The register select (RS) input 22 selects two registers in each state, one being read-only and the other write-only. The read/write (R/W) input 18 defines which of the two selected registers will actually be accessed. Four registers (two read only and two write-only) can be addressed via the data bus at any particular time. The following truth table defines these registers and the required addressing. In this table, the notation C1b6 and C1b7 refers to the sixth and seventh bits of control register #1 respectively and the notation X refers to a "don't care" condition. It is important to note that bits 6 and 7 of control register #1 provide supplementary address codes which allow the indirect addressing of additional register under program control.
______________________________________ R/W RS Clb6 Clb7______________________________________Control Register #1 (write-only) 0 0 X XStatus Register (read-only) 1 0 X XControl Register #2 (write-only) 0 1 0 0Control Register #3 (write-only) 0 1 1 0Sync Code Register (write-only) 0 1 0 1Transmit Data Register (write-only) 0 1 1 1Receiver Data Register (read-only) 1 1 X X______________________________________
A summary of the operation of the SSDA as defined by the functional operation of its internal registers is provided by the following tables in which Table 1 provides a definition of directly addressed registers, Table 2 provides a definition of indirectly addressed registers and Table 3 provides additional details on the programming of the word length select bits provided in control register two in order to program various word length options for the SSDA.
In the heading of Table 1 a Boolean notation is used to define register address in terms of the logical state of the RS input 22 and the R/W input 18 (FIG. 1). For example, the notation RS � R/W indicates that the RS input is at a logical "1" level simultaneous with the R/W input at a logic "0" level. A similar notation is used in Table 2 to define register addresses in terms of bit 6 and bit 7 of control register #1. For example, the notation C1b6.C1b7 indicates that in control register #1, bit 6 is at a logic "1" state and bit 7 is at a logic "0" state.
TABLE 1__________________________________________________________________________DEFINITION OF DIRECTLY ADDRESSED REGISTERSRegisterAddressRS . R/W RS . R/W RS . R/W RS . RW__________________________________________________________________________ Receiver ControlBus Data Register StatusLine Register Number 1 RegisterNumber(Write Only) (Read Only) (Write Only) (Read Only)__________________________________________________________________________0 Data Bit 0 Rx Reset Rx Data Avail. (RDA)1 Data Bit 1 Tx Reset Tx Data Reg. Avail. (TDRA)2 (See Table 2) Data Bit 2 Strip RX DCD Sync Char.3 Data Bit 3 Clear CTS Synchronization4 Data Bit 4 Tx Interrupt Underflow Enable (TIE) (unfl)5 Data Bit 5 Rx Interrupt Overrun Enable (TIE) (OVRN)6 Data Bit 6 Address Control Parity Error #1 (ACI) (PE)7 Data Bit 7 Address Control Interrupt #2 (AC2) Request (IRQ)__________________________________________________________________________
TABLE 2__________________________________________________________________________DEFINITION OF INDIRECTLY ADDRESSED REGISTERSRegisterAddress C.sub.1 b.sub.6 . C.sub.1 B.sub.7 C.sub.1 b.sub.6 . C.sub.1 b.sub.7 C.sub.1 b.sub.6 . C.sub.1 b.sub.7 C.sub.1 b.sub.6 . C.sub.1 b.sub.7__________________________________________________________________________Register TransmitterName - Control Control Sync Code DataBus Line Register #2 Register #3 Register RegisterNumber (Write Only) (Write Only) (Write Only) (Write Only)__________________________________________________________________________0 PC1 Parallel-to-Serial Sync Bit Tx Data 0 Bit 01 PC2 1 Sync/2 Sync Sync Bit Tx Data Mode 1 Bit 12 1 Byte/2 Byte Clear CTS Sync Bit Tx Data Transfer 2 Bit 23 Word Sel #1 Clear Underflow Sync Bit Tx Data (WS1) 3 Bit 34 Word Sel #2 -- Sync Bit Tx Data (WS2) 4 Bit 45 Word Sel #3 -- Sync Bit Tx Data (WS3) 5 Bit 56 Tx Sync Code -- Sync Bit Tx Data on Unfl 6 Bit 67 Error Interrupt -- Sync Bit Tx Data Enable (EIE) 7 Bit 7__________________________________________________________________________
TABLE #3______________________________________WORD LENGTH SELECTIONWS.sub.1 WS.sub.2 WS.sub.3 Word Length______________________________________0 0 0 6 bits + Even Parity1 0 0 6 bits + Odd Parity0 1 0 7 bits No Parity1 1 0 8 bits No Parity0 0 1 7 bits Even Parity1 0 1 7 bits Odd Parity0 1 1 8 bits Even Parity1 1 1 8 bits Odd Parity______________________________________
|Cited Patent
|Filing date
|Publication date
|Feb 28, 1963
|Mar 21, 1967
|Time shared telegraph transmission system including sequence transmission with reduction of start and stop signals
|Aug 12, 1965
|Sep 3, 1968
|Universal code synchronous transmitter-receiver device
|Nov 30, 1962
|Dec 31, 1968
|Burroughs Corp
|Modular computer system
|Feb 14, 1966
|Dec 31, 1968
|Burroughs Corp
|Input/output control system for electronic computers
|Feb 29, 1972
|Jul 24, 1973
|Bell Telephone Labor Inc
|Translator memory decoding arrangement for a microprogram controlled processor
|Aug 31, 1971
|Sep 4, 1973
|Texas Instruments Inc
|Computing systems cpu
|Feb 12, 1971
|Nov 6, 1973
|Honeywell Inf Systems
|Communication control device utilized as an input/output module for a remote terminal system
|Sep 13, 1972
|Jul 23, 1974
|Action Communication Syst Inc
|Binary synchronous communications processor system and method
|Dec 26, 1973
|Feb 10, 1976
|Xerox Corporation
|Input/output connection arrangement for microprogrammable computer
|Feb 18, 1975
|Aug 17, 1976
|Motorola, Inc.
|Asynchronous communication interface adaptor
|Citing Patent
|Filing date
|Publication date
|Apr 25, 1978
|Feb 5, 1980
|The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
|High-speed data link for moderate distances and noisy environments
|Oct 4, 1977
|May 27, 1980
|Ncr Corporation
|Digital communications system utilizing controllable field size
|Apr 9, 1979
|Oct 21, 1980
|Honeywell Inc.
|Bus allocation synchronization system
|Apr 14, 1978
|Jun 2, 1981
|Compagnie Internationale Pour L'informatique Cii-Honeywell Bull
|Apparatus enabling the transfer of data blocks of variable lengths between two memory interfaces of different widths
|Mar 4, 1980
|Apr 27, 1982
|Bell Telephone Laboratories, Incorporated
|High capacity elastic store having continuously variable delay
|Sep 5, 1978
|Aug 24, 1982
|Motorola, Inc.
|NRZ/Biphase microcomputer serial communication logic
|Mar 21, 1980
|Nov 9, 1982
|Motorola, Inc.
|Control circuitry for data transfer in an advanced data link controller
|Mar 28, 1980
|Dec 21, 1982
|Pitney Bowes Inc.
|Serial communications bus for remote terminals
|Mar 21, 1980
|Jan 11, 1983
|Motorola, Inc.
|Advanced data link controller having a plurality of multi-bit status registers
|Jun 5, 1980
|Dec 6, 1983
|Bell Telephone Laboratories, Incorporated
|Voiceband data set
|Sep 22, 1980
|Dec 13, 1983
|Etablissement Public De Diffusion Dit "Telediffusion De France"
|Unidirectional data transmission system
|Jan 15, 1982
|Sep 25, 1984
|Hitachi, Ltd.
|Data transfer system in which time for transfer of data to a memory is matched to time required to store data in memory
|Aug 2, 1982
|Jan 22, 1985
|International Business Machines Corporation
|Microprocessor-controlled adapter circuit for real-time controls, in particular for print hammer controls
|Jun 24, 1982
|Apr 2, 1985
|Wang Laboratories, Inc.
|Data transmitting link
|Mar 5, 1982
|Apr 30, 1985
|Burroughs Corporation
|Byte-oriented line adapter system
|Oct 9, 1980
|May 7, 1985
|Burroughs Corporation
|Multiplexed data communications using a queue in a controller
|Jan 28, 1983
|Jun 11, 1985
|Gould Computer Systems Inc.
|Synchronous communications multiplexer
|Dec 27, 1983
|Jan 28, 1986
|Rockwell International Corporation
|Multiplex equipment monitoring apparatus
|Nov 21, 1983
|Apr 29, 1986
|The United States Of America As Represented By The Secretary Of The Navy
|Digital bus adaptor
|May 3, 1984
|May 13, 1986
|Billy Jean C
|Multiplexer, demultiplexer and multiplexing-demultiplexing equipment with reconfigurable frames
|Mar 28, 1983
|Sep 9, 1986
|Digital Equipment Corporation
|Circuitry for identifying the validity of received data words
|Sep 15, 1983
|Feb 10, 1987
|Pitney Bowes Inc.
|Interface for mailing system peripheral devices
|Sep 5, 1986
|Jun 9, 1987
|The United States Of America As Represented By The Secretary Of The Air Force
|Network interface module and method
|Feb 19, 1987
|Jul 12, 1988
|Sony Corporation
|Coding digital data
|Apr 22, 1985
|Oct 18, 1988
|The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
|Laser Doppler Velocimeter multiplexer interface for simultaneous measured events
|Aug 29, 1986
|Nov 15, 1988
|Hewlett-Packard Company
|Digital data buffer and variable shift register
|Apr 25, 1986
|Nov 15, 1988
|International Business Machines Corporation
|Error detection using variable field parity checking
|Jul 24, 1986
|May 2, 1989
|Digital Equipment Corporation
|High speed interconnect unit for digital data processing system
|Nov 9, 1987
|Jun 20, 1989
|The United States Of America As Represented By The United States Department Of Energy
|Universal null DTE
|Jun 28, 1984
|Nov 27, 1990
|Westinghouse Electric Corp.
|Digital IC-microcomputer interface
|Oct 30, 1989
|Mar 26, 1991
|International Business Machines Corporation
|Data synchronizing buffers for data processing channels
|Apr 1, 1986
|Apr 9, 1991
|Westinghouse Electric Corp.
|Bidirectional communication and control network with programmable microcontroller interfacing digital ICS and controlled product
|Sep 1, 1987
|May 28, 1991
|Nec Corporation
|Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data
|Apr 15, 1991
|Nov 19, 1991
|Bayerische Motoren Werke Aktiengesellschaft
|Circuit arrangement for serial data transfer
|May 26, 1989
|Jun 2, 1992
|International Business Machines Corporation
|Parallel processing method and device for receiving and transmitting hdlc sdlc bit streams
|Mar 13, 1992
|Jul 6, 1993
|Hitachi, Ltd.
|Integrated data processor having mode control register for controlling operation mode of serial communication unit
|May 2, 1990
|Jul 13, 1993
|Digital Equipment Corporation
|Synchronous communication interface for reducing the effect of data processor latency
|May 17, 1991
|Aug 31, 1993
|National Semiconductor Corporation
|Buffered asynchronous communications element with receive/transmit control and status reporting
|Feb 4, 1991
|Jan 4, 1994
|International Business Machines Corporation
|Data storage buffer system and method
|Jan 22, 1990
|Jan 11, 1994
|Vlsi Technology, Inc.
|Variable sized FIFO memory and programmable trigger level therefor for use in a UART or the like
|Mar 26, 1993
|Feb 15, 1994
|National Semiconductor Corporation
|Buffered asynchronous communications elements with receive/transmit control and status reporting
|Apr 21, 1993
|Nov 1, 1994
|Hitachi, Ltd.
|Integrated data processor having mode control register for controlling operation mode of serial communication unit
|Apr 5, 1995
|Mar 12, 1996
|Monolithic System Technology, Inc.
|Reduced CMOS-swing clamping circuit for bus lines
|Feb 16, 1993
|Mar 26, 1996
|Sony Corporation
|Bus system with virtual logical buffer
|Mar 22, 1995
|Jul 16, 1996
|International Business Machines Corporation
|Field programmable general purpose interface adapter for connecting peripheral devices within a computer system
|Sep 11, 1995
|Oct 1, 1996
|Silicon Systems, Inc.
|Configurable architecture for serial communication
|Feb 25, 1994
|Oct 8, 1996
|Silicon Systems, Inc.
|Reconfigurable architecture for multi-protocol data communications having selection means and a plurality of register sets
|Dec 10, 1993
|Nov 19, 1996
|Monolithic System Technology, Inc.
|Wafer-scale integrated circuit interconnect structure architecture
|Jun 6, 1995
|Jan 7, 1997
|Monolithic System Technology, Inc.
|Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system
|Sep 14, 1994
|Mar 18, 1997
|Monolithic System Technology, Inc.
|Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system
|Jun 27, 1994
|Apr 22, 1997
|Brother Kogyo Kabushiki Kaisha
|Data processing apparatus having a bidirectional interface with receiving buffers, three-state buffers, and enable terminals for automatically switching the direction of data transmission and reception
|Jul 5, 1994
|Aug 5, 1997
|Monolithic System Technology, Inc.
|Resynchronization circuit for a memory system and method of operating same
|Jun 6, 1995
|Sep 9, 1997
|Monolithic System Technology, Inc.
|Fault-tolerant hierarchical bus system and method of operating same
|Oct 27, 1995
|Mar 17, 1998
|Monolithic System Technology, Inc.
|Termination circuits for reduced swing signal lines and methods for operating same
|Jun 6, 1995
|Apr 7, 1998
|Monolithic System Technology, Inc.
|Resynchronization circuit for circuit module architecture
|Oct 3, 1996
|Jun 16, 1998
|Lg Semicon Co., Ltd.
|Apparatus for receiving and transmitting a serial data
|Feb 5, 1996
|Jul 14, 1998
|Lsi Logic Corporation
|High speed phase locked loop test method and means
|Jan 17, 1996
|Jul 14, 1998
|Lsi Logic Corporation
|Method for interleaving network traffic over serial lines
|Jan 17, 1996
|Jul 28, 1998
|Lsi Logic Corporation
|Loop-back test system and method
|Jun 23, 1997
|Aug 4, 1998
|Lsi Logic Corp.
|Self test of core with unpredictable latency
|Aug 9, 1996
|Nov 3, 1998
|Monolithic System Technology, Inc.
|Termination circuit with power-down mode for use in circuit module architecture
|Jan 13, 1997
|Dec 1, 1998
|Monolithic System Technology, Inc.
|Circuit module redundancy architecture process
|Jun 24, 1996
|Dec 8, 1998
|U.S. Philips Corporation
|Method of and system for interleaving real-time files with different periods
|Apr 25, 1996
|Mar 2, 1999
|Northern Telecom Limited
|Data transfer method and apparatus
|Feb 5, 1996
|Apr 20, 1999
|Lsi Logic Corporation
|Programmable synchronization character
|Sep 12, 1995
|May 4, 1999
|Zsp Corporation
|Processor having a hierarchical control register file and methods for operating the same
|Jan 17, 1996
|Sep 21, 1999
|Lsi Logic Corporation
|Wrap-back test system and method
|May 15, 1995
|Oct 12, 1999
|Zsp Corporation
|Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution
|Sep 19, 1997
|Nov 16, 1999
|Samsung Electronics Co., Ltd.
|Serial interface circuit for adaptively supporting the serial interface of read/write channel circuits in a magnetic disk drive
|Mar 9, 1995
|Jun 27, 2000
|Lsi Logic Corporation
|Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file
|Mar 3, 1999
|Jul 11, 2000
|Hitachi, Ltd.
|Synchronous data transfer system
|Mar 17, 1998
|Dec 19, 2000
|Lsi Logic Corporation
|System and method for establishing unique sequence identification in an information exchange of a system network
|Oct 30, 1997
|Aug 7, 2001
|Monolithic System Technology, Inc.
|Data processing system with master and slave devices and asymmetric signal swing bus
|Jan 28, 2000
|May 21, 2002
|Monolithic System Technology, Inc.
|Dynamic address mapping and redundancy in a modular memory device
|May 16, 2000
|Jan 7, 2003
|Cisco Technology, Inc.
|Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
|Dec 8, 2002
|Dec 9, 2003
|Cisco Technology, Inc.
|Group and virtual locking mechanism for inter processor synchronization
|Oct 15, 2002
|Apr 6, 2004
|Monlithic System Technology, Inc.
|Latched sense amplifiers as high speed memory in a memory system
|Mar 23, 2000
|Jun 22, 2004
|Monolithic System Technology, Inc.
|Memory array with read/write methods
|Mar 28, 2000
|May 10, 2005
|Cisco Technology, Inc.
|Method and apparatus for high-speed parsing of network messages
|Mar 21, 2005
|Jul 1, 2008
|Cisco Technology, Inc.
|Method and apparatus for high-speed parsing of network messages
|Aug 23, 2006
|Oct 6, 2009
|Nec Electronics Corporation
|Semiconductor device
|Mar 11, 2004
|Dec 15, 2009
|Mosys, Inc.
|Error detection/correction method
|Apr 1, 2005
|May 3, 2011
|Freescale Semiconductor, Inc.
|Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface
|May 18, 2010
|Jun 25, 2013
|Electronics And Telecommunications Research Institute
|Apparatus and method for transmitting and receiving data
|Jun 29, 2014
|May 31, 2016
|Freescale Semiconductor, Inc.
|Memory controller
|Mar 11, 2004
|Dec 23, 2004
|Monolithic System Technology, Inc.
|Latched sense amplifiers as high speed memory in a memory system
|Mar 21, 2005
|Jul 28, 2005
|Silvano Gai
|Method and apparatus for high-speed parsing of network messages
|Apr 1, 2005
|Oct 5, 2006
|Quiroga Emilio J
|Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface
|Aug 23, 2006
|Apr 19, 2007
|Nec Electronics Corporation
|Semiconductor device
|Mar 6, 2008
|Aug 28, 2008
|Mosys, Inc.
|Error Detection/Correction Method
|May 18, 2010
|Nov 25, 2010
|Electronics And Telecommunications Research Institute
|Apparatus and method for transmitting and receiving data
|Dec 6, 1985
|Oct 9, 1990
|At&T Bell Laboratories
|Voiceband data set
|Mar 12, 1996
|Apr 25, 2000
|Lucent Technologies Inc.
|Viceband data set
|Sep 5, 1979
|Mar 13, 1980
|Motorola Inc
|Sep 19, 1980
|Jul 2, 1981
|Honeywell Inf Systems
|Mar 27, 1981
|Apr 1, 1982
|Pitney Bowes Inc
|Serieller kommunikationsbus fuer fernterminals
|Jun 6, 1997
|Jun 14, 2006
|Samsung Electronics Co., Ltd., Suwon
|Serieller Schnittstellenschaltkreis
|Dec 2, 1981
|Dec 15, 1982
|Ncr Co
|Chip topography for integrated circuit communication controller.
|Dec 2, 1981
|Dec 11, 1985
|Ncr Corp
|Chip topography for integrated circuit communication controller.
|Jun 6, 1991
|Dec 11, 1991
|Mita Industrial Co. Ltd.
|A signal communication system
|Jun 6, 1991
|Mar 23, 1994
|Mita Industrial Co Ltd
|Title not available
|Oct 17, 1991
|Apr 29, 1992
|AT&T Corp.
|Message-oriented bank controller interface
|Oct 17, 1991
|Feb 1, 1995
|AT&T Corp.
|Message-oriented bank controller interface
|Oct 9, 1980
|Apr 16, 1981
|Burroughs Corp
|Improvements in or relating to data communications
|May 21, 1981
|Dec 10, 1981
|Western Electric Co
|Voiceband data set
|Oct 29, 1981
|May 27, 1982
|Wang Laboratories
|Data transmitting link
|Jan 27, 1984
|Aug 2, 1984
|Gould Computer Syst Inc
|Synchronous communications multiplexer
|U.S. Classification
|710/305, 375/219, 375/377, 710/62, 370/503, 370/472
|International Classification
|Cooperative Classification
|European Classification


text:
VideoHive Dead Planet Intro 9905600
After Effects Project \ Openers \ 3D \ Object
Planet \ Included \ Compatibility \ Duration \ Questions \ Maestro \ Kirill
After Effects Project - Dead Planet Intro 9905600 by Maestro_O @ VideoHive
After Effects Project \ Openers \ 3D \ Object
Hello, dear colleagues!
Here is Dead Planet Intro!
Project features.
- No plugins required
- Very easy to use – just put your Logo and edit text
- Full HD resolution (1080p), 25fps
- Duration – 00:20
- CS5, CS5.5, CS6 compatibility
- Music track are not included
- Music you can find here
- If you have any questions – please, contact me via my email: [email protected]
Thank you!
Requires Plugins: No; After Effects Version: CS5, CS5.5, CS6; Resolution: 1920x1080; File Size: 245mb.
Frozen Logo Intro; Fabric Logo Intro; Torn Paper Package; News Program Opener; TV News Package.
Keywords: 3d, armageddon, cinematic intro, epic intro, film intro, glow, intro, logo, planet, planet intro, space, star, stars, trailer.
Create VideoHive Dead Planet Intro 9905600 style with After Effect, Cinema 4D, 3DS Max, Apple Motion or PhotoShop. VideoHive Dead Planet Intro 9905600 from creative professional designers. Full details of VideoHive Dead Planet Intro 9905600 for digital design and education. VideoHive Dead Planet Intro 9905600 desigen style information or anything related.

subset: commoncrawl


text:
Latin Kingz Trailer (2003)
04 March 2003
Everyone wants to get their hands on a valuable stash of narcotics in this gritty crime drama from writer/director Daniel Zirilli. Set on the mean streets of South Florida, Latin Kingz sees the cargo lost by its original owner and found by a band of local thugs. The small-timers think they've hit the motherload, but in the world of crime, nothing's that easy. Before long the smugglers show up to reclaim their goods by any means possible.
Watch the official Latin Kingz 2003 trailer in HD below or find more Latin Kingz videos on Vidimovie.


text:
Product Description
The power mat is made from a non-conductive, non-corrosive composite fiberglass construction. Mats are designed to be permanently buried in your batter's box 3" below grade. Rigid design will not curl. Eliminates dangerous holes created by "digging in". Size: 32"W x 60"L. (Shown prior to installation.)
Product Reviews
This product hasn't received any reviews yet. Be the first to review this product!


text:
Tag Archives: Emitters
28Aug 2017
Last week on August 15th, Quebec and California of the Western Climate Initiative held the twelfth joint cap and trade auction. The auction was a success, with both current 2017 and future 2020 vintage allowances selling out completely. The success of the auction reflects that the cap and trade program is firmly cemented into the ...Continue Reading
14Jun 2017
The second Cap and Trade Auction, held on June 6th, completely sold out current (2017) emission allowances. 53.7% of future 2020 emission allowances were sold as well, which is more than double the amount that were sold in the previous auction. The Ontario Cap and Trade program is off to a solid start. The first […]Continue Reading
14Jun 2017
One critique of carbon markets and cap and trade programs is that they are complicated and difficult to understand. CSG has developed visual diagrams that help explain the complexities of two carbon market systems (1) the Western Climate Initiative (WCI) carbon market between California, Quebec and Ontario (when linked in 2018), and ...Continue Reading
14Jun 2017
For Ontario to have a complete cap and trade system as contemplated in the Ontario government's announcements, there are two significant elements left to be added. Those elements are (i) the creation of a link with California and Quebec and (ii) the creation of an Ontario offset system. This article deals with an important part ...Continue Reading
13Jun 2017
The Climate Solutions Group Limited has created a structured offset product that will represent a proportionate share of the deliveries from a portfolio of offset contracts to be used by emitters to assist in satisfying compliance obligations in an efficient and economical manner. The offsets will be usable, as chosen by the GHG ...Continue Reading
26May 2017
Strong results of the 11th Joint Auction between California and Quebec of the Western Climate Initiative (WCI) were announced by regulators on May 24th, 2017. The auction, held on May 16th, 2017, sold out current vintage allowances for the first time since November 2015. The WCI auction results are good news for Ontario. Why? The ...Continue Reading
09May 2017
The Ontario Cap and Trade Forum, held on April 26th and 27th in Toronto brought together government representatives, industry associations, regulated emitters, and a range of carbon market service providers who all share a stake in Ontario's emerging carbon market. A number of presentations and panel discussions across two full ...Continue Reading
25Apr 2017
On April 6th, the California Court of Appeal upheld the California Air Resource Board's cap and trade program. This is a big deal. California is the world's sixth largest economy and it is balancing the priorities of economic growth tackling climate change. This sets a precedent for other jurisdictions and shows that cap and ...Continue Reading
20Apr 2017
By and large, Ontario's first cap and trade auction was a success. 2017 emission allowances were completely sold out which signals that regulated emitters in Ontario have embraced the cap and trade program and are preparing for the transition to a low carbon economy. The fact that 26% of the available 2020 vintage allowances ...Continue Reading


text:
Re: Alexander Shephard Young Lusk
In reply to:
Re: Alexander Shephard Young Lusk
Mike Lusk 9/27/12
That is what I thought and found as well. Thanks! Have you come across any information regarding the Lusk school in Johnson City, TN or Jonasborough?Was just wondering, evidently Alexander was 1 of 8 local school teachers in the area, and the Lusk school does appear but having trouble putting the two together. Probably need to find a local historian of the area for more information. Forgive me if I asked you this already...:)


text:
Fear the Asterisk! wahaha...
Somebody keeps stealing the padlocks in our house.
It all started before Christmas, and so far they've managed to filch three of our locks. It's actually more annoying than intimidating, as new locks are quite expensive (the good ones cost about 2 and half dollars, which is already a handful here in our country) and we have to update our keys every time it gets lost. So far we don't know who the culprit(s) is/are, although Mom says it's probably some of the bored kids roaming around the neighborhood, which kind of makes a lot more sense than my theory involving keymaker elves bent on a worldwide conspiracy to monopolize the padlock industry. But I'm still not taking the jumper cables off the gate though (hahaha just kidding*)


text:
Due to high order volume, orders can take 5 to 7 business days to ship.
- Description
Ruger 3235 LC9s Standard Double Action 9mm 3.1" 7 1 Integral Grip Blued Steel
The striker-fired Ruger LC9s features a short, light, crisp trigger pull
for faster shooting and improved accuracy. The LC9sprovides slim,
lightweight and compact personal protection with a blued steel slide, a
high-performance, glass-filled nylon grip frame, aggressive checkering and
an easily acquired 3-dot sight system. The LC9s fits all LC9 accessories
and holsters and is just slightly larger (less than 1" in both height and
length) than the Ruger LCP.
Mfg Item Num: 3235
Category: PISTOLS
Type :Pistol
Action :Double
Caliber :9mm
Barrel Length :3.1"
Capacity :7 1
Safety :Manual
Grips :Integral
Sights :3-Dot
Weight :17.20 oz
Frame Finish :Blued
Frame Material :Polymer
Barrel Type :Alloy Steel
Slide Description :Blued Alloy Steel
Barrel Length Range :3.00" to 3.99"
Weight Range :16.00 oz to 31.99 oz
Ruger 3235 LC9S 9MM Striker Fired LC9 This compact 9 mm is truly special at just 6 long and 4.5" tall. The LC9S is designed to fit a variety of holsters and provide concealed carry options. A few features: Rugged construction with through-hardened alloy steel or stainless steel slide and black, one-piece, high-performance, glass-filled nylon grip frame. Strong grip frame provides a secure and comfortable grip. Includes finger grip extension floor plate that can be added to the magazine for comfort and grip. Fixed front and rear sights are integral to the slide, while the hammer is recessed within the slide. Product specifications: Caliber: 9 mm Luger Slide Material: Through-Hardened Alloy Steel Slide Finish: Blued Barrel Material: Steel Barrel Finish: Blued Barrel Length: 3.12" Sights Adjustable 3 dot Length: 6" Width: 0.9" Height: 4.50" Weight: 17.2 oz. Sights:3-Dot Capacity: 7 1 Grip Frame: Black High-Performance, Glass-Filled Nylon Twist: 1:10" RH Grooves: 6
- Additional Information
Additional Information
Manufacturer Ruger SKU GAG_93837 Condition New in Box Action Type No Caliber 9mm UPC 736676032358 Model LC9s Type No Manufacturer Part Number 3235 Accessories No Barrel Length No Finish Per Color Black Capacity No Firing Casing No Frame Per Material No Hand No Sights No
- Reviews
Customer Reviews 24 item(s)
- Happy with Grabagun
What can I say? I ordered this gun on Wed night (10PM), turned in FFL paperwork Thursday morning at 9AM, and had the gun Friday. So easy and such a great price. The LC9S is a great concealed gun for the price!
Value Quality
- Small But Mighty
I purchased my first LC9s in August 2014, and now have over 700 rounds (range ammo and hollow points) through it without a single malfunction. It has been rock solid. The trigger is amazing, as is the accuracy of the pistol, especially given its diminutive size. With the right IWB, OWB or pocket holster it is perfectly suited for concealed carry. Also, I find the manual safety very easy (but not too easy) to engage and disengage. (My second LC9s is the nickel plated, engraved Prescott anniversary edition and hasn't made its way out of the safe yet.) I highly recommend this pistol.
Quality Value
- Ruger LC9S
I recently purchased the Ruger LC9S and have only put 100 rds through it but had no issues at all. I love the trigger on this gun accuracy is good and the fact that its still small enough to to pocket carry if I choose. The finish looks good and all cosmetics are up to par. The only one wish I have and just my preference is I wish they would make the dots on the sights a bit bigger for us older shooters. I really like this gun so much I am going to install the some tru glow sights which will fix this issue for me. I also have to say Grab a gun is amazing how they can sell this gun for this price and ship it out for 2 day delivery for $5 is great thanks Grab a gun this is why I keep coming back .
Value Quality
- Great Gun, Great Transaction
Researched the gun I wanted to buy and of course GAG had the best price. It was in stock so picked up the same day I ordered online. I will always shop GAG first.
Value Quality
- Great Gun, Great Transaction
Was looking for a CCW for my wife. She had some specific requirements in a gun. Watched several videos and decided on the LC9S and of course GAG had the best price of any place I looked. I'm local to their location so fortunately it was in stock and I was able to pick up same day and we were shooting that night.
Gun shoots very well and wife really likes it. GAG is definitely the place to buy your firearms.
Value Quality
- Outstanding product ---Outstanding Customer Service
Great handgun, outstanding Customer Service. I order this pistol in Oct 2015, absolutely love it. Ordered my second gun from Grab a Gun last week. Customer service called Tuesday evening 7/5/16 to tell me it shipped and my local FFL dealer called this morning 7/6/16 before 11:30 am saying it had arrived.... From Texas to WV in less than 24 hours! OUTSTANDING!
I will order again Soon!
Value Quality
- THE BEST on the web
To me;this is the sweetest pistol I have ever fired. the pull on the trigger is excellent with no adjustment.I have several concealed weapons that I used to carry;know they stay locked up most of the time. Very pleased with the shipment from GAG,and the entire transaction was a joyful experience {never said that before}: and yes I would recommend this to a friend or enemy. Do yourself a favor and check out GAG .
Quality Value
- Poor design on safety
Great gun. My only complaint is the safety. Too mushy. Going from one position to the other there is very little click. I holstered it with the safety on. When I pulled the gun out of my IWB holster the safety was off. I did this 5 times. 3 out the five times the safety was off after pulling it. My Ruger SR9c has a super great safety. They should have incorporated that design on the LC9s.
Value Quality
Value Quality
- I will always shop here first
Had excellent dealings with Grabagun. Super fast delivery, kept in touch. A very nice gun. Thanks Grabagun
Value Quality
- Great deal on a great compact 9mm ! A+
AWESOME, AWESOME, AWESOME! I had the original LC9 & hated the trigger! Sold it & purchased this striker fired version & love it! Nice & compact, good firepower, great trigger & Ruger reliability! Not to mention, the great price & super fast delivery from Grabagun!
Value Quality
- I would rec. to friends
My 4th order from these guys. All prices reasonable. Placed phone order Monday recieved by FFL dealer Tuesday. Picked up Ruger LC9 S 24 hours after order was placed. No credit card fee.
Value Quality
- Excellent Concealed Accurate Firearm
I did not go with the Pro because I appreciate the safety features this firearm has to offer. Took it out on the range and had no accuracy issues up to 15 yards! Compact, slim, comfortable, and easily passes as one of the current top ten concealed firearms.
Value Quality
- Love it!
I love this gun. It fits perfect in my hand with the magazine extender on it. Fires flawlessly even using cheap range ammo (so far). Many comparisons are being made to this and the S&W Shield. The takedown is a bit harder, but plenty easy. My only complaint is the fact S&W comes with 2 clips.
Quality Value
- Great Product - Even Greater delivery
I ordered this gun late in the evening April 6th, and received an email from UPS that it was delivered today at my FFL, and picked it up after work. Extremely happy with the price, and the ease of dealing with them. I called my local FFL and he said they already had his info, and sure enough, it was on their drop-down list. I will very likely order through them again as I am extremely happy.
Thank you Grab-A-Gun!!! Until next time...
Value Quality
- Definitely an improvement
I purchased the original LC9 when Grabagun first offered it and I liked it. The LC9S is an improvement to a very good model. I am very satisfied with the results and have recommended it to friends and family.
Quality Value
- Great concealable weapon.
Nice handgun with it's narrow profile. Fits easily in my coat pocket and can also be carred in a front jean pocket. Very pleased with the gun. Well thought out and produced. I like the safety both the trigger and external. I use it when I want to (easily switches off) or not use it if I am in a tight situation.
I would recommend it. My gunsmith liked it and my gun buddies also liked it.
Value Quality
- Most excellent
Great little gun, well made and solid. Pocket gun yes, but with great confidence. Shoots well, easy and smooth. Only issue I have is the sensitive mag release. Smooth trigger and spot on sights. Take down is a hiccup- maybe they could learn a bit from the PPS. All in all well worth it and great value at GAG
Quality Value
- Pro version was a nice surprise!!
This is a great shooter. Ordered two and was pleasantly surprised to have had two LC9s Pro versions show up. Fixed is the redundant safeties. The trigger is crisp and smooth. Ruger should really step up and add a second magazine, but still not enough to knock down the 5 stars of this shooter.
Value Quality
- Great CCW gun!
This was my first Ruger purchase. Overall I like the gun. I have a couple of things I would change if I could. For example, the takedown can be a PITA. You have to hold the slide back just in the perfect spot while pushing the pin out from the gun with something. That takes a bit of getting used to.
Also, I do not recommend this for women. Racking the slide back is harder than other guns. The spring is pretty stiff. Operating the slide release cannot be done one-handed. I even have to pull the slide back while pushing down in order for it to go forward. That could be a serious issue if your put in a situation where you need to re-load fast. Chances are, one mag will be enough but you never know. The trigger pull is very nice and it fits in the hand pretty well. I'll admit I'm a little spoiled with my full size Walther PPX but, all in all, I recommend this gun for carry.
Value Quality
- Awesome and Terrible
Awesome for what you want it to do easily concealable, great trigger, good fit and finish, reliable; I love shooting it.
Terrible because of external and magazine safety. This is a defensive handgun and Ruger aught to get rid of the extra safeties. If they ever make a model without a manual safety I'll upgrade to that. Also a little clunky for taking down and cleaning.
Despite the extra safeties; the gun shoots so well I still love it.
Value Quality
Ruger has made a very good gun into the perfect pocket gun with making it striking fired & an amazing trigger!! This was my first time ordering online & Grab a Gun exceeded my expectations. No problems in shipping to my FFL!! Thank U Grab a Gun!!
Quality Value
- Fantastic!
- The LC9s is a great little gun, with an amazing trigger. The accuracy is incredible for such a short barrel. So far, it has been 100% reliable, with both FMJ and HP ammo. This gun is a real gem.
- Great improvements.
I own the LC9 and the LC9s. Ruger's new LC9s is much better than its predecessor. The new striker fired system makes the trigger pull MUCH softer. The recoil spring/guide rod assembly is now a DOUBLE recoil spring system. Very nice.
Quality Value


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138 Lyndhurst Rd Kingston 5 JamaicaGet directions
238 Lyndhurst Rd Kingston 5 JamaicaGet directions
Agri & Industrial Packaging Limited is the manufacturer of industrial packaging items such as shopping, laminated, money bags and juice bag rolls. Operating for over 25 years
in Jamaica, Agri & Industrial Packaging Ltd is easily the most recognisable name in the business.
Agri & Industrial Packaging Limited, provides packaging solutions to Retail Stores, Supermarkets, Bakeries, Plant Nurseries, Manufacturers, Banks and Hospitals. They are equipped to produce a wide variety of plastic packaging solutions of any size, style and colour.
Converters of Polypropylene
Converters of Polyethylene
Plain & printed bags up to six colours with UPC (Bar) codes. Read more......Read less
3196 Spanish Town Rd Kingston 11 JamaicaGet directions
CROWN Packaging Jamaica Limited has been manufacturing metal cans since 1950, for a wide range of companies for the packaging of Agri-products, Food, Beverage, Paints and Chem
At Crown Packaging Jamaica Limited we provide complete packaging solutions to the Caribbean for several business industries.
Our clients include companies from the painting to food industries and we pride ourselves in providing the highest customer service and satisfaction for our products.
We have a team of highly trained employees who ensure that the containers produced are of the best standards. Our packaging solutions are created to ensure that whatever standard is needed to protect your products we can create. Read more......Read less
416 Ashenheim Rd Kingston 11 JamaicaGet directions
At JPI, we have been serving our clients for over 50 years and will continue to provide quality products in the corrugated cartons business. Our highly trained professionals o
ffer technical assistance, personalised selling, warehousing and delivery of paper packaging to a large cross section of the Jamaican business community and household. Our quality service provided over the years, has built a reputation for reliability. We are proud of our achievements and hold our clients as our most valuable assets as we look to continue to be their "supplier of choice"
Jamaica Packaging Industries Ltd is your ideal one stop packaging centre. At our retail outlet, apart from our corrugated cartons, you will find a vast selection of products such as: stretch wraps, mesh bags and packaging dispensers. We also carry bubble wraps, grease proof paper, paper bags, paper rolls, pre-packaged cutlery sets and other packaging accessories. Read more......Read less


text: As much as we plan, and discuss, and kibitz, and even book the trip, it doesn't really hit us that we will be in WDW till we hit 180 days out and can start making ADRs! 180 to go today, booked Le Cellier for first night, Tony's for our MVMCP night, and Crystal Palace at 8:05 breakfast on our last full day. Several more likely to come on less important nights. I now finally completely feel like we will be there! Woohoo!


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Problem: As a manager with multiple direct reports, I find that I often avoid difficult conversations with my employees. Although I don't know for certain, I believe I avoid difficult conversations because I fear that my relationships with others are or will become strained. I also tend to avoid difficult conversations when the stakes are high and I'm less confident in my conversational skills.
Having difficult conversations to improve employee and work group performance is a necessity in today's competitive business environment. However, if the employee or work group is defiant or non-responsive many leaders choose to delay or avoid the difficult conversation. How common is this avoidance? A 2012 study from the Learning Consultancy Partnership showed that 60 percent of leaders "often or sometimes put off difficult conversations." Leaders have a lot of reasons for avoiding difficult conversations. Some of the reasons leaders avoid difficult conversations include:
As much as leaders may want to avoid difficult conversations, it is best to develop the resolve and conviction to engage in them. Over my many years of practice and research I have learned that avoidance usually leads to poor outcomes. When I was a supply chain manager for the military, it became clear that planning for my difficult conversations greatly improved my chances for successful outcomes. My current research continues to demonstrate that mapping your conversation in advance will help you get to where you need to go. Below are some practical tools that any leader can use to map their personal route to success in their difficult conversations.
Here are three ways you can get on the road to success with difficult conversations.
Scott Van Ness is an instructor of operations management in the UCCS College of Business. He is a U.S. Air Force retired lieutenant colonel with more than 21 years of service in the area of operations and supply chain management. Scott is also an executive education facilitator through the college's OPED office. He is also a small business owner of National Loan Clearinghouse in Colorado Springs. He can be reached at firstname.lastname@example.com.


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Many of us are still stunned from the news that Donald Trump was actually elected to be the president of the United States. The shocking news has left many people scared and concerned for the future of America, due to some of the vicious statements he has made in the past — but did one TV series try to warn us?
The BBC series Black Mirror, which is now a Netflix original, has seemingly been predicting the future lately, with its most notable event being the prediction of a political figure committing an embarrassing act of bestiality.
An equally prophetic episode no one seems to be talking about is "The Waldo Moment," which clearly spelled out the 2016 presidential election results — and we didn't even see it coming.
The Lunacy of 'The Waldo Moment'
The episode begins with a failed comedian who starts flirting with politics — as an animated character — in order to get his name in front of the public again. Soon, Waldo's outrageous moments in front of the camera catch the TV executives' eyes and they encourage the cartoon Waldo to run for president. Although he appeals to the UK people's need for change, he says things that are hateful and come from a place of anger with no thought. The comedian behind Waldo also lets his personal life blend in with his new political persona, and things get even worse from there.
Even when the comedian wants to pull the plug on his character's run for office, Waldo wins political office without him. The credits end with a dystopian-looking future and cops beating down the comedian in the street for simply not moving fast enough.
'The Waldo Moment' Mirrors The 2016 Election Flawlessly
The similarities between "The Waldo Moment" and the 2016 election are endless. Like in the episode, Waldo appeals to people's passion for change. He does so in a manner, however, that includes shouting, foul language and slinging hateful words at the other candidates. What is unnerving is that Waldo's words are actually nicer than a lot of the hateful words Trump said about Muslims and Hispanics. While Waldo only used his outrageous behavior towards other political candidates, Trump encouraged acts of violence against fellow Americans.
Just like in this episode, it was pretty shocking during the 2016 election when such an outrageous person was elected to such an important place in office.
The comedian behind Waldo also uses people who have personally slighted him to fuel his political campaign with devastating consequences. Donald Trump has said on numerous occasions that he will get revenge against people who have spoken out against him.
What Does 'The Waldo Moment' Say About Us Now?
At the end of the episode, society is in deep trouble. The streets are filled with the homeless and martial law is clearly in place. Advertisements are everywhere pushing consumerism on those who can still afford to take part in it.
Is that the future we'll actually see? The next four years will have to play out for us to know. Whereas life under President Hillary Clinton would've been relatively predictable, no pundit or politician has any idea what our country is going to look like now. Millions of people feel like their futures are pretty bleak, but the future does not have to be dark, because we have the power to change it at any time.
Nevertheless, Black Mirror is king of predicting the worst-case scenario. "The Waldo Moment" was my (and many others') least favorite episode of the series; it seemed silly at the time, but now, it's just plain scary.


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Technology Development and Field Trials of EGS Drilling Systems Geothermal Lab Call Project
From Open Energy Information
Last modified on July 22, 2011.
|Project Title
|Technology Development and Field Trials of EGS Drilling Systems
|Project Type / Topic 1
|Laboratory Call for Submission of Applications for Research, Development and Analysis of Geothermal Technologies
|Project Type / Topic 2
|Drilling Systems
|Project Description
|A recent EGS well construction technology evaluation has shown that drilling services and consumables can exceed 50% of total wellbore construction costs. Conventional geothermal drilling is hampered by the challenges of hard rock, fractured formations, high temperatures, and the frequent loss of circulated drilling fluids to the formation. In the past, this drilling difficulty has been a point of distinction between geothermal and oil and gas applications. Recently this distinction is less pronounced as the oil and gas industry encounters more difficult drilling conditions. This blurred distinction can benefit the geothermal industry as technology developed for oil and gas, backed by significant research and testing, can be adapted for use in geothermal drilling. This project proposes to introduce two mature oil and gas drilling technologies for use in geothermal well construction: Percussion Hammers and PDC Bits. Pneumatic down the hole hammers (DTHH) are routinely used in the mining industry and the oil and gas industries for penetrating hard formations. PDC bits are another rock drilling technology that has not been adopted for geothermal drilling, largely due to past reliability issues and higher purchase costs. These technologies will be specifically tailored for use in geothermal drilling and demonstrated on a production geothermal drilling project.
|New Mexico
|Develop EGS drilling system based upon existing rock penetration technologies, Percussion Hammers and polycrystalline diamond cutting (PDC) bits.
|Awardees (Company / Institution)
| Sandia National Laboratories
|Funding Opportunity Announcement
|DOE Funding Level (total award amount)
|Total Project Cost
| $981,000.00
|Principal Investigator(s)
| David W. Raymond
|Targets / Milestones
| - Laboratory evaluation of design and improvements of geothermal drilling systems.
|Location of Project
| Albuquerque, NM
|Funding Source
|American Recovery and Reinvestment Act of 2009
|EERE Geothermal Technologies Programs[1]


text: The one thing I really don't want to give up is the AutoText feature on my BlackBerry. I've created many phrases using my very own short hand. This makes typing info I use on a regular basis quick and easy. While searching I came across an app called FireKeys. It claims it allows you to add AutoText the same way you can on a BlackBerry. This is the site describing the app: http://www.firekeys.com Does anyone know if this will work? Are there any other apps besides this one that can be used for AutoText? If this app works, then I'll definitely hop aboard the Android Train!


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The House offers accommodation in 2 apartments recently renovated and comfortable.
+Share your photos!
The House offers accommodation in 2 apartments recently renovated and comfortable.
Apartment (4 + 2 persons), 90 m2, located on the ground floor, composed of a fully equipped kitchen, dining room, living room, two bedrooms with double bed, bathroom with shower and a bathroom with bath, terrace with sea view. In the living room there is a sofa that can serve as an extra bed for a maximum of two people. Apartment-Flat Rental in Opatija #9213 >
One small place with good place for beautiful nature in Plitvicka Jezera nacional park, Croatia
Two apartment one with 3 bed smool kichen and bathroom, second with two room on first floor and down with living room with kitchen and bathroom. One room with 3 bed and bathroom. In garden is swimming pool and place for playng. Apartment-Flat Rental in Plitvička Jezera #69592 >


text: The mechanical features of human movement are of great interest in a range of endeavors, from engineers designing car seats or keyboards to physicians treating sports injuries. Human movement obeys basic laws that govern static and dynamic bodies, and this textbook takes a quantitative approach to studying human biomechanics. The book features numerous homework problems and worked examples, both of which are vital for classroom use. The book will be welcomed by teachers of engineering mechanics, statics and dynamics, and biomechanics courses that assume familiarity with calculus and vectors.


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Know more about this business than we do? Cool! Please submit any corrections or missing details you may have.Help us make it right
Be the first MLive.com user to add photos or videos of White Apartments
The management of these apartments are crooks. They have been video taped in tenants apartments taking medication while they were not home. Paperwork is always screwed up, your rent is not what they promise it will be. They tape your personal information on your door so they do not have to make or keep appointments with their tenants. Other people can see your social security number, bank...
Call today to find out how to make White Apartments your home! Please call for an appointment today!
White Apartments is located at 320 W Kalamazoo St, Bloomingdale, MI. This business specializes in Apartments and Property Management and has 1 review(s) with a star rating of 1.0.


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The Last Lie! Obama's final lying speech revealed by Tomi Lahren
It's over, nearly. The farewell speech is finished. Snowflakes cried, Obama spoke for an hour, and we celebrated with a beer! But what of his speech? Well, it was pretty much one big lie!
To save you the painful details – it's best summed up by American patriot and Trump supporter, Tomi Lahren!


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Organic Lush Wedding Inspiration with Elegant Details
Wedding Design
Photos by:Maria Lamb
Here at Ruffled, we know no better way to get through the end of the week than with some serious pretty. Thanks to Maria Lamb and Sinclair & Moore, we've got heaps of it to share with you all! At the Sinclair & Moore workshop, the team paired ornate details and romantic accents to create Old World charm sure to inspire all lovers of natural beauty. We can't get enough of that gorgeous blue!


text: come on experienced ones sound off!! In general when you give a bid or even on properties you already have I am curious what you shoot for your profit range. 10%? 20%? 30%? meaning after your costs are paid on a property what is the profit range you are looking to try and get and still be competitive? hopefully this question makes sense.


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I know I already called you, but I just can't believe the response!
One week after a mass mailing, I was cast in "Peter Pan" with Cathy Rigby. The phone has not stopped ringing!
Obviously, I have a resume to back up my photo, but clearly there is no denying that your photos have given me those crucial extra seconds of a casting director's or agent's time.
Thank you so much!
Your fan!
John F. Stevens


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In this article, students will learn about four basic and most important career related questions which every career guidance professional asks during career counselling sessions. Try giving answers to these four important questions as it will help you in selecting the correct career path.
Students who study humanities at school are often confused about career options in this stream. Generally, they have an idea that no good career options are available through Humanities. Therefore, we bring here a list of career options for Humanities students.
Students who are about to completer their schooling can know all about career in actuarial science after class 12. This article explains the exact nature of the job of actuary and the courses that are being offered to qualify as an actuary.
In this article you will get to know about the most important things about career coaching or a career coach. Here you will get to know that how a career coach can help you get a clear career path and tackle various other career related problems.
In this article, we will learn the meaning of career goals with an example. We will also learn about types of career goals and why it is important to have career goals in life. Here, we will also learn how to create realistic and achievable career goals in life.
In this article you will get familiar with the most exciting and unconventional career options you can pursue after CBSE Class 12. Here you will know alternate career options other than the traditional ones; Engineering, medical, law or teaching. You will get to know how your pursuit and hobbies can turn to be the best earning option for you.
In this articles students can get to know the top tips on how they can proceed to their dream career early from their high school days. They can learn the top 6 must do's which can help them to achieve the desired goals and ambitions.
What after class 12th in Science with PCB/PCM/PCMB? Science stream offers various career options including Medical and Engineering profession. Student can read here about different career options available after they complete their class 12 with science stream with their choice of subjects.
In this article we have discussed various constraints that a student and his parents should keep in mind while choosing his engineering stream. It confuse moslty all students who want to pursue Engineering that which branch to choose.
Read the given article to know the reasons of why to choose Engineering as career. To choose career is the biggest decision of everyone. So, if you are thinking about doing Engineering, go through the article to know the merits of choosing Engineering as your career.
This article talks about the top 7 jobs for high school students that can be pursued along with continuing their academic career. Get to know about the 7 easy to do jobs that can help you meet your financial requirements and also enhance your skill-set.
This article brings the most effective tips and suggestions for school students to plan the right career for future. Here, students can learn about the various interests and strengths to be worked on in order to achieve the dream career. Learn how self-analysis can be helpful to choose the right career.
Choosing career is the biggest decision of everyone's life. Many student get confused while choosing their career. Read this article to know whether engineering as career is suitable for you or not.
This article will provide great help to school going students who want to start planning their careers while studying at school itself. They will learn various aspects to support their dreams of getting their dream job.
More and more school students are looking for extensive information about the further courses they should undertake and which career, industry or company to join once they pass out from school. Here we provide few simple and effective ways to help them in making right choice.
More and more school going students, especially those studying in class 10 and upwards are looking for part-time jobs to earn their own money and also to get hands on experience to prepare themselves for their future.
Most of the students get confused at the end of their final year of engineering degree. In this article we will talk about 5 things that you can do after the completion of your graduation in engineering.
Schools are not only about getting academic and theoretical knowledge as lately school students have become more demanding and active to receive practical and market knowledge to prepare for their future.
This article will guide students who have cleared their class 12 board exams to pick up the most attractive and well-paid careers according to their aptitude and interest.
In order to help young students to make an informed career decision, Jagranjosh.com brings you some of the hottest science careers students can choose after class 12.


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It is always appreciated to know before you arrive what you can expect, what processes need to be followed, details, and changes that have occurred over the winter so that there are no surprises and that your check-ins are stress and hassle-free.
Fishing Licence and the New Outdoors Card
All anglers fishing in Ontario waters are now required to purchase at the time of licencing, both an Outdoors Card along with a Fishing Licence of their choice ** See the information below.
Non Resident 1 Yr. Sport Fishing Tag: $83.27 Cdn. or approx. $68.25 U.S. funds
Non Resident 8 Day Sport Fishing Tag: $53.54 Cdn. or approx. $43.89 U.S. funds
Possession Limit of 4 Walleye, 4 Northern Pike, 4 Smallmouth Bass & 2 Lake Trout.
** Exception to the above applies to Smallmouth Bass – prior to July 1st possession limit is 2 and both must be under 13.75 inches. Muskie – zero possession limit on Lac Seul
Non Resident 1 Yr. Conservation Tag: $51.65 Cdn. or approx. $42.34 U.S. funds
Non Resident 8 Day Conservation Tag: $30.53 Cdn. or approx. $25.02 U.S. funds
Possession Limit of 2 Walleye, 2 Northern Pike, 2 Smallmouth Bass, 1 Lake Trout.
Canadian Resident 1 Yr. Sport Fishing Tag: $55.16
Possession Limit of 4 Walleye, 4 Northern Pike, 4 Smallmouth Bass & 2 Lake Trout
Canadian Resident 1 Yr. Conservation Fishing Tag: $32.69
Possession Limit of 2 Walleye, 2 Northern Pike, 2 Smallmouth Bass & 2 Lake Trout
Temporary Canadian/Non Resident Outdoors Card: $9.68 Cdn. or approx. $7.93 U.S.
All non-residents of Ontario require an Outdoors Card and current Fishing Licence. Non-residents under the age of 18 may fish without a license if accompanied by a licensed adult family member. Any fish caught are part of the limit of the person with the licence.
For those guests that fished in Ontario over the past few years and have received an Outdoors Card (plastic card) please bring it with you on your return trip to fish with us in 2017- it will save you an additional $9.68 in licencing fees. For those guests that have been unable to join us for the past couple of years or for guests new to our camp that have not fished in Ontario we will issue you a Temporary Outdoors Card along with your fishing licence tag and you will then receive a permanent Outdoors card in the mail for future trips.
We open for the fishing season on the 3rd Saturday in May for Walleye, Northern Pike, Smallmouth Bass and Lake Trout. Angling for Muskellunge opens the 3rd Saturday in June and our fishing season for all species ends in early October. Our Fall Bear Hunt occurs the first two weeks in September, our Fall "Cast n' Blast" – Fishing/Grouse Hunting packages are available starting September 15th and our Moose Hunt is conducted the second week in October.
We are asked quite often what the fishing regulations are in our area and if guests can take fish home (this is because many outfitters do not allow you to take fish home at the end of your trip.) Our answer to that is YES! When fishing with Anderson's, you are given choices it the type of licence you purchase. The type of licence will in turn determine how many fish you can take home and the time of year that you choose to fish determines what species are available. In the Sioux Lookout District, we are fortunate to have lake management plans based on current biology which has determined that selective harvest is acceptable and still leaves the fisheries in great shape, providing great angling opportunities for years to come. Listed above are the types of licences, the limits applied and the current pricing.
Additional catch and possession regulations apply to area lakes and can be reviewed in the Ontario Sport Fishing Regulations.
General Hunting and Firearm Information
- Registration of your firearm is required. For your convenience we will mail you the required forms for declaring your firearms for your entry into Canada.There is available Pre-Arrival Processing for firearms, which can save you time in crossing the border. This pre-processing is available either at Fort Frances, Ontario or at Sault Ste. Marie, Ontario border crossings only. For this procedure please contact Canada Customs in Fort Frances at 807-274-3655, ext. 240. For regular processing and registration, we will mail you the registration form and recommend that you fill out the declaration before you arrive to save some time. However, note that the form must be signed in front of the Customs Officer at the point of entry. The fee for your Firearm Declaration is $25.00 in Canadian funds and will be payable at the time of submitting your forms. Should you have any questions about the form, please give us a call and we will be happy to assist you in filling it out.
- Customs officials will check your firearms. To assist in as little delays as possible, we recommend that you have your valid hunting license from another state or province and if you have – a license to own the firearm. There are no restrictions on the amount of ammunition brought into Canada except for bulk quantities over 5000 rounds. The use of handguns for hunting or personal protection is prohibited in Canada.
- In order for you to obtain an Ontario hunting license you must produce a valid or expired hunting license from another province or state, which you must also carry with you while hunting in Canada. To allow us to prepare your Canadian license ahead of time, please send a clear photocopy of your existing license. The license must have a serial number, the state or province it was issued in and the date of issue.
- You are required by law to wear full block hunter orange. The minimum requirement is a ball cap and a vest. Please note that Camo Orange is not legal.
For clarification or further information please refer to the Ontario Hunting Regulation Summary that will be mailed to all guests who choose to hunt with us. This summary is also available online at the Ministry of Natural Resources website.


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The MTA brass considering fare hikes for next year got an earful from a few dozen subway and bus riders who showed up at two hearings Monday to complain about paying more for stagnating service.
A 13-person panel consisting of MTA Chairman Thomas Prendergast, agency officials and board members heard from 30 riders in Baruch College, while another panel of officials heard from 15 straphangers at Hostos Community College in the Bronx.
The MTA board will vote on the fare hike proposals this month.
Sherrod Staton, a 24-year-old college student and retail worker from Ozone Park who takes the A train, bluntly called the options for the fare hike "garbage" and unfair to riders who have seen wages stay stubbornly flat.
"It's really unfair to common New Yorkers to have to constantly, constantly pay this increased fare," Staton said. "I don't see anything being done with the quality of the trains."
The hikes being considered would increase the fare 25 cents to $2.75, with a better cash bonus, or keep the fare flat at $2.50 and nix the bonus. Weekly unlimited MetroCards would go to $31 from $30 and 30-day cards would go up to $116.50 from $112.
Jo-Ann Polise, an east sider and a nonprofit office manager, said she decided to testify after limited buses drove past her stop earlier in the day.
"I'm not happy. Everybody I know is trying to do more with less," she said after her testimony.
There were a few colorful suggestions for raising money without fare hikes. Two people wanted to see tourists pay more, like a two-tiered system for visitors or a fare hike during the months in the peak tourism season. Nancy Rankin, of anti-poverty group Community Service Society, wants low-income New Yorkers to get a break on fares to boost ridership, which is already at a post-war record.
A suggestion from community organizer Ryan Carson, a 23-year-old living in Bedford Stuyvesant, got loud applause for suggesting that MTA officials take a pay cut.
"It's actually insulting to me" to shoulder the financial burden, he said.
Still, the meeting was a staid affair with few people showing up compared to the raucous hearings before the "doomsday cuts" of 2010. There were apparently no state elected officials, who have a say in MTA finances, present. There were only a few speakers who actually opined on the two fare hike options before the MTA.
Still, the MTA's chief spokesman Adam Lisberg said agency officials and board members took seriously the concerns of people who made an effort to attend. He also defended the need to raise fares and seek public opinion.
"Nobody likes to pay more for anything," he said. "We know that any fare and toll increase is difficult for some people, but our costs are increasing despite more than a billion dollars worth of cuts we've made."