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OAKLAND (KPIX 5) — In Alameda County, computer problems that are so bad some people are being wrongfully arrested.
Since august the Alameda County Court has been using the new court management software system…it was supposed to be an upgrade…but now public defenders and prosecutors agree.. It's causing chaos… And could be hampering justice.
Alameda County Public Defender Brendon Woods said, "It's more than frustrating. It's completely outrageous."
Woods said the new computer software that the county court is using is processing inaccurate records and causing legal nightmares.
"There are misdemeanor cases that are now felonies. We had a 12500 which is driving without a license show up as a felony," Woods said
Woods filed a motion with the Alameda County Court blaming the software — called Odyssey – for wrongful arrest, unwarranted jail time and wrongly listing defendants in the system as sex offenders.
And in a court hearing Tuesday, court administration and even the district attorney all agreed, the software isn't working. They call it cumbersome, requiring multiple steps, screens and clicks to complete one action, making it prone to mistakes.
Woods said, "What would take a court clerk a minute or two to update normally, takes them 20-25 minutes, so clerks who are really working hard and trying to keep up simply can't."
So for some defendants, they show up to court, have their warrants recalled, but the information doesn't show up in the system.
In the worst examples, defendants are wrongly arrested on outdated warrants.
Woods said it is making the justice system "extremely inefficient."
"I would say people's constitutional rights are being violated on a daily basis," Woods said.
The judge is giving parties a week to come up with a solution to the software. The problem now: money. The county already paid $4.5 million for Odyssey and would need to come up with new funds if they decide to replace it.
The maker of Odyssey tells the San Francisco Chronicle that it's committed to supporting Alameda County, but that the problems aren't the fault of the software and that it's working just fine in other places.


text:
Joe has yet to fill out a bio.
Charlie Arndt posted 2062 days ago
scUM, Your life must be so freakin' terrible that you have nothing to do but swarm THE Ohio State University fan page and ridicule the best B1G linebacker of the 1990's.
Joe does not have any awards.
Joe does not have any fans.
Joe does not have any favorite writers.

subset: commoncrawl


text:
I was wondering if It's possible/stable/legal to run games with streaming off? For Instance, I play BlackDesert which requires a lot of AFK playtime. So I would like to keep the game on, but turn the stream off to minimize the resource usage on my laptop. Does Windows shut off after a certain amount of time has passed without streaming?
Any input is appreciated!
Edit: Rig seems to time out after 30 minutes of inactivity even while streaming a game. Any suggestion for preventing it from automatically shutting off?
Last edited: August 28th, 20:51


text:
What a Democracy we have in this world ?
We are living in a country where we have a man earning Rs.30 lacs per hour and in the same country 30 lacs people are with out shelter, two crores people sleep hungry per day and crores of persons are jobless un-employed. A common man is struggling to earn his daily bread to fill his basic need of his & his family's stomach.
Immense corruption is prevailing and influential class persons is looting money enough for hundreds of generation( when there may not be any surety tomorrow they live or die with some kind of disease, accident, or any other way) and gap between the rich & poor is widening day by day. Humanity in rich class is getting loosed, selfishness increasing- pure KARMA-DHARMA is not seen in their heart, they go to temples to find God solving their personal problems-sufferings-donate crores of Rupees as to buy God even, but don't find God in their own hearts, as it is too dirty with full corruption, then how can Almighty God remain there, when nature of even a dog is to clean place with his tail where he wish to sit. They have killed their ATMA's Voice (which is real part of Almighty God PARAM-ATMA to guide the minds)
, they don't listen its voice in their hearts. They don't understand that Almighty God in poor's heart as ATMA (soul) where there is no corruption in their hearts, they are clean from inside, if they are not getting food even.
SARKAR KE PASS JADOO KI CHHADI NAHI HAI, BHRASTACHAR KO KHATM KARNE KE LIYE- P.M. & LOOTER MINISTERS, say always when ever they are asked to stop corruption. Congress party had ruled more than FIFTY YEARS, HOW MUCH TIME THEY LIKE TO HAVE MORE TO FINISH CORRUPTION? God only might know that. Is their intention to fill their pockets more and more to have more time saying "SARKAR KE PASS JADOO KI CHHADI NAHI HAI, BHRASTACHAR KO KHATM KARNE KE LIYE".
Why are not the reasonable restrictions/ preventive actions imposed by SUPREME COURT or LOK SABHA SPEAKER- RAJYA SABHA SPEAKER etc on MPs- MLAs to maintain law and order in the Institution Parliament (which is meant to make laws for the same purpose)when they are fighting-shouting like barking street stray dogs (when another dog from other area come in their area)- breaking chairs-furniture-snatching loudspeaker from Honorable top most post of Speaker of the law making institute Parliament or Rajya Sabha etc, wasting crores of Rupees public expanses daily, it does not look like this institution Parliament is meant for making laws for general/ common persons' betterment whose they are suppose to be representatives. It shows as if dogs are fighting for their own piece of chicken or meat of any dead body. This trend is not found in our country only at present time, but found the same trend in other parts of the World too. What are remedies for these corruptions to be abolished from whole of the World, I will tell you latter some times.
Who has given them full liberty to be indiscipline, rowdy and gundas in the Institutions of making laws?
What are actions taken against this type of person? If some action is taken against them were only suspensions for seven days from Parliament or Rajya Sabha which they enjoy at home with drinking-eating chickens and …………………………- .many more un-social activities as they have got leave from their duties.


text:
stop off
Also found in: Dictionary, Thesaurus, Medical, Legal, Financial, Encyclopedia.
Related to stop off: stop over
stop off (some place) (for a period of time)
to halt or pause for a certain period of time. I need to stop off for a rest. Let's find a little town and stop off. I have to stop off at the store for a minute. We stopped off for a while at the park.
stop off
Also, stop over. Interrupt a journey for a short stay somewhere, as in When we drove through Massachusetts we stopped off for a few days at Cape Cod, or When you're in the area try to stop over and see our new house. [Mid-1800s]
stop off
To interrupt one's course or journey briefly in order to visit or do business somewhere: I stopped off at the gas station on my way home. We stopped off in San Francisco for a night before continuing on to Honolulu.


text:
Good morning Dinks. Here we are again. In the office with kids I don't know. Yesterday I was coming out of the ladies bathroom at my office and there was a little boy standing there. My reaction? I immediately froze. I didn't know who the little boy belonged to or why he was in my office, yet there he was – standing face to face with me, looking me right in the eyes.
Pro or No: Kids in the office
I'm sure this is no surprise to you but I don't spend much time around kids. Actually I don't spend any time around kids. I don't know anyone with kids and the truth is kids make me very uncomfortable. They are so small and fragile and they are just all around awkward.
When I first saw the little boy standing in the hallway my first reaction was, WOW this is not the place for kids. How do you feel about kids in the office? I am not sure why people bring their kids to the office, maybe it's because they feel they need to show off their creations. Or maybe they just want to get out of the house and can't leave their kids at home. Either way, it makes me uncomfortable. I just politely smile, tell my co-worker how cute their kids are and I move on back to my desk.
The money obligation of kids in the office
Do people in your workplace solicit donations and sell goods for their kid's school fundraisers? They do in my office. I don't mind contributing every now and then but why should I have to pay for other people's kids? I love a good box of cookies and chocolate bars just as much as the next person but I don't like feeling obligated to donate money.
I also don't want to be the only person in the office not contributing, so whenever my co-workers ask I give money to their kids. I don't want to be known as the cheap girl in the office but that doesn't change the fact that I'd much rather spend my money on myself. I want to spend my money how I want to, not because I'm forced to.
What do you say to the kid question?
As a woman in my 30s with a long term boyfriend people always ask me when are we going to have kids. They don't ask if we want to have kids, they just assume we are going to start a family and for some reason they want to know when I am going to get pregnant. Besides the fact that it's really no one's business, I find the question highly inappropriate for the workplace.
I used to tell people that I didn't want kids, but I got sick and tired of people staring at me like I was crazy. So now whenever someone asks me when my boyfriend and I are planning to have kids, my standard answer is "Soon".
Photo from flickr
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text:
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text:
Paper Chase is a research database designed to offer abstracts of research articles published in journals that have a highly rated impact factor as determined by ISI Impact Factor and PageRank. Abstracts are organized by date, with the most recently published papers listed first.
Paper Chase
HCF-1 is cleaved in the active site of O-GlcNAc transferase.
Department of Microbiology and Immunobiology, Harvard Medical School, Boston, MA 02115, USA.
Host cell factor-1 (HCF-1), a transcriptional co-regulator of human cell-cycle progression, undergoes proteolytic maturation in which any of six repeated sequences is cleaved by the nutrient-responsive glycosyltransferase, O-linked N-acetylglucosamine (O-GlcNAc) transferase (OGT). We report that the tetratricopeptide-repeat domain of O-GlcNAc transferase binds the carboxyl-terminal portion of an HCF-1 proteolytic repeat such that the cleavage region lies in the glycosyltransferase active site above uridine diphosphate-GlcNAc. The conformation is similar to that of a glycosylation-competent peptide substrate. Cleavage occurs between cysteine and glutamate residues and results in a pyroglutamate product. Conversion of the cleavage site glutamate into serine converts an HCF-1 proteolytic repeat into a glycosylation substrate. Thus, protein glycosylation and HCF-1 cleavage occur in the same active site.
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text:
Deirdre G
My Profile
I enjoy swimming, sailing and playing the piano. I support the Manna Society and MS Society and Cancer Research charities.
Friend Request
has been sent a request to be your friend.
Total money raised so far: £0.00
My Friends
Become the first Charity Choice friend of Deirdre.


text:
de·clare (dĭ-klâr)
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v. de·clared, de·clar·ing, de·clares
1. To make known formally or officially; proclaim: declare that a fugitive has been captured; declare a mistrial. See Synonyms at announce.
2. To state emphatically or authoritatively; affirm: "He wrote another prayer declaring that his conscience was weighed down with guilt" (Leo Damrosch).
3. To reveal or make manifest; show: His smile declared his agreement.
4. To make a full statement of (dutiable goods, for example).
5. Games
a. To designate (a trump suit or no-trump) with the final bid of a hand in bridge.
b. To reveal (a combination of cards) to be added to one's score.
1. To make a declaration.
2. To announce one's intention to run for public office: "My gratitude would keep me loyal to McCarthy even after Bobby Kennedy declared for president" (James Carroll).
3. To proclaim one's support, opposition, choice, or opinion: "The party ... has changed, openly declaring for centralized federal power" (Ronald Reagan).
declare war
1. To state formally the intention to carry on armed hostilities against.
2. To state one's intent to suppress or eradicate: declared war on drug dealing in the neighborhood.
[Middle English declaren, from Old French declarer, from Latin dēclārāre : dē-, intensive pref.; see DE- + clārāre, to make clear (from clārus, clear; see kelə-2 in the Appendix of Indo-European roots).]
de·clara·ble adj.
de·clarer n.
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text:
Bengals vs. Falcons Free Pick
ATLANTA, GA (ATS Consultants) – Two playoff teams from a year ago will square off at the Georgia Dome tonight when the Falcons host the Bengals at 8:00PM ET in Week 1 of the 2013 NFL preseason.
NFL Odds: According to oddsmakers from online sports book Bovada.lv, the Falcons are currently 2.5-point favorites over the visiting Bengals, while the over/under total is sitting at 36.5.
NFL Line Movement: Atlanta opened as a 4-point betting odds favorite and moved to 2.5 or 3 in most books. The total opened at 36.5 and remained there in most books.
NFL Public Betting: Of the wagers currently placed on tonight's game, 52% of the betting public favors the Falcons -2.5. These numbers are subject to change leading up to the opening kickoff, however, so make sure to click on the link above to get the most up-to-date information.
NFL Preseason Free Pick: Take the under. Expect both coaches to rely on their backups in this game. Atlanta is looking to make a run to the Super Bow so there's no reason to play Julio Jones or Tony Gonzalez. Steven Jackson could get a brief look tonight but they know what the veteran can do. When both teams take the field on Thursday night, the defenses should shine because Pro Bowl wide receiver A.J. Green and speedy slot receiver Andrew Hakwins (ankle) are also out..
The Bengals have an underrated defense that ranked sixth in the NFL in yards allowed with 319.7 per game. In the last eight games of the season, they allowed just 12.8 points and totaled 31 sacks. The addition of veteran linebacker James Harrison can only help their cause.
These are playoff teams that want to look at their backups and have very little competition amongst the starters. Expect a lot of Dominique Davis for Atlanta against John Skelton for the Bengals. In other words, expect a low-scoring game.
ATSSportsline.com has been providing winning sports picks since 1992. Want more from ATS Consultants? Click Free Picks to get daily winners delivered directly to your inbox with no obligation!


text:
Every year we make our annual trip to Ashland Oregon. Having done this for 15 years now, we have our favorites in Ashland, but decided to venture out for a change having just finished a Saturday matinee. Googling wasn't turning up much.
Found references to a fairly new restaurant- Elements, a tapas bar, in the old Samovar location. Tapas, in Southern Oregon? But we were "wow"ed!
Started with chilean sea bass with a pepper, paprika and infused olive oil sauce. Couldn't believe how good it was. Not the least bit over done and the skin just slightly crispy. Then had duck slices with a cherry cinnamon sauce, spiked with whole fresh cherries. Another amazing dish. The table next to us ordered a 2nd dish of duck. Had the patatas bravas, spicier than I have had in San Francisco but good. The medley of 3 lamb meatballs at the next table would have been our next dish, but we wanted dessert. Finished with a fresh strawberry granita and husband had a flourless chocolate cake with housemade vanilla bean ice cream.
Amazing food in the middle of a somewhat moribund downtown.
If you are in Ashland, definitely worth the 20 minute drive for food as good as in any major city on the coast.
101 East Main Street, Medford, OR


text:
Daily briefs of the top news stories impacting Christians around the world.
In today's edition:
- Humanitarian Needs Increase in Gaza
- Bangladeshi Muslims Force Christian Grandparents from Home
- Most Protestant Churchgoers Open to Other Denominations
- Egyptian Judge Ejects Lawyer for Christian from Court
Humanitarian Needs Increase in Gaza
Mission News Network reports that Christian Reformed World Relief Committee (CRWRC) has partnered with another Christian group in Gaza to directly help its people. "Gaza is very heavily populated, and residents cannot flee because all of the borders are closed. There seems to be an agreement of 900 dead and more than 2,000 wounded," said Jacob Kramer with CRWRC. "The hospitals are in great need of medicine, and that's where the CRWRC will try to make a small difference. We've started to help the hospitals and clinics there with supplies." According to Kramer, a number of Christians still live in the region, but have often been forced to close their churches and schools. Kramer asked that Christians pray for "the hearts of terrorists" at work in the region, as well as for those suffering.
Bangladeshi Muslims Force Christian Grandparents from Home
Compass Direct News reports that Muslims in a village in western Bangladesh have forced two brothers to expel their parents from their home for converting to Christianity. Ishmael Sheikh, 70, and his wife Rahima Khatun, 55, were baptized on Nov. 9. By the end of the month, Sheikh told Compass, Muslim neighbors in Kathuly village, near Gangni town in Meherpur district, had compelled their two sons to expel them from their house. The Muslims threatened that the children of Sheikh's sons would not be allowed to marry anyone from the village if the brothers allowed their parents to remain in their home. "We are the first converted Christians in this village," Sheikh said. "Neighbors told my sons, 'Why should your parents live in this village? They do not have a right to live here because they are no longer Muslims.'"
Most Protestant Churchgoers Open to Other Denominations
ASSIST News Service reports that a new survey shows that seven out of 10 regular churchgoers would be at least somewhat open to switching denominations, with Protestants being much more open to the idea than Roman Catholics. According to a news release from Ellison Research, respondents who attend worship services once a month identified the specific denomination (e.g. not just "Baptist," but "Southern Baptist") they attended most often, and were then asked what role that denomination would play if they could no longer attend their current church. Three out of 10 churchgoers said they would only consider attending one denomination and would not be open to anything else. Another 44 percent have one preferred denomination, but said they would also consider others. Nine percent said denomination was not a factor in their church attendance.
Egyptian Judge Ejects Lawyer for Christian from Court
Compass Direct News reports that an attempt by an Egyptian convert from Islam to legally change the religion listed on his identification card to "Christian" hit a setback on Jan. 6 when a judge ordered security personnel to remove his lawyer from court. Attorney Nabil Ghobreyal was expelled from the courtroom at Cairo's Administrative Court following a heated argument with Judge Mohammad Ahmad Atyia. The dispute arose after Atyia refused to acknowledge the existence of legal documents detailing the successful attempt of a Muslim man to convert to the Baha'i faith. Ghobreyal had planned to submit the court records of the decision in support of his case. The convert, Maher Ahmad El-Mo'otahssem Bellah El-Gohary, is only the second Egyptian Christian convert raised as a Muslim to request such a change.


text:
Cocktail Making Outfit of the Night
I left my hair down with a ton of Batiste XXL to give it that Cheryl Cole boost. I kept my make up fairly simple to counteract the bright top - think nudes, lashings of mascara and eyeliner with bronzed cheeks and glossy nude lips.
I wish I'd had my camera with me for the actual night, but I didn't want to whack my bridge camera out in the middle of everything! I would have loved the chance to photograph the Mudslides and Russian Brides, but I'm pretty sure I'm returning for the boyfriends birthday very soon, so watch this space!
What's your favourite cocktail? (for you over 18's and 21's ;) Mine is most definitely the Mudslide, an alcoholic chocolate milkshake - what's not to love!
Suz x
*For links to the top and skirt please see my haul, as the prices and links are featured there! (Link Here)
12 comments
I love this outfit especially the skirt and the wedges!:DReplyDelete
Strawberry Daiquiri all the way! xxReplyDelete
Love the outfit:-)ReplyDelete
I adore wedges!
love your outfit!xxxReplyDelete
This looks so pretty - the wedges are so beaut <3333ReplyDelete
Love the wedges :) xxReplyDelete
Mudslides are amazing. Little bit of cherry liquor in them tastes so good.ReplyDelete
Love that skirt and the colour of the top together with it.
This looks lovely :) I love those shoes, and I am totally a dress for all the different elements kinda girl!ReplyDelete
I'm a typical Cosmo girl, partial to Sex on the beach (Obvs the drink! So much fun to order :/)
Laura xoxo
Lovely outfit, I agree with Laura-xo- I'm a Cosmo girl too ;-)ReplyDelete
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text:
About Rhea Tregebov
Rhea Tregebov is a published author of children's books. Some of the published credits of Rhea Tregebov include The Secret Wish of Nannerl Mozart, What-If Sara, Sasha and the Wind.To edit or update the above biography on Rhea Tregebov, please Log In or Register.
Link to this page: https://www.jacketflap.com/rhea-tregebov/130106
Published Works by Rhea TregebovClick a book's title or cover for more details and to read reviews


text:
PG&E Tumble May Hurt MBIA, ACE, But Ratings Appear Secure
Related Articles
- Calif. County Tax Bills Go Unpaid As Utility Sinks Into Bankruptcy. Maurice, Alex // Bond Buyer;04/12/2001, Vol. 336 Issue 31117, p1
Reports that Pacific Gas & Electric Co. has paid only about half of the property taxes its was scheduled to pay to 49 California counties. Bankruptcy filing of the company; Wait-and-see attitude of bond fund managers.
- Calif. Utility's Bankruptcy Sparks Bank Credit Fears. Rieker, Matthias; Mandaro, Laura // American Banker;4/10/2001, Vol. 166 Issue 69, p20
Focuses on the views of several bank spokesmen on the Pacific Gas and Electric Co.'s bankruptcy filing on April 6, 2001. Efforts to downplay market concerns over banks' exposure to the bankruptcy; Total value of claims of the Bank of New York Corp. against the utility; Speculations of analysts...
- PG&E Tells Creditors It Needs 6 Months. // American Banker;2/2/2001, Vol. 166 Issue 23, p2
Reveals that PG&E and its utility subsidiary, Pacific Gas & Electric Co., have told debt holders they may need more than six months to raise new money to repay commercial paper that they defaulted on in January 2001. Length of time it may take to work out a structure that will let the companies...
- PG&E Files Chapter 11. // Transmission & Distribution World;Apr2001, Vol. 53 Issue 4, p12
Reports on the decision of Pacific Gas and Electric Co. to file for reorganization under Chapter 11 of the United States Bankruptcy Code. Objective of the company in relation with the bankruptcy filing.
- UTILITY BANKRUPTCY COMPLICATES CALIFORNIA'S ENERGY CRISIS. // ENR: Engineering News-Record;04/16/2001, Vol. 246 Issue 15, p20
Reports on the electric utility, Pacific Gas and Electric Co.'s (PG&E) filing for bankruptcy protection. Implications of the bankruptcy filing on relationship between the state of California and PG&E; Overview on the financial problem of the PG&E; California Governor Gray Davis' criticism on...
- Calif. Utility Bankrupt Owing Banks $9B. Leibowitz, Alissa; Mandaro, Laura // American Banker;4/9/2001, Vol. 166 Issue 68, p27
Reports on the announcement of California electric utility Pacific Gas and Electric Co. that it has filed for bankruptcy. Total outstanding bank debt of the utility; Impact of the announcement on the stocks of regional and money-center banks known to have exposure to the utility.
- PG&E bankruptcy is warning to other investors. Leckey, Andrew // Journal of Business (10756124);05/03/2001, Vol. 16 Issue 10, pA23
Reports the impact of bankruptcy of Pacific Gas & Electric on investors in California. Companies filing for bankruptcy; Sale of transmission lines by Southern California Edison to avoid bankruptcy filing; Performance of post-bankruptcy stocks.
- State Asks Feds to Nix Power Utility's Exemption From Federal Act. Jones, Rene'e Beasley // San Diego Business Journal;11/25/2002, Vol. 23 Issue 47, p15
Reports that the California Attorney General's Office has asked federal regulators to deny Pacific Gas & Electric Corp.'s exemption from regulation under the federal Public Utility Holding Company Act. PGE&E's renewal of its exemption as part of its request of the approval of its bankruptcy...
- Two visions for land stewardship. LITTLE, JANE BRAXTON // High Country News;9/5/2011, Vol. 43 Issue 15, p5
The article reports on the rightful ownership of Humbug Valley in California. It notes that the valley has been designated to another owner after Pacific Gas and Electric Co. has filed bankruptcy. It says that California Department of Fish and Game and Maidu Indians are fighting for the...


text:
Consultation outcome
Disabled students in higher education: funding proposals
- From:
- Department for Business, Innovation & Skills
- Part of:
- Higher education participation and Access to higher education
- Published:
- 1 July 2015
- Last updated:
- 2 December 2015, see all updates
Download the full outcome
Consultation on targeting funding for disabled students in higher education from 2016 to 2017 onwards - government response
Ref: BIS/15/657 PDF, 243KB, 46 pages
Consultation on targeting funding for disabled students in higher education from 2016 to 2017 onwards - equality analysis
Ref: BIS/15/658 PDF, 824KB, 79 pages
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Detail of outcome
The changes that will take effect from academic year 2016 to 2017 are:
- higher education (HE) providers will be expected to take primary responsibility for most non-medical help in bands 1 and 2, and DSAs will keep primary responsibility for funding sighted guides
- DSAs will keep primary responsibility for non-medical help under bands 3 and 4, with the exception of specialist transcription services, which will be the primary responsibility of the HE provider
- DSAs funding will not be available for specialist accommodation provided by HE providers or their agents, other than by exception (additional costs should no longer be passed to the student)
- printers, scanners and digital voice recorders will no longer be provided as standard
- standard computer peripherals and other accessories will be funded by exception only
- laptop carry cases will continue to be provided as standard
Detail of feedback received
201 responses were received from a wide range of organisations including:
- disabled students
- assessment centres
- DSAs service providers
- publicly funded institutions and alternative providers
- disability charities and organisations
- higher education providers and representative bodies
Original consultation
Seeks information to help us direct the funding for disabled students in higher education more effectively.
This consultation ran from
Consultation description
We want information and evidence to help us direct funding for disabled students in higher education (HE) more effectively. We want to balance the support available for all disabled students from HE providers, and that available from Disabled Students' Allowances (DSAs).
The consultation is relevant to:
- HE providers
- disabled HE students (current and prospective)
- stakeholders working with disabled students in HE or wishing to enter HE
- disability charities
- advocacy organisations working with disabled people
- DSAs assessment centres
- non-medical help suppliers
The questions only relate to HE students entitled to receive support from Student Finance England.
Consultation on targeting funding for disabled students in Higher Education from 2016/17 onwards
Ref: BIS/15/81 PDF, 733KB, 49 pages
Document information
Published: 1 July 2015
Updated: 2 December 2015
- Added government response and equality analysis.
- First published.


text:
The Basics of Investing: Beyond the Piggy Bank
Over the years, we've had many requests for a "Basics of Investing" training course. We listened, and we're happy to announce a new series of five sessions just for you.
"The Basics of Investing: Beyond the Piggy Bank" is a five-part webinar series for novice and experienced investors who want to better understand the investment process, learn how to put their income to work, and grow their wealth for the long-term. Whether you are an ingénue or want to brush up on your investing skills, we've got you covered.
The sessions start April 19th and will run through May 24th. (No meeting on May 17th.) The course is online and each session will be recorded. So if you can't make one session, or if you want to review anything, you'll be able to download and listen at your convenience.
Registration for all five sessions is just $99.00. Sign up now to hold your place. If you are a current Urban Wealth Management client, ask us for your promotional discount code!
|April 19th
|Session 1
|Getting started
|April 26th
|Session 2
|"Fixed What?" Fixed income Investments
|May 3rd
|Session 3
|Equities: Taking Stock
|May 10th
|Session 4
|Building a Portfolio: The Next Step
|May 17th
|[No session]
|May 24th
|Session 5
|Stay Current. Stay Informed.
At Urban Wealth Management, our mission is to create a supportive and secure environment where women are encouraged to be engaged in their financial affairs and take ownership in creating the life they desire and deserve. Our vision is that every woman should live a life of her design, using her wealth to fulfill her dreams, enjoy her passions, and expand her interests. If you're ready to begin the journey, download our 50 Things About Lifestyle and Personal Finance e-book and/or connect with us for a complimentary one-hour assessment session.


text:
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text:
Coyle confident over Cahill appeal
Bolton manager Owen Coyle is confident the Football Association will overturn the red card shown to Gary Cahill on Saturday and has hinted that he is unhappy with the performance of referees' chief Mike Riley.
Cahill was given a straight red following a late tackle from behind on Scott Parker in the early stages of Bolton's 3-0 defeat at Tottenham. Referee Stuart Attwell decided that Cahill denied Parker a clear goal-scoring opportunity despite the fact that the defender hauled down the 31-year-old 40 yards from goal when Bolton had plenty of cover.
Coyle said: "I will be appealing the decision as soon as I can. It was baffling, bemusing."
The Bolton boss has seen five of his players sent off so far this season and thinks a number of decisions have gone against him since he took over at the Reebok Stadium in January 2010.
The 45-year-old continued by suggesting that Riley, the man who monitors refereeing standards for the Professional Game Match Officials Board, has not taken his remonstrations seriously.
Coyle said: "I spoke to him after we lost to an offside goal in the 94th minute at Liverpool. He said he'd ring me back.
"I rang him after we played at White Hart Lane, Spurs got two penalties and we had the biggest shout when Cahill was brought down, but was booked for diving. I rang him three or four days later after he was supposed to ring me back, so you can draw your own conclusions on that. Mike's obviously in charge of those refs."
When asked if he felt his side were not getting the rub of the green with refereeing decisions because they are not one of the division's top clubs, the Scot replied: "There's a lot of merit in the question."


text:
Avril Lavigne enjoyed some quality time with her girlfriends over the weekend.
The punk rock singer joined a few besties in Las Vegas to watch Britney Spears' residency show "Piece of Me" at the Planet Hollywood hotel.
Looking stunning in a black and white beaded mini dress and wearing her golden locks long and straight, Avril smiled from ear to ear while posing for a picture with the Princess of Pop.
"Thank you @britneyspears for having me at your show last night," she captioned the photo. "You looked stunning! We had a spectacular time. #GirlsTrip."
She also shared another photo, posing with her four friends who all looked so happy to be in attendance at the show.
"Besties birthday weekend. #GirlsTrip @britneyspears," she wrote beside the girly photo.
Meanwhile, the trip was definitely a happy getaway for Avril, who's been involved in a tough battle against Lyme Disease for over a year.
In fact, one of the last times she visited Vegas (for her 30th birthday), she ended up sick in her hotel room, which eventually led to her diagnosis. Following that, she was bedridden for five months.
"There were definitely times I couldn't shower for a full week because I could barely stand. It felt like having all your life sucked out of you," the singer said during an interview with People magazine in April 2015. "I felt like I couldn't breathe, I couldn't talk and I couldn't move. I thought I was dying."
She decided to go public about her battle after several months after fans began questioning her absence from the spotlight.
"The get-well messages and videos they sent touched me so deeply," she recalled after coming out about the illness. "I lay in bed watching them and cried so much because I felt loved."
Today, Avril has a new outlook on life. "This was a wake-up call. I really just want to enjoy life from here on out."
After continuing to battle hard, it looks like that's exactly what she's doing!


text:
A website devoted to Minnesota legal rights governing
shareholders in closely held corporations
In order to protect minority shareholders in closely held corporations, the Minnesota legislature has provided the courts with broad equitable authority to protect the interests of minority shareholders. See Minn. Stat. § 302A.751 ("Section 751"). Section 751 provides for the buy-out of a minority shareholder's interest when "the directors or those in control of the corporation have acted in a manner unfairly prejudicial toward one or more shareholders in their capacities as shareholders or directors . . . or as officers or employees of a closely held corporation."
If the parties have not entered into clear contractual agreements governing the right of the corporation to terminate the shareholder's employment, or governing redemption of the minority shareholder's shares of stock upon events such as resignation or termination of employment, the shareholders may be forced to sue each other to sort out the confusion in the event of a corporate breakup.
In cases of minority shareholder oppression, a Minnesota shareholder that has been treated in an unfairly prejudicial manner may have the right to sue the corporation and/or the majority shareholders for equitable relief including the forced buy-out of the minority shareholder's shares at "fair value" as determined by the court.
According to the courts, the phrase "unfairly prejudicial" in Section 751 is to be interpreted liberally. See Pedro v. Pedro, 463 N.W.2d 285, 288-89 (Minn. Ct. App. 1990).
One commentator, who helped draft certain revisions to the Minnesota Business Corporation Act and Section 751, stated that: "The section is remedial in nature and should be liberally construed as an addition to the rights afforded non-controlling shareholders by law and the corporation's governing documents. The broad scope of Section 751 reflects the Legislature's trust in the ability of the judiciary to achieve equitable results on the facts appearing in individual cases." See Joseph Edward Olson, Statutory Changes Improve Position of Minority Shareholders in Closely Held Corporations, The Hennepin Lawyer, Sept. - Oct. 1983, at 11.
In deciding whether to order a buy-out, the courts should consider "the reasonable expectations of the shareholders" with respect to each other and the corporation. See Minn. Stat. § 302A.751, subd. 3a. Oftentimes, a shareholder's reasonable expectations include a significant voice in management and an opportunity to work. See Olson at 23.
Examples of minority shareholder oppression may include:
The rights of minority shareholders to challenge these oppressive actions is often called "minority shareholder rights" and can be very powerful, including the right to obtain a forced court-ordered buy-out at "fair value" and recovery of attorney's fees and court costs.
If the minority shareholder can demonstrate unfairly prejudicial conduct by the corporation or the majority shareholder(s), it is even possible that the court will disregard the valuation formula contained in any written buy-sell agreement or shareholder agreement in extreme cases of minority shareholder oppression. In other words, if necessary, the court can throw out the terms of the contract negotiated between the parties and has the power to value the company at "fair value" which is generally determined after the parties submit expert appraisals.
© 2009-2013 Trepanier MacGillis Battina P.A.
Minnesota shareholder rights attorney Craig W. Trepanier of Trepanier MacGillis Battina P.A. in Minneapolis, Minnesota represents individuals, corporations, minority shareholders, and majority shareholders in closely held corporations, limited liability companies (LLCs), and other legal entities throughout the Twin Cities and Greater Minnesota area regarding Minnesota shareholder disputes, Minnesota shareholder oppression, Minnesota minority shareholder rights, Minnesota shareholder squeeze-out, Minnesota shareholder freeze-out, Minnesota shareholder termination, Minnesota corporate deadlock, Minnesota corporate impasse, Minnesota corporate dissolution, Minnesota shareholder buy-out motions, forced buyouts, and buyouts for fair value or fair market value, Minnesota business disputes, Minnesota business partnership disputes, Minn. Stat. 302A.751, Minn. Stat. 322B.833, breach of fiduciary duty, unfairly prejudicial conduct, shareholder fraud, fraudulent inducement, fraudulent misrepresentation, quantum meruit, unjust enrichment, equitable accounting, constructive trust, unpaid profit distributions, corporate self-dealing, usurpation of corporation opportunity, Minnesota shareholder lawsuits, Minnesota shareholder litigation, Minnesota shareholder's derivative suits, and Minnesota special litigation committees, including representation of clients in Minneapolis, St. Paul, Apple Valley, Blaine, Bloomington, Brainerd, Brooklyn Park, Burnsville, Coon Rapids, Duluth, Eagan, Eden Prairie, Edina, Lakeville, Mankato, Maple Grove, Minnetonka, Moorhead, Plymouth, Richfield, Rochester, St. Cloud, Stillwater, Twin Cities, Woodbury and other cities within the State of Minnesota (MN) (Minn.).


text:
|Publication number
|Publication type
|Application number
|Publication date
|Aug 8, 1989
|Filing date
|Jul 20, 1988
|Priority date
|Jul 20, 1988
|Fee status
|Publication number
|John L. Batzer, Kristine N. Kneib
|Original Assignee
|Itt Defense Communications
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (4), Referenced by (44), Classifications (8), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates to apparatus for synchronizing or locking a receiving modem to a transmitting modem and more particularly to apparatus for utilizing a burst signal for assuring the synchronization of a receiving modem and an associated data set to a transmitting modem.
As one can readily ascertain, time and timing are extremely important factors in any digital transmission system. It is apparent that when signals are generated by a transmitter and received by a receiver the speed of the receiver must be the same or very close to that of the transmitter. In this manner it follows that whenever a receiver accumulates a timing error, it will process data incorrectly.
Thus, as one can ascertain, all currently used data transmission systems are synchronized in some manner. One prior art technique is referred to as start/stop or asynchronous operation. With such systems a character begins with mark-to-space transition at the beginning of the start space. Then a number of unit intervals later the timing causes the receiving device to sample the first information element which simply is a mark or space decision. The receiver continues to sample at one-bit intervals until the stop mark is received. In start/stop systems the last information bit is the most susceptible to cumulative timing errors. Such systems have other problems regarding the mutilation of the start element and so on. Synchronized data systems do not have start/stop elements but consist of a continuous stream of information elements or bits.
As such, such systems have timing generators or clocks to maintain stability. The transmitting device and its companion receiver at the far end of the circuit must maintain a timed system. In normal practice the transmitter is the master clock of the system. The receiver also has a clock and in every case the receiver's clock is corrected by some means to its transmitter's master clock equivalent at the far end.
As such, there are many techniques for providing such correction. The prior art, for example, utilized what is referred to as a "rubber" clock. Such "rubber" clocks or programmable interval timers are available at the receiver which essentially has logic circuitry for deriving a receiving clock from the transmitted waveform. The receiving circuitry uses the derived clock to synchronize its sampling clock with the clock derived from the transmitted waveform.
This in turn assures that the receiver will sample at the correct intervals to thereby regenerate the transmitted data. In any event, the use of programmable interval timers or "rubber" clocks requires a great deal of additional hardware and further makes the circuit in the receiver extremely complicated. As indicated, the most prevalent system in use today is one that uses transition timing where the receiving device is automatically adjusted to the signaling rate of the transmitter by sampling the transitions of the incoming pulses. This type of timing offers advantages in regard to automatic compensation for variations in propagation time. With this type of synchronization the receiver determines the average repetition rate and phase of the incoming signal transitions and adjusts its own clock accordingly.
As one can understand in digital transmission, the concept of a transition is very important. The transition is what really carries the information. In binary systems the space-to-mark and mark-to-space transitions as positioned in a time reference contain the information. In sophisticated systems, decision circuitry generates and retimes the pulses on the occurrence of a transition. Unlike decision circuits, timing circuits that reshape the pulse when a transition takes place must have a memory for the case when a long series of marks or spaces is received.
Hence, modem internal timing systems tend to have a long term stability of 1�10-8 or better at both the transmitter and receiver. At a data rate of 2,400 bps before a significant timing error can build up, the accumulated time difference between the transmitter and receiver must exceed 2�10-4 seconds. Whenever the circuit of a synchronized transmitter or receiver is shut down, the clocks must differ at least by 2�10-4 seconds before significant errors take place. This essentially means that the leading edge of the receiver clock equivalent timing pulse is 2�10-4 in advance or retarded from the leading edge of the pulse received from the distance end.
Thus, in such systems an idling signal is sometimes sent to synchronize data circuits during periods of no traffic to maintain the timing. Such systems utilize high stability clock circuits which require resychronization over prolonged intervals. Thus, as indicated, the above types of prior art systems utilize a great deal of additional hardware that is necessary in order to synchronize the receiving clock to the transmitting clock. This additional hardware increases the cost of such systems and further reduces the reliability.
It is, therefore, an object of the present invention to provide an improved locking system or synchronizing system for locking a receiving modem to a transmitting modem without the use of additional hardware.
The apparatus and method to be described employs a modem phase locking technique which technique employs a burst signal for such synchronization and which signal avoids complicated circuitry as implemented by the prior art.
Apparatus for locking a receiving modem to a remote transmitting modem, said receiving modem communicating with said transmitting modem over a communications channel of a given bandwidth for accommodating a given data rate with said transmitting modem providing an analog signal for transmission, which signal is generated by said transmitting modem using a clock for sampling digital data from a data set and converting said data according to said clock into an analog signal, comprising receiving means for receiving said analog signal and for converting said signal to a digital signal, an interpolation filter means responsive to said digital signal for providing a retimed digital output signal, said interpolation filter means having coefficient input means to enable said retimed signal to vary according to selected coefficients, means coupled to the output of said interpolation filter means and responsive to said retimed signal to provide an error signal at an output indicative of differences in bit positions of said retimed signal, means for applying said error signal to said coefficient input means for varying said retimed signal according to said error signal to lock said retimed signal to said transmitted analog
FIG. 1 is a simple block diagram showing a data communication system according to this invention.
FIGS. 2A, B and C depict a series of timing diagrams useful in explaining the operation of this invention.
FIG. 3 is a detailed block diagram of a modem according to this invention.
FIG. 4A is a block diagram of an interpolation filter according to this invention.
FIG. 4B is a diagram showing the transfer function of the interpolation filter according to this
FIG. 5 is a waveform depicting sampling between bits of a sampled waveform and an interpolated waveform.
FIG. 6 is a block diagram of a baud sync measurement circuit according to this invention.
FIGS. 7A-7C show flow charts describing in detail the operation of the interpolator filter.
FIGS. 8A-8C show flow charts describing in detail the operation of the baud sync measurement circuit.
FIGS. 9A-9B show flow charts describing the operation of the block-to-serial conversion circuit.
FIG. 10 is a block diagram depicting the selection of filter coefficients from the phase error signal developed by the baud sync measurement circuit.
Referring to FIG. 1, there is shown a typical data communication system which essentially includes an input-output (I/O) device 10. The I/O 10 is coupled to a data set 11 which essentially transmits digital data to a transmit modem 12. The modem 12 receives the data via the data line and synchronizes the data set 11 by means of a clock which is the system's reference clock. The modem 12 is a transmitting modem and essentially the word modem is an acronym for Modulator Demodulator. The function of the modem 12 is to convert the digital data received from the data set 11 to an analog signal for transmission over a typical transmission channel 14 which may for example be a telephone line.
At the far end of the telephone line, there is a receive modem 15 which receives the transmitted data and converts the data into digital data to be applied as a data input to a receiver data set 16. The receiving modem also supplies a clock and digital data to the data set 16 which data set operates on the digital data for converting the information so it is received by an I/O 14 which device 14 is compatible with device 10 in the transmitting modem. It is noted that the system of FIG. 1 is a general example of a data communication system. It is well known that the term data set is sometimes referred to as data processing terminal equipment (DPTE). See a text entitled "Telecommunications System Engineering" by Robert L. Freeman, (1980), John Wiley & Sons, Chapters 9 and 10. The input-output devices 10 and 11 are generally referred to as data input-output devices (I/O) and for example such input devices may handle paper tape, punched cards, magnetic tapes, disks, drums, visual displays, and printed page copies. Such input devices may include keyboard sending units, card readers, paper and magnetic tape readers, optical character readers and a host of other devices. Output devices include printers, card punches, paper and magnetic recorders, visual displays and so on.
One will immediately understand that one can employ many different input output devices in conjunction with a data set as 11. In a similar manner one can employ many different types of devices as 17 in conjunction with a data set. As one can understand from FIG. 1 and from the above description, the transmitting modem 12 takes a digital signal, converts it to an analog signal which is transmitted along a conventional transmission channel 14 which in this case is a telephone line. The transmitting modem includes a modulator for converting the digital data signals into a suitable modulated signal such as a PCM signal (pulse code modulation), a PSK (phase shift keying) signal, QPSK signal (quadrature phase shift keying) and so on. A typical data rate which is transmitted over such a telephone line may for example be 2,400 bits per second (2,400 bps). At the other end of the telephone line 14 or transmission channel, the receive modem 15 receives the transmitted analog signal and converts the signal into digital data. This digital data is sent to the data set 16 with a clock signal on separate lines as provided by the receiving modem. The data and the clock signal enable the data set to regenerate the transmitted information. As one will understand, if the receiving clock at the receive modem 15 is not locked to the transmitting clock as derived from the transmitting modem 12, data which is regenerated by the data set 16 will not be in synchronism with the transmitted data. Hence the received data will not correspond to the transmitted data. Thus, as one can understand and as indicated in the Background of the Invention, there is a requirement that the clock of the receiving modem 15 be locked to the clock of the transmitting modem 12.
As indicated, the prior art provided many techniques for doing this which included additional circuitry. The present invention, as will be explained, utilizes a burst technique which enables the receiving modem 15 to lock to the transmitting modem 12 to enable the receiving data set 16 to reproduce the transmitted data. The technique to be described eliminates the need for synchronizing the sampling clock of the receiving modem to the transmitted signal and therefore substantially reduces the amount of circuitry necessary to perform such synchronization.
Referring to FIG. 2, there is shown a series of timing diagrams which depict the various clocks and data signals which are used and are necessary to explain the operation of the system.
Before describing the operation of the system, it is indicated that the system to be described utilizes a transmission channel 14 of FIG. 1 as a telephone line. In this manner the bit rate is 2,400 bits per second which is conveniently transmitted over the telephone line. It is further understood that different data rates can be employed wherein the above example is indicative of one particular system employing the data rate of 2,400 bits per second.
FIG. 2A shows a receive and transmitting sampling clock which is a 7.2 KHZ clock. As one can ascertain, the clock rate of 7.2 KHZ is three times 2.4 KHZ which is the data transmission rate. The higher sampling rate is selected according to the conventional Nyquist criterion. As shown in FIG. 2A, a block or frame time consists of 5 milliseconds which essentially includes 36 clock pulses at the 7.2 KHZ rate.
FIG. 2B shows the receiver data clock which consists of pulses at a 3.6 KHZ rate indicative of the burst signal followed by a burst gap. The burst gap is devoid of pulses.
FIG. 2C shows the data output from the receive modem which is shown for the block time of FIG. 2A. As one will understand, the total burst signal encompasses eighteen 3.6 KHZ clocks for the 5 millisecond period. In any event, the burst pulse signal plus the gap is always equal to eighteen clocks at 3.6 KHZ. As will be explained, the burst consists of 12 cycles of 3.2 KHZ clocks which can vary �1 cycle. Because the burst signal can vary �1 cycle then the gap can vary between 6�1 cycle.
As will be explained, the burst time plus the gap interval is always equal to 18 clock cycles. Therefore, if one transmitted 12 data bits as shown in FIG. 2C, the gap would be 6 bits providing a total sum 18. Due to the synchronization technique to be described, one may transmit 13 data bits which will therefore provide a gap width of 5 again totaling 18 or one may transmit 11 data bits thus providing a gap width of 7 again totaling 18.
In this manner, by use of the burst signal, one can synchronize the receiving modem to the transmitting modem, as will be explained. Furthermore, the sychronization provided by the above-noted burst technique eliminates the need for synchronizing the sampling clock of the receiving modem to the clock of the transmitting modem as utilizing prior art locking techniques such as a "rubber" clock or a programmed interval timer. It is noted that in FIG. 2 the burst rate was selected at 3.6 KHZ which essentially is the sampling rate (7.2 KHZ) divided by 2. This is selected so that the burst frequency is higher than the data rate of 2.4 KHZ. It is, of course, understood as indicated above that if different data rates are employed then different burst frequencies can be employed.
In any event, as indicated and as shown in FIG. 2, it is important to note that the burst data clocks plus the gap is always equal to 18 clocks at 3.2 KHZ rate during a 5 millisecond frame or block time. The effective rate of the clock signal (FIG. 2B) and the data signal (FIG. 2C) is 2,400 HZ to enable a conventional data set as 16 to synchronize to the 3.6 KHZ burst and data as the effective 2.4 KHZ rate will operate the data set 16 as if there was a continuous 2.4 KHZ data and clock signal.
Referring to FIG. 3, there is shown a systems level block diagram of a typical modem subsystem. It is noted that the modem subsystem as shown in FIG. 3 is employed for a particular type of system and the burst locking technique which is the subject matter of this invention can be utilized in any other typical modem subsystem.
As shown in FIG. 3, the modem consists of a receiving path and a transmitting path at each location. The modem is connected or coupled to a telephone line 14 which interfaces with a hybrid 20. The hybrid 20 receives a transmitted signal from the Codec 22 indicative of an analog output for transmission on the telephone line 14. This signal may be a phase shift keyed signal or a QPSK modulated signal. A QPSK signal includes 1,200 symbols per second with each symbol being two bits. This is a well known technique. The hybrid 20 also serves to couple an analog input signal to the receive Codec 21. The word Codec stands for Coder-Decoder and operates to convert an analog signal to a digital signal in the case of the receive Codec 21 or to convert a digital signal to an analog signal in case of the transmit Codec 22. The functions of Codecs are well known and many examples exist in the prior art. As shown, the input to the modem subsystem include the two-wire telephone line 14. Once per output cycle of the 7.2 KHZ clock signal a receive transmit sample is read from and a transmit sample is written into the receive and transmit Codecs 21 and 22.
This clock (FIG. 2A) is used to provide sampling strobes for both the transmit and receive sides of the Codec. This invention is primarily concerned with the receive modem whereby the receive modem will operate to synchronize the data set 16 to the transmitted signal as will be explained. As one can understand, the Codec 21 includes an analog-to-digital converter which operates to sample the analog signal at the 7.2 KHZ rate. The received digital samples generated by the Codec 21 are 8 bits in length which are semilogorithmically coded. These samples are converted to 13 bit linear samples and subsequently grouped into 36 sample blocks. It is understood that the size of the block which is 36 samples corresponds closely to desired system operating characteristics and as shown in FIG. 2A a block or a frame would constitute 36 samples of the 7.2 KHZ clock. The output from the Codec 21 consists of the digital samples which as indicated are stored in the Codec 21 and outputed as 8 bit samples. These are directed to a module 23 which is MU Law to linear converter and block generator. Essentially, the module 23 contains a memory or table lookup and converts the bits into 13 bit linear samples which are grouped into 36 sample blocks. As shown, the output of module 23 consists of 36 samples or one block for each 36 samples.
Techniques for doing this are well known in the art. Once per 5 millisecond block time 36 received samples are coupled to the input of the module 24 labeled echo cancellation and AGC. Also inputted into this module are 6 symbol phasors which correspond to the 36 transmit samples as transmitted when the above-mentioned 36 received samples were received from the Codec. These six phasors are applied via a delay buffer 35 to the input of the echo cancellation and AGC circuit 24. The echo cancellation and AGC module 24 removes the transmit echo and adjusts the time average energy of the result to a predetermined reference level. The operation of an echo cancellation and AGC module as 24 is also well known.
The output of the echo cancellation and AGC module 24 contains 36 samples which are applied as an input to an interpolation filter and block size adjustment module 25. The interpolation filter has two outputs designated as a sample output and a block size output. These two outputs are coupled to a baud sync measurement circuit 26 which produces a phase error for application in a feedback loop to the interpolation filter and block size adjuster 25. The error signal from module 26 is used to control the filter coefficients of the interpolation filter 25. The interpolation filter 25 and the baud sync measurement module 26 adjust the block sizes such that the symbol rate matches that of the far end terminal. This is exactly the synchronizing scheme to be described in greater detail.
The outputs from the interpolation filter are coupled to module 27 which is indicated as a receive demodulation module. The module 27 demodulates the digitized phase shift keyed signal with a 36 complex sample adaptive equalizer and produces a vector of 6�1 dibits as an output. The block-to-serial conversion module 28 converts the 6�1 dibits to 12�2 bits per block. The module 28 then time averages the 12�1 bits per block then serializes and outputs the bits to the data set 16. Thus, the output of the block-to-serial conversion module 26 is indicated as RX clocks and RX data which are shown respectively in FIGS. 2B and 2C. The data set 16 receives the burst signals as indicated in FIGS. 2B and 2C from module 28.
As will be further described, the interpolation filter 15 retimes the sampled waveform so that a symbol period at the receiver is locked to the transmitter. A symbol size is six samples at the 7.2 KHZ rate. In a typical system the bit rate which is received over the telephone line is 2,400 bits per second and the system employs a QPSK modulation technique wherein 2 bits are transmitted for each symbol or 1,200 symbols are transmitted per second. The QPSK modulation technique as indicated above is a well known technique which is employed in many modems.
As shown in FIG. 3, the interpolator or interpolation filter 25 is used to retime the transmitted clock. The interpolator transforms a fixed length set of symbols into a variable length set of symbols at its output and conveys the number of signal samples to the baud sync measurement circuit 26 while informing the circuit of the particular block size. As one can ascertain, the interpolation filter can transmit 30, 36 or 42 samples which are sent to the baud sync measurement circuit 26. The number of samples transmitted is referred to as the block size. The baud sync measurement circuit 26 determines the symbol frequency and controls the coefficients for the interpolation filter by generating a phase error signal.
The interpolator 25 is basically a digital filter which is a circuit or computer program that is linear and time invariant and operates on discrete time signals. Digital filters are well known and are fabricated with conventional digital hardware such as adders, multipliers and shift registers for delay. Digital filters can also be implemented as computer programs for use with suitable general purpose or special purpose computers. The basic analysis tool for digital filters is the Z transform which is described and shown in many references.
The digital filter as employed for interpolator 25 is an FIR filter. The term FIR stands for finite impulse response. The filter as will be seen is a multi-ordered filter and, as indicated, its employing circuit 25 transforms a fixed length set of symbols into a variable length set of symbols to enable synchronization between the transmitted and receive clocks. The baud sync measurement circuit 26 receives the retimed samples from the interpolator filter 25 and receives information regarding the block size. The output from the baud sync measurement circuit 26 is indicative of the phase error of the retimed samples with respect to reference samples and operates to control the coefficients of the interpolation filter as will be explained.
The block size as indicated is the number of sets of six samples and that number corresponds to the block size which is responded to by the interpolation filter 25. The outputs of the interpolation filter 25 are coupled to the demodulation circuit 27 which produces one dibit for every six samples. Thus, the output of the demodulator 27 produces 6�1 dibits which are coupled to the block-to-serial conversion module 28 with information indicative of the number of dibits. The block-to-serial conversion module 28 then converts the output of the demodulator 27 to the waveforms shown in FIGS. 2B and 2C. It is indicated herein that techniques for performing such conversions as performed in module 28 are well known and there are many well known circuit configurations which will produce the two waveforms shown in FIGS. 2B and 2C for applying the same to a typical data set. The block-to-serial conversion module 28 is essentially a parallel-to-serial converter which stores the dibits in a register of a length according to the number of dibits. The stored bits are then shifted out at the 3.6 KHZ rate with the proper width to always equal 18 clocks according to the waveform of FIGS. 2B and 2C. The flow chart in FIG. 9 describes the operation of the block-to-serial module 28.
Referring to FIG. 9, there is shown the operation of the block-to-serial conversion module 28 of FIG. 3. The module essentially contains a plurality of registers, or register buffer. For the first block of data output from module 27 of FIG. 3, module 910 forms the value OBITS as that number of bits equal to twice the number of dibits output from module 27, then unpacks these dibits and places the resulting bits into positions 0 to OBITS-1 of the register buffer. On second and subsequent blocks of output from module 27, modules 912 to 920 operate to generate 11, 12, or 13 clocks with data, as follows. Module 912 forms the value NBITS as OBITS plus twice the number of dibits output from module 27, then unpacks these dibits and places the resulting bits into positions OBITS to NBITS-1 of the register buffer. Modules 913 to 917 determine the output count, OUTCNT, number of clocks to generate as being either 11, 12, or 13. Module 918 generates these OUTCNT number of clocks with data from register positions to 0 to OUTCNT-1. Module 919 moves the contents of the register buffer so that the first bit of the next set of bits to be output is placed in position 0 of the register buffer. Finally, module 920 determines the number of bits yet to be output from the register buffer as NBITS less the output count (OUTCNT). Thus, one will understand from FIGS. 9A and 9B how the operation of the block-to-serial module 28 is implemented. As one can ascertain, the output of the block-to-serial converter assures the proper rate signal as containing 11, 12, or 13 clocks within the 5 millisecond frame as shown in FIGS. 2B and 2C.
Again referring to FIG. 3, it is indicated that the block-to-serial conversion module 28 will initially not provide the output clock signal to the data set. The interpolation filter 25 and the baud sync measurement module 26 pass data through unaltered until the AGC function module 24 detects signal energy and the demodulation module 27 detects a carrier at which point in time the interpolation filter 25 and the baud sync measurement circuit 26 will be activated. The block-to-serial conversion module 28 will not produce clock outputs until after the appropriate start of a message sequence is detected by the demodulator module 27.
Shut down may be instigated by the loss of signal energy which is detected by the AGC module 24, loss of carrier which is detected by the demodulation module 27 or by a suitable command from terminal control. In the transmit path the serial-to-block converter 30 will initially not produce transmit clock outputs to the data set (as 11 of FIG. 1). The data buffers which are included in the linear to MU Law conversion and block conversion module 31 are loaded with one or more blocks of binary zero linear samples and the TX modulation module 32 expels 36 sample blocks of binary zeros and phasors of zero magnitude until activated with a suitable input. The serial-to-block conversion module 30 accepts inputs from a source other than the data set during formulation of the message header and contains sufficient buffer capacity to switch to the data set input source while maintaining continuity of data flow after providing its initial output.
In a similar manner shut down on the transmit path is initiated by a command from terminal control after which time the serial-to-block conversion module 30 will stop sending clock outputs to the data set and a TX modulation module 32 will revert to generating binary zeros to squelch the analog output. These system functions as briefly described above should enable one to more fully understand the system environment. Thus, briefly referring to the modem transmitting section, operation is as follows. Serial data are inputted from the data set at an average rate of 2,400 bps.
This average rate is indicative of the 3,600 HZ burst signal as for example shown in FIG. 2C. The bits in the 5 millisecond block time are grouped into blocks of 6 dibits each. This conversion is performed in module 30 designated as serial-to-block conversion. The TX modulation module 32 converts each dibit into a phase shift of 45, 135, 315 or 225 degrees corresponding to a dibit value of 00, 01, 10, or 11 respectively. These phase shifts are added to an 1,800 HZ rotating phasor once per baud time to produce six phasor outputs per block time. These phasors are stored in the delay buffer 25 for subsequent processing by the echo cancellation module 24 in the receive path. Each of the six phasors is converted to an 18 sample sinusoidal symbol, window weighted with a sine (X)/X function and overlaid on its predecessor with a six sample intersymbol time displacement.
This TX modulation technique is widely utilized in many modems. The linear to MU Law conversion and block conversion modules 31 semilogorithmically encodes the sample for subsequent output to the TX Codec 22. Hence, they are converted to an analog signal as a QPSK modulated signal and applied to the telephone line 14 via the hybrid 20.
As indicated above, the TX and RX samples are the input to and the output from the Codec 21 and 22 with a common strobe from a 7200 HZ clock (FIG. 2A). The transmitter clock of the far end terminal which provides the analog input to the RX Codec 21 is not precisely aligned with and will drift with respect to the receiving clock which is employed for example in the receiving section.
As shown in FIG. 3, the input to the baud sync measurement circuit 26 is a block of either 30, 36 or 42 samples. The baud sync measurement module 26 employs windowed filters which operate to detect the positions of the baud transitions with respect to baud transitions which have been retimed. The phase error which is the output of the baud sync measurement module represents an uncorrected timing error. This phase error is fed back into the interpolation filter 25 to change the filter coefficients and, subsequently, to reduce the uncorrected timing error for next block processing. As illustrated in the flow diagram, FIG. 7, the interpolation filter generates a fractional 7200-HZ clock-period delay to the input samples to produce the output samples, said fraction represented by an integer numerator ranging from 0 to 63 and a denominator of 64, said numerator corresponding to a particular set of 64 sets of interpolator coefficients.
Also as indicated in the flow diagram, FIG. 7, the interpolator filter keeps track of the amount of delay it has applied to its input samples by use of a state variable, which is designed to contain one of 386 integer values ranging from -1 to 384, inclusive. When the interpolator filter increases or decreases its delay by 1/64 of one 7,200-HZ clock period, the interpolation filter increments or decrements the state of the variable. As illustrated in the flow diagram of FIG. 7, the interpolator filter generates 36 output samples for all state variable values except -1 and 384. For a state variable value of -1, the filter generates 42 output samples and changes the state variable value to 383; for a state variable value of 384, the filter generates 30 output samples and changes the state variable value to zero. The time average value of the block size which is nominally 36 samples will be locked to the baud rate at the far end terminal.
As indicated above, the purpose of the interpolation filter is to calculate what a receive sample value would be if the receive Codec 21 were to be strobed a fraction of a 7200 HZ clock cycle late. A constant amount of lateness (phase) is applied to all samples for a given block.
Referring to FIG. 4A, there is shown a typical example of an interpolation filter which operates according to this invention. The diagram of FIG. 4B describes a multi-order interpolation filter. As one can see from FIG. 4B, a curve is fit to contain the samples closest to the desired phase point and that is indicative of the interpolation filter operation. The value of the interpolated sample is the value of that point on the curve at the desired phase. To reduce computation load, the filter coefficients which represent the solutions to a phase-linear system are precomputed and placed in a Read Only table which is included within the interpolation filter module 25. The table is a Read Only memory which is accessed by the method indicated in the flow chart of FIG. 7. During the run time, the interpolation filter needs only to look up the appropriate set of filter coefficients by using the interpolator state value to calculate a table index. This value is determined by all previous values of the phase error from the baud sync measurement circuit 26.
Thus, as seen from FIG. 4A, the interpolating filter receives the 36 input samples and operates to multiply these samples by the filter coefficients which are indicated as input to multiplier modules 40, 41 and 42. As one can understand from the diagram of FIG. 4A, the interpolation filter is a relatively conventional design and operates to provide solutions to a phase-linear system. The coefficients a0, a1 and aN which are supplied to the multiplier modules 40, 41 and 42 are obtained from the memory lookup table as accessed by the phase error signal provided by the baud sync measurement module 26. The output of the various multipliers as indicated are summed in a summer 43 where they provide an output which is the retimed samples as directed to the baud sync measurement circuit 26. The operation of the interpolation filter circuit is described in detail in the flow charts of FIG. 7.
Referring to FIG. 7, there is shown the flow chart operation of the interpolator filter. As one can see from FIG. 4, the interpolator filter contains a plurality of registers each designated as Z-1. As shown in the flow chart, these registers are all set to zero via the procedure indicated by module 702. The system also acknowledges that the interpolator filter has been accessed for the first time. After setting the registers to zero, module 705 indicates that the signal is moved by shifting thirty six registers to the left. This as indicated in module 706 places 36 samples of the input signal into the upper thirty six registers. The phase error, as indicated in module 707, is the phase error provided by the baud-sync-measurement circuit. Depending on the magnitude of the phase error as being greater than or less than zero and as indicated by modules 707 and 709, one employs the sign of the phase error to increment and decrement the internal state of the interpolator. As indicated by module 711, the interpolator then determines which set of coefficients it will use. As indicated, the set of coefficients for the interpolator are stored in the memory look-up table which table is accessed by the interpolator routine. This as shown in FIG. 10 is further explained.
In any event, the interpolator utilizes the phase error to perform a state integration then decodes the phase error and selects coefficients which are stored in memory look-up tables. This is indicated by modules 712, 713 and 714 as shown in the flow diagram of FIG. 7. After selecting such coefficients, the interpolator then generates 30, 36 or 42 output sample values whereby the output-sample counter is then incremented as indicated by module 718. The filter operates to process and to generate one output sample as indicated by module 719. It then proceeds to generate a sufficient number of output samples indicative of the block size as indicated by module 723. Thus, the interpolation filter provides the output sample through the output sample block size and also provides the block size as an output. This is shown in FIG. 3 in module 25.
Referring to FIG. 6, there is shown a simple block diagram of the baud sync measurement circuit 26. The baud-sync measurement circuit 26 contains a sample register which operates in conjunction with a plurality of summers, squarers, timers, integrators, and comparators to produce a phase error as output. Essentially, the phase error is an indication of the residual timing error that has not been corrected. The baud-sync-measurement circuit includes a sample register 50 which receives input samples and block size as also indicated in the block diagram of FIG. 3. The sample register has a plurality of outputs which are coupled to the respective summers as 51, 52, 53 and 54. The outputs of the summer are squared by means of the squarer circuits 69, 70, 71 and 72. The output of squarer circuit 69 goes to an input of output summer 55 having as another input the output of squarer circuit 71. In a similar manner, the output of squarer circuit 72 serves as an input to summer 56 which summer has another input received from the output of squarer circuit 70.
Essentially, the summer 55 produces a signal indicative of an early sum while the output of summer 56 produces a signal indicative of a late sum. The terms "early" and "late" sum are indicative of the phase delay between measured samples as shown for example in FIG. 5. The early summer 51 provides the sum of four consecutive samples as for example 0-3 while the summer 52 provides the sum of four consecutive samples 3-6 and so on for each summer until all samples have been summed. Thus, all the sums of "early" summers as 0-3, 6-9 . . . etc. are summed in summer 55 and all sums of later samples as 3-6, 9-12 . . . etc. are summed in summer 56 after sampling. Thus, the output of the summer 57 produces a drift error. This drift error signal is applied to one input of a summer 58 which receives another input through a register 60 designated as SIGERR. The register 60 as shown in the flow chart is a holding register and provides a delay equal to 5 milliseconds. The output from the summer 58 is applied through a time delay 59 which provides a delayed output signal which signal is applied to the-input of the summer 58. The same signal is applied as an input to summer 61 which receives a delayed input from a delay register SACC which is a signal accumulator register. The output from the adder 61 is applied to a divide by eight 63 whose output is applied to a summer 64 at one input. The other input to summer 64 is the signal output from the 0.5 second timer 59. The output of summer 64 is applied to the input of a divide by thirty-two or multiply by one/thirty-two 65 whose output is applied to one input of a 3-input adder circuit 66.
Another input to the adder 66 is obtained through a delay register 67 designated as MACC which is metric accumulation register. The output of that register is applied to one input of the adder 66, as indicated. Another input from the adder 66 is obtained from the output of a threshold decision module 68. The input of the threshold decision module 68 is supplied from the output of the adder 66.
The threshold decision module 68 produces a signal indicative of the phase error. This signal is either +1, -1, or zero, as will be further explained.
Referring to FIG. 8, there is shown in detail the baud-sync-measurement circuit operation. The circuit operation is shown in terms of a flow chart. Essentially, at the start which is designated by module 80, the system determines whether this was the first time the measurement has been executed. This is indicted by module 81. If it was the first time then the registers as the MACC register, the SACC register, the SIGERR register and the TIMCNT (timer of 59 of FIG. 6) are set to zero. Module 83 indicates that one now resets the first time executed indicator. In any event, this means that the program will continue as indicated. Module 84 indicates that the early, late and start outputs are set to 0, 0, 1 respectively. In modules 85 and 86 one accumulates the early window energies as well as the late window energies for the present six-sample symbol. This six-sample symbol is stored in a register. The apparatus via module 87 then determines the start of the next six-sample symbol and accumulates energies for all six-sample symbols within a block as indicated by module 88. If all energy has been accumulated within a block as indicated by module 88, one now goes to module 89 to calculate the drift error which is the difference between the early and late signal energies. The output goes to module 90 where the drift error is integrated. Module 91 indicates that one accumulates 5 milliseconds units of time after integrating the drift error. This 5 milliseconds is one data frame. The timer counter which is timer 59 is tested to see whether it has counted to 500 milliseconds. If it has then the signal is set equal to the error signal, the register SIGERR is set to zero and the TIMCNT is set to zero. From module 94 one enters module 95 where the error signal is integrated. In module 96 a metric is formed which is operative to change the interpolator state. Module 97 indicates that the metric is integrated. The output of the integrated metric now determines the phase error which is basically the threshold decision circuit 68. Hence, the threshold detector looks to see whether the contents of the MACC register is less than -1 or greater than 1. If its is not greater than either then the phase error is set to equal zero and the output phase error is provided for subsequent use by the interpolator filter as will be further explained by referring to FIG.
In FIG. 10 there is shown a simple block diagram where the phase error as developed by the above-noted circuitry or at the output of the threshold decision detector 68 of FIG. 6 is applied to a state integrator 120. The output of the state integrator 120 is applied to the decode circuit 121 whose output accesses a memory look-up table 122 to provide the various filter coefficients for the interpolating filter. The state integrator 120 takes the phase error as described above and adds this error to the interpolator state in order to decode all phase errors via decoder 121 and to access the memory look-up table 122. Essentially, this function is performed by the interpolation filter as the operation performed by modules 707 and 709 of FIG. 7. The look-up memory is indicated in FIG. 7 and accessed via modules 711-715.
FIG. 5 shows a typical sampled waveform where the squares stand for the sampled waveform points and the circles stand for the retimed or interpolated waveform points. This signal as indicated is sampled and produces a cumulative phase error between the sampled waveform and the interpolated waveform as shown.
The summers in FIG. 6 are shown by way of example and it is understood from FIG. 6 that there are additional summers operative to sum all desired samples in a 5 millisecond frame period. Thus, as one can understand from the above description an average traffic of 2,400 bits per second occurs between the modem and the data set. This is achieved by providing a burst of nominally 123,600 HZ clocks in a 5 millisecond time interval as shown in FIG. 2C. The actual number is 12 for the internal modem TX and either 11, 12, or 13 for the internal modem RX. The 12 clocks at 3.6 KHZ per 5 millisecond is equivalent to a traffic rate of 2,400 bps. The provision for 11 or 13 clocks during any given 5 millisecond interval allows the modem subsystem which generates the clocks to lock to the transmitting clock of the far end terminal.
Once per 5 millisecond block time in the receive path, the block labeled block-to-serial conversion 28 determines the number of dibits 6�1 which were demodulated. These are converted to 12�2 bits which accumulate in an internal buffer within the block-to-serial conversion module 28. If the internal buffer is relatively light, moderate or heavy with data then either 11, 12, or 13 bits respectively are expelled on an FIFO basis from an internal buffer at a 3,600 HZ burst rate during the next 5 millisecond block time.
It is also indicated that based on the above description, many of the routines basically described can be implemented by programs which control a typical processor circuit which is inherently included in most modems as shown for example in FIG. 3. It will be immediately ascertained that based on the timing diagrams of FIG. 2, that one can transmit the burst signal to a data set and depending upon the number of data signals detected can assure synchronization of the receiving modem with the far end transmitting modem.
Thus, as one can see and ascertain from the above description, the system herein relies on the transmittal of burst data during a fixed 5 millisecond period. The burst data is followed by a burst gap which data and gap are always equal to 18 samples of the 7.2 KH clock. In this manner, the number of data or clock pulses can be transmitted as 11, 12 or 13 resulting in a burst gap of 7, 6 or 5. This enables synchronization of the receiving modem to the transmitting modem and allows correct operation of the data subsets.
As far as the data set is concerned, based on the selection of the burst signal at the frequency of 3.6 KHZ, the data set receives an average data transmission of 2,400 bps and Operates synchronously due to the above described technique.
Thus, it is understood that one need not synchronize the sampling clock of the receiver to the sampling clock of the transmitter as accomplished in prior art systems as in this system one automatically receives synchronized data due to the burst frequency technique.
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|U.S. Classification
|375/354, 375/222, 708/313
|International Classification
|Cooperative Classification
|European Classification
|Jul 20, 1988
Owner name: ITT CORPORATION, 320 PARK AVENUE, NEW YORK, NEW YO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:BATZER, JOHN L.;KNEIB, KRISTINE N.;REEL/FRAME:004936/0327
Effective date: 19880715
|Sep 8, 1988
Owner name: ITT CORPORATION, 320 PARK AVENUE, NEW YORK, N.Y. 1
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:KNEIB, KRISTINE N.;REEL/FRAME:004937/0738
Effective date: 19880808
|Jan 28, 1993
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