text:
|Publication number
|Publication type
|Application number
|Publication date
|May 6, 2008
|Filing date
|Jan 31, 2005
|Priority date
|Jan 31, 2005
|Fee status
|Publication number
|Geoffrey W. E. Steckel
|Original Assignee
|Bluespec, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (12), Non-Patent Citations (33), Referenced by (17), Classifications (7), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention is related to the following co-pending and commonly assigned U.S. patent application Ser. No. 11/047,329 titled, System and Method for Scheduling TRS Rules, which application is hereby incorporated by reference as though fully set forth herein.
1. Field of the Invention
This invention relates generally to the verification and simulation of digital circuits developed in a hardware design process, and more specifically to the use Term Rewriting System (TRS) rules in the simulation of synchronous digital circuits.
2. Background Information
Hardware Description Languages (HDLs) have been used for many years to design digital systems. Such languages employ text-based expressions to describe electronic circuits, enabling designers to design much larger and more complex systems than possible using previously known gate-level design methods. With HDLs, designers are able to use various constructs to fully describe hardware components and the interconnections between hardware components. Two popular Hardware Description Languages are Verilog, first implemented by Phil Moorby of Gateway Design Automation in 1984, and later standardized under IEEE Std. 1364 in 1995, and VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Design Language), standardized in IEEE Std. 1076. Both, these languages, and other similar languages, have been widely used to design hardware circuits.
As the complexity of digital circuits has increased, conventional HDLs such as Verilog and VHDL have increasingly shown their limitations. New HDLs based on Term Rewriting System (TRS) technology address some of the limitations of the conventional methods. A TRS employs a list of "terms" that describe hardware states, and a list of "rules" that describe hardware behavior. A "rule" captures both a state-change (an action) and the conditions under which the action can occur. Further, each rule has atomic semantics—that is, each rule executes fully without interactions with other rules. This implies that, even if multiple rules are executed on a given state, they can be considered in isolation for analysis and debugging purposes.
More formally, a Term Rewriting System has rules that consist of a predicate (a function that is logical true or false) and an action body (a description of a state transition). A rule may be written in the following form:
rule r: when π(s)=>s:=δ(s)
where s is the state of the system, π is the predicate, and δ is a function used to compute the next state of the system. In a strict implementation of a TRS, only one rule may execute on a given state. However, as explained further below, concurrent application of rules is desirable for efficient execution. Therefore, if several rules are applicable on a given state, some implementations may allow more than one rule to be selected to update the system. Afterwards, all rules are re-evaluated for applicability on the new state of the system and the process continues until no further rules are applicable.
While a TRS approach has been advantageously employed in the design of digital circuits, improvement in the verification (the proving or disproving of the correctness) of these digital circuits has lagged. As the complexity of digital circuits increases, verification consumes an increasingly large portion of the development process' time and resources, now often consuming as much as sixty or seventy percent of development time for a reasonably complex circuit. The development of a digital circuit typically follows an iterative flow, including a variety of stages of design and verification, such that any bottlenecks at a particular stage may typically set back the entire development project's completion.
Next, functional verification (step 140) is typically performed on the RTL description. Functional verification is a key step in the development processes, where desired functionality is checked and most functional bugs are located and corrected through modification of the RTL code (see prior step 130). During functional verification, a combination of direct and random tests are typically employed on a simulation of the digital circuit. Such a simulation generally loads HDL code and simulates its behavior in a software environment adapted for testing and analysis. As digital circuit designs become increasingly complicated, the computations necessary for simulation have become a problematic and time-consuming issue in the verification process.
After functional verification, logic synthesis tools are typically employed (step 150) to convert the RTL description (of step 130) to a gate-level netlist (step 160), which is a description of the circuit in terms of gates and connections between them. Logic synthesis tools (from step 150) generally attempt to produce a gate-level netlist that meets timing, area, power and other specifications of the design specification. Such specification factors may be checked through logical verification (step 170). Results generated in logical verification may be compared with results obtained during functional verification (see step 140) to ensure correctness of operation. Again, if errors are found, RTL description (from step 130) may be altered and the sequence repeated. After successful logical verification (see step 170), a physical layout of the digital circuit showing the position of gates and connecting traces is typically created (step 180) with a Place and Route tool. Such a layout is typically subject to layout verification (step 190) and, if any issues are detected, the physical layout (from step 180) may be appropriately modified. Once this verification is complete, the device may be fabricated onto a chip to produce a finished hardware device in step 195.
As noted above, the functional verification and simulation stage is a key stage in the hardware development process. In more detail, functional verification typically begins with the creation of a functional test plan, a fundamental framework for the testing of the digital circuit. Based on this test plan, various routines adapted to test specific functionality of the circuit are developed. These test routines are designed to be applied to a simulation of the digital circuit, often referred to as the design-under-test (DUT). Commonly, a High-Level Verification Language (HVL), such as VERA developed by Synopsys, Inc., is employed to aid in writing test routines and in creating a test environment around the DUT that facilitates testing. HVLs typically combine object-oriented programming approaches with parallelism and timing constructs and thus are well suited for verification. HVLs may be further employed to create input drivers, output drivers, data checkers, protocol checkers, coverage analysis testers, and other devices useful in the verification process.
The test environment interacts though an interface with the simulation of the DUT. Generally, simulators are classified into three basic types, based upon the manner in which they perform simulation. Interpretive simulators, such as Verilog-X, available from Cadence Design Systems Inc, operate by reading in an HDL design, creating data structures in memory, and running a simulation interpretively. Interpretive simulators are characterized by their compiling of HDL code each and every time the simulation is run.
Compiled-code simulators, such as VCS available from Synopsys, Inc, operate by reading in an HDL design and converting it to a programming language, such as C. This code is then compiled by a standard compiler to produce a binary executable that may be executed to run the simulation. Compile time may be lengthy for compiled code simulators, but in general, execution speed is faster than possible with interpretive simulators.
Finally, native-compiled-code simulators, such as Verilog-NC available from Cadence Design Systems Inc., operate by reading in an HDL design and converting it directly to binary code for a specific machine platform. Compilation is optimized specifically for this platform, making the simulation machine specific. Due to the machine specific optimizations, native-compiled-code simulators can yield significant performance benefits compared to other types of simulators.
Regardless of their type, HDL simulators employ a simulation strategy to simulate design elements. The simplest simulation strategy is termed "oblivious," or alternately "exhaustive," simulation. In oblivious simulation, the simulator processes and updates state values of all elements (modules) in the design, irrespective of changes in signals. That is, the state value of each module is updated every time step (clock cycle), regardless of whether there is activity, or a change in the state of the system that affects the particular module. Computing all state values for all clock cycles is typically redundant and generally consumes unnecessary computing resources. Indeed, an oblivious simulator may perform quite inefficiently when a module is inactive, i.e. does not change state, for many clock cycles.
In an attempt to address this inefficiency, various schemes have been developed for reducing the amount of computation necessary for simulation, including schemes for reordering, rewriting, queuing, deferring, or otherwise systematically evaluating a subset of the system's state values. One of the most prevalent approaches to reducing computation is termed "event-driven" simulation. Event-driven simulation is characterized by the computation of state values for modules only when signals at the inputs of these modules change (herein termed an "event"). Accordingly,
When an event is delivered to a module 230, 232 and 234, a child process, 240, 242 and 244 is called to execute the code in the module. A current state 250, 252 and 254 for the module 230, 232, 234 is also formed, representing an event triggered by the child process 240, 242, 244 and the current state of any global variables used as inputs to the module. The child processes 240, 242, 244 typically execute under the control of an operating system until execution is completed. Typically, an event-driven simulator operates within a multi-threading operating system, with each child process 240, 242, 244 representing a separate thread of execution, all of which threads execute contemporaneously within the processor's runtime operation.
While event-driven simulation offers significant improvements over oblivious simulation, the approach still contains notable inefficiencies. In event-driven simulation, when an event is processed, all dependant data is updated, through the triggering of additional events, to determine a new global state of the system. Values for data that will not control the next state transition of the system, and values for data which is transient, i.e. that will not be stored due to subsequent logic control, are still updated, and cause events to be triggered, even though these values are not used. For example, consider the effects of event-driven simulation on a hypothetical digital circuit design which include the following HDL pseudo code:
reg [3:0] q;
reg [3:0] e;
wire [3:0] y=q+5;
always @(posedge clock) begin
always @((posedge clock) begin
In the above hypothetical example, the value of y depends on the value of q, which in turn depends on the value of z. Hence, in an event-driven simulator, a change in the value of z would trigger events causing the value of y and q to be updated by child processes. Yet the values of y and q are only needed when they control the next state transition, in this example, only when the Boolean value controlsignal is logical true. Thus when controlsignal is logical false, needless computation is performed by an event-driven simulator to update values of y and q that are never used.
Again, as digital circuit designs become increasingly complex, simulation emerges as a primary computational bottleneck in the overall hardware development process, consuming unacceptable processing time. The inefficiencies associated with computing redundant or transient values in an oblivious or an event-driven simulator merely compound the already-computationally intensive stage of simulation. It would be desirable for such an HDL simulator to function in a manner that would eliminate computation of unnecessary values that do not affect the current state of the system. An improved simulator should address this inefficiency, while not requiring an inordinate amount of computation in other areas, so that an overall performance gain may be realized.
Briefly, the present invention provides a system and method for simulating a digital circuit that uses scheduling information from Term Rewriting System (TRS) rules to limit the computation of simulation values to only those values used by the rules scheduled to execute on the current state of the system. In a TRS based digital circuit design, typically only a small subset of TRS rules are scheduled to execute on any given state. This novel system and method for simulation uses scheduling information for these rules to determine which values are needed for the executing subset of TRS rules, and only computes these relevant values. Since, for TRS rules, the logic for computing rule activation, i.e. the predicates, is separate from the logic for executing the actions, i.e. the action bodies, the simulator need only consider a limited amount of additional information to determine which rules are executed on a given cycle. Broadly stated, the system and method of this invention employs a top-down approach to device simulation (as opposed to the bottom-up approach typically employed by prior simulators), looking first to which rules are to be executed, and only then, to the values needed by those rules.
The new simulation system and method may be used to create a standalone simulation of a synchronous digital circuit from an asynchronous circuit specification. A TRS compiler creates executable code which models the circuit's functions. This executable code may be linked by a code simulator with a runtime executable, which provides input interfaces, output interfaces, data-checking and testing tools. The executable code may further be linked to a runtime library of primitive objects, i.e. gates and other logic devices, which provide requisite timing characteristics for the simulation.
The inventive system and method avoids inefficiencies associated with traditional techniques, such as event-driven simulation, by avoiding computation of redundant or transient values for data that will not control the next state transition of the system. Further, due to the inherent structure of TRS rules, the advantages of the new simulator may be achieved with minimal additional computations so as to determine which rules will execute.
The invention description below refers to the accompanying drawings, of which:
Both TRSC 320 and code simulator 340 are software applications that, when executed on a computer, implement the circuit simulation approaches described below. In one embodiment of the circuit simulation system 300, the executable (computer-readable) programming code 330 may take the form of C code. It should be noted, however, that the executable code 330 may alternately be implemented in another programming language, such as, for example, the Java programming language first developed by James Gosling of Sun Microsystems.
Considering this system in more detail, asynchronous circuit specification 310 may be specified according to a Term Rewriting System (TRS). A Term Rewriting System generally employs rules that have a predicate and an action body, and may be written in the general form:
where π is the predicate and s:=δ(s) is the action body. Function δ is used to compute the next state of the system from the current state s. The system functions by selecting a rule whose predicate is true, and then atomically (without interaction with other rules) executing the rule's action body. The selecting and executing of rules continues as long as some rule's predicate is true.
Such a system is suited for design and verification of complex digital systems as explained in Arvind and X. Shen, "Using Term Rewriting Systems to Design and Verify Processors," MIT LCS Memo CSG-419, IEEE Micro, May/June 1999; Mithal et al., Digital Circuit Synthesis System, U.S. Pat. No. 6,597,664; and Mithal et al., Digital Circuit Synthesis System, U.S. patent application Ser. No. 10/264,962, all of which are incorporated by reference herein in their entirety.
In an illustrative embodiment, the asynchronous circuit specification 310 may be specified in Bluespec™ System Verilog (BSV) which implements Term Rewriting System semantics in combination with other high level programming constructs as described in the Bluespec™ System Verilog Version 3.8 Reference Guide, incorporated herein by reference. It is expressly contemplated, however, that other suitable languages implementing a general form or function of a Term Rewriting System may be employed with the approaches described herein. If asynchronous circuit specification 310 is a BSV specification, TRSC 320 may be a Bluespec™ Compiler (BSC) or another suitable compiler adapted to implement the scheduling and circuit synthesis approaches described herein. Further, the code simulator 340 may be a Bluespec™ C simulator or other suitable simulator adapted to implement the approaches described herein.
To illustrate an example of TRS rules in hardware design, let asynchronous circuit specification 310 characterize a circuit for computing the greatest common devisor (GCD) of two numbers using Euclid's algorithm. This example is chosen merely to illustrate a possible use of Term Rewriting System rules, and in no way limits the type of circuit that can be characterized by, or the syntax used in, asynchronous circuit specification 310. In the chosen example, the exemplary asynchronous circuit specification 310 may read in part:
Referring to the exemplary code above, the module defines two registers, registers x and y. Further the module defines two rules, flip and sub, that implement Euclid's algorithm on registers x and y. Each rule contains a predicate and an action body. For example in rule flip, the expression,
forms the predicate and the register write statements,
form the action body.
If a predicate is omitted, the rule is assumed to always apply, and if the action body is omitted the rule has no effect. Assuming the registers x and y have been initialized with input values, the rules will repeatedly update the registers with transformed values, terminating when the register y contains zero. At that point, the rules cease executing, and the GCD result is placed in register x. Note that, in this basic example, the two rules flip and sub are never applicable at the same time. In more complicated examples, predicates for multiple rules may be true for a given state. For example, the expression "x>y" may be replaced with "x>=y" in the predicate of rule flip. In this new example, more than one rule could apply in each cycle and a determination would have to be made as to whether the rules conflict. Thus, the system would have to determine whether to execute rule flip, rule sub, or both rules on the same state.
Considering in more detail some of the steps described above, in step 410 the TRSC 320 maps storage elements in the asynchronous circuit specification 310 into a variety of representations of actual circuit elements whose values determine the state of the system. Asynchronous circuit specification 310 may include data-type declarations for a variety of types of storage elements. If scalar storage elements are used, the mapping by the TSRC 420 may be direct into a representation of a register circuit. If abstract storage elements are used, such as a register files or FIFO queues, the TRSC 420 may map these elements into representations of predefined circuit elements, for example, from a runtime library.
In step 420, the TRSC 320 models logic for the predicate and the action body of each Term Rewriting System rule. Formally, for a rule i, TRSC 320 considers expressions, πi(s) and δi(s) where the term s represents the state of the system, i.e., the values in all the storage elements.
In step 430, the TRSC 320 determines which rules may conflict if they execute concurrently and which rules are free from conflicts. Conflict-free rules are rules that can execute simultaneously without incident, that is, they do not update the same state nor update the state accessed (read) by the other rules. Such conflicts may be thought of as two devices attempting to access the same hardware resource, such as, for example, a single memory port, whereby only one device may have access at a time.
The conflict-free condition between two rules may be stated formally as follows. Consider two rules, rule i and rule j, with predicates πi and πj and next states defined by functions δi and δj. Further, let s be the state of the system. If πi(s) and πj(s) are both true for some state s, then both πi(δi(s)) and πj(δj(s)) must also be true so that both rules remain enabled after the state transition enabled by the other rule. Furthermore, the effect of the updates must not depend on the order of the updates, that is, δi(δj(s)) must equal δj(δi(s)).
A variety of algorithms and data structures may be employed to help determine which rules are free from conflicts. One such structure is the Binary Decision Diagram (BDD), a data structure commonly thought of as a rooted, directed, acyclic graph with vertices that represent variables and edges connecting the vertices that represent values of the variables. Thus, a path through a BDD represents a particular assignment of values to variables. Such a structure may be advantageously employed to determine that two rules may never execute on the same state and therefore may never be in conflict.
In step 440 the TRSC determines a schedule that indicates which rules should execute in a particular cycle of a model of a synchronous implementation. Such a determination may be performed by a scheduler that implements one of a several scheduling methods. One type of scheduler that may be employed is a priority encoder which asserts one executable rule in each clock cycle. This type of scheduler may also include round-robin functionality that ensures that if a rule remains applicable for a sufficient number of consecutive clock cycles then it will be selected for execution. Another type of scheduler that may be employed is an enumerated scheduler (also termed direct table encoder). In an enumerated scheduler, applicable rules are listed in an enumerated encoder table, a lookup table constructed to contain an explicit listing of the rules that can execute given a certain combination of applicable rules. Such a table is constructed so that the maximum number of non-conflicting rules execute on a given clock cycle. Preferably, a scheduler that implements a preference order in scheduling conflicting rules may be used. That is, a scheduler may be employed that is adapted to schedule more preferred applicable conflicting rules over less preferred applicable conflicting rules. In this manner, the most preferred rule of a conflicting set is scheduled to execute on a given state. Thus, where two or more rules conflict, and only one may be chosen to execute, the preference order is used to break the tie. Such preference order may be user inputted, or generated by the TRSC. As in other implementations, non-conflicting applicable rules are allowed to execute concurrently with the chosen conflicting rule.
A schedule for TRS rules may be incorporated into a new system and method for simulation that addresses the shortcomings and inefficiencies of prior simulation techniques. Accordingly, in an illustrative embodiment a top-down approach to simulation is employed, where the simulation system first considers which Term Rewriting System (TRS) are scheduled to execute on the current state of the simulation. Thereafter only the simulation values used by those rules are calculated. In a TRS-based digital circuit design, typically only a small subset of TRS rules are scheduled to execute on any given state. Thus, by limiting computation of simulation values to only those rules active on that present state, performance gains may be realized.
Operation of the simulation system and method may be illustrated by referring to a hypothetical example of an asynchronous circuit description including TRS rules. The reader is reminded that this hypothetical example is merely an illustration of one possible set of TRS rules the simulator may operate upon, and in no way limit the function, syntax, or other aspects of the TRS rules this invention is applicable to. A hypothetical example may read:
typedef UInt#(51) NumTyp;
interface ArithIO_IFC #(parameter type aTyp); // aTyp is a paramerized type
method Action start(aTyp num1, aTyp num2);
method aTyp result( );
endinterface: ArithIO_IFC
// The following is an attribute that tells the compiler to generate // separate code
for mkGCD
(* synthesize *)
module mkGCD(ArithIO_IFC#(NumTyp));
// here aTyp is defined to be type Int
Reg#(NumTyp) x( );
// x is the interface to the register
mkReg#(?) the_x(x);
// the_x is the register instance
Reg#(NumTyp) y( );
mkReg#(0) the_y(y);
rule flip (x > y && y != 0);
x <= y;
y <= x;
rule sub (x <= y && y != 0);
y <= y − x;
method Action start(NumTyp num1, NumTyp num2) if (y == 0);
x <= num1;
y <= num2;
endmethod: start
method NumTyp result( ) if (y == 0);
result = x;
endmethod: result
endmodule: mkGCD
This hypothetical description performs the same function as the hypothetical code discussed above in reference to event-driven simulation. Yet, rather than compute values for y and q for each change in z, as would be done in event-driven simulation, the simulation system and method of this invention works backwards from the rule predicates to compute a minimal subset of values that are actually used to generate the next system state. That is, rather than assuming any change in the system may cause an indefinite number of dependant events, and therefore computing all values dependant on any value change, the new simulator can avoid computations that are not used. Thus if, for example, the scheduler determines that controlsignal is false in the above example, values for q and v need not be calculated. Similarly if the scheduler determines that rule e is in conflict with another rule, and this other rule has been selected to execute rather than rule e, then values for q and v again need not be calculated. Only when the scheduler determines controlsignal is true, and is the selected rule to execute if a conflict exists, are sub-routines called to generate values for q and v.
Such a simulation system and method is ensured of having worst-case performance no worse than prior event-driven methods, since the computations in worst-case scenarios would be equivalent. In most other cases, significant computational savings may be realized.
Consider a hypothetical set of subroutines A, B, C, D, and E, which operate to simulate the functions of a hypothetical digital circuit. Note, this example is chosen merely to illustrate a strategy for computation of subroutines, and in no way limits the type of subroutines that may be used with this simulation system. Considering the case where subroutine A (710) requires values from subroutines B (720) and E (730), as denoted by the branch lines therebetween. Likewise, subroutine B (720) requires values from two instances of subroutine C, namely C (740) and C′ (750), which in turn requires values from subroutine D (760). Depth-first execution would cause the subroutines to execute in the order: A, B, C, D, C′, E, progressing to the bottom of the subroutine chain, before beginning the next path. Such a depth-first technique may complement the advantages of the simulation techniques discussed above, ensuring values are quickly returned to the highest level of simulation.
A further performance enhancing technique that may be used with the above described simulation system and method is the technique of lazy evaluation of rule predicates. Lazy evaluation may include several strategies, one of which is minimal evaluation. In minimal evaluation, an expression is only evaluated until the point where its final value may be determined. That is, execution of an expression is abbreviated when it is not necessary to evaluate all parts of the expression to determine the final result. For example, consider a hypothetical rule predicate (a && b). If the value of a is determined to be logical false, the value of b is not needed to determine that the entire expression evaluates to logical false. Therefore a simulator practicing lazy evaluation need not run a sub-routine to evaluate the value of b in some situations. Such a computation minimizing technique may be advantageously employed to further reduce computations in the above described simulation system and method.
The foregoing has been a detailed description of a several embodiments of the present invention. Further modifications and additions can be made without departing from the invention's intended spirit and scope. It is expressly contemplated that any or all of the processes and data structures described above can be implemented in hardware, software, or a combination thereof. A software implementation may comprise a computer-readable medium containing executable program instructions for execution on a computer. It should be remembered that the above descriptions are meant to be taken only by way of example, and not to otherwise limit the scope of this invention.
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|Citing Patent
|Filing date
|Publication date
|Mar 25, 2008
|Oct 9, 2012
|Nec Laboratories America, Inc.
|Accelerating model checking via synchrony
|Dec 20, 2010
|Dec 25, 2012
|International Business Machines Corporation
|Task-based multi-process design synthesis with reproducible transforms
|Dec 20, 2010
|Mar 5, 2013
|International Business Machines Corporation
|Task-based multi-process design synthesis with notification of transform signatures
|Dec 20, 2010
|Mar 26, 2013
|International Business Machines Corporation
|Task-based multi-process design synthesis
|Mar 5, 2013
|Mar 18, 2014
|International Business Machines Corporation
|Task-based multi-process design synthesis
|Nov 10, 2014
|Jan 31, 2017
|Mentor Graphics Corporation
|Compiler for closed-loop 1�N VLSI design
|Dec 8, 2014
|Feb 28, 2017
|Synopsys, Inc.
|Dynamically loaded system-level simulation
|Nov 18, 2005
|May 24, 2007
|Huelsbergen Lorenz F
|Method and apparatus for evolution of custom machine representations
|Jun 22, 2006
|Jul 5, 2007
|Tatung Company
|Process of automatically translating a high level programming language into a hardware description language
|Mar 25, 2008
|Nov 13, 2008
|Nec Laboratories America, Inc.
|Accelerating model checking via synchrony
|Apr 29, 2009
|Nov 4, 2010
|Synopsys, Inc.
|Logic simulation and/or emulation which follows hardware semantics
|Dec 20, 2010
|Jun 21, 2012
|International Business Machines Corporation
|Task-based multi-process design synthesis with notification of transform signatures
|Nov 10, 2014
|Jun 18, 2015
|Mentor Graphics Corporation
|Compiler for closed-loop 1xn vlsi design
|Dec 8, 2014
|Aug 13, 2015
|Synopsys, Inc.
|Dynamically loaded system-level simulation
|Oct 30, 2009
|Jan 14, 2015
|Logic simulation and/or emulation which follows hardware semantics
|Apr 7, 2010
|Nov 4, 2010
|Synopsys, Inc.
|Logic simulation and/or emulation which follows hardware semantics
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|Jan 20, 2011
|Synopsys, Inc.
|Logic simulation and/or emulation which follows hardware semantics
|U.S. Classification
|716/106, 716/136
|International Classification
|Cooperative Classification
|European Classification
|Jan 31, 2005
Owner name: BLUESPEC, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STECKEL, GEOFFREY W.E.;REEL/FRAME:016242/0224
Effective date: 20050131
Owner name: BLUESPEC, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STECKEL, GEOFFREY W. E.;REEL/FRAME:016242/0206
Effective date: 20050131
|Nov 7, 2011
|Fee payment
Year of fee payment: 4
|Dec 18, 2015
|Maintenance fee reminder mailed
|May 6, 2016
|Fee payment
Year of fee payment: 8
|May 6, 2016
|Surcharge for late payment
Year of fee payment: 7


text:
- 1
How to Be So Frugal That You Spend Almost Nothing: An Extreme Approach
Are you sick and tired of spending all of your hard-earned money and ready to take an extreme approach to frugality? Here are some ridiculous tips to save some ridiculous money.
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How to Get Over a Crush You See Every Day: 5 Effective Tips
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Excuses to Not Dump a Cheater
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How to Confront a Cheater With Proof
Did you recently snoop through your partner's stuff or spy on their activities, and you found out that they're cheating? Here's what to do next when it's time to confront them.
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10 Ways That Women Drive Men Away
Are you afraid that you might be pushing your man away and not realizing it? Check out these 10 ways that you might be unconsciously making him run.
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5 Important Questions to Ask Your Boyfriend Before You Get Too Serious
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How to Get Over Rejection From Someone You Love
Whether it's an obsessive crush or just a long-time burning love that eventually came to light, getting rejected can be a heart-wrenching experience. Here's how to get over it faster.
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Are you thinking of getting into a relationship, but something in your gut is telling you to reconsider? Check out these 9 signs that your potential partner might not be the one for you.
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How to Get Over Jealousy in a Relationship: Simple Steps to Stop Obsessing
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- 3
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Things to Do While Bored and Waiting at the Airport
At the airport? Have nothing at all to do and just want to kill time? Here are some suggestions that may or may not get you into trouble: 1 - Read. Get bored and stop reading. 2 - Watch TV. Get bored and stop...
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So you have a gay friend. She's a confirmed bachelorette, a girl who likes girls, a follower of Sappho's teachings. The thing is, you get the feeling that maybe she's feeling gay about someone specific lately, and that...
- 7
Does Liking Crossdressers Make You Gay?
This subject can cause anxiety in some people, making them frantically question their sexuality because they happened to find a given woman attractive, then realized somehow that she was not physically female.
- 1
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Does someone keep coming on to you, wanting more than just your friendship, and the feeling is just not mutual? Do you feel at a loss as to what yo do?
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Why is it that some guys are just chauvinistic bastards that still, in this day and age, feel the need to disrespect women and express to the world their disdain for them? There are at least a few reasons.
- 7
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Ever wanted to make people think you're terribly smart, but don't want to go through the long, drawn-out effort of actually working on yourself intellectually? Here is the solution to your problem.
- 12
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What if you run into a guy like that, who wants nothing more than to get into your lesbian pants? What are the signs that he likes you, in spite of your declared gay tendencies?
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It seems like few people around these parts (meaning, where I live) realize that probably half the world or so sleeps on the floor. It's a legitimate decision to make--where to sleep, that is--and it's worth not just...
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Cats are actually pretty easy to understand. They like to pretend that they're more sophisticated than they really are by ignoring you and behaving in a manner that could be interpreted as pompous, but really, inside...
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5 Things Girls Might Do That Creep a Guy Out
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How to Pretend to Ignore Someone That You Have a Crush On
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Oftentimes, the small talk gets to be a bit old when we're wanting to get to the core of a person right off the bat. Generic questions tend to lead to generic, predictable responses. Mix things up a bit with this list.

subset: commoncrawl


text:
08-25-2010 #1
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ONE of the pioneers of railway travel has taken his place in transport history thanks to detective work by one of his descendants.
Edward Robinson was the world's first railway guard, supervising passengers on the Liverpool to Manchester line from 1830-1842. He later emigrated to America with his wife Mary and six children.
Now his great-great-great-grandaughter Stacy Miller has traced him to Liverpool Road station, Manchester. She contacted the Museum of Science and Industry, which stands on the site of the station, to tell them of his role in the first passenger service.
Michael Bailey, museum trustee and railway historian said: "We have objects in our collections which tell the story of the world's first railway, but it is accounts such as Edward's which help to demonstrate how the railway changed lives."


text:
|Message view
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|[Bug 120260] suggest to locate the installation files in temp folder and then remove it after installation finishes
|Fri, 13 Jul 2012 00:37:42 GMT
https://issues.apache.org/ooo/show_bug.cgi?id=120260 --- Comment #2 from louqle <email@example.com> --- The files are unpacked from the .exe file. In most cases, when I install a software, I just click Next,Next...even not notice that there is a unpacked folder located on my desktop. When I want to modify or repair it, I will find the original .exe and then double-click it again. The first time when I see the unpakced installation folder, I don't know what it is and when I placed it there... -- You are receiving this mail because: You are the assignee for the bug.
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text:
TROY BAYLISS extended his lead at the top of the World Superbike standings after winning both races at Monza.
But the fourth round of the series in Italy yesterday was frustrating for former champion James Toseland who did not complete the first race after suffering brake problems and coming off. Ten Kate Honda rider Toseland is still third in the standings but he was pipped to fourth place on the final lap in the second race by Alex Barros.
Bayliss (right) remained on course for the second title of his career after extending his lead at the summit to 36 points from defending champion Troy Corser. "It was quite hard the guys got a bit of a jump on me. But we got there," said the 37-year-old Ducati Xerox rider Bayliss, who following up his Valencia double made it four race wins in a row.


text:
welcome – my name is michael. i talk with a lot of people, read a lot of books and drink an awful lot of coffee and guinness. i really should drink more water.
after spending the past few years deconstructing and re-constructing my own theological and philosophical leanings, i've recently begun to put into practice a type of re-framing of both my faith and family narratives – appreciating the traditions i've been born into and raised in, but also discovering rebirth – finding beauty and the presence of the divine in all things – not only in my present and future interactions, but also in my past; not only in my own life or the lives of those within my own faith, but also in the lives of others in their faith traditions, or lack thereof.
the lessons of leaving behind the narratives of pride and shame i've inherited, navigating the pain of my past and the challenge of restoring what's been broken left much for me to embrace, and much for me to let go of on the WayWard path of learning to live and love like the jesus found in the gospel narratives.
i'm grateful for the friendships and communities of which i've been fortunate to be a part, and am continually in the process of learning, provoking, asking questions and challenging the status quo. i am convinced we can do better… that the 'good news' really is actually good news, for everybody.
i am part of a growing movement of individuals and organizations who are deeply compelled by and committed to the life, teachings and example of jesus. increasing numbers of us are concerned with the way his fan club has, in many ways, damaged and undone his life's work of not only proclaiming, but living out the good news of unconditional love to all people.
i am interested in seeking new ways of doing theology and living biblically; new understandings and practices of mission; new kinds of faith communities; new approaches to worship and spiritual formation; new integrations and conversations and collaborations seeking the common good for common folks – which is just common sense.
because i am rooted in a generous christian heritage, i am eager to collaborate with people of other faiths. i believe networks of dialogue and action extend beyond just self-identified christian communities to persons of all faiths, as well as to communities and neighborhoods that are not themselves faith-based.
i'm energized by engaging in conversation surrounding these ideas with my readers, and look forward to hearing about your own journeys and challenges; figuring out how we can each walk alongside one another as we together learn to love well.
for those who are looking for it, my 'official' bio is below ::
want to join the conversation? subscribe here!
interested in having me speak to your group? fill out this form.
want to participate in changing the face of christianity in north america? go here.
want to support me in this work? give here.


text:
I was willing Arsène Wenger to get through. I watched his side play Fulham last Saturday and some of the football was absolutely outstanding. They have been accused of having a bit of a soft underbelly, especially since they lost Patrick Vieira, but when Real took hold of the game in the second half they just could not break the Gunners down.
I enjoyed seeing Liverpool stage that fantastic comeback in last year's final - particularly because I watched it on holiday in a room full of Milan supporters - but while I admire Chelsea and Liverpool I don't look forward to watching them.
Arsenal are so pleasing on the eye. It is a black mark that they had no Englishmen on the pitch but I do think it is appropriate, with Chelsea and Rangers and Liverpool out, that they are the team to carry the flag for our game in the Champions' League.
They can go on and win it, too. They will not be in awe of anyone. If you can go to the Bernabeu and play like they did and come away with a 1-0 victory you can go anywhere, and those teams that avoided them in the draw for the quarter- and semi-finals will be relieved.
2. Chelsea need a Ronaldinho
There was not much between Chelsea and Barcelona. Over the two legs Chelsea had some misfortune and I can sympathise with Jose Mourinho because at that level games are decided on that sort of thing. But Ronaldinho stood out and it was only right that his goal was decisive because he was head and shoulders above anyone else.
You could never see Chelsea scoring enough goals. At the top end of the Champions' League you have to have the best, and Ronaldinho is the best. I'm sure you'll see Chelsea throw everything into getting a player in his mould this summer.
3. Sometimes honesty doesn't pay
The issue of diving keeps coming up. I would never tell a player to cheat but it leaves a bitter taste when I see a player punished for being honest, which is effectively what happened to Ade Akinbiyi when we were not given a last-minute penalty against Crewe last week. He was clearly being fouled but tried to stay on his feet. He ended up in a 50-50 situation with their keeper; if he had not been fouled it would have been 80-20 in his favour.
A penalty would probably have won us the game so what should Ade have done? We are telling players not to dive but I would say that 99 players out of 100 would go down. I'd say to Ade, "Look at it again and decide what you should or shouldn't have done," but you should not have to ask a player that.
4. One player's success gives everyone a lift
When Phil Jagielka walked into training with the Championship Player of the Year trophy he was awarded last weekend there was a burst of spontaneous applause. Phil is a level-headed lad who has been with Sheffield United since he was a kid. He plays the game as it should be played and he has a great career ahead of him. Whether we can keep him depends on where this club goes in the next couple of years. He has given the whole club a lift.
5. Even pie throwers deserve a helping hand
Our players have responded to the crisis at Rotherham by raising £2,000 in a whip-round, in addition to the £9,000 the club passed on from the television beam-back of our derby against Sheffield Wednesday. We've also allowed them to keep two of our players on loan without charge.
I used to play for Rotherham and I think they are a lovely club, even though I get pies thrown at me when I go back to Millmoor. Hopefully, now I've done my bit, I can at least expect them to be warm and with plenty of gravy.
- More about:
- Arsenal
- Chelsea F.c.
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- Jose Mourinho
- Liverpool FC
- Manchester City
- Patrick Vieira
- Premier League
- Ronaldinho


text:
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The Gate Islington, award-profitable restaurant and younger sibling of our initial task The Gate Hammersmith, was originally opened to maintain us occupied whilst we re-made our first website in Hammersmith in time for its twenty fifth birthday celebrations.
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NOPI's menu improvements in accordance with the seasons but signature dishes by Ramael Scully involve courgette and manouri fritters, coriander seed-crusted burrata with slices of blood orange and 2 times-cooked baby chicken with lemon myrtle salt and chilli jam. NOPI serves breakfast, lunch, pre-theatre and dinner menus.
There's a desk in the back of our Notting Hill branch which seats 10 people today but food items and pastries are normally bought to take-absent listed here. We don't consider reservations and, unfortunately, would not have a buyer toilet. The day by day menu is printed and might be emailed from 11am so you're able to contact Luana, our supervisor, for the check here copy.
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Google Chrome is a freeware web browser developed by Google that uses the WebKit layout engine (later versions will use Blink, a fork of WebKit). It was released as a beta version for Microsoft Windows on September 2, 2008, and as a stable public release on December 11, 2008. As of February 2013, according to StatCounter, Google Chrome has a 37% worldwide usage share of web browsers making it the most widely used web browser in the world.
Home » Vocabulary » Thing » Google Chrome
About Denver Prophit Jr.
Co-Founder of StrikeHawk eCommerce, Inc. Whose mission is to provide commercial open source e-Commerce through various popular open source projects such as osCommerce, Zen-Cart and others.
I invite you to collaborate with me through the blog's comment system and via social networks listed on the blog.


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by Beaba
Order now to get it by: Saturday May 13 - Monday May 15
Get it on Sunday May 7th with expedited shipping.
Select the expedited delivery option after adding this item to your cart.
Condition: New
Product ID: 673597
Delivery Information |Returns & Exchanges |Payment Methods
A patented compact countertop appliance that functions as a steamer, blender, warmer and defroster to prepare fresh,
healthy meals for baby. Quickly steam cook vegetables, fruits and meats in 15 minutes or less, while preserving their
vitamins and flavors. Puree and blend food to the desired consistency making it super smooth, chunky or anywhere in
between for baby. Clean up is quick and easy with a top-rack dishwasher safe bowl and basket. Comes with a spatula and
recipe booklet.


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- Description
DetailsCaptivating flavours of green apple and tropical fruit enhance an upfront floral bouquet in this medium-bodied golden wine. It will develop to reveal layers of ripe fruit and integrated oak.
- Details & Instructions
Additional Information
Type White Origin California Body Medium Sweetness Dry Oak Intensity Medium
- Reviews
- Customer Q&A
Browse 2 questions Browse 2 questions and 3 answersHow many gallons does the kit make?Does this product contain everything needed to make wine?BEST ANSWER: Thanks for the inquiry! This wine recipe kit contains the juice, additives, and yeast needed, so is all the ingredients. If you look up the instructions as a pdf, it will indicate the equipment required. Our Master Vintner kit featuring big mouth bubbler has everything needed to make the wine, then you also need bottles. I hope this helps!
- Reply
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Southern Ontario's Premier Skydiving Facility
Driving Directions to Skydive Burnaby from Toronto or along QEW
On this page there are a number of easy options to get directions to the Skydive Burnaby DropZone.
• Option #1- For driving directions to Skydive Burnaby from Toronto, and the GTA enter your address here. A new window will open with complete printable directions from you to Skydive Burnaby.
Enter your location - ( Street, City, Province or State.)
• Option #2 - is to use the available directions just beneath this text. Included here are simple driving directions from Toronto or anywhere along the QEW, complete with Downloadable PDF Files.
• Option #3 - Enter this information into your favourite map generator:
Address: 11631 Burnaby Rd. Wainfleet On. Postal Code: L0S 1V0 (L-Zero-S-One-V-Zero)
Directions From Toronto / QEW
• Take the QEW towards Niagara
• Take Exit 57, Victoria Avenue (HWY 24)
• Follow Victoria South for 20-25 minutes
• The road will end at HWY 3, make a left
• Make your first right at Burnaby Road
• We're on the left about 1km down the road
These directions are useful if you're driving to the Skydive Burnaby skydiving center from anywhere in Toronto, the GTA, Mississauga, Oakville, Burlington, Hamilton, Stoney Creek, Grimsby or anywhere along the QEW, Gardiner Expressway, Highway 400 and 401.
We also encourage you to download the
Toronto Directions PDF
Learn To Skydive Here
Social Media & Links


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Siemens Expert
This project was successfully completed by xarisx for $30 USD in 5 days.Get free quotes for a project like this
Project Budget$30 - $250 USD
Completed In5 days
Total Bids7
Project Description
We are requiring a program to be made on a Siemens PLC, with Step 7 version 5.5.
The program manages 4 movements of an equipment, also it has the ability to block or unblock each equipment for movements purposes. It will communicate with a SCADA made by us. The specific work is:
1. PLC program specification, discussion with PLC & SCADA programmers, in order to clarify all integration issues.
2. PLC program logical diagrams design.
3. PLC program implementation.
4. PLC program test & support during tests in office.
Completed by:
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Peterson Whiffs 20
Oregon's David Peterson pitched one of the best games of the season Friday
Oregon's David Peterson pitched one of the best games of the season Friday
Three teams, including Maryland, move into the Top 25 this week.
Three SEC series will have a big impact on division races
The latest projected NCAA regional field from our experts
West Virginia, Texas A&M and Houston move into the rankings and UNC moves up
The Beavers stay atop the heap, with three teams moving in
Teddy and Mike each break down three of the biggest college storylines
Our latest projections for the NCAA field of 64
Jason Dietrich has already made a quantifiable impact on the Oregon staff
Oregon, Michigan and Connecticut enter the Top 25 this week
The top six teams stay in place while three teams move in
Luke Heimlich and the Beavers are our projected No. 1 seed
John Savage believes the U.S.'s WBC win will impact all of Team USA's programs
Baseball America's recruiting class rankings, compiled by Teddy Cahill
CROP RATING Solid, not spectacular Rating compares this year's group to wh[...]
Several stadiums split schedule between college, pro teams
Matt Krook has struggled to pitch with confidence this season
Creighton one of four teams to enter the rankings this week
Oregon tops Oregon State; big wins for Louisiana Tech, Alabama State
Minnesota moves into the Top 25 for the first time since 2009.
The Gators are back on top, with six teams entering the rankings.
Three teams enter the rankings, including Michigan State
Miami remains No. 1; Michigan State, Louisiana-Lafayette, Coastal Carolina move [...]
Keep track of all the Top 25 movement, including NC State re-entering the rankin[...]


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As January comes to a close, and a new year of doll discoveries awaits us, let's take a gander at what some well-known people have said about doll creations. With the Oscar nominations hitting this week, and presidential news conferences taking center-stage, it's fun to see which stars have chatted about being collectible, in both a dignified and charming manner, and in a bold and boisterous way.
Photos courtesy of Lady With a Past
In addition to being a first-rate doll artist and historical researcher, Theresa Merritt is a born conversationalist. Probably because she loves history so much, she is gifted with the ability to share stories of her life, her ambitions, her dreams, and her accomplishments. Theresa doesn't just answer a question; she weaves a tapestry of intrigue and excitement.
Photos courtesy of Southern Angels Nursery
While the new year is still in its infancy — I have to confess, I am having a hard time writing "2017," it doesn't seem possible — my focus for this week is understandably on babies. Yes, I am highlighting the little faces and wiggly toes that make the world that much sweeter and enjoyable. It makes sense to celebrate baby dolls in January because of the "New Year Baby." Does anyone out there know what I'm talking about, or has this onetime popular icon gone the way of the Discman, the Walkman, and the transistor radio? (Try wearing a Walkman or a Discman while you jog or speed-walk around town. You might as well be dressed in a Paul Revere costume — that's how antiquated the headgear has become!)
Photos Courtesy of Linndolls
The year 2017 is beginning, and the aspect of a brand-new, clean-slate existence is certainly appealing. Everyone has baggage that they've overstuffed with regrets, missed opportunities, poorly chosen words, and roads not taken. For some people, this emotional baggage is a simple carry-on-luggage–sized worry; for others, it is a lifetime of not being sure that the right choices had been made; perhaps their path took a wrong turn and the road just kept wending away from them.
When I look back at what I've chronicled for the aptly named Doll Chronicles, I have to declare that 2016 was the Year of the Real Woman. Now, in the doll industry, that shouldn't be such an earth-shaking proclamation. After all, the majority of doll artists are female; the overwhelming abundance of doll creations are female; and the consumer base is very much female-centric. Like Beyoncé has sung, who rules the world? In the doll world, it has always been girls. And I guess that is why the Year of the Real Woman is so definitely different. From dolls that represented women who — God forbid — wore a size 12 to a headstrong, capable 12-year-old Disney princess, the world of dolls was given a much-needed makeover. This year many girl dolls became young women.
As the countdown to December 25 continues — it's less than a half week away . . . Yikes! — it's tempting to shed one's equanimity, isn't it? In other less sophisticated terms, it's easy to lose one's cool. Funny, when living in the Northeast, Northwest, or the Midwest, when temperatures are dipping down as far as they can go, emotions often spike higher and higher. People at the mall can be reaching boiling points when it comes to waiting one more minute on line. Folks who are taking the easier route — doing all their browsing and buying online — can feel their passions bubbling over when UPS or FedEx loses or misdelivers an item. Ah, the unexpected "joys" of Christmas shopping.
The holidays are the best time for doll aficionados, don't you agree? Whereas all year round, one might be met by suspicious or quizzical looks when a doll reference is dropped — "You mean, you STILL PLAY with dolls?" — during the Christmas season, tolerance reigns supreme. Since December 25 is a day when adults often indulge their childlike wonder and excitement — getting and giving oversized plush-animal slippers, comically decorated PJs, socks with emojis emblazoned on them — the request-and-receipt of a doll is greeted with seasonal understanding. Any quirky gift can fit snugly in a stocking, so all is right with the world!
Photos courtesy of Bo Bergemann
I was so happy today to receive an e-mail from Bo Bergemann, an artist who is often associated with tropical climes and swaying palm trees. Even though paradise-like locales and temperate breezes pop into my mind when I think of Bo, she's also extremely connected to Christmas and all things "merry and bright." If Santa's elves learned to master the hula dance, and traded in hot cocoa for coconut juice, Bo's dolls would be right at home at the North Pole. (Or, more likely, the re-named Very Hot and Sultry Sunny South Pole!) Though most of her dolls have an "Ariel, the Little Mermaid" vibe, she is quite adept at coaxing out her inner Olaf, the jolly snowman from "Frozen."
Photos courtesy of Plusczok Puppen
Thanksgiving week was a rollicking and frolicking one for me. In addition to my own children, I invited my little niece and nephew to come back home with us after Turkey Day, where we pretty much destroyed the myth that tryptophan makes you tired. (That's the amino acid that is found in turkey and supposedly accounts for Uncle Joe immediately snoozing after the last drumstick is devoured.)
Photos courtesy of Amy van Boxel
Now that we are officially in the upswing of the holiday season — radio stations are sprinkling Christmas tunes into their playlists — we all have certain songs that we look forward to hearing more than others. I admit I like all the old familiar standards — the Nat King Cole, Frank Sinatra, Peggy Lee, and Doris Day crooners can make me tear up as I listen to them crisply enunciate the themes. (The lyrics from "Have Yourself a Merry Little Christmas" particularly slay me: "Through the years, we all will be together — if the Fates allow . . . ") It's a rare Noel opus that talks so beautifully and poignantly about future celebrations where revelers may no longer be around to attend. It makes you appreciate every day with one another, doesn't it?


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"Maarten Bavinck has replaced Marja Spierenburg as director of CERES as of November 1st, 2016. Maarten Bavinck has been on the CERES board since 2012, and serves as professor at the University of Amsterdam as well as at UiT The Arctic University of Norway. His research centres on the governance of human activity in coastal and marine zones, with an emphasis on South Asia. More details on his experience and interests can be found at: http://www.uva.nl/over-de-uva/organisatie/medewerkers/content/b/a/j.m.bavinck/j.m.bavinck.html
Marja Spierenburg has accepted a position as full professor in development studies at Radboud University (see http://www.ru.nl/caos/vm/spierenburg/). Her farewell to CERES is reproduced below:"
Between January 2013 and July 2016 I had the pleasure of serving as Scientific Director of CERES. I truly enjoyed working with the Board, the members and the Bureau. These were challenging times, with many of our members experiencing pressure to join local graduate schools, and general support for national research schools dwindling. Nevertheless, we managed to continue with CERES, albeit in a slightly different form, without the Working Programmes. With support from the members, and building on the hard work of my predecessors, we continued to improve the PhD training programme. Thanks to a dedicated team of core trainers, the programme continues to receive positive evaluations and still attracts many PhD-students. We organized a number of additional activities, including some memorable Summer Schools/Annual Conferences and quite recently, a seminar on the politics of research valorization and a panel at the SDG-conference in Amsterdam. I am grateful to the members of the Board, the Bureau and the individual members who supported me and contributed to the training and the organization of the activities.
On the 1st of August I joined the Radboud University, to take up the Chair in Development Studies. This is a full-time position, which would have been difficult to combine with the work for CERES. It was with sadness that I gave up my position with CERES. However, I am confident that my successor Prof. dr. Maarten Baavinck will take excellent care of CERES and will develop some new ideas for the future. Maarten will start officially on the 1st of November, but of course he has been involved in CERES before, as a dedicated member of the Board. I am looking forward to the activities that he no doubt will organize, and will do my utmost best to participate in and contribute to these. Maarten, I wish you the best of luck in your new position, and hope you will enjoy it as much as I did!


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Getting in shape is as fun as you want to make it. Some people love jogging to stay fit, some prefer hitting up the gym every day to try and gain those muscles. However there is one type of exercise that is underrated and not discussed in many circles and it is rowing. Whilst this may not sound like a very practical exercise if you don't live near a lake or river, you can get an indoor rowing machine to substitute for the real thing and it can provide you with one of the best workouts you could ask for. Today in this review we are going to be taking a look at one in particular, the Sunny Health and Fitness SF0RW5515, and seeing just how good it really is. If you want to take a look at other rowing machines whilst you are at it, then why not pay Home Rower a visit and do just that!
Tell me about the features
This is no ordinary rowing machine as it incorporates some different technologies in an attempt to make your whole experience more efficient and better for you. The first and most important of these technologies is the magnetic tension system with 8 different levels of resistance. This makes things that little bit tougher when compared to a regular indoor rowing machine! The second impressive feature on show with the Sunny is the large LCD console which displays time, count, calories, and the total count of the distance you've travelled. The seat is fully padded and the handlebars have been made non-slip for added comfort. Also worth a quick mention are the anti-slip foot pedals.
What are the good points?
This machine has been designed to work for most people and the maximum weight allowed on it is 250 lbs. It has wheels built in so that it can be transported from room to room easily, and the padding on the seat is something you will notice after the first use. The technology inside the machine, not only in the LCD screen but also in the magnetic tension system, will ensure that you get the best possible workout in the least possible time.
What are the bad points?
It is something that very rarely happens in today's world, but customers have not managed to find one complaint about the Sunny throughout their use of the machine. This is a very impressive fact as pieces of exercise equipment like this are more often than not pushed to their limits and used almost every day, so for it not to have any faults as of yet is very impressive!
This rowing machine is very close to perfect. It has more technology and should give you a better workout than most of its competitors within a similar quality band, and it does all this whilst being very user friendly and intuitive. If you want a simple yet efficient addition to your home gym then the Sunny Health and Fitness rower is a good place to start.


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|Exam Name:
|Check Point Certified Security Master
|Exam Code:
|Total Questions:
|350 Q&As
|Last Updated:
|Note: We Will send Email Of PDF Within 8 hours after Payment Successfully .
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