text:
|Publication number
|Publication type
|Application number
|Publication date
|May 13, 2008
|Filing date
|Jun 21, 2005
|Priority date
|Jun 21, 2005
|Fee status
|Also published as
|Publication number
|Paul Burkley, Prashant Chandra
|Original Assignee
|Intel Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Referenced by (3), Classifications (11), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
The field of invention relates generally to computer and telecommunications networks and, more specifically but not exclusively relates to methods for optimizing memory unit usage to maximize packet throughput for a multiprocessor multithreaded architecture.
Network devices, such as switches and routers, are designed to forward network traffic, in the form of packets, at high line rates. One of the most important considerations for handling network traffic is packet throughput. To accomplish this, special-purpose processors known as network processors have been developed to efficiently process very large numbers of packets per second. In order to process a packet, the network processor (and/or network equipment employing the network processor) needs to extract data from the packet header indicating the destination of the packet, class of service, etc., store the payload data in memory, perform packet classification and queuing operations, determine the next hop for the packet, select an appropriate network port via which to forward the packet, etc. These operations are generally referred to as "packet processing" operations.
Modern network processors (also commonly referred to as network processor units (NPUs)) perform packet processing using multiple multi-threaded processing elements (e.g., processing cores) (referred to as microengines or compute engines in network processors manufactured by Intel� Corporation, Santa Clara, Calif.), wherein each thread performs a specific task or set of tasks in a pipelined architecture. During packet processing, numerous accesses are performed to move data between various shared resources coupled to and/or provided by a network processor. For example, network processors commonly store packet metadata and the like in static random access memory (SRAM) stores, while storing packets (or packet payload data) in dynamic random access memory (DRAM)-based stores. In addition, a network processor may be coupled to switch fabrics, cryptographic processors, hash units, general-purpose processors, and expansion buses, such as the PCI (peripheral component interconnect) and PCI Express bus.
Network processors are often configured to perform processing in a collaborative manner, such as via a pipelined processing scheme. Typically, different threads perform different portions of the same task or related tasks, with the output of one thread being employed as an input to the next thread. The threads are specifically tailored for a particular task or set of tasks, such as packet forwarding, packet classification, etc. This type of scheme enables packet-processing operations to be carried out at line rates for most packets, also referred to as "fast path" operations.
In general, the foregoing packet processing operations require multiple memory accesses to one or more memory units. As a result, packet throughput is inherently related to memory (access) latencies. Ideally, all memory accesses would be via the fastest scheme possible. For example, modern on-chip (i.e., on the processor die) static random access memory (SRAM) provides access speeds of 10 nanoseconds or less. However, this type of memory is very expensive (in terms of chip real estate and chip yield), so the amount of on-chip SRAM memory on an NPU (e.g., scratch memory) is typically very small.
The next fastest type of memory is off-chip SRAM. Since this memory is off-chip, it requires a special interface (e.g., bus) to access it, adding a level of latency to the memory access. However, it still has relatively-low latency.
Typically, various types of off-chip dynamic RAM (DRAM) are employed for use as "bulk" memory units. Dynamic RAM is slower than static RAM (due to physical differences in the design and operation of DRAM and SRAM cells), and must be refreshed every few clock cycles, taking up additional overhead. As before, since it is off-chip, it also requires a special bus to access it. In most of today's network processor designs, DRAM memory stores with enhanced performance are employed, including RDRAM (Rambus DRAM) or DDR DRAM (double data rate), RLDRAM (reduced latency RAM) etc. via dedicated signals. As used herein, a memory unit comprises one or more memory storage devices having associated memory spaces.
An application designer faces the challenging task of utilizing the memory units available to an NPU in such a fashion as to ensure that a minimum amount of latency is incurred during packet processing operations, in order to maximize the packet throughput. Currently, memory unit utilization is done on a trial and error or educated guess basis in consideration of projected traffic patterns and service levels to be provided by the network element in which one or more NPU's are installed. This produces inefficient memory utilization, reducing packet throughput.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:
Embodiments of methods and software for optimizing memory unit usage to maximize packet throughput for multi-processor multi-threaded architectures are described herein. In the following description, numerous specific details are set forth, such as implementations using Intel's� NPUs, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In accordance with aspects of the embodiments disclosed herein, techniques are provided for optimizing memory unit usage to maximize performance levels. While the following examples pertain to NPU architecture implementations in particular, the general principles and teachings of the techniques may be employed in other architectures and systems as well.
This specification describes an algorithm to find an optimal use of a network processor's memory units, given the availability of a dynamic simulator capable of simulating a given application on the network processor (and/or environment in which the NPU is deployed). For purposes of the algorithm, the use of memory units is put in terms of data structures and data structure accesses. Data structures have a defined size, while memory units have a defined (storage) capacity. During packet processing, data structures may be accessed, either written to or read from. The actual commands used to access the data structures will incur pre-determined latency penalties as dictated by the specifications of the relevant memory unit types (e.g., scratch memory, off-chip SRAM, off-chip DRAM, etc.) The size of the data structure accesses will tax the buses connecting the issuing processing engines to the relevant memory units. These buses have a defined bandwidth that limits the maximum achievable data transfer rate.
The algorithm described herein iteratively allocates data structures to memory units in search of an allocation that maximizes packet throughput. Two constraints exist when allocating data structures to memory units:
The memory capacity constraint exists because only so many data structures may be allocated to a memory unit before it becomes full. The memory bus bandwidth constraint exists because if and when a bus becomes over-loaded, the latency of accesses to the memory unit grow exponentially and packet throughput is ultimately degraded. It is noted that headroom may be factored into the algorithm if desired, by down-grading the available capacity and/or bandwidth before commencing the search for an optimal solution.
Once data structures have been allocated in such a way as to satisfy the capacity and bandwidth constraints, the packet throughput is measured and assessed in view of the dynamic simulation. Different allocations may be tried in order to find the one that maximizes packet throughput. In one embodiment, this entire process is automated via execution of a software tool on a computer system.
Satisfying Capacity and Bandwidth Constraints
The algorithm works by iteratively allocating data structures to memory units and assessing the constraints after each individual allocation. As soon as the constraints are no longer satisfied, the current allocation is undone and the next possibility tried. This indicates that there isn't sufficient bandwidth and/or capacity for the current allocation. After one data structure is successfully allocated to a memory unit, the next data structure is allocated, and so on until all data structures are eventually allocated. In general, more than one successful allocation may exist; however, in one embodiment, the first successful allocation that is found is returned by the algorithm. As described below, this initial allocation may be modified, if necessary, to identify an optimum allocation.
Allocation here simply means subtracting the data structure's resource usage from the memory unit's resource availability. For capacity this will be in bytes, while for bus bandwidth this will be in bytes/second. Prior to commencing the search, a data structure's size and bandwidth usage are defined or determined. Similarly, a memory unit's size and bandwidth availability are also defined or determined. The bandwidth data can be derived from a dynamic simulation engine that simulates the data structure accesses on the network processor and assesses the loading on the buses.
In one embodiment, the data structures are ordered in terms of highest resource usage to lowest resource usage. Resource usage here refers to both capacity and bandwidth usage. The biggest (capacity) and most accessed (bandwidth) data structures are considered first, while the smallest (capacity) and least accessed (bandwidth) are considered last. In this way, the algorithm attempts to pack the biggest pieces into the available space first, before proceeding to the smaller pieces. This optimizes the search for the optimal allocation by pruning futile paths from the search tree.
The memory units being allocated to are ordered in terms of lowest latency to highest latency. Latency here is relative and is not measured as an absolute, just a relative ranking to compare memory units to each other. For example, scratch memory will be considered to have lower latency than off-chip SRAM, which in turn will be considered to have lower latency than off-chip DRAM. In this way the algorithm will try to allocate data structures first to lower latency memory units, and only if they don't fit then to higher latency memory units. This helps to find a solution likely to yield a high packet throughput, by minimizing the latency associated with accesses to the data structures.
One embodiment of the allocation algorithm body is described in pseudo-code as shown in
Another initialization operation is performed in a block 202, wherein a list of data structures is initialized. A data structure table 310 containing an exemplary list of data structures including four entries is shown in
After the initialization operations of blocks 200 and 202 have been performed, iteration through the main loops of the algorithm are commenced. This includes iteration through the data structures as depicted by an outer loop defined by start and end loop blocks 204 and 218, and iteration through the memory units as depicted by an inner loop defined by start and end loop blocks 208 and 216.
The outer loop begins with the current data structure index set to 0. Accordingly, the current data structure entry DS0 (e.g., having an index of 0) is retrieved from data structure table 310 in a block 208. Next, iteration of the inner loop is performed, beginning with the first memory unit (e.g., memory unit MU0) of memory unit table 300. In a block 210, the current data structure is allocated to the current memory unit. Then, in a decision block 212, a determination is made to whether both the capacity and bandwidth constraints are met. In view of this first iteration, a data structure DS0 having a size of 256 KB and a bandwidth of 4.0 MB/s is allocated to a memory unit MU0 having a size of 32 KB and a bandwidth of 2.0 MB/s. Thus, neither of the constraints are met, since the size of data structure DS0 is larger than the size of memory unit MU0, while the bandwidth usage of data structure DS0 is greater than the bandwidth availability for memory unit MU0. This result is depicted in the first row of an iteration result table 320 shown in
During the second iteration of the inner loop, data structure DS0 is allocated to memory unit MU1 in block 210. As before, the answer to decision block 212 is NO, since the size of memory unit MU1 is too small, causing unallocation of data structure DS0 to memory unit MU1 in block 214. The memory unit index is again incremented by 1 in end loop block 216, returning the logic to start loop block 208 for the next iteration.
During this third iteration of the inner loop, data structure DS0 is allocated to memory unit MU2 in block 210. This time, both the capacity and bandwidth constraints are met, and the answer to decision block 212 is YES. The causes the logic to jump to end loop block 218, wherein the data structure index is incremented by 1. The logic then loops back to start loop block 204, with the entry data for the second data structure DS1 in data structure table 310 being retrieved in block 206. This data structure is then allocated and unallocated (as necessary) in the iterative fashion described above for allocating the first data structure DS0 to a memory unit until both the capacity and bandwidth constraints are met. This allocation process is then repeated until all data structures have been allocated to corresponding memory units will satisfying the capacity and bandwidth constraints.
When a data structure is allocated to a memory unit, the resource usage required for the data structure must be accounted for. Accordingly, the available (i.e., remaining) capacity of the memory unit is reduced by the size of the data structure, while the available (remaining) bandwidth is reduced by the size of the bandwidth usage for the data structure. Meanwhile, when a data structure is unallocated to a memory unit, the available capacity of the memory unit is increased by the size of the data structure, and the available bandwidth is increased by the bandwidth usage for the data structure, restoring the available capacity and bandwidth for the memory unit to their respective values prior to allocation of the data structure.
As a result, during the fourth iteration, data structure DS1, which has a size of 24 KB is allocated to memory unit MU0, which reduces the available capacity of memory unit MU0 from 32 KB to 8 KB, and the available bandwidth from 2.0 MB/s to 0 MB/s. During the fifth iteration, an attempt to allocate data structure DS2 to memory unit MU0 is made. However, this attempt fails, since the (now) available size and bandwidth of memory unit MU0 are insufficient to met the corresponding size and bandwidth usage of data structure DS2. Thus, during the following sixth iteration, data structure DS2 is allocated to memory unit MU1, with the available capacity of memory unit MU1 being reduced by 16 KB to 48 KB, and its available bandwidth being reduced from 4.0 to 1.0 MB/s.
The iterative allocation sequence is continued until the memory and bandwidth constraints are met for the allocation of the final data structure DS3 in the data structure list of data structure table 310. Under the illustrated example, this allocation is made during an eighth iteration with data structure DS3 being allocated to memory unit MU1. At this point, all of the constraints are met and all of the data structures are allocated to a memory unit, completing the allocation of data structures portion of the algorithm.
In case a solution with all the data structures allocated can't be found, the maximum number of data structures allocated can optionally be recorded. The solution with the maximum number of data structures allocated is deemed the best solution.
In one embodiment, in addition to allocating data structures to lower latency ranking memory units before higher latency ranking memory units, the algorithm will attempt to allocate data structures to memory units of the same latency in a round-robin fashion. This will help to achieve more balanced allocations in the case that the constraints are easily met. For example, instead of filling SRAM channel 0 to capacity before starting to fill SRAM channel 1, data structures should be allocated to each channel in turn when searching for a solution. Note this won't inhibit finding a solution if only one, or a handful, of solutions exists. The same solution search takes place, but in a slightly modified order.
It may be desirable to exclude certain data structures from the allocation algorithm, i.e. to lock them down in their current location to prevent them from being moved. The search algorithm can treat such locked down data structures specially, by automatically allocating them to their respective memory units at the beginning of the search, to account for their resource usage. This will help optimize the search process.
The allocation algorithm also needs to consider the validity of moving a data structure to a given memory unit. Each data structure may be accessed by different commands. When considering moving a data structure to a memory unit, the commands used to access the data structure need to be supported by the new memory unit. If they aren't supported, the move is invalid and will not be considered. This further restricts the set of possible solutions, and helps to further optimize the allocation process.
Maximizing Packet Throughput
Once memory bandwidth and capacity constraints are satisfied, the next stage in the algorithm is to maximize the packet throughput. Because of the complex nature of multi-processor, multi-threaded architectures, it's not practical to statically calculate the packet throughput for a given allocation of data structures to memory units. Instead, a dynamic simulator is employed to accurately simulate the processing of packets for a given allocation. This simulation is used to determine the packet throughput for the allocation, and should simulate a sufficient number of processor cycles such that an average packet throughput rate can be accurately extrapolated.
At this point (after the foregoing allocation process has been implemented), an allocation has been found that satisfies bandwidth and capacity constraints, and that allocation will tend to have the more frequently accessed data structures in the lower latency memory units due to the ordering discussed previously. This makes the allocation a very good starting point from which to improve upon. Note if no allocation has been found up until this point then there is no point in continuing further and the algorithm aborts.
The way this second phase of the overall algorithm improves packet throughput is by reallocating data structures to lower latency memory units than those in which they currently reside (as identified by the first phase of the algorithm). To maximize packet throughput by allocating data structures to memory units, each data structure is considered in turn. The current data structure is restricted to progressively lower latency memory units and with each restriction imposed, a solution is searched for that satisfies the capacity and bandwidth constraints, while respecting the latency restriction. This requires the addition of some logic to the part of the algorithm described previously, whereby before allocating a data structure to a memory unit, any latency restriction imposed on the data structure must be met by the memory unit, otherwise the allocation is skipped and the search continues.
The algorithm first searches for solutions with the current data structure free from any latency restrictions, and then with the data structure progressively restricted to lower latency channels. If an allocation is found with a data structure restricted, then further allocations are searched for with the remaining data structures restricted. This search will find all allocations that meet the original capacity and bandwidth constraints, and that also have some latency restrictions imposed on the data structures. Note one of the allocations tried will be that with no data structures restricted, and this will yield the original allocation found. Further allocations that are found will have one or more data structures restricted to lower latency memory units than those in which they originally resided, and this may result in an improvement in packet throughput. The packet throughput of each allocation found is calculated by the simulation engine, and the allocation that yields the best packet throughput is recorded.
Pseudo-code for one embodiment of the algorithm body for this second optimization phase is shown in
After the initialization operation of block 500, operations contained within an outer loop defined by start and end loop blocks 502 and 532 are iteratively performed. Another loop that iterates over the data structures is depicted by a start loop block 504 and end loop block 522, beginning with the first data structure DS0. In a block 506, data corresponding to the current data structure is retrieved (e.g., for DS0). The relative latency rank of the memory unit to which the current data structure is currently allocated is then retrieved in a block 508. As shown in data structure table 600 and the first iteration row in an iteration result table 610 of
Next, the first operation of another loop that partially overlaps the data structure loop is performed, as shown by a start loop block 510. This loop begins with the current relative latency value for the current data structure and is decremented by 1 with each loop as depicted by an end loop block 528. In a decision block 512, the current value of the latency rank loop is compared with the latency rank for the current data structure. If the loop of the latency rank is >= than the memory unit latency rank (i.e., the latency rank of the memory unit to which the current data structure is allocated), the logic proceeds to end loop block 524, wherein the data structure index is incremented by 1, and the logic loops back to start loop block 504 to begin evaluation of the next data structure (e.g., DS1).
If the result of decision block 512 is YES for one of these iterations, the logic is branched to a block 514 in which a maximum latency restriction is imposed for the data structure. The algorithm of
It is noted that the logic of this loop is implemented such that a single change in the combination of data structure allocations is made (relative to a previously-tried combination) for each iteration, rather than multiple changes at a time. An exemplary set of updated allocations are shown in a DS0 max column 614, DS1 max column 616, DS2 max column 618, and DS3 max column 620 in the iteration result table 610.
After a reallocation to the data structure allocation is made (via a corresponding maximum latency restriction being applied to at least one of the data structures), the simulator engine is run for that allocation in block 524. If the packet throughput is increased, data pertaining to the reallocated data structures is stored as the best allocation in block 526. If the packet throughput is not increased, the best allocation remains the same as existed at the end of the previous iteration.
The operations and logic contained within the outer loop are continued on an iterative basis until either all of the combinations have been tried, or the process aborts. At this point, the allocation stored in the best allocation table is deemed the optimum allocation for the particular environment being simulated.
Exemplary allocations and throughput values are shown in the iterative result table 610. During the first iteration, none of the allocations are changed. This corresponds to the original allocation shown in
During the third iteration, the maximum latency for data structure DS2 is set to low, while the prior restriction on data structure DS3 is removed. This also results in a possible allocation, and the corresponding simulation shows a packet throughput of 1,050,000. During the fourth iteration, a maximum latency restriction of low is imposed on both of data structures DS2 and DS3, which results in yet another possible allocation. In this instance, simulation shows a packet throughput rate of 1,125,000. As illustrated by this result, implementing an allocation that includes a combination of allocations that provided corresponding improvements individually will usually not yield an overall improvement that is the sum of the individual improvements.
Finally, during the fifth iteration, a maximum latency of medium is imposed on data structure DS0. However, since the size of data structure DS0 (256 KB) is larger than the combination of the capacity for all memory units that provide at least a medium latency or better (32+64=96 KB for the combination of memory units MU0 and MU1), this allocation is not possible, and the process aborts. Accordingly, no further improvement is possible, and thus the allocation corresponding to iteration 4 is deemed the best.
Exemplary Simulation Environment
Network processor 701 includes n microengines 702. In one embodiment, n=8, while in other embodiment n=16, 24, or 32. Other numbers of microengines 702 may also me used. In the illustrated embodiment, 16 microengines 702 are shown grouped into two clusters of 8 microengines, including an ME cluster 0 and an ME cluster 1.
In the illustrated embodiment, each microengine 702 executes instructions (microcode) that are stored in a local control store 708 using multiple hardware threads. Included among the instructions are data structure to memory unit allocation instructions 710 that initialize and manage the use of various memory units in accordance with the data structure/memory unit allocation employed for a given simulation.
Each of microengines 702 is connected to other network processor components via sets of bus and control lines referred to as the processor "chassis". For clarity and simplicity, these bus sets and control lines are depicted as an internal interconnect 712. Also connected to the internal interconnect are an SRAM controller 714, a DRAM controller 716, a general purpose processor 718, a media switch fabric interface 720, a PCI (peripheral component interconnect) controller 721, scratch memory 722, and a hash unit 723. Other components not shown that may be provided by network processor 700 include, but are not limited to, encryption units, a CAP (Control Status Register Access Proxy) unit, and a performance monitor.
The SRAM controller 714 is used to access an external SRAM store 724 via an SRAM interface 726. Similarly, DRAM controller 716 is used to access an external DRAM store 728 via a DRAM interface 730. In one embodiment, DRAM store 728 employs DDR (double data rate) DRAM. In other embodiment DRAM store may employ Rambus DRAM (RDRAM) or reduced-latency DRAM (RLDRAM).
In the context of the foregoing description, each of SRAM store 724 and DRAM store 728 may be deployed as one or more memory units of a corresponding latency type. For example, SRAM controller 714 may be a multi-channel controller, with each channel used for accessing a respective bank of memory in SRAM store 724. Accordingly, each bank of SRAM memory could comprise a separate memory unit with a latency type=SRAM off-chip (or latency=medium under the foregoing algorithm). Similarly, scratch memory 722 may be deployed as one or more memory units with a corresponding latency type.
General-purpose processor 718 may be employed for various network processor operations. In one embodiment, control plane operations are facilitated by software executing on general-purpose processor 718, while data plane (e.g., fast-path) operations are primarily facilitated by instruction threads executing on microengines 700.
Media switch fabric interface 720 is used to interface with the media switch fabric for the network element in which the line card is installed. In one embodiment, media switch fabric interface 720 employs a System Packet Level Interface 4 Phase 2 (SPI4-2) interface 732. In general, the actual switch fabric may be hosted by one or more separate line cards, or may be built into the chassis backplane. Both of these configurations are illustrated by switch fabric 734.
PCI controller 722 enables the network processor to interface with one or more PCI devices that are coupled to backplane interface 704 via a PCI interface 736. In one embodiment, PCI interface 736 comprises a PCI Express interface.
During initialization, coded instructions (e.g., microcode) to facilitate various packet-processing functions and operations are loaded into control stores 708. Data structure to memory unit allocation instructions 710 are also loaded at this time. In one embodiment, the instructions are loaded from a non-volatile store 738 hosted by line card 702, such as a flash memory device. Other examples of non-volatile stores include read-only memories (ROMs), programmable ROMs (PROMs), and electronically erasable PROMs (EEPROMs). In one embodiment, non-volatile store 738 is accessed by general-purpose processor 718 via an interface 740. In another embodiment, non-volatile store 738 may be accessed via an interface (not shown) coupled to internal interconnect 712.
In addition to loading the instructions from a local (to line card 702) store, instructions may be loaded from an external source. For example, in one embodiment, the instructions are stored on a disk drive 742 hosted by another line card (not shown) or otherwise provided by the network element in which line card 702 is installed. In yet another embodiment, the instructions are downloaded from a remote server or the like via a network 744 as a carrier wave.
The basic idea for simulation is to simulate packet-processing operations performed by various components of the simulated environment. For example, packets in a modeled stream of packets are to be forwarded and (optionally) classified using the various components in the simulated environment. The simulator calculated processing latencies incurred during the simulated packet processing operations. In particular, memory latencies are calculated based on a modeled latency for each type of memory unit, as well as bottlenecks caused by bandwidth constraints (as applicable). For example, the memory latency for scratch memory 722 would have a first modeled latency, the memory latency for SRAM store 724 would have a second modeled latency greater than that for scratch memory 722, while the memory latency for DRAM store 728 would have a third modeled latency greater than that for SRAM store 724. Other memory latencies could also be modeled, such as latencies for local memory resources for each microengine (not shown).
At the same time, other processing latencies are calculated or otherwise employed in the simulation. For example, some percentage of packets typically pose some type of problem, and cannot be handled by fast-path processing (i.e., handled by the microengine threads). Accordingly, these problem packets are forwarded to slow-path processing handled by general-purpose processor 718. Other packet processing operations are similarly modeled, so that packet-processing operations that would be performed by an actual implementation of line card 700 are accurately simulated in view of the modeled packet stream. From the simulation, a packet throughput rate may be determined. Based on changes to the data structure/memory unit allocation, different packet throughput rates will be calculated by the simulator, as illustrated above in iteration result table 610.
In accordance with aspects of the embodiments described herein, the foregoing algorithms may be implemented by software programs and/or modules running on appropriate processing elements and/or systems. For example, software may be executed on a computer system to generate data structures allocations in accordance with the pseudo code and/or flowcharts illustrated herein. Thus, embodiments of this invention may be used as or to support software components executed upon some form of processing core (such as the processor of a computer) or otherwise implemented or realized upon or within a machine-readable medium. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium can include such as a read only memory (ROM); a random access memory (RAM); a magnetic disk storage media; an optical storage media; and a flash memory device, etc. In addition, a machine-readable medium can include propagated signals such as electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.)
With reference to
Computer 800 may also optionally include a compact disk-read only memory (CD-ROM) drive 822 into which a CD-ROM disk may be inserted so that executable files and data on the disk can be read for transfer into the memory and/or into storage on hard drive 806 of computer 800. Other mass memory storage devices such as an optical recorded medium or DVD drive may be included.
In one implementation, software for implementing the algorithms described herein is included as part of a NPU software design tool. In one configuration for the design tool, both software for performing the algorithms and software for implanting the simulator engine are provided within an integrated toolkit.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
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|Canon Kabushiki Kaisha
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|John Rhoades
|Data processing architectures
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|Qiu Chaoxin C.
|Systems and methods for management of memory in information delivery environments
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|Magnus Jandel
|Configuration of a flexible infrastructure
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|Mar 24, 2005
|International Business Machines Corporation
|Methods and apparatus for allocating bandwidth for a network processor
|Citing Patent
|Filing date
|Publication date
|Feb 15, 2011
|Democrasoft, Inc.
|Connection acceptance control
|Oct 31, 2006
|May 1, 2008
|Charles Michael Storry
|Multicast communication resource management apparatus and methods
|Mar 17, 2008
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|Arthur Douglas Allen
|Connection Acceptance Control
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Jun 21, 2005
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURKLEY, PAUL;CHANDRA, PRASHANT;REEL/FRAME:016713/0847;SIGNING DATES FROM 20050620 TO 20050621
|Sep 21, 2011
|Fee payment
Year of fee payment: 4
|Oct 28, 2015
|Fee payment
Year of fee payment: 8


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A Traveller, Jan 2016, US
21 people looked at this hotel in the last hour
Most recent review
"Staff were friendly and helpful, Hotels.com do not identify the true cost and this caused bad feelings when I checked in."
A Traveller, Nov 2015, US
16 people looked at this hotel in the last hour
Most recent review
"It was great but the wifi was too expensive and the bed were horrible (it was not comfortable at all)."
A Traveller, Jan 2016, US
16 people looked at this hotel in the last hour
Most recent review
"Nice hotel! People there are super friendly. Pool was nice! Ideal for Scuba diving!!!"
A Traveller, Mar 2015, US
- Island Resort And Golf ClubNo Guest Reviews yet
4 people looked at this hotel in the last hour
Hotels within 4 miles of Theos Wreck
22 people looked at this hotel in the last hour
Most recent review
"I chose this hotel mainly because of the price but i felt like i got more than my moneys worth. the elevator requires a hotel key to actually go up...nice security feature. the beds were comfy and it has a fridge."
A Traveller, Nov 2014, US
Map of hotels near Theos Wreck
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- Shark Alley
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Tiberian Sun Reborn is a standalone game that aims to recreate the atmosphere and combat of Tiberian Sun in a FPS. The original effort was started in 2004 by a small group of dedicated modders, leading to its first official release in 2008 as C&C Reborn.
As of November 2011, TSR has been entirely reimagined and redesigned to stick closer to its Tiberian Sun roots while allowing you to benefit from what we've learned from playing the original Reborn and our work on the other Bluehell Productions projects, with room left for imagination and exploration of the Tiberian Sun atmosphere. We invite you to visit our website for more information.
Be sure to check out our forums for the latest news and discussion, plus our semi-regular development blogs!
It is with pride to announce that the team has begun work on the Tiberian Sun: Reborn 184.108.40.206 release!
Several people have been questioning the future of Reborn, along with what has been happening behind the scenes. This post is here to clear up a lot of things and answer these questions, as well as present a small preview of what is planned for Reborn's next major release.
Below is an excerpt from Lead Producer of Tiberian Sun: Reborn, Wallywood.
A lot of you know that the game is a hobby for us so, sometimes real life steps in the way of that. This past year, I have been struggling with a lot of real life issues. These have included: A hand surgery, unemployment, and even the loss of my father; all this while trying to maintain a healthy family environment. So-needless to say-these things have taken up the majority of my time. Much like life, even the roughest storms will calm, and life starts to level out. With this hobbies can become relevant again. I am proud to announce the team has begun work on the Tiberian Sun: Reborn 18.104.22.168 release!
The team will be revisiting the entire game and will prep it for what could very well considered a final release. Development will not stop necessarily, as future items can always still be implemented. Tiberian Sun: Reborn will be made to feel complete. If future items were to be included, this will not directly affect the core of the game.
Much like Red Alert: A Path Beyond's Delta Release, balance will be solid and adding new units or vehicles could be added on a whim without disrupting the current gameplay.
You can expect several things in this new release, including (but not limited to):
■ A complete overhaul of the gameplay and balance, making TSR more fun overall!
■ A complete redo of several of our buildings and units! Perhaps even some new ones!
■ Overhauls to existing maps, reintroduction of some old maps, and even some new maps!
■ Some brand new features to make your TSR more interesting!
■ And of course, bug fixes.
We are still working out of most of the details regarding TSR 2.0, and will provide more updates soon. Expect pictures, videos, and in-depth details about what all to look forward to.
Thank you for your continued support!
W3D Hub have once again open their doors to accepting tester applications! If you enjoy following games such as Tiberian Sun: Reborn, Red Alert 2: Apocalyse...
Tiberian Sun: Reborn has a new update out! Read about it and the future of TSR in the full news update!
A sneak peak at the next version of Reborn! In video form!
Our new community W3D Hub is looking for testers! We are a community housing 5 W3D Engine games such as Apocalypse Rising, Tiberian Sun: Reborn and Battle...
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The W3D Hub launcher is your one stop shop for your W3D gaming needs, providing game downloads and automatic updates, an integrated server browser, centralised...
This is the latest edition of my mad texture pack. If you want someone in this texture pack continue, but please tell me about it.
Retained for posterity, this Feb. 2008 build is only now serves as a curiosity and is entirely unsupported; use at your own risk. Radical changes have...
This is a video of the GDI Ion Cannon featured in reborn, taking direct influence from the C&C3 Ion cannon with it's separate beams joining to create...
A video showing the fast paced gameplay of C&C Reborn
A teaser voideo made from the latest internal alpha!
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Brilliant game!
I remember this being on the BHP launcher. What happened?
The BHP Launcher became the W3D Hub Launcher.
W3D games on android vote: http://goo.gl/forms/wnVoX9EMfb .
i dont know how to download tiberian sun reborn
Get the W3D launcher then in the games tab you can download ts reborn
any update on bot maps with vehicles?
come la.. make infantry and vechical for bot map... more fun .. not all using good connection...
Please, Can you add version for android?
Only registered members can share their thoughts. So come on! Join the community today (totally free - or sign in with your social account on the right) and join in the conversation.


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|9 Reviews
|Property type
|Minimum Stay
|6 nights
When you book through the HomeAway checkout, your booking is backed by our Book with Confidence Guarantee™ offering comprehensive payment protection.Learn more
CHECK IN /check out IS ON SATURDAY
This lovely cottage is in the Anne of Green Gables region of Prince Edward Island (PEI). It is ideal for a family of up to six. If you have a larger party, consider renting both the cottage and the farmhouse, which may be seen at HomeAway 200196 . The large tree shaded yard makes a wonderful playground. Peace, privacy and safety are abundant. Set back in a woods 1/3 mile from the farm road, there is no road noise or automobile hazard for children. The bathroom has been renovated, with new fixtures, since 2014. A beautiful secluded beach is just five minutes away. Excellent restaurants are a short drive away. And New London Bay with its fishing and lobster fleet is ten minutes away.
To see exact location enter 'Chrissydale Cottage' on Google Earth.
Many diverse family entertainment attractions, excellent golfing, and tennis courts are nearby. For a peaceful, relaxed visit to one of the world's most beautiful islands, this is the perfect spot.
Convenient Location: Chrissydale Cottage is located in the heart of the island, convenient to the most desirable north shore beaches, to the Anne of Green Gables historical sites, to shopping, golf, fishing and family entertainment. Set back a third of a mile from the road in a wooded site, it is also free from road noise and the risk of a child running into traffic. There is considerable peace and privacy.
Seclusion, peace and privacy: Only Chrissydale Cottage and a Victorian farm house are one this site, unlike the cluster cottages found in many places on the island. The caretaker of the cottage, Donald Johnstone, lives in the farm house across the road, so he is available for any needs, but is unobtrusive.
Clean and Comfortable: Chrissydale is furnished comfortably and is maintained for cleanliness and maximum livability. The spacious rear deck is also well furnished for relaxed living. The bathroom has been renovated, with new fixtures, since 2014.
I live in Florida and have been spending 2 weeks out of each summer in Prince Edward Island since 1990. I have 4 children who have all been here to visit with me. My youngest child, Alexa, has fallen in love with the home and the island as I have. She has been coming with me every year since she was 3 years old. I am an artist and find great inspiration from the beauty which surrounds my home in Long River. It is my retreat back into a simpler time where things all make sense to me. My heart resides in PEI all year round.
The Owner purchased this farmhouse in 1991
My Mom and Dad found this property and purchased the 180 year old Victorian Farm House in 1990. My Mom called to let me know about this 'cute little farm house' located on the same property which was also for sale. I came up and immediately fell in love with their place as well as mine. My Mom and Dad spent many precious summers here. My Mom's last visit was in June of 2009. Although she was weak and frail she gathered up her strength for one last time to go to the place she loved the most. She died the following November. We released her ashes at Cape Tryon which was a place she loved to go to at sunset.I treasure our family memories of this beautiful magical island and feel such gratitude to my parents for finding it. We have friends now that we have become very close to in PEI and have watched their families grow along with ours.
For large families a unique benefit is to be able to rent both places out and be right next to each other. The privacy of our homes is very special. We are located inthe middle of cow pastures and potatoe farms. We wake up to birds singing and cows mooing every day.We are in the middle of the Island which makes it easy to get to all places you want to go. Our beach at cousin's shore is unique in the fact it has a freshwater stream which meanders from a lake and flows into the ocean, this stream is very warm in the summer and being shallow it is a great place for children to frolic. It is common to have bonfires at night on the beach.There are wonderful restaurants close by and last year (2013) Sting had a tour stop/performance in Summerside ,which is 15 minutes from our house. He was amazing. WE love going into Charlottetown for shopping,festivals,and fine dining. It is 45 minutes from our house.
Property is well described on the web-site.
Clean, well maintained, located away from traffic. Very quiet, convenient, equipped with all necessary amenities.
Easy to reach and close distance from a nice non-crowded beach, stores, restaurants. Ideal for family rental.
Helpful and friendly owners are next door to answer visitors questions.
Good opportunity to spend wonderful vacations on PEI at very reasonable price.
Chrissydale Cottage is a perfect setting for a fun, relaxing and comfortable vacation. I went with 2 friends and we were all comfortable in our bedrooms and found the house well stocked with provisions. I won't repeat what other guests have said other than to reiterate that the description and pictures posted here a very accurate. The location is a great hub for visiting many places around PEI, but the cottage and it's setting are so charming and relaxing that you'll want to stick around some as well. The nearby beaches and eateries are great. The neighbors are friendly and helpful but not intrusive. This is a great spot for a vacation and my friends and I highly recommend Chrissydale. We loved it!!!
We selected the cottage due to its proximity to Cavendish - only 10 minutes to the boardwalk and Cavendish beach. The cottage was very clean and accomodating for a family of 5. The bathroom is newly renovated and the three bedrooms upstairs had very comfortable beds. You don't need to bring a thing along to the cottage except for a nice bottle of wine to sip on the deck overlooking the rolling farmland. There is beautiful beach just 5 minutes away - a must to see for a walk on the beach at sunset. The owners were very easy to deal with along with the caretakers - who phoned and dropped by to make sure everything was up to our liking. If you are looking for a nice, affordable family vacation check out PEI and stay at Chrissydale!
We returned to Chrissydale in 2011 following a beautiful vacation spent in the summer of 2010 there and were not disappointed. The bathroom has been freshly renovated and the kitchen freshly painted adding to the beauty of this cottage. The cottage is exactly as described on the site. It is close to a public beach (Cousin's) and a short drive to Cavendish, Brackley and all the other lovely attractions that make PEI so special. Being so far back from the road adds to the special feeling of this location, especially for people like us who are not too sociable on vacation. The Annandale Farmhouse is close to the cottage but having experienced 4 different sets of renters in Annandale we can honestly say that this has never caused a problem noise wise, and people going there seem to be seeking, like us, tranquility. The cottage is very clean, plenty of linens, quilts, towels (nice quality towels) and everything needed for hassle free packing (my husband hates packing the car for vacation!) The washer and dryer are fantastic for those with children and I was so surprised when the cleaning lady came and brought us clothing detergent, another extra!! The view off of the back porch is so relaxing, looking out over rolling potatoe fields and red roads. Within a stones throw of the cottage is a 9 hole free golf course which my husband and son enjoyed immensly going nearly every day. Within 5 minutes is a fantastic seafood outlet where we bought oysters and quahogs to eat after a nice day at the beach. I think I have nothing negative to say about this cottage. It is not luxurious but feels very homey, the furniture is very nice, the couches extremely comfortable, I would take it as my own cottage just as is. A must visit approximately 20 minutes away is the "The Great Canadian Soap Factory" the experience with the children was incredible! They were able to bottle feed baby goats and have a tour of the little farm where the goats provide milk for the soap making. Also "The Dunes" art shops and restaurants is another must see, 5 minutes from the Soap Factory.
We have sincerely never felt so relaxed anywhere. It was so quiet we could hear the flies passing by while watching the sunrise on the porch. The cottage is a beautiful "home away" with everything a person could possibly need on a summer vacation. From beach towels and toys, to lobster pots and oyster knives. The beds are comfortable and clean with extra sheet if needed. Washer and dryer a big plus with a young family. The long driveway is perfect for young children to ride their bikes and the beach is very close. It is so beautiful that we reserved right away for the following summer!! Highly recommended for those who need to get away from it all!!
--> I just want to thank you for the great vacation in PEI. Everything you described in the email about the house and area was exactly as you said. We had perfect weather and
enjoyed everyday exploring a different part of the province. We went to Anne of Green Gables, Seal Watching in Murphy Harbour, Anne of Green Gables the musical in Charlotte Town and spent a day at Cabot Beach. Your property made for great pictures, especially the long driveway with the kids walking out it. The only disappointing part of the trip was when we had to leave. Once again thank you very much and I will highly recomend my friends to visit Chryssidale Cottage.
Thanks Scott, Kerry, Dalton, Kyrianne, Jarrett Thomas O'Leary
Chrissydale Cottage is near a beautiful secluded beach at Cousin's Shore (a five minute drive) . Also, the beach is free, whereas the National Park beach at Cavendish costs $17 a day. Excellent restaurants are a short drive away. And New London Bay with its fishing and lobster fleet is ten minutes away. Privacy, peacefulness, and pastoral beauty are important features of the Chrissydale site. A spacious, tree shaded yard is great for family play. The large deck, with a 'million dollar view' into the church steeple community of Long River, is ideal for lounging with your morning coffee and for barbeques (propane grill provided). Many diverse family entertainment attractions, excellent golfing, and tennis courts are nearby. For a peaceful, relaxed visit to one of the world's most beautiful islands, this is the perfect spot. Nestled in a valley surrounded by pastures with cows, trees full of singing birds,and freshly plowed fields of grain,wheat or potatoes. This windswept island holds magic in its land.
|Rate Period
|Weekend Night
Jul 2 2016 - Sep 2 2016
6 night minimum stay
Sep 3 2016 - Sep 30 2016
6 night minimum stay
|cleaning and changeover
$700 - $800.00/week
Rate is in US dollars. Payment may be made in either US or Canadian dollars.
A deposit of one half is requested at the time of reservation, with the balance paid one week prior to taking occupancy. Personal check or travelers check is accepted.
If you are concerned about having to cancel your reservation, please purchase travel insurance: http://www.insuremytrip.com/


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Top Definition
Same as fluffer; person on porn movie set whose job it is to keep male cast erect by providing oral sex.
The plater wasn't good enough at her oral craft to keep Sir Fuxalot hard enough for his next scene.
מאת TheCurmudgeon 29 באוקטובר, 2011
Trending Now
a retard; one who usually is suckish at gaming.
Dude! That guy is such a plater at WoW
מאת xKaZx 28 באפריל, 2008


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Avery Bed with Storage Drawer
Returns & Guarantee
Avery Queen Storage Bed
Headboard Height: 48h
Fabric: Merit grey
Product Details
Soft fabric upholstery embellished with tufting puts a modern twist on a classic style. Featuring quality craftsmanship, the Avery storage bed with a tall headboard adds texture and color to your room. Plus, a hidden drawer pulls out from the foot of the bed to add storage space. No box spring required.
Details of Avery Queen Storage Bed
- Dimensions: 67"w 88"d
- Footboard Height: 12"h
- Floor to Bottom of Mattress: 11"h
- Underbed Clearance: 67"w 69.75"d 2"h
- Mattress Space: 60.5"w 80.75"d
- Construction: benchmade, fully padded hardwood frame with reinforced joinery
- Drawer Detail: full-extension ball-bearing glides; extends 33"
- Drawer Interior: (1) 58"w 36"d 5"h
- Legs: none are removable
- Includes: complete bed frame and mattress support system; mattress not included
- Mattress Support: slats; eliminates the need for a box spring or foundation; platform boards available for mattresses requiring a solid surface
- Mattress Support Details: 12 steel 2"w 1"h slats
- Considerations: bed designed for a mattress only; box spring not recommended; mattress height of 13" or shorter creates the ideal bed proportions; shop our mattresses for a perfect fit
- Assembly: delivery includes assembly
- Product Origin: made in North Carolina
- Item Number: 138694
- Fabric: Merit grey See full fabric details
- Fabric Content: 75% Solspun, 25% polyester
- Fabric Description: Merit looks like felted wool but offers high-tech performance. Created from solution-dyed engineered polyolefin, this durable fabric is inherently resistant to pilling, staining and fading. Worry-free and beautiful, Merit adds modern elegance to any room.
Reviews (31)
$1,399 - $1,999
Product Care


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Very Pissed - Gunman At My Kid's School Bus Stop
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[quote:2nd Amendmant 25192708:MV8yMDExODY2XzMzODA2ODcyXzQ3QzU4QjZB] [youtube]http://www.youtube.com/watch?v=e4OMfzaPJZ4[/youtube] [/quote]
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So...I take my children to school every morning. All 3 ride the school bus home. I am able to pick the youngest one up but the other two walk home a quarter mile from the school bus stop. The first few weeks of school I walked them home from the school bus just to be sure they felt safe. Eventually they wanted to buddy up with their friends so I stayed home more often when the two older ones walked home. (11 and 13).
Last Thursday a man went to the school bus stop where my kids get off the shool bus. However, he went there in the morning time and my kids do not ride the bus to school, they only ride it home. Anyway, the guy was dressed in all black and was wearing a ski mask. According to 15-20 students he produced a knife and a gun and started threatening the kids. He told them he would kill them if they screamed or ran. A parent driving by saw the kids all crying and huddling next to the fence so she stopped. She found out the gunman had already left but she called the cops anyway. The kids were released to go to school via the school bus when it arrived.
Now...since we do not have our kids ride the bus to school in the morning, my kids didn't witness this. And, it wasn't until the following day, after school when my son walked home that I started to find out what happened. Apparently two students in his classroom were part of the victims of this gunman. The day before they were asked to keep quiet until the gunman was caught or an investigation could be carried out. Many were taken home by their parents the day of the incident due to shock.
So...the day AFTER this happened, I find out from my 11 yr old son what happened. My daughter ended up being brought home by another parent who was scared for our kids to ride the bus home. When they arrived at my house I heard from the parent even more details. The cops had made a full sweep of the area and had issued a BOL for the guy. However, the cops never told any parents and the school never notified any parents. They didn't even write a letter home. This school has vowed that safety is number one...they dropped the ball on this one!
So...this incident happened. The school didn't notify anybody. About 2 hours after my son told me what happened and my daughter came home I met with fellow neighbors in my area. We agreed that we would all tackle this together. One called the elementary school, one called the junior high school (both pick up from the same bus stop) and one called the cops. About an hour after the schools were called about the incident, we all got phone calls telling us what happened. Of course, there was no mention of weapons and the whole incident was downplayed by the schools.
I agreed to be present at the bus stop from now on with a few other parents at different times in order to help keep a look out and protect the kids.
Not once since this happened have any police been present, have any school officials come to the bus stop when kids are loading/offloading. I am pissed. Oh...and as far as I know of...no news report has come from this yet either. This is bullshit.
We are from Modesto, California. This is the city where Laci Peterson and her unborn child Connor were murdered by Laci's husband Scott several years ago. It's also the location where James Ferrario Jr shot and killed a sheriff's deputy and a locksmith several months ago while they attempted to evict him from a home he hand't paid payments on for 8 months. That was the first of several iconic shootings throughout the country that don't add up. Other shootings include the batman shooter, James Holmes in Colorado and the Wisconsin shooter Wade Michael Page at the Sikh temple.
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Some Chinese Developers Cut Down Payments, Business News Says
Some Chinese developers are allowing first-time homebuyers to delay their down payments to boost sales, China Business News reported today, citing unidentified agents.
Developers in cities including Nanjing, Shenzhen, Guangzhou and Wuhan sold some projects with a 10 percent down payment, the newspaper reported. The sellers advanced the remaining 20 percent, which buyers don't have to pay back for as long as three years in some cases, the newspaper said, citing agents and sales people it didn't identify. First-home buyers in China need to pay a minimum 30 percent down payment.
The marketing strategy, used by some developers in 2008, gained popularity recently as housing inventories grew, according to AJ Securities Co. China's January home prices recorded their worst performance in at least a year, with none of the 70 cities monitored by the government posting gains as Premier Wen Jiabao reiterated his determination to maintain property curbs.
"Developers have fairly strong needs to boost sales under this environment," said Zuo Hongying, a Shanghai-based analyst at AJ Securities, adding that the practice "won't become too widespread" as delaying down payments in effect increases leverage and risk.
China has since 2010 battled rising home prices with measures including higher down payments and mortgage rates, as well as home purchase restrictions in more than 40 cities.


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Microsoft Sidewinder Force Feedback 2 Joystick
I know that this should be in the hardware section but it doesn't look like anyone looks around in there anymore! I was just curious if anyone has had any luck with the Microsoft Sidewinder Force Feedback 2 Joystick for X-wing alliance? I want a forcefeedback joystick to play it with.
Answered your post @ XWA Upgrade. ;)
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Two motorcyclists were injured, one critically, when a large
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A large trike-style motorcycle had left the road and rolled
before coming to rest in a ditch.
One of the riders was assessed by the rescue helicopter's
intensive care paramedic before being flown to Nelson
Hospital in a critical condition.
The other rider, who sustained moderate injuries, was taken
to hospital by ambulance.
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Bill O'Reilly is Fox's biggest scumbagpolitics|chroma601 (stoptellingliesaboutliberals.com)
submitted by PoliticBot to /r/POLITIC
The U.S. Constitution begins with "We the people" not "We the corporation." It never once mentions the Corporation or company-So why then, do they seem to have absolute control our entire way of life?politics|JaywalkerX (stoptellingliesaboutliberals.com)
submitted by PoliticBot to /r/POLITIC


text:
Another term for anus.
Too many jalapenos made my crinklestar burn.
by Roy-G-Biv March 26, 2008
Trending Now
Top Definition
Another word for Asshole!
My crinkle star is dirtier than uasual!
by Ben Morris and Jimmy Dornbush January 13, 2009
My crinkle star itches I need to wipe.
by Lingopronva November 10, 2014


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UPDATE: Representatives from Square Enix have asked me to pull my blog, in the interest of preserving their privacy, I will not be including their request, but I am including the letter I wrote to them below:
Mielke informed me of your interest in having my recent blog post "Dear PR, You Cannot Embargo Public Knowledge" removed and as I'm sure you understand, I can't do that. While I recognize that there are absolutely emails we receive on a daily basis with PR and Developers and publishers which contain sensitive information, the point of the blog is that this particular release which painstakingly outlines an embargo concerning a game and information within the game that is already available both across the sea and more relevantly, on the Internet. The point of the entry in question is that information that exists in the public domain cannot, should not and most importantly won't be relegated to silence. Ultimately doing so flies in the face of the very people you and your company need (especially with VP2) to attract -- gamers.
While it may seem counterproductive for your constant struggles with dealing with the overarching arm of Square Japan, your internal corporate relationships aren't of any interest to what will or won't appear on my blog. Were this a game that was not already available, the request of an embargo (let alone your meta request of embargoing an embargo via the censorhsip of my blog) would absolutely be justifiable and followable (I point that out within the text of my blog) but in terms of further illuminating to the 1UP Readership precisely how the PR machine in the industry that they care about works -- I stand behind the editorial content within the lukems.1up.com page and will continue to do so.
I look forward to continuing to grow the relationship between Square Enix and 1UP News in the coming weeks and months,
Enjoy your weekend,
Luke Smith
On the heels of the No Comment blog and a News Feature I
Rather than tell a long-drawn out story about dealing with reps from EA and Blizzard, this email from Square Enix, which we (and the rest of the gaming press) received tells a pretty strong story.
With summer in full swing, the sun's come out to say hello, and our Japanese counterparts have unleashed a behemoth known as VALKYRIE PROFILE 2: SILMERIA in their home land. While the game sits in stores thousands of miles away, it's inevitable that some of you will import it to sample the delight that will be coming to North America in late September.
With that in mind, I feel it is necessary to highlight some key areas that you should not include in your coverage:
* Please do not write about spoilers of any kind
* This includes spoiler elements of the main plot, the appearance of Freya and Lenneth as playable characters and of course, the ending
* Please do not post CG movies of any kind
* This is a Square Enix staple that runs the gamut for Japan releases, so please refrain from posting videos of our CG or pivotal cutscenes, you will be able to post CG from the English game at a later date
* Please do not post music of any kind
* Do not sample or record the music from the game, there is an
official OST out for VP2 and we can't infringe on its copyright
* The following areas are embargoed until the corresponding dates:
* 6.23.2006 - Dipan, Dipan Castle, Royal Underground Path, Kythena
Plains, Coriander, Sedberg Mountain Runes, Turgen Mine, Vilnore</font color=#FFFFFF>
* 6.30.2006 - Ancient Forest, Audola Temple on the Lake, Kalstad,
Surts Volcano Caverns
* 7.7.2006 - Sahma Desert, Chateau Obsession, Crawsus Forest Ruins
* 7.14.2006 - Crell Monferaigne, Dragonscrypt, Palace of the Venerated
* 7.21.2006 - Sukavia Gorge, Royal Underground Path
* 7.28.2006 - Dipan Castle, Forest of Spirits, Ravine Caverns
* 8.4.2006 - Bifrost, Yggdrasil, Hall of Valhalla
Please let me know if you have any questions, and thanks again for your cooperation!
This is not a "see I can break an embargo" blog. Those are reactionary and immature (I'm only
Read that again.
The information of what happens in VP2 is readily available if you know where to look. Our own Jeremy Parish used his own hard-earned cash to import a copy of VP2 so that he could stare a list of no fewer than seven embargoes in the face from Square Enix on a game that functions on the same plane of irrelevance as Square Enix releases have for the last 10 years.
Yet, Square insists on trying to keep things quiet. Does that make sense to you, gamers? Another quick Square-related story: representatives from Square suggested that we put one of their big upcoming PS2 games in the pages of CGW. In its 25-year history, CGW hasn't ever devoted a page, nevermind TWO pages to a console game -- and Square Enix suggested that
It's blind, more than it is short-sighted, to attempt to embargo or conceal information that is already available on message boards, YouTube, other websites and it should be equally concerning to you -- the gaming community -- that PR firms are trying to direct information down specific channels. Until 1UP
Very, very soon now, I'll be talking about some new opportunities for you, the readers and members of the 1UP community, here at 1UP News.


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|This article does not cite any sources. (September 2008) (Learn how and when to remove this template message)
Henry John Moberly, also known as Harry or Harvey (1835–1931) was a fur trader. He entered the Hudson's Bay Company's service in 1854, and in 1862 was in charge of the post on Stuart Lake; gave his name to Moberly Lake in the Peace River country. After nearly 40 years service, retired in Saskatchewan, in 1894.
Moberly was born at Penetanguishene, Ontario, on 2 August 1835. His father was Post-Captain John Moberly, R.N., and his mother Marie Foch, a Polish lady whose ancestral home was in Alsace-Lorraine. Henry John was a younger son. Several of the Moberlys have given distinguished service in the fields of engineering and exploration of Canada.
Moberly was educated at the Barrie Grammar School and Upper Canada College. Study, however, to one of his restless and adventurous temperament, became irksome, and at the age of sixteen, his father having secured for him a position with the internationally-known English insurance house of Lloyd's, he left school and was sent to the St. Petersburg agency of the firm. Once the novelty of a strange environment wore off, life in Russia palled on the boy and his roving nature again asserting itself, after two years he quit his employment and returned to Canada in 1853.
Soon afterwards Moberly met a member of the party sent by the overland route via the Mackenzie to the Arctic in search of Sir John Franklin. His account of the Saskatchewan country, the immense herds of buffalo, the droves of deer, freedom from restrictive laws, Indians on the warpath and dearth of police, fired Moberly's youthful soul. Without hesitation Moberly wrote to Sir George Simpson then Governor of the Hudson's Bay Company, requesting to be sent to the Saskatchewan, in the service of the ancient organization.
Sometime in January 1854, Moberly received a reply from Sir George, with a five-year contract and instructions to meet the canoes at Sault Ste. Marie, from which point he was to travel with Sir George to his destination.
Departure from his home after the opening of Navigation on Lake Huron would have allowed plenty of time to reach the Sault, however, the desire of making a start toward the promised land was too strong for his patience and he left the East during the next month.
In February, 1854, Henry Moberly, a youth of eighteen, stood one day on the street of his native village, bargaining earnestly with some First Nations people. At that time, the Government employed Indians to carry the mail on sleds from Penetanguishene to the Sault. They were required to haul one hundred and eighty pounds on each sled, besides their food, cooking outfit and blankets, using no dogs but doing the work themselves.
For five dollars the two carriers agreed to take Moberly and his outfit, as far as Fort la Cloche, a Hudson's Bay Company post situated on the north-shore mainland of Lake Huron, opposite Manitoulin Island. He landed at Manitou Island where he remained a few days with the Indian Agent, Captain Ironside. Moberly then crossed to the mainland at the mouth of the La Cloche River where he made his first acquaintance with a Hudson's Bay Company trading post and the first Hudson's Bay Company officer he had ever seen.
Waiting a few months at Fort La Cloche for the canoes, they came as customary up the Ottawa, thence down the French River to its mouth in Lake Huron and via Manitoulin Island to Fort La Cloche. They brought a letter from Sir George, who was coming by rail through Chicago, instructing Moberly to meet him at Sault Ste. Marie. After the men had rested for a few hours they embarked. The canoes were in charge of Robert Campbell, a commissioned officer who had spent many years at the Hudson's Bay Company's posts on the Yukon, the lower Mackenzie, Dease Lake and Peel River. Moberly found him to be a most agreeable companion who gave him much information about the north.
For almost 40 years following this, Henry John Moberly worked for the Hudson's Bay Company, at various locations in the Canadian North-West, retiring from active service in the spring of 1894. From Red River carts, horses, draught oxen, dog trains, York Boats, canoes and pack mules, Moberly witnessed the change to the conveniences of modern civilization, wagon roads, railroads, steamboats, telegraphs, telephones and electric lights.
This page uses Creative Commons Licensed content from Wikipedia. A portion of the proceeds from advertising on Digplanet goes to supporting Wikipedia.


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text:
Olympia-EZ, Munich
MORE Mirror's Edge!
This has the shape of the madhatter, its great!
Amazing work ! Great composition and such quality of light (in every single picture of your gallery actually )
such good color and angle!
Nice work! these are the true colors ?
Nice work! these are the true colors ?
I fixed the upper orange part which was more yellow than orange to begin with (God knows what the architect was thinking). The rest is true.
Nice, really dig these symmetrical shots! I like shooting the exact same kind :]
Excellent color and symmetry.
The contrasting colours make this photo amazing!! It reminds me of Mirrors Edge.
OH! Look at this! Look at that orange color! Awesome!
This is fantastic, you should definitely do more architecture based photography in the future!
Thanks, I definitely will. I had not gotten the hang of it until very recently, but now I am all over it.
soooooo preeeetyyyy
Sieht echt scharf aus.


text:
District of Louisiana Civil Rights Cases
Housing/Accommodations Cases, Dockets and Filings
Cases filed
Cases 1 - 10 of 163
Alameri v. Ibis Trail at Covington LLC et al
as 2:2016cv12743
Plaintiff: Ali Alameri
Defendant: Ibis Trail at Covington LLC, Astor Property Management Services LLC, Astor Property Management LLC and others
Cause Of Action: Housing Discrimination
Carrier v. Louisiana CVS Pharmacy, L.L.C.
as 2:2016cv09641
Plaintiff: Stephen Carrier
Defendant: Louisiana CVS Pharmacy, L.L.C.
Cause Of Action: Americans With Disabilities Act
Rodriguez v. st charles parish school district
as 2:2015cv06599
Defendant: St Charles Parish School District
Cause Of Action: Civil Rights of Handicapped Child
Greater New Orleans Fair Housing Action Center, Inc v. Dorian Apartments et al
as 2:2015cv06406
Defendant: Dorian Apartments, LLC, John Centanni, Joni Centanni Gravolet and others
Plaintiff: Greater New Orleans Fair Housing Action Center, Inc. , Hoyt Baugh , Shawn Bates
Cause Of Action: Fair Housing Act
Evergreen Presbyterian Ministries Inc et al v. Town of Haughton et al
as 5:2015cv02666
Plaintiff: Evergreen Presbyterian Ministries Inc , Barron Builders of Pineville Inc
Defendant: Town of Haughton , Carlton C Anderson
Cause Of Action: Fair Housing Act
Velocity Foundation et al v. New Orleans City et al
as 2:2015cv05407
Defendant: New Orleans City , Jared Munster , Donna Pearson
Plaintiff: Velocity Foundation , Kenneth Reynolds
Cause Of Action: Fair Housing Act
Sherrill v. Morgan et al
as 3:2015cv00710
Defendant: Danny Doe, John P Morgan
Plaintiff: SoYong Sherrill
Cause Of Action: Fair Housing Act
Gilmore v. Louisiana State University et al
as 3:2015cv00638
Defendant: F. King Alexander, Board of Supervisors of Louisiana State University and Agricultural and Mechanical College, Louisiana State University
Plaintiff: Wayne Gilmore
Cause Of Action: Americans with Disabilities Act
Gilmore v. R B River IV L L C
as 6:2015cv02335
Plaintiff: Wayne Gilmore
Defendant: R B River IV L L C
Cause Of Action: Americans with Disabilities Act - Public Accomodations
Gilmore v. Lake Charles PC, L.P.
as 2:2015cv04098
Plaintiff: Wayne Gilmore
Defendant: Lake Charles PC, L.P.
Cause Of Action: Title III Americans with Disabilities Act
Disclaimer: Justia Dockets & Filings provides public litigation records from the federal appellate and district courts. These filings and docket sheets should not be considered findings of fact or liability, nor do they necessarily reflect the view of Justia.


text:
Radium Golf – Golf in BC's Rocky Mountains in Radium Hot Springs
Come play in 2016 and see the exciting results of our ongoing golf course refurbishment program.
Come enjoy the amazing golf experiences; great, fresh food; and mountain views with Radium Golf Group! We look forward to hosting you on our courses.
We are also excited to announce that the Windmill Golf Group and Radium Golf Group have entered into a strategic management agreement which will bring together both companies' strengths in the golf business and allow both parties to grow and offer expanded facilities to members and guests.
The Radium Course
Welcome to the Radium Course
Perched high over the Columbia Valley in the rugged terrain bordering Kootenay National Park, the course features tight, tree-lined fairways, undulating greens and dramatic elevation changes. The Radium Course can be forgiving to the average golfer – just like you would expect from an old friend – while offering challenges for the low handicapper, making it a perfect complement to The Springs.
The Springs Course
Welcome to The Springs
The Springs is set high along the banks of the mighty Columbia River. The wide open spaces of the Columbia Valley, the snow-capped Purcell Mountains to the west and the imposing Rockies to the east create a stunning backdrop for this meticulously maintained par 72 course. Add in relaxed, unpretentious atmosphere, attentive service and one of the best practice facilities in Canada and The Springs is a Canadian classic you'll remember.
Radium Springs Estates
4th Annual Butterfly Gala
4th Annual Butterfly Gala The Hospice Society of the Columbia Valley is hosting the 4th Annual Butterfly Gala at the Radium Course Dining Room this year. The event is on Saturday, April 30 and all proceeds go to benefit the Hospice Society of the Columbia Valley. The evening will feature: Signature Bucket List and Dessert […]
The scenic upper tee on the 2nd hole at Radium Course is open!
Renovations are complete and the iconic upper tee on the 2nd hole is ready for play. This means the course now plays to a par of 72 with four tee boxes per hole playing anywhere from 5,389 to 6,269 yards. Other improvements include a new green on the first hole, re-contouring of the 13th fairway and […]
Opportunity Abounds for Junior Golfers
Growing the game of golf through junior golfers is part of what every golf course strives to do. Right now there are several options to turn kids into junior golfers! Junior Golf Camps are offered Tuesdays & Wednesdays throughout July & August at The Radium Course. Perfect for beginner and intermediate levels. Click to see […]
Golf Tournaments
Playing golf in a tournament can reignite your passion for the game, if not at least get your adrenaline going! Or it can be a day of fun golf in a team environment. Whichever way you approach tournament play you'll find a tournament at our courses that fits you. The Springs Course hosts: Charlie Osterloh […]
Refreshed Menus at the Radium Course and The Springs Restaurants
Both the Radium Course & The Springs restaurants refreshed menus are receiving rave reviews. The menus offer exciting new additions to those trusted favourites you've come to expect. The Radium Course restaurant menu is prepared under the guidance of Executive Chef Bruce Edmondson. At The Springs, Chef Noah Darraugh has prepared the menu in response to the suggestions offered by […]


text:
pointsPlus� Value: 7
Servings: 12
Preparation Time: 20 min
Cooking Time: 45 min
Level of Difficulty: Moderate
This Mexican lasagna will last up to five days in the refrigerator.
6 people want to try | 5 have favorited
Preheat oven to 350F. Coat a lasagna pan with cooking spray.
Place chicken in medium saucepan and fill with enough cold water just to cover chicken. Set pan over high heat and bring to a boil. Reduce heat to medium and simmer until chicken is cooked through, about 10 to 15 minutes; drain. When chicken is cool enough to handle, cut into 1-inch pieces.
Transfer chicken to a large bowl and add beans, sour cream, 1 cup of shredded cheese, chilies, cumin, and pepper; mix well and set aside.
Arrange half of tortillas in bottom of prepared lasagna pan, overlapping pieces to cover surface. Top tortillas with half of chicken mixture, layer with remaining tortillas and then top with remaining chicken mixture. Sprinkle with remaining cup of cheese.
Bake until filling is bubbly and cheese is melted, about 30 minutes. Let stand 5 minutes before slicing into 12 pieces. Serve with salsa on the side.
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text:
Climate is supposed to be the major force in the cure of consumption. It is important, but only one element in the proper management of this disease. The vital object is to increase the resisting power to the bacillus; everything that tends toward that end is important. Climate may be made to help toward it in some cases; but it does not always help—sometimes it hinders, and greatly does so. It is a pitiable waste when it does not help; it ought always to benefit somewhat or not be invoked. Many times it is worse than useless, and brings disappointment and chagrin where it ought to give comfort, and so throws discredit on the whole subject. A measure capable of so much good ought not to be discredited by the unwise use of it, or by unwarrantable belief in it. Fatuous faith leads to neglect of other needful things. Because
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Secondary menu
Two and a Half Men actor claims he wants to put an end to people blackmailing him over illness
Armed police rush to actor's home in Beverly Hills to tackle 'gunman' – but it is yet another hoax call
Tabloid Tales: actor gives Babe Ruth baseball; Katie Holmes spends fortune on daughter's gifts
Tabloid tales: R-Patz disses One Direction, Vampire on the loose in Serbia, Pippa Middleton is a 'sinner of the year'
Teenage actor who played Charlie Sheen's nephew tells viewers to turn off US comedy after finding God
Tabloid Tales: William talks babies with bystanders, Cole and Barlow are haunted, Lohan disappears
Tabloid tales: Sheen throws iPad, man caught with monkey in pants, hotel gets ferret request
Red top tales: Security asks 'Is that something in your pocket?'; Charlie Sheen 'tweeted during sex'
Red top tales: Strip bar forced to pull 'Charlie Sheen Room', The Wanted told to avert eyes from Britney
Red top tales: Worried Gaga calls in astrologers, lustful Simon Cowell regrets engagement
Troubled star thrown a lifeline with TV show based on Jack Nicholson's movie Anger Management
Sheen climbs building clasping machete and bottle of 'Tiger Blood' after being fired from Two and a Half Men
Plug pulled on Two and
a Half Men after troubled
star rants on radio
Capri Anderson locked herself in bathroom during Sheen's tantrum. Time for a remake of Eloise at the Plaza?
Female jail administrator
wants less leniency for
'Two and a Half Men' star