text:
|Publication number
|Publication type
|Application number
|Publication date
|Jan 2, 1996
|Filing date
|Jul 22, 1994
|Priority date
|Jul 22, 1994
|Fee status
|Also published as
|Publication number
|William R. Reohr, Yuen H. Chan, Pong-Fei Lu
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (16), Referenced by (39), Classifications (18), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
The present invention generally relates to a sense amplifier and bit decoder usable, for example, in electronic random access memories and, more particularly, to a sense amplifier with an integrated latch function combined with a bit decoder for memories which have extremely short access and propagation times and which may be operated in a pipelined mode to include, for example, a write-only access during a portion of a memory cycle as well as to perform other functions within the memory such as the concatenation of sense amplifier output fields read out over multiple memory operation cycles.
2. Description of the Prior Art
Electronic data processing, at its most basic level, usually involves a fetch of an instruction and/or data signal from memory, performance of an operation on or in response to that signal and storage of a resulting signal. The speed at which a data processing operation or instruction can be executed is therefore highly dependent on the cycle time required for a memory operation to retrieve and/or store a digital signal in memory. Digital signal storage can be done in many diverse media; each having characteristic properties, advantages and access times.
Static memories include a bistable memory element. Dynamic memories require refreshing since their memory elements rely on stored charge. Both static and dynamic memories typically use sense amplifiers to detect and amplify small signal voltage differences produced by the memory cells. Sense amplifier are designed to minimize noise sources: transistor parametric variations, charge sharing, signal coupling, and power supply noise.
Whether the memory is of the static or dynamic type, certain additional structure is necessary in order to access a particular memory cell, to determine its contents and to develop and deliver an output which is stable and reliably timed. Whether in the form of latches, gates inverters or other types of circuits, such structures generally perform logical functions within the memory device. In the past, such logic circuitry has been of generally the same design as would be used to perform logic functions in a processor or any other form of digital circuit. That is, the response of the circuit was generally designed to be approximately symmetrical relative to an input voltage level. Thus, when the input voltages, often including a clock signal, became relatively stable, a stable output and sufficient noise margins were generally assured and recovery from noise disturbances were possible within the same clock cycle. (These forms of logic circuit will be referred to hereinafter as static logic to more readily distinguish from so-called precharged logic circuits, occasionally referred to as dynamic logic, which follows.)
More recently, several significant advantages over static logic circuits have been realized by the development of logic circuit designs which are highly asymmetrical in response to both input voltage levels and response speed. The basic theory of the response speed improvement in such devices is that propagation time of a logic element will be minimized if the circuit can be brought to a logic state from which it may rapidly be switched to another logic state before data is applied to it. Then, when data is applied, switching of the logic state is only done when the input signal requires such a change. Thus, the circuit can be easily optimized to enhance the speed of such a transition. The establishment of the logic state before an input signal is applied is generally referred to as precharging.
Other advantages also accrue from such logic designs. Consider, for example, a CMOS inverter comprised of an N-channel FET and a P-channel FET. To obtain symmetrical response, the P-channel FET must be of approximately twice the size (and gate capacitance) of the N-channel FET. In a dynamic or precharged logic device having a comparable function, complementary transistors need not be provided with a consequent decrease in element count and gate capacitance. Moreover, the transistor used to provide or hold the precharged state may be very weak (e.g. of relatively low conductivity) and thus of reduced size.
Unfortunately, while the potential gains in speed of operation are substantial using precharged or dynamic logic, response of the circuit is more sensitive to noise and recovery from a transition triggered by noise cannot readily be accomplished within the same cycle time (e.g. a clock cycle or a memory operation cycle).
For this reason also, precharged logic circuits require meticulous tracking and analysis of effects such as noise sources, charge sharing, signal coupling, power supply considerations and the like, particularly when used in critical paths of digital signal processing circuitry. In this regard, it should be understood that digital signal processing generally involves logical operations on combinations of signals and signals of the correct logical levels must be present at the time the logical operation is carried out in order to achieve the correct result. Therefore, variations in signal level which may be encountered in normal operations of digital circuits may cause erroneous operation when applied to precharged logic circuits unless timing is carefully analyzed and controlled to assure that voltage levels will be properly recognized as the logical states they are intended to represent.
However, precharging of a circuit and the design of circuits in which precharging can be exploited are not necessarily straightforward since states of transistors may be achieved which cause transient serial conduction paths if precharge and evaluation transistors are simultaneously active. This results in excessive power consumption which may, in turn, affect response speed or pull voltage levels away from the intended logic states. Precharging can thus easily defeat the gains to be derived by design for asymmetrical circuit response and precharging, particularly where precharging proceeds in a sequence of steps. Further, providing a high impedance state of one or more transistors may increase susceptibility of the circuit to noise from any of several sources which would be especially deleterious to the operation of a precharged circuit.
It should also be noted that the above asymmetrical response speed design concept and precharging cannot reliably be used in circuits which receive signals from a circuit which is not driven solidly to logic level voltages (e.g. power supply and ground). If such a circuit is precharged and supplied with an ambiguous input voltage, the output may be in error since precharged logic circuits, by their nature, have little noise tolerance and thus may result in outputs having voltages which are even more ambiguous as well as including effects of noise sources and power supply variation (e.g. "bounce") when common-mode currents are drawn; possibly being of sufficient severity to cause erroneous operation or triggering of a precharged circuit. When such a circuit (including dynamic logic circuits) is erroneously triggered after precharge, it is virtually impossible and certainly highly impractical to provide for recovery prior to the next operation cycle.
In view of the above design considerations, it is often attractive to mix dynamic and static types of logic circuitry to optimize both the design efficiency and performance of a particular digital processor arrangement or logic directly responsive to memory output. For example, it is known to add a static latch to a sense amplifier to extend the time period during which a bit read from memory will be available beyond the end of a particular memory cycle.
As is known, sense amplifiers generally operate by initially bringing a bistable circuit to a balanced condition between its stable states; from which condition, the sense amplifier can be unbalanced and made to assume one of its stable states by an extremely small voltage difference. Therefore, a sense amplifier must be precharged. Precharging must be completed prior to the development of the small voltage difference (which represents the memory cell state) on the sense amplifier internal nodes. A small voltage must exist at the inputs of the sense amplifier in order for proper operation of the sense amplifier to occur.
By the same token, since precharge of the sense amplifier also balances the voltages on the output nodes, data is not available from the sense amplifier once precharging of the sense amplifier has begun. Additionally, in known designs which add a static latch to the sense amplifier, the static latch must be reset or precharged prior to a subsequent enabling of the sense amplifier. Therefore, some aspects of timing may remain critical when extremely high speed of operation is required.
It should also be understood that, at the present state of the art, substantial design effort may be expended to obtain a seemingly small percentage increase in response speed. An improvement of 10%, for example, is considered to be a very large improvement. One reason for the difficulty in obtaining larger improvements is that each design strategy, such as precharging of circuits with asymmetrical response speeds, also requires a finite amount of time to carry out and some finite time margin to reach a stable operating state of the circuit in response to such an operation. For example, if precharging does not occur sufficiently early in a memory cycle to be completed before a memory cell is accessed to couple the memory cell output to the sense amplifier, malfunction of the sense amplifier may occur because the precharge network will retard the development of a differential voltage on the sensing nodes.
Other uses of a sense amplifier within a memory device, such as multiplexing inputs thereto to provide additional operations within a single cycle can also cause an erroneous write to memory unless precautions are taken. As alluded to above, much design effort has been expended in seeking to obtain several operations within a single clock cycle. One such technique is referred to as pipelining, in which several operations, which may be of different types (such as read and write) regularly occur at different phases of the same clock cycle. For example, a memory which provides two read-write operations and one write-only operation in a single processor cycle of 15 nanoseconds is disclosed in "A 200 MHz Internal/66 MHz External 64 kB Embedded Virtual Three Port Cache SRAM" by G. Braceras et al., 1994 International Solid State Circuits Conference, ISSCC94/Session 15/Static memory for High-Bandwidth Systems/Paper FA15.3, which is hereby incorporated by reference.
It is therefore an object of the present invention to provide a memory including a sense amplifier including a latch and multiplexer and using asymmetrical response speed circuits with precharging which is capable of directly driving static and precharged types of logic circuits.
It is another object of the invention to provide a sense amplifier for a memory which has a high degree of noise immunity.
It is further object of the invention to provide support circuits for a memory to enable performance of both a read operation and a write operation within a single operating cycle delineated by a clock.
It is yet another object of the invention to provide a latching function of a sense amplifier such that data read from memory can be selectively maintained over a plurality of memory cycles in order to support additional memory operations such as concatenation of data fields.
In order to accomplish these and other objects of the invention, a precharged sense amplifier arrangement is provided including a bistable differential amplifier, an arrangement for enabling sensing of a differential voltage by the bistable differential amplifier including an arrangement for causing latching of outputs of the differential amplifier, and an arrangement for precharging at least the arrangement for enabling sensing and inputs of the differential amplifier in sequence, including an arrangement for resetting the arrangement for causing latching of outputs of the differential amplifier.
In accordance with another aspect of the invention, a sense amplifier support circuit is provided including a decoder, an arrangement for gating a reset of the decoder, an arrangement for precharging the decoder in response to a logic state of an output of the decoder subsequent to a reset of said decoder, and an arrangement for simultaneously disabling all outputs of said decoder.
In accordance with a further aspect of the invention, a method of operating a memory including a sense amplifier including a bistable differential amplifier selectively connectable to a plurality of bit lines is provided including the steps of precharging the sense amplifier in response to a precharge signal, enabling the bistable differential amplifier to amplify a voltage difference connected to inputs thereof in response to a sense amplifier enable signal, latching an output of the bistable differential amplifier, and terminating the latching step in response to a precharge signal.
In accordance with yet another aspect of the invention, a method of operating a memory device including at least two sense amplifiers, each of said at least two sense amplifiers including means for precharging a respective one of said sense amplifiers in response to a precharge signal is provided including the steps of performing a read operation concurrently with the at least two sense amplifiers, interrupting a precharge signal to at least one of the at least two sense amplifiers, and performing a further read operation with at least another of the at least two sense amplifiers in the same cycle as the interrupting step.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a generalized depiction of a dual slope sense amplifier,
FIG. 2 is a circuit disclosed in U.S. Pat. No. 5,204,560 which is useful in understanding of some aspects of the present invention,
FIG. 3 is a circuit disclosed in U.S. Pat. No. 4,843,264 which is useful in understanding of additional aspects of the present invention,
FIG. 4 is a schematic diagram of the core sense amplifier circuit of the present invention,
FIG. 5 is a logic diagram of the sense amplifier support circuit in accordance with the present invention,
FIG. 6 is a timing diagram illustrating the operation of the invention,
FIG. 7 is a schematic diagram of a bit decoder usable in the circuit of FIG. 6,
FIG. 8A illustrates another bit decoder allowing single cycle read and write operations,
FIG. 8B is a variation of the bit decoder of FIG. 8A,
FIG. 9 is a timing diagram illustrating the operation of the invention to provide single cycle read and write operations, and
FIG. 10 is a simplified schematic diagram showing a circuit for providing read and write accesses within a single clock cycle.
Referring now to the drawings, and more particularly to FIG. 1, there is shown a generalized depiction of a dual slope sense amplifier similar to that employed in the present invention. It is to be clearly understood that no admission is made that any portion of the depiction of FIG. 1 is prior art as to the present invention or that any particular known device is depicted. The depiction of FIG. 1 is intended to convey a general understanding of the design of a particular type of sense amplifier over which the present invention provides an improvement in order that certain features of the present invention may be more readily understood.
The term dual slope sense amplifier derives from the design feature that the sense amplifier enable signal, SAE, first turns on a small transistor 21 of low conductance to bias the cross-coupled differential amplifier 18, 19 after an initial voltage (typically 100-200 mV for 2.5 volt technology) develops across the active bit lines. Then, once sufficient voltage is developed across nodes N1, N2, (typically 500-1000 mV) transistor 31 is activated to rapidly complete the sensing operation. Specifically, this low conductance transistor 21 draws a small current from node N4 and tending to pull the voltage at N4 toward ground, permitting conductance of the sensing transistors 18 and 19 connected to nodes N1 and N2, respectively.
However, due to the cross-coupled connection of transistors 18 and 19, the conductance of one will increase while the other will decrease, depending on the differential voltage from the bit lines connected thereto. The sense amplifier enable signal is also delayed for a short period by the serial propagation times of inverters I1 and I2 at nodes N5 and N6, respectively, before being applied to a second, high-conductance, transistor 31 which completes the sensing operation and brings node N4 and one of nodes N1 and N2 solidly to ground and the sense amplifier to a stable operating state at increased speed. This two-stage operation thus avoids a large common-mode current from being drawn through both sides of the cross-coupled sense amplifier circuit when the sense amplifier is in a relatively balanced conduction state where nodes N1 and N2 are close to the same voltage (differing only by a voltage due to voltage difference of the memory cell and both transistors 18, 19 of the sense amplifier are in a conductive state).
This mode of operation reduces the possibility of falsely triggering the inactive output of the sense amplifier which ultimately permits the sensing of small differences in input voltage. Further, any noise or rise at the inactive output could falsely trigger dynamic logic gates which are driven by the sense amplifier and which have reduced noise margins compared with static circuits.
Also shown in FIG. 1 is a multiplexor or bit switch C1 which serves to selectively connect the bit lines BL or other signals to the differential input nodes N1, N2 of the sense amplifier. The multiplexor C1 of FIG. 1 is often provided in two portions: a first portion, often referred to as a bit line switch which receives bit line decode signals to connect a particular bit line to the sense amplifier, and a second portion, also commonly referred to as a multiplexor (but distinct from the bit line switch) for alternatively providing connection to other signals when the bit line switch is inactive. It is common practice for this second multiplexor portion (hereinafter referred to by the abbreviation "mux" to distinguish the term from multiplexor C1) to be used to clamp other circuitry to the sense amplifier for purposes of memory testing, such as is shown in U.S. Pat. No. 5,204,560 to Bredin et al.; a schematic diagram of which is shown in FIG. 2.
In the circuit shown in FIG. 2, it can readily be appreciated that bit line switching is done in the circuit enclosed by chain line 11 and the mux is enclosed by dashed line 25. The mux is enabled during testing procedures by an additional clock signal AC in addition to clock signal BC which is used to gate the output signal. The AC clock is only asserted in the testing mode when the bit line switching circuit 11 is idle. Conversely, mux 25 is disabled by the absence of the Ac phase clock pulse during system operation. It should be further noted that the mux 25 of Bredin cannot be used during system mode operation since there is no provision for assuring an absence of selection in the bit line select switching circuit when the mux 25 is enabled, as is necessary for SRAMs.
Referring now to FIG. 3, a known implementation of an integral latch with a sense amplifier is shown as disclosed in U.S. Pat. No. 4,843,264 to Galbraith. In this circuit topology, a pre-amplifier is formed by transistors M5 and M6, together with transistor M7 prior to a cross-coupled differential amplifier formed by M3 and M4. The differentially applied input signals IN and IN B are thus amplified by transistors M5 and M6 before they reach the latching nodes N1' and N2' (primes being added to node reference numbers in FIG. 3 to distinguish from the node reference numbers used to explain the invention). Further, when the enable signal is asserted low during precharge of the sense amplifier circuit, the sense amplifier output nodes N6' and N7' are precharged high by a downward pulse on EQB through transistors M15 and M16. Since nodes N1' and N2' are high, M9 and M10 are off. The remaining transistors M11 and M12 are off since their sources have been precharged high by M21. That is, during precharge, transistors M15, M9, M11, M16, M10 and M12 are all inactive prior to enable signal SE again being asserted high so that dynamically stored charge can be used to keep N6' and N7' high. However, the high impedance states of inactive transistors M9-M12 is susceptible to noise disturbances.
In contrast to the known arrangements illustrated in FIGS. 2 and 3, a preferred embodiment of the invention, shown in FIG. 4, provides both an integrated latch and multiplexor for the sense amplifier depicted in FIG. 1. As an overview, the improved latching section of the sense amplifier separates the sense amplifier enable signal SAE from the precharge signal pcn (precharge negative; the precharge signal being considered active when low) which allows fast and direct precharge of the latch such that precharge is accomplished before the address decoding is completed in the bit line select switching circuit. Further, the separation of the sense amplifier enable function and the precharge function allows data to be statically held by the latch beyond the termination of the sense amplifier enable signal SAE until the static latch is reset by another precharge signal pcn.
More specifically, the circuit of FIG. 4 may be initially considered as including three major functional elements: bit line switching is provided by the circuit enclosed in box Cl, the mux switching is provided by the circuit enclosed in box C2 and the sense amplifier, including an integral latch and precharge circuit, is enclosed in box C3. (reference numerals used in FIG. 1 correspond to the same elements in FIG. 4 except that both bit line select circuit C1 and box C2 are included within box C1 of FIG. 1.)
As shown in FIG. 4, the cross-coupled differential sense amplifier is preferably provided by a pair of cross coupled inverters comprising complementary transistors 16, 18 and 17, 19, respectively. Sensing nodes N1 and N2 are precharged and equalized by transistors 13 and 15, which are connected to the power supply voltage, with transistor 14 connected between the sensing nodes N1 and N2 so that transistors 13, 14 and 15, when simultaneously conductive, form a single node connected to the power supply voltage. Output buffer amplifiers, such as are formed by transistors 32, 33, and 36, 37, each precharged by transistors 34 and 35, respectively, are preferably provided for each of the sense amplifier outputs but are only important to the practice of the invention to the extent that they repower the sense amplifier signal.
The sensing transistors 18 and 19 are connected to ground by transistors 21 and 31 which are operated in sequence as discussed above with reference to FIG. 1 to provide a dual slope function in the sensing operation. Note also that the function of transistors 16 and 17 is to return the high node, either N1 or N2 to the power supply voltage since inevitable common mode current through transistors 18 and 19 will otherwise cause the high node to droop. Additionally, a transistor 30 of complementary conductivity type to transistor 31 is provided to precharge node N4 to the positive power supply to disable transistors 18 and 19 to further ensure a balanced state of the sense amplifier prior to sensing. The delay provided by the propagation times of inverters I1 and I2 of FIG. 1 are preferably provided (as shown in FIG. 4) by inverters formed of transistor 24 (I1), precharged by complementary transistor 23, and both transistors 27 and 28 (I2), respectively, precharged by transistor 29. Transistors 25 and 26, connected as an inverter to the input of transistors 27 and 28 of inverter I2, are small, low conductance transistors which are used to latch the SAE signal voltage on node N6 for transistor 31.
The sense amplifier support arrangement of FIG. 4 is precharged in several stages in response to the pcn signal; the delay to establish these stages being provided by a sequence of three inverters having outputs on nodes N7, N8 and N9, respectively. The pcn signal, itself, is coupled to precharge transistor 23 to precharge inverter I1 and cause resetting of inverter I2, in turn, as well as to the input of the sequence of inverters which establish the precharge sequence in accordance with the invention. A delayed and inverted precharge signal appearing on node N7 is then applied to transistor 29 to pull node N6 to ground. Pulling node N6 to ground, in turn, turns off transistor 31 and activates precharge transistor 30 to pull node N4 up to the power supply voltage and inactivate the sense amplifier.
In this regard, it is important to an understanding of the invention that transistor 31 provides a latching function for the sense amplifier outputs. In previous sense amplifier arrangements, it was customary to continue the sense amplifier enable signal, SAE, at an active level until precharge was initiated in order to maintain the output levels in accordance with the voltage differential which was sensed since, in the absence of a pcn signal which causes a high level on node N7, node N6 will remain high due to latching of the SAE signal by the feedback inverter circuit preferably comprising transistors 25 and 26. This high level on N6 maintains transistor 31 in an active, conductive state to maintain the sense amplifier output. Therefore, the SAE signal can be reduced to a very short pulse which need be of only sufficient duration to allow the onset of amplification of the voltage differential developed (e.g. the start of the dual-slope amplification function) and applied to the sense amplifier from the bit lines. Thus, the latching function is separated from the duration of the SAE signal and is controlled entirely in response to the delayed pcn signal at node N7. Accordingly, the data in the sense amplifier can be maintained well into the next clock cycle and, furthermore, other memory operations may be provided in the same memory cycle in which a read is performed.
The output of the next inverter in the sequence, node N8 (which is active when low), is applied to transistors 13, 14 and 15 to precharge the input/output nodes of the sense amplifier. It should be noted that, as pointed out above, transistor 31 is turned off by a low voltage at node N6 when transistor 29 is turned on by the input on node N7 to this inverter stage. Transistor 31 is thus inactive before transistors 13, 14 and 15 become active in response to a down-going pulse on N8. This sequence prevents large currents being drawn through sensing transistors 18 or 19 during precharge.
The output of the last stage of the sequence of inverters, node N9, which is active when high), is applied to the gates of precharge transistors 34 and 35 to precharge the output buffer amplifiers of the sense amplifier to a low level. The propagation delay of this last inverter approximately matches the time of precharging of the input/output nodes N1, N2 of the sense amplifier which turns off transistors 32 and 37, again to prevent a large current being drawn through either of the buffer amplifiers during precharge.
From the foregoing, it is seen that the circuit of FIG. 4 provides for precharge of all components within the propagation time of three inverter stages and thus less than the time for propagation of a signal through the bit line decoder C1. In this regard, it should be noted that a decoder suitable for producing a 1-of-n code (to enable a single bit line or pair of bit lines) must include at least one AND gate or its equivalent which must, in turn, include at least two serial stages through which a signal must be sequentially propagated (e.g. a true-complement generator and combinatorial logic) and the bit switch transistor (e.g. 1-8 of FIG. 4) will have an additional propagation delay. Therefore, the duration of the precharge operation may, in fact, be fairly closely matched (but nevertheless shorter than) to the duration of the decoder operation, particularly in regard to the preferred embodiment thereof as will be discussed below in connection with FIG. 5. This condition is important to the invention since coupling of bit lines to the sense amplifier while the precharge operation continues would interfere with the development of a differential voltage from the active memory cell. By ensuring that the precharge completes slightly before the decoding operation can complete, even with an optimal decoder, this condition will unconditionally be achieved with no time penalty in the operation of the memory.
This timing during the operation of the precharge portion of the circuit of FIG. 4 is evident from the "cycle 1" portion (which is actually a first portion of a memory operation cycle in the preferred embodiment of the invention) of FIG. 6 in which the PCN signal is slightly delayed from the clock pulse which establishes a memory cycle. The clock signal is preferably provided by a local clock synchronized with a system or processor clock, as is well-understood in the art. The width of the pcn pulse is such that the pcn pulse terminates prior to the assertion of the word line and bit line decoder outputs. The last portion of the precharging operation, responsive to a delayed pcn pulse at node N9, which precharges (precharged low) the outputs (out and out-- n) of the output buffer amplifiers is performed after N1 and N2 have been precharged. This precharge of the sense amplifier support arrangement outputs enables dynamic logic (e.g. precharged domino logic) driven by the sense amplifier to precharge after the outputs of the sense amplifier are precharged low and before assertion of SAE.
It should also be noted that, as discussed above, SAE is thus decoupled from the resetting of a latch for holding a data signal beyond the end of a clock cycle period since the sense amplifier, once enabled, will function as a latch until the fast set transistor 31 is turned off by the precharging operation. Therefore, the latching function of the sense amplifier provides stable outputs until the next cycle begins. In contrast, for example, in known self-resetting CMOS where precharge is triggered from the sense amplifier outputs, the outputs return low before the end of the cycle time which causes subsequent logic to return erroneous results unless a separate latch is provided at the logic inputs.
The bit line selector switch section of the multiplexor shown enclosed in rectangle C1 is of conventional design, the particulars of which are unimportant to the practice of the invention. As depicted, the bit line selector switch includes as many transistors as bit lines it may be desirable to connect to the sense amplifier; four pairs (for differential sensing) being shown in the example of FIG. 4. These transistors are preferably arranged in corresponding groups to correspond to bit line pairs connected to memory cells. Gates of these groups of transistors 1-4 and 5-8 are respectively connected to receive a 1-of-n code from a decoder such as that included in the sense amplifier support circuit of FIG. 6. These transistors then function as transmission gates to connect respective sense amplifier inputs N1, N2, to respective bit lines of a bit line pair (e.g. bl1, br1; bl2, br2; bl3,br3; bl4, br4) connected to a row or column of memory cells.
The mux section of the multiplexor is shown enclosed in rectangle C2 which is preferably constituted by an inverter comprising complementary transistors 10 and 11 receiving a mux-- in input and transistors 9 and 12, functioning as transmission gates controlled by a mux-- sel input to deliver the mux-- in input signal and its complement to the inputs N1, N2, of the sense amplifier and, when, turned off, to prevent drawing current from sense amplifier nodes N1 and N2 during a read operation.
As alluded to above, the operation of the mux and the bit line select switch must be mutually exclusive. This mutual exclusivity is achieved in the circuit of FIG. 3 by the use of different and mutually exclusive clocks for respective operational and test modes and which thus effectively precludes use of a mux to couple signals to the sense amplifier during the operational mode. This limitation is avoided, in accordance with the arrangement shown in FIGS. 6 and 8.
As shown in FIG. 5, the portion of the sense amplifier support circuit which drives the bit switch of FIG. 4 comprises bit decoders preferably formed of an array of AND gates 61-64, each arranged to provide both true and complement outputs, (e.g. dec1 and dec1-- n). The number of AND gates is one-half the number of transistors (e.g. equal to the number of pairs of transistors) in the bit line select switch. Each AND gate is connected to a unique combination of true and complement inputs of the bit line address in order to detect a unique combination thereof, as is appropriate to a 1 of n code. However, in accordance with the invention, each of the AND gates 61-64 is also provided with an additional input which receives an inverted (e.g. by NOR gate 65) mux-- sel (or write) signal to cause the outputs of all AND gates to be driven to the same (e.g. logical "0") state when the mux-- sel signal is active. (An asserted write signal is the same as or derived from the mux-- sel signal with the multiplexer input off. A pipelined write operation does not enable the mux port.) Thus, all bit switch transistors may be simultaneously turned off and the sense amplifier input/output nodes isolated from the memory array in response to a mux-- sel signal when it is desired to apply another signal to the sense amplifier or to decouple the bit lines from the sense amplifier from the bit lines during other operations. This enables a write or other memory manipulation operation to be performed in the same memory operation cycle without disturbing the data in the sense amplifier and serves to permit pipelining to be used to effectively increase the bandwidth of the memory and the processor connected thereto.
SAE is a timed signal which can be derived in many ways, such as by detecting an active word line, and applied to the gates 61-64 in conjunction with the pcn signal in a manner which will be discussed more fully below with reference to FIGS. 8A and 8B. However, the SAE and pcn signal inputs are not required for a simple self-resetting decoder circuit such as that shown in FIG. 7.
Also shortly after the end of the pcn pulse, the bit decode outputs are enabled and a voltage differential begins to form on the bit lines, discharging the parasitic capacitance thereof, assuming that the mux-- sel signal is not asserted. As soon as a voltage differential which is reliably detectable by the sense amplifier has been developed, the SAE signal is asserted and the sense amplifier begins operation in the dual-slope mode described above (hence the three differently sloped regions at the leading edge of the bit line waveform).
As the sense amplifier pulls the bit lines and its output to the power supply voltages, the previously precharged low outputs of the sense amplifier arrangement also are pulled to different logic levels (e.g. at the power supply voltages. The latching action of transistor 31 is evident since the output voltages (out and out-- n) are available once SAE is asserted until the precharge of the next cycle.
Further in FIG. 6, the time period labelled cycle 2 (which, as with cycle 1. can be included in the same system or processor cycle) may be used to connect data to the sense amplifier through the mux input as discussed above in regard to FIG. 4. As shown in FIG. 5, the mux-- sel signal (or its complement, derived from inverter 65, as the logic function of gates 61-64 dictates) is applied to gates 61-64 to drive the dec1-dec4 outputs to logical "0" (and the dec1-- n-dec4-- n outputs to logical "1") regardless of any other address signals applied to the decoder.
As shown in FIG. 6, the waveforms of cycle 2 are very similar to those of cycle 1 except that no bit decoder output occurs since it is suppressed by the mux-- sel signal. A slight voltage fluctuation occurs on the bit lines due to partial select in response to the word select signal but this fluctuation is blocked from reaching the sense amplifier. The assertion of the SAE signal causes the precharged outputs to assume states corresponding to the logical value of the data input to the mux; again latching the data until the precharge in the following cycle.
Furthermore, the pcn signal can be gated or otherwise controlled (e.g. suppressed) to allow the latch to continue to hold data indefinitely for any desired purpose such as pipelining of operations as will be discussed in further detail below. For example, by suitably interrupting (e.g. with an AND gate) the delivery of a pcn signal and disabling the bit decoder with a bit decoder disable signal (e.g. a pipelined-- write signal) to a particular sense amplifier or group of sense amplifiers in a memory, a stored bit or group of bits can be stored and held while other bits may be selectively read from memory or input through the mux port. In this way, data fields can be concatenated in any desired manner and for any purpose. Such a function could be particularly useful for changing or suppressing flag bits or error checking bits.
A suitable form of a gate (e.g. 61-64 of FIG. 5) is shown in detail in FIG. 7. This form of gate circuit also utilizes precharged logic for high response speed and is self-resetting. Thus a pulse of a predetermined pulse width or length is produced and provided to the bit switches. More specifically, an AND/NAND function is provided by the series connection of transistors 701, 702 and 703 (or more if desired) in conjunction with precharge transistor 704 and noise suppression transistor 705 (also referred to as a half-latch).
The configuration of decoding transistors is not important to the practice of the invention and other forms of decoding logic can be used. However, in the exemplary configuration shown, transistors 701-703 must all be conductive to sense a particular combination of input signals. When all of these transistors are conductive, N11 is pulled down and a low voltage applied to the gates of transistors 707 and 708, connected in inverter configuration. The output of this inverter is fed back to another inverter including transistors 705 and 706 which thus forms a latch with the inverter having transistors 707 and 708. Transistors 705 and 706 are preferably sized to be of low conductance since they need only form a weak input latch for transistors 707 and 708.
The output of the inverter including transistors 707 and 708 is provided as an inverting or complement output, dec-- n, of the decoder gate and is also used to initiate reset and precharge of the decoder gate, as will be explained in greater detail below, since a high logic level at the dec-- n output node disables the bit line precharge circuits 1109-1111 and enables the write transistors 1108 and 1112 of FIG. 10. The true output, dec, of the gate, to complete the AND function is provided by an additional inverter including transistors 710 and 711. (As regards the true/complement nomenclature, it should be noted that transistors 1-8 of FIG. 4 are rendered conductive when a low logic level is applied thereto which may also be considered to be within the AND function of the gate.)
The self-resetting precharge functions of the circuit of FIG. 7 are carried out in the following manner. The input address signals are assumed to be relatively short pulses, consistent with the intended processor high speed and short cycle time with which the invention may be used to greatest advantage. Therefore, the duration of the decoder gate output signals are governed by the delay provided in the reset and precharge loop preferably including five inverter stages in sequence, each having a predetermined propagation delay of a signal therethrough. Although any type of delay can be utilized, the first two stages, enclosed in box C11 and including transistors 713, 714 and 715, 716, respectively, correspond to a minimum time the bit switches 1-8 of FIG. 4 must be active for a voltage to build up on the bit line inputs to the sense amplifier sufficient for reliable logic level sensing. An additional delay is provided by a third inverter stage including transistors 717 and 718 which also derives an appropriate logic level for the preferred conductivity of transistor 704 which is sized to overcome 706. Once node N18 goes low in response to dec-- n going high and after the delay and inversion of dec-- n by the first three of the sequential inverter stages, node N11 is also precharged high by transistor 704.
Assuming the input pulse to at least one of transistors 701, 702 and 703 has terminated, the feed through current drawn through transistor 704 will be limited (after charging the capacitance of the node N11) by the relatively low conductivity of transistor 706. In this regard, the function of transistor 706 is to hold down node N11 after termination of the address pulses a, b and c until precharge is performed when that latching function is overwhelmed by conductance of transistor 704. (Transistor 706 can also be omitted in many instances because this condition of node N11 will often be satisfactorily accomplished by dynamic charge storage.)
The signal on N18 is then inverted and delayed by transistors 730 and 731 to provide a high voltage on node N19 drive transistor 709 to pull the output node dec-- n low after transistor 707 has been turned off as described above. Then the voltage on node N19 is again inverted and delayed to pull node N10 low and control precharge of the dec output.
A variant form of bit decoder for allowing single cycle read and write is shown in FIG. 8A. In this case, the circuit is modified to be partially self-resetting and precharge is externally controlled, in part, and gated by the SAE signal through the circuit enclosed in box C11. Otherwise, the operation of the circuit is generally the same as that of FIG. 7. Transistors and identified nodes common to both figures are labelled with the same reference numerals and need not be further discussed.
More specifically and as introduction to the following detailed descriptions of the circuit and operation of FIGS. 8A and 8B, the novel precharge/reset arrangement includes transistors 813-827. The goal of the precharge is to provide a wide active read pulse (or write pulse in the case of a write-through operation) in the first portion of the cycle for one address, and then in the second portion of the cycle, a narrower active write pulse which may be applied to the same or a different address. The data written in the second portion of the cycle is decoupled from the sense amplifier by suppressing the bit decoder (dec-- n) output which drives the bit switches in circuit C1 of FIG. 4. A read operation requires more active pulse duration for evaluation (e.g. when bit lines are released and active) than a write. By arranging for the active pulse widths to be only as long as dictated by each of the read and write operations, respectively, the overall cycle time, which is equal to the sum the active signal (for evaluation of logic function), the precharge operation and the resetting of the precharge, can be reduced.
Thus in FIGS. 8A and 8B, transistors 822-827 capture the SAE pulse and hold it through the end of the cycle. The SAE signal may be pulsed twice in a read/write cycle with no effect of the sense amplifier latch or the bit decode reset. Transistors 822 through 825 form a latch which is cleared by the pcn signal at the beginning of the next cycle. The SAE signal thus gates the reset of the bit decoder and the circuit is arranged such that node N3 is high long before the arrival of the SAE pulse. During a read or write-through in the first portion of a cycle, the bit decoder can be reset after the sense amplifier is asserted through the SAE signal. During a further (e.g. write) operation in the second portion of the cycle, transistor 818 stays active since the active SAE signal is latched onto node N17. Thus the reset progresses more quickly because reset is not gated by the SAE signal. Additionally, the bit decoder of FIG. 8B becomes fully self-resetting because transistor 818 effectively shorts node N6 to the drain of transistor 828.
Operationally, the principal difference between the circuit of FIG. 7 and the circuits of FIGS. 8A and 8B is that, in the circuit of FIG. 7, a minimum pulse width is provided in accordance with the active time required for a read operation to be reliably conducted whereas in FIGS. 8A and 8B, the minimum pulse width is provided in accordance with the shorter time required for a write operation. Transistor 819 is added to assert the precharge immediately after the sense amplifier has been activated. The circuits of FIGS. 8A and 8B principally differ in that the resetting of the precharge occurs earlier in the circuit of FIG. 8A.
The principal difference between the circuit of FIG. 7 and the circuit of FIG. 8A may be appreciated by noting that the dec-- n signal is provided directly to the gate of transistor 821 which is serially connected to transistor 820. Transistor 820 receives a delayed dec-- n signal (the high state of which triggers reset of the decoder and a low state of which indicates reset of the the decoder has been completed; either or both of which are referred to as an output reset signal) through a two inverter stage delay C20 (but which could be provided by any delay structure). This serial connection provides an AND function and thus requires that the dec-- n signal be of a predetermined minimum duration established by the delay of C20 before precharging can be started. The dec-- n signal is also applied to the gate of low conductivity transistor 817 which pulls node N18 to the power supply voltage to terminate the precharge operation when dec-- n switches low, indicating that the precharge operation has been completed.
The circuit shown in box C11 also provides for latching of the SAE signal when it is applied to transistor 827 which is serially connected to transistor 826 which receives a pcn pulse for resetting the latch formed by transistors 822-825. This circuit then operates in the following manner.
Assuming that dec-- n has been high for a period determined principally by C20, as discussed above, the onset of the SAE signal will cause node N18 to be pulled down and begin a precharge. To accomplish this, the SAE signal is applied to both transistors 827 and 819, the latter being connected in series with transistor 817 (which is off when dec-- n is high) and serially connected transistors 820 and 821 which are rendered conductive by the dec-- n and delayed dec-- n signals. Node N16 is also pulled down in response to the SAE signal and applied to an inverter preferably formed by serially connected transistors 822 and 823 to pull up node N17 and turn on transistor 818 which is connected in parallel with transistor 819. Thus a first read operation is gated by the SAE signal.
The signal on N17 is also fed back to another inverter preferably formed of transistors 824 and 825 to latch the SAE signal until application of a pcn pulse to transistor 826 causes the circuit of C11 to be reset after the end of a cycle in which both read and write operations can be carried out. More specifically, the active SAE signal is cleared from the bit decoder at the beginning of the cycle by application of the pcn signal to transistor 826 to pull node N16 high. The latch formed by transistors 824 and 825 can be a weak latch and the action of transistor 826 overcomes the latching function of transistor 825 in much the same way that transistor 704 overcomes the latching function of transistor 706, described above.
Thus two periods are established during which different memory operations can be performed in each memory cycle. It is also important to the full realization of the advantages of the invention that the period for the second operation is determined by the delay in C20 and can be made shorter than the first period which is gated by the SAE signal. Since write operations take less time than read operations (during which a differential voltage must be allowed to build up on the bit lines) shortest overall cycle times will be achieved by adjusting the first and second time periods to be unequal and closely matched to the operations to be carried out in the respective periods. (The manner in which the precharge is accomplished can also be applied to the word line decoder.)
More specifically and with reference to FIG. 9, it is seen that the latching of the SAE signal and the turning on of transistors 818 and 819 disables the bit decoder outputs by executing a precharge operation, as indicated by the curved arrows therein. The duration of this first precharge operation, corresponding to a read, is controlled by the delay corresponding to the propagation time of the SAE signal through the decoder precharge network. The second (e.g. write) operation is controlled in duration principally by the delay of C20. Therefore, this second period can be made as short as may be consistent with the write memory operation. This uneven precharge contributes to the production of the shortest overall memory cycle times consistent with the pipelining of plural memory operations in the same memory cycle period.
Incidentally, it is preferred that only two operations be pipelined in the same memory cycle in view of the very short processor cycle times currently available. However, the principles of the invention described herein could be extended to greater numbers of operations, if desired. It is also important to note from FIG. 9 that the bit decoder output to the sense amplifier can be suppressed by the mux-- sel signal in any or all of the operations which are carried out in any given memory cycle period while a bit decoder output can be provided to other bit line switching transistors 1-8, as may be desired. In the preferred embodiment, therefore, independent read and write decoders should be provided for the single cycle read and write function. The read bit decoder is disabled by an active pipelined-- write signal.
Another embodiment of the bit decoder circuit is shown in FIG. 8B. The basic difference of this embodiment from that of FIG. 8A is the omission of transistor 821 and the provision of the delayed dec-- n signal at node N3 to both transistors 817 and 820. As with the circuit of FIG. 8A, this delay is shorter than the delay to the onset of the SAE pulse and the enablement of the precharge operation to be gated by SAE will have been accomplished prior to the leading edge of the SAE pulse. In other words, in the embodiment of FIG. 8B, the SAE signal gates the reset during the read portion of the cycle, as in the embodiment of FIG. 8A but occurs more quickly because of the smaller transistor stack. However, the embodiment of FIG. 8A provides more rapid termination of precharge by bypassing C20.
The improved cycle time provided by the circuit of FIG. 8B derives from the omission of transistor 821 which has been found to slow the gating of the precharging signal by the SAE signal because of the increased series resistance.
Referring now to FIG. 10, an exemplary schematic is shown for performing both read and write operations at the same or different addresses during a single memory cycle in accordance with either of the embodiments of FIGS. 8A or 8B. The memory cell array is shown to the extent of two exemplary memory cells respectively connected to word line 1 and word line n, one being shown in detail and comprising transistors 1101-1106. Of course, the form of the memory cell is not important to the practice of the invention. For example, while a static type of cell comprising a bistable circuit is shown, a dynamic charge storage structure including a capacitive cell could also be used. The sense amplifier of FIG. 4 is shown connected to representative bit lines 1120 and 1120'. The sense amplifier also receives inputs from the bit decoder of FIGS. 5, 7, 8A or 8B to control connection of pairs of bit lines to the sense amplifier, as described above. A write circuit 1130 is also connected to the bit lines (in pairs) through transmission gate transistors 1108 and 1112.
Prior to partial selection of a memory cell by application of voltages to a word line, the voltages on the bit lines are equalized by precharging them high through low conductance transistors 1109, 1110 and 1111. The opening of transmission gates preferably formed by transistors 1108 and 1112 (the form of the transmission gates is not critical to the practice of the invention) is done simultaneously with turning off the precharging transistors 1109-1111. It should be noted in this regard that if both the sense amplifier and write circuit are active, a write-through to the sense amplifier can also be done. This operation involves the same bit lines since the write-through is fed through to the sense amplifier.
In view of the foregoing, it is seen that the sense amplifier arrangement and support circuitry in accordance with the invention provides a relatively simple circuit which can be fabricated at very small size and high integration density but yet is capable of operation at very high speed and with the flexibility for inputting signals to the sense amplifier through a multiplexer, latching any signal for an indefinite period of time and allowing pipelining of plural memory operations in a single memory cycle while retaining data (e.g. read from memory or input through the multiplexor at the sense amplifier output. It is also seen that the invention provides a memory using precharged circuits having asymmetrical response speed and noise immunity and capable of directly driving both precharged and static types of logic.
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
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|International Classification
|Cooperative Classification
|European Classification
|Jul 22, 1994
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REOHR, W.R.;CHAN, Y.H.;LU, P.;REEL/FRAME:007093/0263;SIGNING DATES FROM 19940721 TO 19940722
|Jun 28, 1999
|Fee payment
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|Jul 23, 2003
|Maintenance fee reminder mailed
|Jan 2, 2004
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Energy Balance through the Tao
In the Western world, exercise focuses mainly on physical fitness and developing muscular strength. In the East, exercise systems balance fitness practices for the body, mind, and spirit. This balance is strongly emphasized in the Taoist system of Tao Yin, one of the oldest and most diverse forms of exercise in China. Tao Yin focuses on creating balance between internal and external energies and revitalizing the body, mind, and spirit with a combination of strength, flexibility, and internal energy exercises. Its ultimate goal is for the practitioner to become pure, responsive, and full of energy, like a child. In Energy Balance through the Tao, Master Mantak Chia introduces 45 fully illustrated Tao Yin exercises to Western readers. He explains the history behind the practice and its connections to other complementary Chinese exercise forms, such as tai chi.


text:
Gender Empowerment Initiative has seven members for the Spring 2017 semester, coming from schools all over the APDA circuit. Here you can learn more about us. Each member is required to hybrid with a younger, non-cismale debater during the semester, so if you meet that description and would like to hybrid with any of us, please reach out!
Joy Jing (Co-Chair)
Hello there! My name is Joy Jing and I'm a senior at Harvard College, pursuing a joint concentration in Environmental Science and Architecture. I started debating in the fall of freshman year, and fell in love with the activity and the community. During my time on APDA, I am particularly inspired by the amazing female leaders and speakers. I hope to give back by providing mentorship for others. I am also an avid painter, traveler, volleyball player, and floor speech dreamer.
Rachel Kane (Co-Chair)
My name is Rachel and I'm a sophomore at GW currently studying political science and public health. I love to run cases about feminism and movement politics, but I'm currently trying to become less awful at Econ. When I'm not studying or debating, I spend an inordinate amount of time and energy attempting to make evenly browned toast. If you ever want to chat about rounds or literally anything else, I'd love to hear from you! I'm incredibly excited to continue to serve on GEI this semester; I hope I can give back a fraction of the support that GEI has given me.
Leah Block
My name is Leah and I'm a junior at NYU majoring in English with a minor in creative writing. I love the community on APDA, the passion, and the focus on open-minded intellectualism. I like to debate about philosophy and feminism, and I typically LO/MG, though it depends on who I partner with. I'm excited to promote gender diversity and inclusivity on the league!
Chiara Caraccio
Hi! My name is Chiara Caraccio and I'm a first year at Columbia, planning on majoring in philosophy. I'm from California and did some high school debate — I'm very inspired by the community of incredible and accomplished female/non-male identifying debaters on APDA! I'm super excited to be on GEI and to get to know everyone on the league better.
Matt Cryer
Hi! My name is Matt Cryer, I'm a sophomore at GW studying international affairs. I started debating in the fall of 2016. I didn't debate in high school, so I know how intimidating it can be, but I've come to love the community. I applied to be on the GEI to combat harmful gender norms, and want to especially be a voice for LGBT and non binary debaters. If you ever want to talk, case, or anything else, please feel free to reach out.
Sonya Huang
Hi! My name is Sonya Huang and I'm a freshman at the University of Pennsylvania, planning on majoring in Economics. I debated all throughout high school, but only started Parli for the first time last semester (although I have done World Schools in the past!) Gender empowerment is an issue close to my heart, and I'm so excited to work with the rest of the GEI committee this year!
Madison Needham
Hello! My name is Madison Needham and I am a UC Berkeley student in my third and final year. While I am majoring in Political Science and Gender Studies, my true passions include writing Star Wars fanfiction and large dogs. My favorite cases are those which appear strange or inconsequential on the surface but contain thought provoking questions within. If you ever want to talk about queer women's issues or disability rights (or Darth Maul), please reach out. Here is to a great year of debate!


text:
Running Boards
Hi Guys :),
Does anybody know the measurements of running boards on a 34 Ford 3 w coupe. I seem to have one longer than the other.
I have the rubber covered Bob Drakes running boards on my '33 sedan - they are 54". I think they are the same between sedan and coupe and between '33 and '34.
Thanks for that :thumbup:
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|DO NOT REPLY [Bug 42410] New: - New ant task sugestion... <inject-xml>
|Mon, 14 May 2007 16:06:13 GMT
DO NOT REPLY TO THIS EMAIL, BUT PLEASE POST YOUR BUG· RELATED COMMENTS THROUGH THE WEB INTERFACE AVAILABLE AT <http://issues.apache.org/bugzilla/show_bug.cgi?id=42410>. ANY REPLY MADE TO THIS MESSAGE WILL NOT BE COLLECTED AND· INSERTED IN THE BUG DATABASE. http://issues.apache.org/bugzilla/show_bug.cgi?id=42410 Summary: New ant task sugestion... <inject-xml> Product: Ant Version: unspecified Platform: All OS/Version: All Status: NEW Severity: enhancement Priority: P3 Component: Core tasks AssignedTo: email@example.com ReportedBy: email@example.com At my job I wrote an ant task which I believe can be extremely useful to put into ant... This task does the following: Take a file "target file" and replace a token in that target file with the token itself, a newline, and entire contents of a "source file". This is specifically written to work with XML and not a flat file, but the task would create some comment markers so that the changes can be undone (by specifying the "source file" and the markers will provide info on what needs to be deleted). The goal was also to ensure that more than 1 run would not create duplicate code in the "target file", as well as the ability to undo the changes. The idea is for doing things like: Modifying web.xml to inject it with new information (lets say we modify some client's install) by injecting web.xml with some other file which contains a list of custom servlet mappings. In any case, I thought I would put the idea out there, if you guys like it I can send you what I have, it needs some work to make it a completely generic ant-task but it seems like a nice thing to have. I do not know how many people need this sort of functionality. Maybe this is more inline with the ant-contrib library? --Dmitriy -- Configure bugmail: http://issues.apache.org/bugzilla/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug, or are watching the assignee. --------------------------------------------------------------------- To unsubscribe, e-mail: firstname.lastname@example.com For additional commands, e-mail: email@example.com
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Market Immersion - Scuba Explorers - Arm Anchor
Posted: July 14 2015
Company Location: Kansas City, MO
Application Deadline: No Deadline
Position: 3 Part-time, Unpaid
Always be on the alert for potentially fraudulent job postings online - never send money to a potential employer.
DescriptionIn search of a Public Relations person to promote various online promotions while keeping the integrity and continuity of our companies' brands.
I am looking for a self-starter who is self-motivated and passionate about doing each job completely and thoroughly.
There are many opportunities for you to establish yourself as an expert in your field. Use your experience here to build your portfolio.
This is a remote-based position, although you will be expected to attend two online meetings per week with me and or the team.
Your work will be displayed on nationally and internationally with massive exposure.
You will interact and coordinate with other team members, learn other skills and share resources.
The beauty of working with me, you will have no constraints of red tape that are typically associated with large corporations. Once we agree on what needs to be accomplished, you can simply make it happen! Nowhere else will you find such flexibility to showcase your natural gifts & talents!
I'm counting on you to act as an entrepreneur and brainstorm with me and my team to come up with unique ideas.
Timeline: Immediate! Approximately 10 hours a week for 15 weeks.
This is an unpaid internship, but the experience is priceless! For the candidates that show consistent intuitive and quickly take an idea, put it into action and implement it into the project, in time, you may prove your way into a more permanent paid position.
One critical fact:
Treat this internship as you would a paid position (only fewer hours). If you commit to a project and then disappear or fail to communicate, you will be instantly & permanently removed from the team without a recommendation.
To Apply: Click on this link (or copy/paste in browser) leave your first, last name & email:
Next, call or text Leslie: 913-730-7170 (either way leave a message)
If you fail to do these two things in order you will not be contacted.
Thanks and I look forward to talking soon!
ResponsibilitiesCopy-writing, press releases, production material, news releases, media alerts, fact sheets, status reports and other materials as directed.
Write about presentations, meetings and brainstorming sessions
And more to discuss later.
RequirementsPublic relations interns will be actively involved, or a recent graduate of, a university public relations, marketing, advertising or other related program. Current students will preferably have at least sophomore standing.
Demonstrate the ability to undertake basic public relations writing assignments.
An understanding of basic media relations skills.
Interact professionally with clients, and good judgment.
A working knowledge of computers, as well as word processing and database management software is necessary.
Prioritize tasks, focus on multiple projects and deadlines simultaneously.
Enthusiasm and great attitude


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ROME -- To all those critics who have clamored for greater accountability for Catholic bishops who drop the ball on sex abuse cases, the Vatican's top prosecutor this morning had a simple message: You're absolutely right.
"We need to be vigilant in choosing candidates for the important role of bishop, and we also need to use the tools that canonical law and tradition give us for the accountability of bishops," said Maltese Monsignor Charles Scicluna.
As a case in point, Scicluna bluntly said it is simply "not acceptable" for bishops to ignore anti-abuse protocols established by the Vatican or by their bishops' conference. He said the church in Ireland, to take one example, "has paid a very high price for the mistakes of some of its shepherds."
tSciculuna was apparently referring, at least in part, to a damning 2011 government report on the Irish diocese of Cloyne, which found that both civil laws and church procedures on handling sex abuse complaints were flouted as recently as 2009.
t"When set standards are not followed, this is unacceptable," he said.
tScicluna said there are actually already provisions in church law to sanction bishops for "negligence and malice in exercising one's duties," suggesting this provision should be more strenuously applied. (He appeared to be referring to canon 128 of the Code of Canon Law, which reads: "Whoever illegitimately inflicts damage upon someone by a juridic act or by any other act placed with malice or negligence is obliged to repair the damage inflicted.")
tScicluna also noted that when canon law specifies penalties that can be imposed on "clergy," that includes bishops as well as priests and deacons – although, he said, the fact it applies to bishops too is sometimes "ignored."
t"Ecclesial accountability has to be further developed," he said. "I agree with you on that."
tScicluna made the remarks to reporters as part of a four-day symposium on the sexual abuse crisis titled "Towards Healing and Renewal", which is being held at Rome's Jesuit-run Gregorian University. It brings together roughly 100 bishops and religious superiors from around the world, in tandem with child protection experts.
tScicluna serves as the Promoter of Justice in the Congregation for the Doctrine of the Faith, a position he first took up under then-Cardinal Joseph Ratzinger, today Pope Benedict XVI. In effect, that makes Scicluna the Vatican's "D.A." on sex abuse cases; among other things, he was responsible for the investigation of the late Fr. Marcial Maciel Degollado, founder of the Legionaries of Christ, which led to a 2006 edict restricting Maciel to a life of "prayer and penance."
Pressed this morning to expand on the theme of accountability for bishops, Scicluna pulled few punches. Without "redefining the church, which will always be hierarchical," he said, it's equally clear that power must be wedded to accountability.
t"Bishops are accountable to the Lord, but also to their people," Scicluna said during this morning's session with the media. "They owe their people good stewardship."
tNoting that church law reserves the power to impose sanctions on a bishop to the pope, Sciculna appeared to suggest that the papal nuncio, or ambassador, in various countries could play a greater role in prompting the pope to act.
t"The nuncio to a country represents the concerns of the Holy Father to that local church, but he also has the duty to listen to the people in order to convey the concerns of the local church to the Holy Father," Scicluna said.
tScicluna rejected suggestions that church law as it presently stands does not have adequate accountability mechanisms for bishops.
"It's not a question of changing laws, but of applying what we have," he said.
He added that more vigorous enforcement of the law should make it clear that, "There is behavior that is not compatible with being a good shepherd."
tScicluna likewise insisted that bishops have a "moral, if not legal" responsibility to consult with experts in making decisions such as responding appropriately to sexual abuse complaints.
tHe noted that his boss at the Congregation for the Doctrine of the Faith, American Cardinal William Levada, had already warned of an "exclusively canon law" approach to the problem of abuse, and Scicluna said he would add the danger of an "exclusively hierarchical response."
t"The hierarchy has to listen to the experts," he said. For instance, Scicluna said, "we need the input of psychologists to help us."
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|Member of:
Marketing Lancashire
This year's Tram Sunday is set to be bigger and better than ever, with more stalls, cars and amusements booked to attend the event on Sunday 17 July!
The Tram Sunday footprint has been extended for 2016 and, for the first time, it will include the Memorial Park where the organisers are planning an exciting finale to this year's event. Watch out for more updates!
Tram Sunday first took place in 1985 as a part of the celebrations for the anniversary of Blackpool trams and continued to develop over the years to include any form of transport: classic cars, motor bikes, buses and of course, not forgetting the trams.
Its popularity has increased through the years with both transport enthusiasts and the local community in Fleetwood. Under the leadership of a new management team in recent years, the festival has grown with the inclusion of further attractions.
In 2014 the "Spare pARTS Festival" ran for the first time in conjunction with the event and brought exciting, transport themed professional arts performances, entertainment and displays to the event including professional street artists, which have been incredibly popular with everyone and only made the event bigger and better!
The information contained in this page is supplied and maintained by the advertising business and is their sole responsibility E&OE.
Click the buttons below to show details for:
|07946 537950
More about SpareParts Festival here
Find out how to Volunteer for Tram Sunday here
Find out how to Book a Stall at Tram Sunday here
Find out how to Enter a Vehicle at Tram Sunday here
Like Fleetwood Festival of Transport on Facebook
Follow on Twitter @FdFestTramSun.
Subscribe to the LeftCoast email
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I've #justsponsored Daniel Foster, who's fundraising for Blackpool Carers Centre on @JustGiving. Donate now justgiving.com/fundraising/Da…
Some more photos of our 'Futurists' @SparepARTs_Fest @SandbachTF at the weekend; a fab time was had by all!… twitter.com/i/web/status/8…
@CreweTCouncil @SandbachTF Hurray! We're looking forward to @trActioncrewe in July! Great that @SparepARTs_Fest wi… twitter.com/i/web/status/8…
Even the horses learn BMX tricks with our #Roadworks team @SparepARTs_Fest in Sandbach!next stop:Crewe on 8th July. pic.twitter.com/H6TdjQABBL
Great line up at @trActioncrewe in July with @SparepARTs_Fest - read more! goo.gl/DyjsFY pic.twitter.com/3J1MhXfV30
#TramSunday Image courtesy of Alex Calvert pic.twitter.com/80l0HFzWZK
New York taxi at Tram Sunday in fleetwood. #tramsunday #tramsunday2016 #yellow #yellowcab #nyc #dayout #funday #fle… pic.twitter.com/tvhDa0esPZ
Double decker classic fleetwood tram at #tramsunday. #tramsunday2016 #tram #masstransit #blackpooltram pic.twitter.com/YHM4LpCmzc


text: Abercairny Photos Abercairny Old Photos Memories of Abercairny Photo Books Nearby Places Displaying all 3 Photos Sort & display options Sort by Default Sort by Most Popular Sort by Recently Added Sort by Oldest Sort by Newest Sort by Description Sort by Memories Shared Show Landscape Images Show Portrait Images Show All Images Abercairny, House 1899 Ref. 44385 Abercairny, And Lake 1899 Ref. 44384 Abercairny, 1899 Ref. 44386 Displaying all 3 Photos


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YP - The Real Yellow PagesSM - helps you find the right local businesses to meet your specific needs. Search results are sorted by a combination of factors to give you a set of choices in response to your search criteria. These factors are similar to those you might use to determine which business to select from a local Yellow Pages directory, including proximity to where you are searching, expertise in the specific services or products you need, and comprehensive business information to help evaluate a business's suitability for you. "Preferred" listings, or those with featured website buttons, indicate YP advertisers who directly provide information about their businesses to help consumers make more informed buying decisions. YP advertisers receive higher placement in the default ordering of search results and may appear in sponsored listings on the top, side, or bottom of the search results page.
Shooting Range in Kyle, TX
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
1.Premier Concealed Handgun
211 Clark Cv
6.44 mi
Rifle & Pistol RangesGun Safety & Marksmanship InstructionSporting Goods
2.Red's Indoor Range
6200 W Highway 290
17.07 mi
Rifle & Pistol RangesGuns & GunsmithsAmmunitionGun Safety & Marksmanship Instruction
I have had a great time at Red's range bought a gun there as well
3.County Line Shooting Center
7061 S Old Bastrop Hwy
San Marcos,TX
15.40 mi
Rifle & Pistol RangesArchery Ranges
This Gun Range is Closed it never opened because of a Law suit.Wish I could give it a glowing report, but closed is closed.
4.Prestige Gunite of South Texas
1510 Fm 1185
14.39 mi
Rifle & Pistol Ranges
5.Capitol City Trap & Skeet Club
8707 Lindell Ave
18.62 mi
Rifle & Pistol Ranges
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
6.Dietz Gun Shop & Range
421 Range Rd
New Braunfels,TX
28.08 mi
Rifle & Pistol RangesGuns & GunsmithsAmmunitionGun Safety & Marksmanship Instruction
Ok, the sign for unloading the gun is obvious. You take a loaded gun to a gunsmith , prepare to be chewed out. That's common sense. After reading these reviews before I went to this range I was skeptical. I have been to the range twice now in the last 2 weeks. These people were friendly and helpful. Have no idea how they got these bad reviews. Great place. Took my 14 year old son and had a good time. Maybe if you don't know the difference between a trigger and a barrel you may have a problem, but these were good people. Sounds like the negative posters probalbly did something stupid or unsafe to warrant the supposed treatment they got. I would bet they deserved it.....
7.Eagle Peak Shooting Range
20026 Lindeman Ln
36.71 mi
Rifle & Pistol RangesGuns & GunsmithsSporting Goods
This place is great, i mean there isnt the best and vast selection of guns to choose from but i still was able to shoot an AR-15 and thats all i wanted!!! Also if you just follow the rules they provide you will have a good time. Dont be a jackass!!!! There are many places to go to be a jackass but this is not one of them. The Staff there was friendly and answered all questions i had and me and my girlfriend today had a great time and were happy.BTW if your wondering about pricing here it is...$10 for entrance fee$10 for membership card (one time fee)$12 to rent any gun~$21 for ammunition$0.25 for a single target or $1.00 for 5$2 to rent goggles and glasses, i recomend getting your own and get those orange foam pieces that go in your ear and expand. They work well!And thats pretty much it. Idk about clay targets and other accessories.Anyone can shoot and as long as your 17 years or older you dont need anyone who is 17 or older with you at all times.This place is great if you just want to take your family out for their first shooting range experience or if your an expert marksman. They take gun safety incredibly serious and you should feel safe here!!
8.Bracken Rifle & Pistol Range
19280 Marbach Ln
San Antonio,TX
38.04 mi
Rifle & Pistol RangesSporting Goods
We love this range! The owners are so great! We've always received nice service and they are very gracious. They keep the range very safe and extremely clean. Three things I really like are: one, the staff actually operate the ranges by calling cease fire and they trade out the targets instead of you having to do it on your own and asking everyone else to stop shooting to do it; second, the spaces/tables are divided by hardware cloth as walls which creates your own designated space for shooting; and lastly, the pistol and rifle ranges are both covered over the spaces/tables so you are in shade. The staff does pick up the empty shells between target trade outs to keep the areas clean - however, you can keep your empty shells if you want, you just have to let the staff know it put them in your bag before the staff comes by to empty the containers. The prices are very reasonable, too. We've come here probably about 15-20 times.
9.Bexar Community Shooting Range
15391 Bexar Bowling
39.42 mi
Rifle & Pistol RangesSporting Goods
10.Red's North Indoor Range
1908 W Pecan St
34.28 mi
Rifle & Pistol RangesGun Safety & Marksmanship InstructionGuns & Gunsmiths
My first time at a shooting range.For me I thought it was a good time. Ammo was a bit higher than other stores, if I'd been prepared...the range is inside and it was cold but it was colder out side SO I was wearing a jacket already. Staff was friendly enough (no complaints here).
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
11.Best of the West Shooting Sports
19500 W State Highway 29
Liberty Hill,TX
49.83 mi
Rifle & Pistol Ranges
Most staff are former military or law enforcement.Clean, well maintained. All the staff are very professional. By far the best range I have had the privilage to train at.
12.Cedar Ridge Range
7110 Fm 1863
37.93 mi
Rifle & Pistol Ranges
Best area range. If you are a know it all don't bother. The test is simple and given after you read the rules sheet. the only people who trouble with it are those who don't take it seriously. Having witness many people who skim the rules sheet and then can't answer the simplest questions I get how they think the owners are condescending. But in reality it is the writer who did not take the time to do the right thing. If you can't take the time to understand the rules I really don't want you shooting next to me.I have several guns worked on and the gunsmithing is outstanding. I like the the privacy the bays offer.
13.Nixon Gun Range
1922 County Road 173
49.68 mi
Rifle & Pistol RangesGun Safety & Marksmanship Instruction
We are a small start up business that appreciates your input to make us better.
14.Nardis Gun Club
4818 Interstate 10 E
San Antonio,TX
50.33 mi
Rifle & Pistol RangesGun Safety & Marksmanship InstructionGuns & GunsmithsSporting Goods
San Antonio's Premier Indoor Gun Range offers a unique one stop shop for gun lovers of all types. We focus on Concealed Handgun License (San Antonio CHL) classes and training, Firearm Concealment, Home Defense, and Tactical Accessories. We cater to both men and women. Our Facility has 12 climate controlled state of the art shooting lanes, 3 classrooms with a wide array of training curriculum including CHL, an on-site Gunsmith, Deli / Coffee Bar, Lounge with Wifi, and a fully stocked Pro-Shop for your Firearms and Accessory needs.
15.Blucore Shooting Center
2000 N Mays St
Round Rock,TX
38.68 mi
Rifle & Pistol RangesGuns & Gunsmiths
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
16.Hill Country Black Rifle
5550 Fm 1516 N
44.46 mi
Rifle & Pistol Ranges
17.Copperhead Creek Shooting Club
7030 E Fm 1431
Marble Falls,TX
44.48 mi
Rifle & Pistol RangesAmmunitionSports Clubs & Organizations
18.Texas Guns
7122 Bandera Rd
San Antonio,TX
57.66 mi
Rifle & Pistol RangesAmmunitionGun Safety & Marksmanship InstructionGuns & Gunsmiths
We are a gun store offering handguns, rifles and tactical guns manufactured by top industry brands. As a full service gun shop, we can help you from start to finish, from choosing the correct gun, learning to use it properly, to backing it up with a lifetime warranty. We even have our own gunsmith on site. Ladies feel free to visit us as well. We believe women should be well armed and trained to use their weapon. In addition to our firearms, we offer a wide array of accessories ranging from gun scopes to ammunition. Our comfortable environment and experienced staff will make even the most novice shooters feel right at home in our firearm shop. Stop in and visit us today!
19.Gun Training San Antonio
8111 Mainland Dr Ste 104
San Antonio,TX
57.50 mi
Rifle & Pistol Ranges
20.Apache Rifleworks
50502 Interstate 10 W
62.34 mi
Rifle & Pistol Ranges
One Hour Range Package For Two+1more
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
21.Central Texas Gun Works
321 W Ben White Blvd
17.38 mi
Guns & GunsmithsGun Safety & Marksmanship InstructionRifle & Pistol Ranges
Concealed Handgun Course for Two+3more
Michael Cargill (owner) and staff are extremely helpful and great supporters of our 2nd Amendment rights. You won't find sneering faces or condescending attitudes here. They provide access to more training courses than you will typically find for a small business. The gunsmithing services they offer are done quickly and competently. You'd be hard pressed to find anyone that will deliver work as promptly. Give these folks a try, you will not be disappointed!
22.Lone Star Gun Range
3795 Dry Creek Rd
14.84 mi
Guns & GunsmithsRifle & Pistol Ranges
We offer a family friendly gun/shooting range with over 200 firearms for rent. Come out and have fun and dont forget your valid ID. We are close to Austin. come out and spend a day in Lockhart to shoot and eat some award winning BBQ.
23.Feel Safe Gun Training
1206 Echo Meadow Ln
Spring Branch,TX
29.34 mi
Gun Safety & Marksmanship InstructionRifle & Pistol RangesSports Instruction
24.Castle Tactical
101 San Mateo Ter
Cedar Park,TX
35.86 mi
Gun Safety & Marksmanship InstructionRifle & Pistol RangesGuns & Gunsmiths
25.A Place To Shoot
13250 Pleasanton Rd Lot A
San Antonio,TX
62.13 mi
Guns & GunsmithsRifle & Pistol RangesAmmunition
I am attending a ladies class they are giving and they are wonderful. I had a fear of guns and was almost dreading the class, but our instructor has relieved all my fears and I actually enjoy the shooting. They are professional and take their training serious. I would recommend them to anyone!! Thank you A Place To Shoot!!Charlotte Loser
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
26.National Shooting Complex
5931 Roft Rd
San Antonio,TX
63.63 mi
Sports & Entertainment CentersRifle & Pistol RangesSports Clubs & Organizations
Red's Indoor Range
6200 W Highway 290, Austin, TX, 78735
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Pope Benedict XVI Quotes About DesireQuotes about: Desire
One of the promising indications of a renewal in the Church's missionary consciousness in recent decades, has been the growing desire of many lay men and women [...] to cooperate generously in the 'missio ad gentes.' As Vatican Council II stressed, the work of evangelization is a fundamental duty incumbent upon the whole People of God.
We are moving toward a dictatorship of relativism which does not recognize anything as definitive and has as its highest value one's own ego and one's own desires. The church needs to withstand the tides of trends and the latest novelties. We must become mature in this adult faith, we must guide the flock of Christ to this faith.
A dictatorship of relativism is being built that recognizes nothing as definite, and which leaves as the ultimate measure only one's ego and desires ... Having a clear faith, according to the credo of the church, is often labeled as fundamentalism. Yet relativism, that is, letting oneself being carried 'here and there by any wind of doctrine,' appears as the sole attitude good enough for modern times.


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Santa Barbara Symphony
2017-18 Season: Classic Beauty NEW
Season subscriptions now available for the 2017-18 season!Read More
Next: Mozart in Dance
2017-18 Season Opener with Mozart's "Requiem" featuring State Street Ballet and Symphony ChorusRead More
Symphony News
S.B. Symphony Announces 2017-18 SeasonRead More
The Symphony Music Education Center
Santa Barbara Youth Symphony
The Youth Symphony is an orchestra of 65-70 young musicians from Santa Barbara and Ventura Counties.
String Workshop - BRAVO!
The String Workshop meet weekly with an instructor in groups of 3-6 students.Read More
Concerts for Young People
The concert is designed to introduce classical music in a concert and ensemble setting.Read More
It is always a thrill to perform together and I look forward to the many more times of exciting musical adventures in the future"
The orchestra inspired me with their passion, virtuosity and blazing risk taking intensity."
I was overwhelmed by the world-class caliber of the Santa Barbara Symphony--making music with them was sheer pleasure"
2016-17 Symphony Sponsors


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We offer detail service options for basic protection (such as a wax or leather seat clean and condition); for car enthusiasts who want their car looking its best in preparation for a big date, selling their vehicle or just because; and for deep cleaning to mitigate for those occasions when "detail happens."
Hand applied polymer wax to give you superior paint protection and shine.
This service includes our Full Serve #1 Wash package.
Machine applied paint sealant for premium paint protection.
This service includes our Full Serve #1 Wash package.
Our top of the line interior detail service includes our Full Serve #1 Wash package to clean and protect the outside of your vehicle. Our team will then clean the interior with the following services:
- Compressed air used to reach dirt and dust in the cracks and crevices
- Thorough vacuum of mats, carpets, seats and storage area
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- Condition all vinyl or leather surfaces
- Carpet Shampoo
Our Executive Detail package is the complete clean for your entire vehicle. This package comes with our Interior Detail package and your choice of our Hand Applied Polymer Wax or Machine Applied Paint Sealant on the exterior.