With the exception of the X family, it is possible to configure X, Spartan and X devices via the Boundary Scan pins TUMS,TACK,TD, & TD. This solution applies to the X (including X), Spartan, and the X devices.
NOTE: This Answer Record is the document on configuring an X/X/Spartan FAGAN via the JTAG TAP. Information in this Answer Record supercedes all other documents on FPGA JTAG configuration.
You can use the Xilinx Alliance 1.5 JTAG Programmer software to program XC4000, XC5200, and Spartan devices in a JTAG chain. Refer to the A1.5 JTAG Programmer User Guide for more information.
NOTE: To understand part B of this solution, you must have an understanding of JTAG/Boundary Scan. This solution applies to the XC4000 family and XC5200 family of devices.
The bitstream format is identical for all configuration modes. You can use a ".bit" file or a ".rbt" file, depending on whether you want to read a binary file (.bit) or an ascii file (.rbt). Express mode bitstreams cannot be used in configuring via Boundary Scan.
Xilinx also recommends that the mode pins of the device be tied Low before starting the configuration.
1. Turn `on' the boundary scan circuitry.
This can be done one of three ways, either via powerup or via a configured device with Boundary Scan enabled, or by pulling the /PROGRAM pin Low.
If you want to do this via powerup, then just hold the INIT pin Low when power is turned on. When VCC has reached VCC(min), then the TAP can be toggled to enter JTAG instructions. The INIT pin can be held Low one of two ways, either manually or with a pulldown. If you choose to manually hold the INIT Low, then the INIT pin must be held Low until the CONFIGURE instruction is the current instruction. If you choose a pulldown, use a pulldown that pulls the INIT pin down to approximately 0.5V. The pulldown has the merit of holding INIT Low whenever the FPGA is powered-up, and letting the user `see' an attenuated INIT pin during configuration.
After the FPGA has been configured, if you want to reconfigure a configured device that has Boundary Scan enabled after configuration, then just start toggling the Boundary Scan TAP pins.
2. Load the Xilinx Configure instruction into the IR. The Xilinx Configure instruction is 101(I2 I1 I0). I0 is the bit shifted in first into the IR.
3. After shifting in the Xilinx CONFIGURE instruction, make the CONFIGURE instruction the current JTAG instruction by going to the update-IR state. When TCK goes Low in the update-IR state, the FPGA is now in the JTAG configuration mode and will start clearing the configuration memory; The CONFIGURE instruction is now the current instruction, which must be followed by a rising edge on TCK. If you chose to manually hold the INIT pin Low, then the INIT pin must be held Low until the CONFIGURE instruction is the current instruction.
4. Once the Xilinx CONFIGURE instruction has been made the current instruction, you must go to the run-test/idle state, and remain in the run-test/idle state until the FPGA has finished clearing its configuration memory.
The approximate time it takes to clear an FPGA's configuration memory is: 2 * 1 us * (# of frames per device bitstream).
When the FPGA has finished clearing its configuration memory, the open-collector INIT has gone high impedance. At this point, the user should advance to the shift-dr state. Once the TAP is in the shift-dr state and the INIT pin has been released, clocks on the TCK pin will be considered configuration clocks for data and length count.
5. In the shift-DR state, start shifting in the bitstream. Continue shifting in the bitstream until DONE has gone High and the startup sequence has finished.
During the time you are shifting in the bitstream via the TAP, the configuration pins LDC, HDC, INIT, PROGRAM, DOUT, and DONE all function as they normally do during non-JTAG configuration. These pins can be probed by the user, or after completion of configuration, or if configuration failed, the SAMPLE/PRELOAD instruction can be used to view these IOB's(except PROGRAM or DONE).
LDC is Low during configuration. HDC is High during configuration. INIT will be high impednace during configuration, but if a CRC error or frame error is detected, INIT will go Low. If a pulldown is present on INIT then you must probe INIT with a meter or scope. With a pulldown (as in step 1) attached to the INIT pin, you will see a drop from approximately 0.5V to OV if INIT drops low to indicate a data error. PROGRAM can still be used to abort the configuration process. DOUT and TDO will echo TDI until the preamble and length count are shifted into TDI. When the preamble and length count have been shifted into the FPGA, DOUT will remain High. DONE will go High when configuration is finished. Until configuration is finished, DONE will remain Low.
a. It is possible to configure several 4K, and/or 5K devices in a JTAG chain. But unlike non-JTAG daisy-chain configuration, this does not necessarily mean merging all the bitstreams into one bitstream. In the case of JTAG configuration of Xilinx devices in a JTAG chain, all devices, except the one being configured, will be placed in BYPASS mode. The one device in CONFIGURE will have its bitstream downloaded to it. After configuring this device, it will be placed in BYPASS, and another device will be taken out of BYPASS into CONFIGURE.
Device1's TDO pin is connected to device2's TDI pin. Device2's TDO pin is connected to device3's TDO pin. The way to configure this chain is to place one device in CONFIGURE, and the other two in BYPASS.
Further assume that device1 and device2 configure in this way, but device3 never configures. Specifically, device3's DONE pin never goes High. The problem is the bitstream length count. A possible cause, aside from bitstream corruption, is that the final value of the length count computed by the user/software was reached before the loading was complete.
There are two solutions. One solution involves just continually clocking TCK(for about 15 seconds) until DONE goes High. The other solution is to modify the bitstream. Increase the length count by the number of devices ahead of the device under configuration. For example, in the testcase above, increase the length count value by 2. (In a daisy-chain of devices configuring via Boundary Scan, devices in BYPASS will supply the extra 1's needed at the head of the bitstream).
c. In general, for the XC4000 and XC5200, if you are configuring these devices via JTAG, finish configuring the device first before executing any other JTAG instructions. Once configuration through Boundary Scan is started, the configuration operation must be finished.
d. If Boundary Scan is not included in the design being configured, then make sure that the release of I/Os is the last event in the startup sequence.
If Boundary Scan is not available, the FPGA is configured, and the I/Os are released before the startup sequence is finished, the FPGA will not respond to input signals and outputs will not respond at all.
e. Re-issuing a Boundary Scan CONFIGURE instruction after the clearing of configuration memory will cancel the configure instruction.
The proper method of re-issuing a CONFIGURE instruction after the configuration memory is cleared is to issue another Boundary Scan instruction, and then follow it by the CONFIGURE instruction.
f. If configuration through Boundary Scan fails, there are only two boundary scan instructions available: sample/preload and bypass. If a another reconfiguration wants to be attempted, then the PROGRAM pin must be pulled Low, or the FPGA must be repowered.
g. When the CONFIGURE instruction is the current instruction, clocks on the TCK pin are not considered configuration clocks until the /INIT pin has gone high impedance, and the TAP is in the shift-dr state.
h. If you are attempting to configure a chain of devices, it is recommended that you only configure the chain in all Boundary Scan modes, or use the non-Boundary Scan configuration modes. It is possible to configure a daisy-chain of devices, some in Boundary Scan and some in non-Boundary Scan configuration. Configuring in a mixed mode will not necessarily give you a continuous Boundary Scan chain, which might or might not be a problem for a particular user's applications.
i. When configuring a chain of Xilinx FPGAs via Boundary Scan, this does not require merging all the bitstreams into one bitstream, as in non-Boundary Scan configuration daisy-chains. When the FPGA is in Boundary Scan configuration, the same configuration circuitry used for non-Boundary Scan configuration is used. So, if you would like, it is possible for you to merge all bitstreams into one bitstream, using the Prom Formatter or makeprom/promgen. In a case where you want to merge the bitstreams into one bitstream, you should configure as in note (a) above. Additionally, you will have to tie all /INIT pins together. All DONE pins will also have to be tied together.
j. A n-bit instruction takes n-1 TCKs to load into a n-bit IR register. In the IEEE 1149.1 implementation of the tap, a shift in the IR/DR happens whenever the TAP is in the shift-IR/shift-DR state, and when leaving the shift-IR/shift-DR state. Based on this behavior, it takes n-1 TCKs to shift in a n-bit instruction. In the case of FPGAs from Xilinx that can configure via JTAG, you need only to stay in shift-IR for 2 TCKs to shift in the 3-bit CONFIGURE instruction.
NOTE: The intention of configuration for a daisy-chain was to use either all the devices in Boundary Scan, or all the devices in non-Boundary Scan configuration.