The Physical IP Division inside ARM creates Physical IPs of various types like Standard Cells, Memory, and Interface which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180nm to 10nm and research work on 7nm solutions is happening at various ARM design centres worldwide.
The candidate’s responsibility includes development, validation and maintenance of the Verilog simulation models for physical IP. Along with that candidate would have complete ownership of the DFT and ATPG models that are used in SoC flow. The role offers a potent opportunity to interact with accomplished circuit designers worldwide for design of best in class Physical IPs on the latest technologies nodes like 16nm, 10nm, 7nm etc. Candidate would serve as interface between the engineering teams, external customers and the third party EDA vendors to track resolution of issues associated with front end validation tools like Functional simulators, LEC, ATPG, STA etc.