Second implementation, counter B will get reset to zero with positive edge of reset and will stay there till reset is cleared. After reset is cleared (or 0) the counter will act as free running counter with positive edge of clock. So as long clock is running and reset is 0, counter will be incrementing till 2^8-1 (=127) value and then restart from 0.
Verilog RTL code examples for counter are discussed below. In this code we have implemented three free running counters with different reset scenarios.
First implementation, counter A is free running counter with positive edge of clock. So as long clock is running counter will be incrementing till 2^8-1 (=127) value and then restart from 0.
Third implementation, counter C will get reset to zero with negative edge of reset and will stay there till reset is set. After reset is set (or 1) the counter will act as free running counter with positive edge of clock. So as long clock is running and reset is 1, counter will be incrementing till 2^8-1 (=127) value and then restart from 0.
Verilog rtl code for above three counter are discussed below.