KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Univ Engn & Technol, Pakistan.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
Frequency signature chipless RFID tag based on spurline resonator is presented in this letter. Resonant response of spurline is explained by analyzing the surface current distribution. Chipless tag consists of a data encoding circuit and two cross polarised monopole antennas. The tag has a data capacity of 16 bits in the range 2.13 to 4.1 GHz. Data capacity of data encoding circuit is enhanced by repositioning the spurlines. The prototype of the tag is fabricated on FR4 substrate. Developed tag can be used for cost effective identification of items in the industry.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. State Key Laboratory of ASIC and System, Fudan University, Shanghai, China .
In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements.
The impact of device sizing on 1/f^2 phase noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarify the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 um to 280 um in the case of noisy tail current. If tail current is clean, the increase is only 4 dB. For 1/f^3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs. A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application. The previous oscillator optimization techniques have been applied in designing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic.
Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Sigma Delta modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages diliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network.
This paper presents a practical phase noise measurement approach, which only requires a spectrum analyzer and a computer, featuring fast setups, accurate results and low cost. Not like the conventional methods using extra assistant circuits to get rid of the frequency drift problem, this approach takes advantage of modern spectrum analyzers to acquire IQ data to calculate phase noise. The low quantization noise of the instrument makes this approach suitable for most CMOS integrated oscillators. The IQ data sampling time can be made small enough so that the frequency drift is not so obvious to harm the measurement accuracy. The experimental results clearly demonstrates the accuracy and the effectiveness of this method through measuring phase noise of two voltage controlled oscillators (VCOs) in 180nm CMOS process at 2.6 GHz and 3.0 GHz respectively.
An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.
A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.
In this paper, the temperature-dependent electronic properties of inorganic-organic hybrid halide perovskite (CH3NH3PbBr3) single crystals are investigated. The dynamic current-time measurement results at different temperatures directly demonstrate that the electrical properties of the perovskite single crystal are dependent on the work temperature. We find that the Poole-Frankel conduction mechanism fits the current-voltage curves at small bias voltage (0-1 V) under darkness, which is mainly attributed to the surface defect states. The capability of carriers de-trapping from defects varies with different work temperatures, resulting in an increased current as the temperature increases under both darkness and illumination. In addition, the different transient photocurrent responses of incident light at two wavelengths (470 nm, 550 nm) further confirm the existence of defect states on the single crystal surface. Published by AIP Publishing.
The development of highly conductive copper patterns on low-cost flexible substrates (PET, PEN, etc.) by inkjet printing is reported. Copper films were obtained from a metallo-organic decomposition (MOD) ink composed of a copper complex and suitable low-viscosity solvents. Upon heating the ink decomposed and was converted into metallic copper under nitrogen as inert atmosphere.Additionally samples were prepared using inkjet technology on various substrates. The required layer thickness for current conduction was assessed by printing on PET and sintering at 150 °C in a vacuum oven.
Radio frequency identification (RFID) and sensing are two key technologies enabling the Internet of Things (IoT). Development of RFID tags augmented with sensing capabilities (RFID sensor tags) would allow a variety of new applications, leading to a new paradigm of the IoT. Chipless RFID sensor technology offers a low-cost solution by eliminating the need of an integrated circuit (IC) chip, and is hence highly desired for many applications. On the other hand, printing technologies have revolutionized the world of electronics, enabling cost-effective manufacturing of large-area and flexible electronics. By means of printing technologies, chipless RFID sensor tags could be made flexible and lightweight at a very low cost, lending themselves to the realization of ubiquitous intelligence in the IoT era.
This thesis investigated three construction methods of printable chipless RFID humidity sensor tags, with focus on the incorporation of the sensing function. In the first method, wireless sensing based on backscatter modulation was separately realized by loading an antenna with a humidity-sensing resistor. An RFID sensor tag could then be constructed by combining the wireless sensor with a chipless RFID tag. In the second method, a chipless RFID sensor tag was built up by introducing a delay line between the antenna and the resistor. Based on time-domain reflectometry (TDR), the tag encoded ID in the delay time between its structural-mode and antenna-mode scattering pulse, and performed the sensing function by modulating the amplitude of the antenna-mode pulse.
In both of the above methods, a resistive-type humidity-sensing material was required. Multi-walled carbon nanotubes (MWCNTs) presented themselves as promising candidate due to their outstanding electrical, structural and mechanical properties. MWCNTs functionalized (f-MWCNTs) by acid treatment demonstrated high sensitivity and fast response to relative humidity (RH), owing to the presence of carboxylic acid groups. The f-MWCNTs also exhibited superior mechanical flexibility, as their resistance and sensitivity remained almost stable under either tensile or compressive stress. Moreover, an inkjet printing process was developed for the f-MWCNTs starting from ink formulation to device fabrication. By applying the f-MWCNTs, a flexible humidity sensor based on backscatter modulation was thereby presented. The operating frequency range of the sensor was significantly enhanced by adjusting the parasitic capacitance in the f-MWCNTs resistor. A fully-printed time-coded chipless RFID humidity sensor tag was also demonstrated. In addition, a multi-parameter sensor based on TDR was proposed.The sensor concept was verified by theoretical analysis and circuit simulation.
In the third method, frequency-spectrum signature was utilized considering its advantages such as coding capacity, miniaturization, and immunity to noise. As signal collision problem is inherently challenging in chipless RFID sensor systems, short-range identification and sensing applications are believed to embody the core values of the chipless RFID sensor technology. Therefore a chipless RFID humidity sensor tag based on near-field inductive coupling was proposed. The tag was composed of two planar inductor-capacitor (LC) resonators, one for identification, and the other one for sensing. Moreover, paper was proposed to serve as humidity-sensing substrate for the sensor resonator on accounts of its porous and absorptive features.
Both inkjet paper and ordinary packaging paper were studied. A commercial UV-coated packaging paper was proven to be a viable and more robust alternative to expensive inkjet paper as substrate for inkjet-printed metal conductors. The LC resonators printed on paper substrates showed excellent sensitivity and reasonable response time to humidity in terms of resonant frequency. Particularly, the resonator printed on the UV-coated packaging paper exhibited the largest sensitivity from 20% to 70% RH, demonstrating the possibilities of directly printing the sensor tag on traditional packages to realize intelligent packaging at an ultra-low cost.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China .
Printed interdigital capacitor DWI on paperboard is a promising solution for low-cost sensors in intelligent packaging applications. The currently available analytical models of multi-layered IDCs are targeted to those fabricated by conventional semiconductor process. For this reason, we have adapted two promising models and assessed their accuracies by comparison with experimental data. We modified these models by treating the paper as non-infinite thick substrate and taking the effect of printed metal thickness into account. The models are studied further to reveal the relationship between the response of capacitance change and various geometric parameters which enables a quick way of obtaining the optimum IDC structure design. The modified Gevorgian model fits our experimental data best, and the sensitivity of IDCs is largely affected by its spatial wavelength and the thickness of sensing material layer, while the finger number, length and metallization ratio have minor impact.