The 2050, a four Byte wide access to memory with a cycle time of 2 micro seconds. Storage size's of 64K through to a max. of 512K. Additional Large Capacity Storage (LCS) was also available. This offered 1 to 8 Meg of additional slower and cheaper core storage. Selector and Byte Multiplexer I/O channels were again internal and shared the Capacity Read Only Storage (CROS) with the CPU for micro-program control. A detailed description of the Standard Interface can be found elsewhere in the Museum. As with the 30 and 40 the consul was a 1052.
The model 50 also had voltage controls and basic memory diagnostics at the top of the front control panel. Many sites placed a cover over these controls to stop the temptation of the operators to fiddle. The memory diagnostics were quite basic, write all ones and write all zeros. One minor problem if you did not know it was that a write all zeroes really did mean that including parity. So if you left the machine after a right all zeros it would not IPL because of parity errors ( odd parity was the correct state within the 360 range).