Hook open drain "power good" to nSTATUS or nCONFIG?
Converting a ByteBlasterMV into a ByteBlaster II?
How to simulate these example CORDIC code?
Xilinx XST 8.2, Error on multi-source, bug?
Xilinx Virtex 5 ISERDES vs ISERDES_NODELAY: which is better for DDR?
Quartus II warning: "pass-through logic has been added"
gate count calculation in xilinx.
TI DSP soft core in Xilinx?