suitable for high efficiency, low current applications.
switching circuitry of the selected channel.
headroom on a per line basis.
‡ All voltages values are with respect to device GND terminal.
NOTE 1: Synchronized PWM frequency equal to one eighth of SCLK frequency.
PMOSFETs into the fully on pass-through or bypass mode to pass the input voltage to any output.
operating, all four outputs are disabled, the DACs are set to zero volts, and the programming registers are reset.
pass-through mode) the DAC continues to increment in 200-mV steps between 13.1 V and the fully on state.
0 V to 15 V, and a maximum transition time between max and min regulation voltages (7.5 V, 13.1 V) of 4 ms.
During this transition period, the channel status may be read via the 4-wire serial port using the read protocol.
The data returned is nonzero while channel is transitioning.
The TPS54900 has a free-running internal ramp oscillator that operates at a nominal frequency of 450 kHz.
begin regulating until the EN pin is pulled above VIH.
four channels step up to VIN in 200-mV increments.
pass-through mode, the overcurrent detection remains active and the hiccup behavior is unchanged.
Thermal shutdown disables the controller if the junction temperature exceeds 150°C. The hysteresis is 10°C.
temperature, it restarts and returns to the programmed target voltages.
are data. Refer to the table titled Serial Command Bit Assignments.
The data field, D7–D0, is used to program output voltage levels and control TPS54900 operation.
The pass through mode may be used to force a channel’s PMOSFETs to remain in the fully enhanced on state.
considered to conserve additional power.
returning to normal operation are not critical.
voltage and start them up at the same time.
cannot be given without powering down the TPS54900 and going through a complete restart sequence.
Not Ready) by returning a non-zero data value. When SDO returns a value of 00h, the channel is in regulation.
be performed in qualifying component and layout decisions.
and routed directly to the TPS54900 VIN and GND pins to minimize trace inductance.
the diodes to the appropriate TPS54900 pins. The EVM layout uses this approach.