I am a first year Graduate Student pursuing Masters from the University of Wisconsin-Madison. I graduated from BITS Pilani in Computer Science.
I have a three year work experience at NVIDIA and was involved in projects including 3D Vision Pro and NVIDIA Grid vGPU. My areas of interest include Virtualization, Systems, Networking and Artificial Intelligence.
I am currently part of a research project to profile the impact on an enterprise network of deploying the network middleboxes on cloud.
Implemented the NVIDIA driver changes for a threefold increase in scalability in terms of the maximum number of vGPU VMs supported on a system.
Improved the virtual machine graphics performance by implementing an optimized guest physical to machine page translation.
Designed and implemented the infrastructure for automated building of vGPU Xenserver driver.
Ported the Logging mechanism of eclipse's Real-Time Software Component (RTSC) to C.
Incorporated additional features based on the requirements from Texas Instruments in thelogging mechanisms.
Minimize the data copying between middleboxes.
Optimize the data transfer time between the middleboxes.
Minimize the computation on a packet as it pass through the middlebox stack.
Load balancing of the computations for the network packets.
Data security by restricting the communication to only a set of authorized middleboxes.
SWAMP is a framework to perform analysis on the user source code and seek for potential security vulnerabilities. I am working to create a plugin for the Eclipse IDE. The plugin will allow the user to ship their project (C/C++, JAVA and Python) from the workspace to the SWAMP cloud infrastructure for analysis. The development effort is in Java.
Motivation: Source code size reduction for embedded systems due to the lack of memory resources.
​Procedural Abstraction: Code is searched for matching sequences and those sequences are then replaced by a single procedure resulting in lower program size.
Additional Compression: We observed that there is an opportunity for further compression by identifying the sequence of instructions that matches only partially (in the opcode part). We proposed a new compression algorithm to seek for repeating sequences of opcodes in the code section. Since the probability of ﬁnding a matching sequence of opcode is greater, it is possible to ﬁnd sequences that are frequent and large in size. The repeating sequences are replaced by a marker instruction and are divided into the opcode and non-opcode parts. The code size reduction is obtained by saving only one copy of the opcode part of the repeating sequence and discarding others.
Opportunity: When tested on multiple small ARMv6 programs, we found out that there is an opportunity for compression in the range of 3-5%.
Proposed a mechanism to virtualize the various GPU engines to be used as independent devices by the Virtual Machines (VM).
Suggested the design architecture to support the feature. The proposal is to build a software unit to trap the I/O requests from the VM corresponding to their GPU engine devices, and manage the execution on the real hardware GPU.