Cadence® QuickView Signoff Data Analysis Environment is the industry’s production-proven full-chip high-performance, high-capacity data-viewing, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data.
The QuickView Signoff Data Analysis Environment is an easy-to-use, high-performance, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The QuickView Signoff Data Analysis Environment loads large layouts (GDSII, OASIS®, LEF/DEF, and manufacturing formats) in seconds, and provides a rich set of debugging features, including net connectivity tracing, visualization, overlay, and GDSII/OASIS® editing.
After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact.