>>>> Up/down coounter on the index.
>>>> It can be 100% digital, and the tracking speed becomes the PLL-LPF.
This is what the 74xx297 is doing with a minimum logic count.
(yeah, yeah I know, we have a new result after every cycle).
> then loads the 2KHz divider.
> Keeping to 0.1%, 2KHz to 0.1% is 2MHz Clock, with ~1000 divider values.
> Table/ROM has 20 entries, of 11 bit binary values.
> Count the 2KHz clocks you actually get, in a 50Hz period.
> is BELOW 40, decrement the Up/Dn counter.
Sounds very much like 74xx297.
> that. You also want to freqency lock, to have a known phase stepping.
receiveing according to TTL specs?
> > Finally after two weeks I have configured the board for the first time.
> > web site and installed SP 3. I am able to generate ACE files that work.
> > should be asserted for those pins?
> I'm glad that you are moving forward with your design work.
> IOs on the headers are 2.5V (or 3.3V if you move a jumper).
> a constant (somewhat delayed) phase relationship to the original.
> to the desired phase.
would not need a parallel port to interface it?
>>a constant (somewhat delayed) phase relationship to the original.
otherwise just wait for soeone to invent a time machine.
> called FLL (Frequeny lock).
it is in frequency lock, but not phase lock.
some edge of an other.
You can do it both with a 'phase comparator', but there is more to it.
This in case mechanical servos for example [for] video head placement.
Sometimes multiple stages are used to get ever better precision.
>where the punches start flying!
used in order to know what timing to expect.
and the other one will act on the falling edges.
IOB_DELAY on or off for the input path.
> This part is not a problem at all.
> there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
> chance accordingly to stay in lock.
probably the easiest way to generate the locked 2kHz.
in software if you have a processor available.
Subject: Re: Hardware book like "Code Complete"?
on larger projects, the performance difference is huge.
> > clock, which means they are the registered (delayed) values.
> > Note that both out1 and out2 have the same cycle-accurate behavior.
> > and use out1 for both.
> would not need a parallel port to interface it?
push buttons, toggle buttons and pulse chains for easy visuals.
will for capturing large amounts of data.
> Just curious: How would one connect two PCIe 4x ports in one card?
> Or would PICe 8x (or PCI 16x) be a better way to go?
> often have tens of DSP's and FPGA's on board.
much. This is where "reconfigurable" computing really comes into play.
analysis requires some significant DSP code. Don't code that in FPGA!
Use the FPGA for what it is good at (i.e., pipelined DCT).
Wasn't it already this way?
> - The first component is an JKFF based phase detector.
> modulus of I/D counter (2KHz DCO) while carry pulse increases it by 1.
> one 50Hz period and they cancel each other.
> this way, period of 2kHz pulses is adjusted according to 50Hz input.
> - N-Counter which devides 2Khz clock by 40.
> The only parameter that I can play with is the modulus of K counter.
Hmm, this should be enought.
clocks. Which are 1/3000 of a 2 kHz period.
> number of 2kHz pulses as 40 in each 50Hz period.
Subject: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
> functional model" in the "Design Utilities" in the process window.
> (verilog) or architecture (VHDL).
> choose the needed generted by you symbol.
> I hope that this helped!
However, I have these two schematics in separate projects.
How do I import my building block into my larger project?
Can I create a symbol library of my building blocks?
> it is in frequency lock, but not phase lock.
> some edge of an other.
in language. Sounds like the common latch/flipflop mixup.
Can you explain further about a full huffman analysis for JPEG?
> > often have tens of DSP's and FPGA's on board.
> > a reasonable solution.
> much. This is where "reconfigurable" computing really comes into play.
> analysis requires some significant DSP code. Don't code that in FPGA!
> Use the FPGA for what it is good at (i.e., pipelined DCT).
fully configurable MB-uClinux and PPC-linux.
What about the memory management in PPC-linux?
What can the PPC-linux do besides networking (multithreading...)?
driver made for normal linux (MV or tarball 2.16.)?
> > have good info on this matter.
> > designed for Mini-Module.
> so it would work on V4MM also.
>> Just curious: How would one connect two PCIe 4x ports in one card?
>> Or would PICe 8x (or PCI 16x) be a better way to go?
require more than one slot to implement more than one PCIe.
cards.  It's a pretty fundamental change from the "one slot, one port"
> data stream 32 bit.
bits of register address, you may also want to check this).
CMD addr + RCRC command).
clear from the app notes).
>>>>> Up/down coounter on the index.
>>>>> It can be 100% digital, and the tracking speed becomes the PLL-LPF.
> This is what the 74xx297 is doing with a minimum logic count.
It is close, but differs in the phase comparison area.
Something that uses a Phase detector, has a lock time.
for the lock to occur ?
> (yeah, yeah I know, we have a new result after every cycle).
I chose a simple example point.
>> then loads the 2KHz divider.
>> Keeping to 0.1%, 2KHz to 0.1% is 2MHz Clock, with ~1000 divider values.
>> Table/ROM has 20 entries, of 11 bit binary values.
>> Count the 2KHz clocks you actually get, in a 50Hz period.
>> is BELOW 40, decrement the Up/Dn counter.
> Sounds very much like 74xx297.
>> that. You also want to freqency lock, to have a known phase stepping.
You can have Frequency lock, and NOT have Phase lock.
> It is close, but differs in the phase comparison area.
> (next cycle) capture time.
> Something that uses a Phase detector, has a lock time.
> for the lock to occur ?
>> so called FLL (Frequeny lock).
> You can have Frequency lock, and NOT have Phase lock.
(fixed) phase relation of other than zero degree is a phase lock.
> >>a constant (somewhat delayed) phase relationship to the original.
> >>to the desired phase.
> otherwise just wait for soeone to invent a time machine.
>>> integral/deviation of each other.
>> You can have Frequency lock, and NOT have Phase lock.
> (fixed) phase relation of other than zero degree is a phase lock.
angle). The offset may not be moving, but it is not a phase lock.
> fully configurable MB-uClinux and PPC-linux.
> in a virtual machine.
> What about the memory management in PPC-linux?
> What can the PPC-linux do besides networking (multithreading...)?
> driver made for normal linux (MV or tarball 2.16.)?