This product is included in the software package SP850.
Can be used with the same operability as that of the debugger for V850 MCU.
The data generated via 0/1 logic and timing chart can be entered while the program is being simulated.
Execution speed required for accurately simulating pipeline operation can be estimated on the host machine.
Can specify the peripheral I/O register status and generate interrupt request or transfer data to the memory at a desired timing when the specified status is encountered (Peripheral I/O register event & action function).
Supports the construction of pseudo-target system and input/output operation using non-MCU devices.