How to represent a graph in memory is a fundamental data structuring problem. In the usual representations, a graph is stored by representing explicitly all vertices and all edges. The names (labels) assigned to vertices are used only to encode the edges and betray nothing about the structure of the graph itself and hence are a "waste" of space. In this context, we present a general framework for labeling any graph so that adjacency between any two given vertices can be tested in constant time. The labeling schema assigns to each vertex a of a general graph a O(delta(x) log(3) n) bit label, where n is the number of vertices and delta(x) is x's degree. The adjacency test can be performed in 5 steps and the schema can be computed in polynomial time. This representation strictly contrasts with usual representations, i.e. adjacency matrix and adjacency list representations, which require O(n log n) bit label per vertex and constant time adjacency test, and O(delta(x) log n) bit label per vertex and O(log delta(x)) steps to test adjacency, respectively. Additionally, the labeling schema is implicit, that is: no pointers are used.

Talamo, M., & Vocca, P. (1998). Compact implicit representation of graphs (extended abstract). In GRAPH-THEORETIC CONCEPTS IN COMPUTER SCIENCE (pp.164-176). BERLIN : SPRINGER-VERLAG BERLIN.

### Compact implicit representation of graphs (extended abstract)

#### Abstract

How to represent a graph in memory is a fundamental data structuring problem. In the usual representations, a graph is stored by representing explicitly all vertices and all edges. The names (labels) assigned to vertices are used only to encode the edges and betray nothing about the structure of the graph itself and hence are a "waste" of space. In this context, we present a general framework for labeling any graph so that adjacency between any two given vertices can be tested in constant time. The labeling schema assigns to each vertex a of a general graph a O(delta(x) log(3) n) bit label, where n is the number of vertices and delta(x) is x's degree. The adjacency test can be performed in 5 steps and the schema can be computed in polynomial time. This representation strictly contrasts with usual representations, i.e. adjacency matrix and adjacency list representations, which require O(n log n) bit label per vertex and constant time adjacency test, and O(delta(x) log n) bit label per vertex and O(log delta(x)) steps to test adjacency, respectively. Additionally, the labeling schema is implicit, that is: no pointers are used.
##### Scheda breve Scheda completa Scheda completa (DC)
24th International Workshop on Graph-Theoretic Concepts in Computer Science
SMOLENICE CASTLE, SLOVAKIA
JUN 18-20, 1998
Slovak Acad Comp Sci, Dept Comp Sci I RWTH Aachen, Slovak Soc Comp Sci
Rilevanza internazionale
Settore INF/01 - Informatica
English
NETWORKS; SEARCH
13
Intervento a convegno
Talamo, M., & Vocca, P. (1998). Compact implicit representation of graphs (extended abstract). In GRAPH-THEORETIC CONCEPTS IN COMPUTER SCIENCE (pp.164-176). BERLIN : SPRINGER-VERLAG BERLIN.
Talamo, M; Vocca, P
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Utilizza questo identificativo per citare o creare un link a questo documento: `http://hdl.handle.net/2108/41894`
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{"ft_lang_label":"__label__en","ft_lang_prob":0.86932456,"math_prob":0.7466067,"size":2676,"snap":"2022-27-2022-33","text_gpt3_token_len":578,"char_repetition_ratio":0.14371258,"word_repetition_ratio":0.8752941,"special_character_ratio":0.20889387,"punctuation_ratio":0.10869565,"nsfw_num_words":0,"has_unicode_error":false,"math_prob_llama3":0.98387235,"pos_list":[0,1,2,3,4,5,6],"im_url_duplicate_count":[null,null,null,null,null,null,null],"WARC_HEADER":"{\"WARC-Type\":\"response\",\"WARC-Date\":\"2022-08-11T16:53:42Z\",\"WARC-Record-ID\":\"<urn:uuid:46d4af3d-1df9-41e2-b9bb-d99798f85e62>\",\"Content-Length\":\"52654\",\"Content-Type\":\"application/http; msgtype=response\",\"WARC-Warcinfo-ID\":\"<urn:uuid:b0d469cb-233b-416e-8705-e632703614fa>\",\"WARC-Concurrent-To\":\"<urn:uuid:c34a3968-86aa-43d1-b287-777a35d4d01b>\",\"WARC-IP-Address\":\"130.186.29.4\",\"WARC-Target-URI\":\"https://art.torvergata.it/handle/2108/41894\",\"WARC-Payload-Digest\":\"sha1:YATGZVEXS43RVUGCHJW2IUN5ISXTPZE5\",\"WARC-Block-Digest\":\"sha1:YAON65DWFZ3RH47FMYOUQVAEKHWUG7OR\",\"WARC-Identified-Payload-Type\":\"text/html\",\"warc_filename\":\"/cc_download/warc_2022/CC-MAIN-2022-33/CC-MAIN-2022-33_segments_1659882571483.70_warc_CC-MAIN-20220811164257-20220811194257-00081.warc.gz\"}"}