# Verilog Binary to gray code conversion example.

A function is discussed below to convert binary number to gray code number. The function is then used in combinational RTL logic. This kind of conversions are widely used in digital design to implement asynchronous clock crossing interfaces. The gray code primarily used to convert counter values before sending across the async interface. With this technique `only one bit` is allowed to change and it limits the error to +/- 1.

Complete logic of program is to generate a `binary counter` and then encode it into gray counter.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

/*Logic to convert binary numbers into Gray coded binary numbers is implemented in the following Verilog Code.
*/
module binary2gray();
reg clk;
reg rstn;
reg [5:0] counter_binary, counter_binary_reg, counter_gray, counter_gray_reg;
integer count, file_wr;

/* Initial block to generate clock and reset */
initial  begin
clk = 0; rstn = 0;  #100 rstn = 1;
forever begin
#10 clk = !clk;
end end

/* Synchronous Logic for registering the data and incrementing the counter for binary data */
always @ (posedge clk or negedge rstn)
begin
if (!rstn) begin
counter_binary_reg <= 'b0;
counter_gray_reg <= 'b0;  end
else begin
counter_binary_reg <= counter_binary + 1;
counter_gray_reg <= counter_gray;
\$display("binary number= 6'b%b : gray en-coded binary number = 6'b%b", counter_binary_reg, counter_gray_reg);   end end

/* Logic is to get Gray code from Binary code */
function[5:0] binary2gray ;
input[5:0] value;
integer i;
begin
binary2gray = value;
for (i=5; i>0; i = i - 1)
binary2gray[i-1] = value[i] ^ value[- 1];
end
endfunction

/* Get gray encoded output */
always @(*)
begin
counter_gray = counter_gray_reg;
counter_binary = counter_binary_reg;
counter_gray = binary2gray(counter_binary_reg); end
endmodule

Tutorials `@fullchipdesign.com`

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

Hope you liked! this page. Don't forgot to access relevant `previous and next sections ` with links below.
{"ft_lang_label":"__label__en","ft_lang_prob":0.82352537,"math_prob":0.8199598,"size":568,"snap":"2022-05-2022-21","text_gpt3_token_len":106,"char_repetition_ratio":0.12588653,"word_repetition_ratio":0.0,"special_character_ratio":0.17957747,"punctuation_ratio":0.060606062,"nsfw_num_words":0,"has_unicode_error":false,"math_prob_llama3":0.9865346,"pos_list":[0],"im_url_duplicate_count":[null],"WARC_HEADER":"{\"WARC-Type\":\"response\",\"WARC-Date\":\"2022-05-29T06:15:58Z\",\"WARC-Record-ID\":\"<urn:uuid:9264883a-eb09-4a88-8f9a-e15fb3965aff>\",\"Content-Length\":\"16161\",\"Content-Type\":\"application/http; msgtype=response\",\"WARC-Warcinfo-ID\":\"<urn:uuid:1676afec-2b68-462f-b4e3-ce0e141711d8>\",\"WARC-Concurrent-To\":\"<urn:uuid:9f17d045-c11c-4d8a-a5cf-66c6fa5b9270>\",\"WARC-IP-Address\":\"35.173.69.207\",\"WARC-Target-URI\":\"https://www.fullchipdesign.com/veriloggray.htm\",\"WARC-Payload-Digest\":\"sha1:IKLN36CNFN6LOH2ETWRD3XYFF66ZKMAM\",\"WARC-Block-Digest\":\"sha1:BBNL56KB6LXHQA7UPJSY6BQ2BIZW6236\",\"WARC-Identified-Payload-Type\":\"text/html\",\"warc_filename\":\"/cc_download/warc_2022/CC-MAIN-2022-21/CC-MAIN-2022-21_segments_1652663039492.94_warc_CC-MAIN-20220529041832-20220529071832-00184.warc.gz\"}"}