### Logic and Digital System Design (CS 303)

2021 Fall
Faculty of Engineering and Natural Sciences
Computer Sci.& Eng.(CS)
4
8.00 / 7.00 ECTS (for students admitted in the 2013-14 Academic Year or following years)
Erdinç Öztürk -erdinco@sabanciuniv.edu,
English
--
Formal lecture,Interactive lecture,Recitation,Laboratory

### CONTENT

Number systems and conversion, boolean algebra, the assetion level concept; minterm and maxterm expensions, Karnaugh maps,and Quine McCluskey minimization, combinatorial logic circuit design, NAND and NOR gate based design. State machines and sequential circuits flip-flops, minimization of state tables, state assignment. Higher level digital system desin using SSI-MSI blocks such multiplexers/decoders, adders, memory and programmable . gate arrays;bus oriented systems. Asynchronous sequential circuits, flow tables, timing hazards.

### OBJECTIVE

To develop the engineering skills for designing digital systems.

### LEARNING OUTCOME

Explain the reasons for using different formats to represent numerical data and how negative integers are stored in sign-magnitude and two?s-complement representation.
Convert numerical data from one format or base to another.
Describe the internal representation of nonnumeric data.
Demonstrate an understanding of the basic building blocks such as logic gates, flip-flops, counters, registers, and programmable logic devices
Demonstrate the ability to minimize logic expressions, and express Boolean functions in different forms and an understanding of the physical considerations of logic elements such as gate delays.
Use mathematical expressions to describe the functions of simple combinational and sequential circuits.
Design combinational and sequential circuits using the fundamental building blocks given the verbal description of the circuits.
Construct a finite state diagram to capture state transition in a sequential circuit.
Demonstrate an understanding of digital systems expressed in register transfer level.

### ASSESSMENT METHODS and CRITERIA

 Percentage (%) Final 35 Midterm 35 Assignment 15 Group Project 15
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