I am trying to understand the difference between byte addressing and word addressing.

A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB.

No of sets in the cache $$= (16 * 1024) / (4 * 8 * 4) = 2^7$$

If word addressing is used :

Block offset $$= 3 \ bits$$

Since PAS is $$4 \ GB$$, total no of addresses = $$2^{32} / 2^2 = 2^{30}$$

So, total address bits $$= 30\ bits$$

Tag bits : $$20 \ bits$$
Set bits : $$7 \ bits$$
Block offset bits : $$3 \ bits$$

Now, suppose the CPU wants to access the 3rd byte of a particular word.

1. The cache controller will use the $$7 \ bits$$ set-field to index into a set and then comparing the higher $$20\ bits$$ tag-field with all of the $$4$$ blocks in the set. If a match is found, then cache hit occurs and the lower $$3 \ bits$$ block offset to put one of the word out of the $$8$$ words in one of the general purpose register. The CPU then extracts the 3rd byte from the word and perform the operation.
2. If tags are unmatched, then cache miss occurs, a memory read signal is sent and due to spatial locality of reference, a block containing the word is transferred into the cache.

If the CPU is byte addressable:

Total address bits $$=32$$

Address Structure : Tag bits : $$20 \ bits$$
Set bits : $$7 \ bits$$
Block offset bits : $$5 \ bits$$

If the CPU wants to access 3rd byte of a word:

1. Same as in Step 1 of word addressable, but the CPU now can directly address the 3rd byte of the word, using the lower $$2 \ bits$$ byte offset. However, I'm confused how that would happen. Since, the CPU register size has a width of 1 word, similar to the word addressing, one word out of the 8 words in the block will be transferred to the register. But how would the "byte extracting" step be easier here? And why do we call it byte addressing if still we are actually addressing a word?
2. Same as in Step 2 of word-addressing. Block of data will be transferred from the memory to the cache in case of cache miss.

Also, this answer says that physical memory is always byte addressable. Now, what is the difference between the addressablity of the memory and addressablity of the CPU architecture?

Word addressing means that, the number of lines in the address bus in the processor is lesser than the number of bits in the word itself.

Lets say we have a 4 byte word. (32 bit address space)

If this machine is byte addressable, then the address bus of the CPU will have 32 lines, which enables it to access each byte in memory.

If this machine is word addressable, then the address bus of the CPU will have 30 lines ($$32 - log_{2}4 =30$$), which enables it to access memory ONLY in words/chunks of 4 bytes and that too from addresses which are a multiple of the wordsize.

Now if you ask the CPU to fetch a byte from a particular address, it will first drop the 2 least significant bits(by drop i mean overwrite them with 0's) of the address, fetch a word from the resulting address and return a byte using the 2 least significant bits as an offset within the fetched word.

This causes memory access time to increase, since the CPU has to spend more time modifying the address and processing the fetched word. But it also helps reduce hardware cost since the complexity of the circuits is reduced due to the reduction in address bus lines.

However, this overhead never arises in a byte addressable machine, hence 'byte extracting' is easier.

• I understand what you're saying. But what'll happen in case of byte addressing? Suppose the CPU needs the 3rd byte of the word. It will send the 32 bit address with the least 2 significant bit set to 10, right? But then how will it store the byte given that it uses register of 1 word width? Won't the CPU in this case also fetch the word from the cache and store it into it's register? Sep 10, 2019 at 10:12
• For you 1st question: Byte addressing CPUs have separate write instructions based on the size of the data to be written. One for a byte, one for a double byte, one for a quad byte, one for a word, etc.(Actually any CPU has separate write instructions each of the for various supported sizes of data to be written) Concerning byte writing, the byte to be written is usually stored in the 8 LSBs of the register, then the write instruction for a byte is executed. This causes ONLY the 8 LSB bits of the register to be loaded on the data bus, and only one byte at the address in memory is modified. Sep 10, 2019 at 17:08
• I didn't understand your 2nd question. Could you elaborate. Sep 10, 2019 at 17:33
• I suppose same thing happens for reading a byte in a byte addressable machine, right? For example, let's say there's an character array char arr and the CPU wants to read the 3rd character, i.e. arr. Then after accessing the byte using 32 bit address, it will store it in the 8 LSBs of the register. But in the case of word addressable, the CPU will first calculate the address of the word to which the 3rd byte belongs(i.e overwrite the 2 LSBs with 0) and fetch the word in it's register. After that it will use the byte offset to get the required byte. Is this correct? Sep 11, 2019 at 3:21
• Many thanks. I would request you to put all these together in the original answer so that it might help any future reader. Sep 11, 2019 at 18:01
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