# A Pipelined Converter (AD876)

The AD876, a CMOS A/D converter circuit, uses switched-capacitor techniques to combine low cost and low power. Figure B1 shows a conceptual block diagram of the AD876. The input is sampled at the front-end by a sample-and-hold (S/H) circuit, which also provides single-ended-to-differential conversion for the A/D's differential circuitry. The device's overall dynamic performance and wideband noise are established at the S/H stage. The conversion, accomplished by a 4-stage pipeline, is iterated by several subblocks that refine the conversion with increasing resolution as they pass the residues from stage to stage.

Each stage performs a flash A/D conversion; converts the result back to analog (D/A), subtracts it from its input, amplifies and holds the difference for the next stage. The digital results are combined via correction logic; and data is converted at the clock rate (but the output at any specific instant has a latency of 3.5 clock cycles (i.e., it represents a 3.5-cycle-earlier input value).

Following each A/D conversion step, the D/A and other analog functions are all implemented in a compact and efficient switched-capacitor circuit. The functions of this circuit, basically a multiplying D/A converter (MDAC), are shown within dashed blocks in Figure B1. Taking a closer look at the MDAC circuit, Figure B2 illustrates its basic operation. When CLOCK is low, the input voltage, VIN, is sampled onto an array of identically sized unit capacitors (amplifier gain=1). When CLOCK goes high, a feedback capacitor is connected around the amplifier. The charge on all the capacitors in the input array is transferred onto the feedback capacitor, resulting in a voltage gain that is the ratio of the number of capacitors in the input array to the feedback cap. At the same time, the input array capacitors are switched to either the positive or negative reference (as selected by the digital results of the A/D conversion), and their sum is thus subtracted from the VIN sum, leaving at the amplifier's output an amplified residue, which is held as an input to the next stage. Thus the gain, D/A, differencing, and S/H have all been wrapped up into one block.

Like the MDAC, the input S/H is implemented as a switched-capacitor circuit, as shown (single-ended for simplicity) in Figure B3. When CLOCK is low, the hold capacitor is connected to the input and is charged up to the input voltage by an input driver (typically an op amp such as the AD8011). When CLOCK goes high, the cap is disconnected from the input and fed around to the output of the amplifier. Since the node that connects to the input of the op amp is now floating, no charge can escape and the input voltage is held. When CLOCK goes low again, the cap is reconnected to the input. If there is a difference between the voltage already stored on the hold capacitor and the voltage at the AD876 input, the capacitor is charged to the new value (after a transient glitch which the op amp must handle, as noted in Applications).

The reference inputs are being switched in the same way as the inputs. Care must be taken to minimize transients in the reference circuit, for example, by using external capacitors to source or sink transient reference currents. Note also that the AD876 differential input range (after the S/H) actually spans between two references, the bottom (or 'negative') reference and top (or 'positive') reference, to accommodate single +5-V-supply systems.
{"ft_lang_label":"__label__en","ft_lang_prob":0.91792554,"math_prob":0.90899354,"size":3460,"snap":"2021-21-2021-25","text_gpt3_token_len":738,"char_repetition_ratio":0.14293982,"word_repetition_ratio":0.007067138,"special_character_ratio":0.20953757,"punctuation_ratio":0.09865471,"nsfw_num_words":0,"has_unicode_error":false,"math_prob_llama3":0.96800315,"pos_list":[0],"im_url_duplicate_count":[null],"WARC_HEADER":"{\"WARC-Type\":\"response\",\"WARC-Date\":\"2021-06-17T23:58:36Z\",\"WARC-Record-ID\":\"<urn:uuid:f8f7cd9b-ee14-47bd-841e-f81fe1ebdffb>\",\"Content-Length\":\"62813\",\"Content-Type\":\"application/http; msgtype=response\",\"WARC-Warcinfo-ID\":\"<urn:uuid:f50830d3-d16e-4f87-8d7c-00f20f19c0c3>\",\"WARC-Concurrent-To\":\"<urn:uuid:3ea00ace-4605-4f0b-b03b-2e2cd8eb903a>\",\"WARC-IP-Address\":\"104.68.247.115\",\"WARC-Target-URI\":\"https://www.analog.com/ru/analog-dialogue/articles/a-pipelined-converter.html\",\"WARC-Payload-Digest\":\"sha1:6HYV23NMFXUDHONAZDRWEUIYDRBTZIQ4\",\"WARC-Block-Digest\":\"sha1:4UDDAN3UJUJK44W6ZTN2PNOSHNOEZOAF\",\"WARC-Identified-Payload-Type\":\"text/html\",\"warc_filename\":\"/cc_download/warc_2021/CC-MAIN-2021-25/CC-MAIN-2021-25_segments_1623487634576.73_warc_CC-MAIN-20210617222646-20210618012646-00321.warc.gz\"}"}