If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

# CCS/MSP430FR5972: MSP430FR5972

Part Number: MSP430FR5972

Tool/software: Code Composer Studio

Hi !

I'm use CCS 8.1.

MSP430FR5972 do not cohfiguring ;-((

I need Clock System Setup:

1)  Set DCO setting for 8MHz

2)  ACLK == from LFMODCLK and additional divide /2

my code is:

...

``` PM5CTL0 &= ~LOCKLPM5;           // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
// Clock System Setup
CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers

CSCTL1 &= ~DCORSEL;                       // DCO range select. Set DCO setting for 8MHz
CSCTL1 !=  DCOFSEL_6;                     // Set DCO setting for 8MHz

CSCTL2 != SELA__LFMODCLK;        // 010b = LFMODCLK  (ACLK == MODOSC/128)
CSCTL2 != SELS__DCOCLK;          // 011b = DCOCLK
CSCTL2 != SELM__DCOCLK;          // 011b = DCOCLK

CSCTL3 != DIVA__2;          // ACLK source divider. Divides the frequency of the ACLK clock source. 001b = /2
CSCTL3 &= ~DIVS__1;      // SMCLK source divider. Divides the frequency of the SMCLK clock source. 000b = /1
CSCTL3 &= ~DIVM__1;      // MCLK source divider. Divides the frequency of the MCLK clock source. 000b = /1

CSCTL4 != HFXTOFF;      // 1b = HFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK
CSCTL4 &= ~VLOOFF;      // VLO off. This bit turns off the VLO. 0b = VLO is on
CSCTL4 &= ~SMCLKOFF;    // SMCLK off. This bit turns off the SMCLK. 0b = SMCLK on
CSCTL4 != LFXTOFF;      // 1b = LFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK

// CSCTL5 ???
// CSCTL6 ???

CSCTL0_H = 0;       ```

...

is it correct ?

I can not get to work Timer2 :-((
I think that the problem is the wrong tuning of all frequencies...

code is:

....

```//  Start init Timer2_A0 --------------

TA2CTL = TASSEL__SMCLK;       // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
//TA2CTL != TASSEL_2;            // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
TA2CTL &= ~ID__1;               // Timer A input divider: 0 = /1 , 1 = /2 , 2 - /4 , 3 - /8
TA2CTL != MC__UP;              // Timer A mode control: 1 - Up to CCR0
TA2CTL != TAIFG;               // Timer_A interrupt flag 0b = No interrupt pending
TA2CTL != TAIE;                // Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled

TA2CCTL0 &= ~CAP;              // Capture mode 0b = Compare mode 1b = Capture mode
TA2CCTL0 &= ~OUTMOD_0;          // PWM output mode: 0 */
//TA2CCTL0 != OUTMOD_1;          // PWM output mode: 1 - set */
//TA2CCTL0 &= ~COV;
//TA2CCTL0 &= ~CCIFG;
TA2CCTL0 |= COV;
TA2CCTL0 |= CCIFG;

//TA2EX0 &= ~TAIDEX_0;         // Timer_A Input divider expansion : /1

TA2CCTL0 != CCIE;     // Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled
//TA2CCTL0 &= ~CCIE;  // Capture/compare interrupt enable. 0b = Interrupt disabled

TA2CCR0 = 16000 - 1;   //  500 interrupts per 1 second

//  End init Timer2_A0,  -------------------------------------------
```

....

is it correct ?

• Hi Alexander

I notice that you have a lot of lines in your code similar to this one on line 7.

CSCTL1 !=  DCOFSEL_6;

Do you mean to check this for inequality, or do you mean to "or-equal" it like this?

CSCTL1 |=  DCOFSEL_6;

The statements in your code that use the != only check if the two arguments on either size of the != are not equal.  They do not actually set the values of any bits in the registers.  The |= will set the registers to their current value, "OR-ed" bitwise with the other value.

As well, can you explain what this code is intended to do?  The way I understand it, you're trying to set the DCO to 8 MHz, select the LFMODCLK as the source for the ACLK, and generate 500 interrupts per second using Timer2.  Is all of this completely correct?

Nate

CSCTL1! = DCOFSEL_6;

I wrote on different C compilers, but more like "Kernighan + Richie C".
The constructions I wrote - I meant this:
to set the bit I want without changing the others:
P1DIR | = BIT4; P1OUT | = BIT4; // Set P1.4 to output direction

reset the bit I need without changing the others:
P1DIR & = ~ BIT0; P1OUT & = ~ BIT0; // Set P1.0 to input direction

"Bitwise OR" - the _result_ of the operation is 1 if one of the corresponding bits is 1, otherwise 0.

Set to 1 the zero bit of the P1OUT port (for example) can be as follows:

P1OUT = 0x01; // hexadecimal notation
or
P1OUT = 0b00000001; // binary record
or
P1OUT = 1; // decimal notation
But at the same time we "spoil" (overwrite) all the others to beat in P1OUT.
I need to install only one bit from the port (register) without changing the rest.

if we want to set in 1 only the zero bit(for example) and not touch the others?

In this case, you need to use "bitwise OR":

set zero bit to one
P1OUT = P1OUT | 0x01;
or by using compound assignment
P1OUT | = 0x01;
As a result, we changed only the zero bit of the port.

"Bitwise operation NOT" - changes the value of the bit to the opposite.
This operation together with the bitwise NOT can be used to reset a particular bit to zero.

reset zero bit
P1OUT & = 0xFE;
or
P1OUT & = ~ 0x01;

With such a record, we put a bit into the unit that we want to zero, then invert the resulting number, Now apply the resulting mask. As a result, we put 0 at only the first bit.

And the code of the program should be written so that you can read it later :)

I'm trying to set the DCO to 8 MHz, select the LFMODCLK as the source for the ACLK,

and generate 500 interrupts per second using Timer2.

Yes. correct.

• I can not get to work Timer2 :-((

Code:

...

```...
void _system_pre_init(void)
{
/* Insert your low-level initializations here */
WDTCTL = WDTPW + WDTHOLD;  // Stop Watchdog timer

__disable_interrupt();  // Это специальная команда!  Это не прерывание.

PM5CTL0 &= ~LOCKLPM5;           // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
// Clock System Setup
CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers

CSCTL1 = 0;
CSCTL1 !=  DCOFSEL_6;                     // Set DCO setting for 8MHz --- установка частоты 8_Мгц

CSCTL2 != SELA__LFMODCLK;        // 010b = LFMODCLK  (ACLK == MODOSC/128)
CSCTL2 != SELS__DCOCLK;          // 011b = DCOCLK
CSCTL2 != SELM__DCOCLK;          // 011b = DCOCLK

CSCTL3 != DIVA__2;      // ACLK source divider. Divides the frequency of the ACLK clock source. 001b = /2
CSCTL3 &= ~DIVS__1;      // SMCLK source divider. Divides the frequency of the SMCLK clock source. 000b = /1
CSCTL3 &= ~DIVM__1;      // MCLK source divider. Divides the frequency of the MCLK clock source. 000b = /1

CSCTL4 != HFXTOFF;      // 1b = HFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK
CSCTL4 &= ~VLOOFF;      // VLO off. This bit turns off the VLO. 0b = VLO is on
CSCTL4 &= ~SMCLKOFF;    // SMCLK off. This bit turns off the SMCLK. 0b = SMCLK on
CSCTL4 != LFXTOFF;      // 1b = LFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK

// CSCTL5 ???
// CSCTL6 ???

CSCTL0_H = 0;                             // Lock CS registers

//  Start init Timer2_A0,  ---------------------------------------------------------------------------

TA2CTL = 0;  //  all bits reset to =0
TA2CTL = TASSEL__SMCLK + ID__1 + MC__UP + TACLR;

/*
TASSEL__SMCLK;       // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
TASSEL_2;            // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
ID__1;               // Timer A input divider: 0 = /1 , 1 = /2 , 2 - /4 , 3 - /8
MC__UP;              // Timer A mode control: 1 - Up to CCR0
TAIFG;               // Timer_A interrupt flag 0b = No interrupt pending  1b = Interrupt pending
TAIE;                // Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled
TACLR;               // Timer_A clear.
*/

TA2CCTL0 = 0;   // all bits reset to =0
TA2CCTL0 &= ~CAP;              // Capture mode 0b = Compare mode 1b = Capture mode

//TA2EX0 &= ~TAIDEX_0;         // Timer_A Input divider expansion : /1
TA2EX0 = 0;

TA2CCR0 = 1000 - 1;   // may be 1000 per sec?  but really = 122(244) per sec ;-((

TA2CCTL0 = CCIE;
//  End init Timer2_A0  ---------------------------------------------------------------------

__bis_SR_register(GIE);

__enable_interrupt();

}

...

// Timer2_A0 interrupt service routine  -------------------------------------------------------
#pragma vector = TIMER2_A0_VECTOR
__interrupt void Timer2_A0_ISR (void)
{

P4OUT ^= BIT2;                      // Toggle P4.2 using exclusive-OR (set-reset an LED)

__no_operation();                       // for debugger
}
...```

...

Work !. but................

TA2CCR0 = 1000 - 1;    may be 8000000 / 1000 = 8000 flash LED per sec? Yes-No?

If 8Mhz / 1000 = 8000 ? Really ? ;)

Really in my oscillograf i see 122Hz (meandr: 122Hz=0 and 122Hz=1)

i.e: 8000000 / 65573 = 122 ???

8-(

but really = 122(244) per sec ;-((

• Hi Alexander

I see you still have some exclamation points "!", where you should have OR operators "|".   To fix that, change every != to |= in your code above.

The other issue is the following lines

CSCTL3 &= ~DIVS__1;      // SMCLK source divider. Divides the frequency of the SMCLK clock source. 000b = /1

CSCTL3 &= ~DIVM__1;      // MCLK source divider. Divides the frequency of the MCLK clock source. 000b = /1

DIVS__1 and DIVM__1 are both equal to 0x0000.  So, when you run these lines, they do nothing, because they set

CSCTL3 = CSCTL3 & 0xFFFF;

which does not change CSCTL3 in the first place.  To fix this, set CSCTL = 0 before making other changes to it.

Finally, if you want to generate 500 interrupts per second, your pin will toggle every 2 milliseconds.  With an 8MHz Clock, that means you will want your counter to count up for 16000 cycles before triggering the interrupt.

I used the following code to get the following output on a logic analyzer.  I made as few changes to your original code as I could.

```#include <msp430.h>
int main(void)
{
/* Insert your low-level initializations here */

WDTCTL = WDTPW + WDTHOLD;  // Stop Watchdog timer
__disable_interrupt();
PM5CTL0 &= ~LOCKLPM5;           // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
// Clock System Setup
CSCTL0_H = CSKEY >> 8;                    // Unlock CS register
CSCTL1 = 0;
CSCTL1 |=  DCOFSEL_6;                     // Set DCO setting for 8MHz

CSCTL2 |= SELA__LFMODCLK;        // 010b = LFMODCLK  (ACLK == MODOSC/128)
CSCTL2 |= SELS__DCOCLK;          // 011b = DCOCLK
CSCTL2 |= SELM__DCOCLK;          // 011b = DCOCLK

CSCTL3 = 0;             // Sets all source dividers to 1
CSCTL3 |= DIVA__2;      // ACLK source divider. Divides the frequency of the ACLK clock source. 001b = /2

CSCTL4 |= HFXTOFF;      // 1b = HFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK
CSCTL4 &= ~VLOOFF;      // VLO off. This bit turns off the VLO. 0b = VLO is on
CSCTL4 &= ~SMCLKOFF;    // SMCLK off. This bit turns off the SMCLK. 0b = SMCLK on
CSCTL4 |= LFXTOFF;      // 1b = LFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK

CSCTL0_H = 0;                             // Lock CS registers

//  Start init Timer2_A0,  ---------------------------------------------------------------------------
//TA2CTL = 0;  //  all bits reset to =0
TA2CTL = TASSEL__SMCLK + ID__1 + MC__UP + TACLR;

/*
TASSEL__SMCLK;       // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
TASSEL_2;            // Timer_A clock source select 00b = TAxCLK  01b = ACLK 10b = SMCLK
ID__1;               // Timer A input divider: 0 = /1 , 1 = /2 , 2 - /4 , 3 - /8
MC__UP;              // Timer A mode control: 1 - Up to CCR0
TAIFG;               // Timer_A interrupt flag 0b = No interrupt pending  1b = Interrupt pending
TAIE;                // Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled
TACLR;               // Timer_A clear.
*/

TA2CCTL0 = 0;   // all bits reset to =0
TA2CCTL0 &= ~CAP;              // Capture mode 0b = Compare mode 1b = Capture mode
//TA2EX0 &= ~TAIDEX_0;         // Timer_A Input divider expansion : /1
TA2EX0 = 0;
TA2CCR0 = 16000 - 1;   // (8000000 cycles / 1 second) * (1 second / 500 interrupts) = 16000 cycles / interrupt
TA2CCTL0 = CCIE;

//Set P4 direction and output;
P4DIR |= BIT2;
P4OUT |= BIT2;

//  End init Timer2_A0  ---------------------------------------------------------------------

__bis_SR_register(GIE);
__enable_interrupt();
while(1){}
}

// Timer2_A0 interrupt service routine  -------------------------------------------------------

#pragma vector = TIMER2_A0_VECTOR
__interrupt void Timer2_A0_ISR (void)

{
P4OUT ^= BIT2;                      // Toggle P4.2 using exclusive-OR (set-reset an LED)
__no_operation();                       // for debugger
}
```

• thank you very much for the help !
{"ft_lang_label":"__label__en","ft_lang_prob":0.5932577,"math_prob":0.9698969,"size":2773,"snap":"2021-43-2021-49","text_gpt3_token_len":935,"char_repetition_ratio":0.15998556,"word_repetition_ratio":0.1434263,"special_character_ratio":0.380815,"punctuation_ratio":0.21471173,"nsfw_num_words":0,"has_unicode_error":false,"math_prob_llama3":0.9660394,"pos_list":[0],"im_url_duplicate_count":[null],"WARC_HEADER":"{\"WARC-Type\":\"response\",\"WARC-Date\":\"2021-10-27T01:05:49Z\",\"WARC-Record-ID\":\"<urn:uuid:69c4f998-7f8a-4d7e-ac2a-097c97ed31b2>\",\"Content-Length\":\"183610\",\"Content-Type\":\"application/http; msgtype=response\",\"WARC-Warcinfo-ID\":\"<urn:uuid:9a029b27-808d-4a14-859a-1d7bec429c17>\",\"WARC-Concurrent-To\":\"<urn:uuid:76b65b71-1568-4313-99a5-3aa681a0d32e>\",\"WARC-IP-Address\":\"104.104.97.72\",\"WARC-Target-URI\":\"https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/707497/ccs-msp430fr5972-msp430fr5972?tisearch=e2e-sitesearch&keymatch=MSP430FR5972\",\"WARC-Payload-Digest\":\"sha1:X6TQFZ7UKDYF2RNUP2S7H5IPYD5KXPJ6\",\"WARC-Block-Digest\":\"sha1:27ILU7WWYXRWXRKWCHWK2FTRLOCQLBLN\",\"WARC-Identified-Payload-Type\":\"text/html\",\"warc_filename\":\"/cc_download/warc_2021/CC-MAIN-2021-43/CC-MAIN-2021-43_segments_1634323587963.12_warc_CC-MAIN-20211026231833-20211027021833-00309.warc.gz\"}"}