# Forum: FPGA, VHDL & Verilog Verilog-Range must be bounded by constant expressions

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module validation(test_input);
input [15:0]test_input;
reg [7:0]test_in;
integer k;

initial
begin
k=0;
end

always@(k)
begin
test_in[7:0]=test_input[7+k:k];//Range must be bounded by constant
expressions.
end

The code is partial with the same idea. The value of k changes in the
original code with maximum k value=7 (not shown here). At each change in
k, I need to copy [k+7:k] bits of test_input to test_in.

eg:
when k=1
test_in[7:0]=test_input[8:1]
when k=4
test_in[7:0]=test_input[11:4]

ERROR:Range must be bounded by constant expressions.

I need to copy 8 bits from 'test_input' to test_in.If variable is not
allowed then, what is the solution.

: Edited by User

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please help to clear this error

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Please start a new thread for a new question. Add as much information as
possible and add a useful question, at least WHAT error you want to get
rid off.

And: attach Verilog files with *.v extension.

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