hardcaml
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`module Port_list : sig ... end`
`type ('i, 'o) t`

base type of the cycle based simulators

`type t_port_list = (Port_list.t, Port_list.t) t`
`val scheduling_deps : Signal.t -> Signal.t Base.List.t`

Specialised signal dependencies that define a graph that breaks cycles through sequential elements. This is done by removing the input edges of registers and memories (excluding the read address, since hardcaml memories are read asynchronously).

Instantiations do not allow cycles from output to input ports, which is a valid assumption for the simulator, but not in general.

Note that all signals in the graph cannot be reached from just the outputs of a circuit using these dependencies. The (discarded) inputs to all registers and memories must also be included.

`val cycle : (_, _) t -> Base.Unit.t`

advance by 1 clock cycle (check->comb->seq->comb)

`val cycle_check : (_, _) t -> Base.Unit.t`

check inputs are valid before a simulation cycle

`val cycle_comb0 : (_, _) t -> Base.Unit.t`

update combinatorial logic before sequential logic

`val cycle_seq : (_, _) t -> Base.Unit.t`

update sequential logic

`val cycle_comb1 : (_, _) t -> Base.Unit.t`

update combinatorial logic after sequential logic

`val reset : (_, _) t -> Base.Unit.t`

reset simulator

`val in_port : (_, _) t -> Base.String.t -> Bits.t Base.Ref.t`

get input port given a name

```val out_port : ?clock_edge:Side.t -> (_, _) t -> Base.String.t -> Bits.t Base.Ref.t```

Get output port given a name. If `clock_edge` is `Before` the outputs are computed prior to the clock edge - `After` means the outputs are computed after the clock edge.

`val inputs : ('i, _) t -> 'i`
`val outputs : ?clock_edge:Side.t -> (_, 'o) t -> 'o`
`val in_ports : (_, _) t -> Port_list.t`
`val out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.t`
`val internal_ports : (_, _) t -> Port_list.t`

get list of internal nodes

`val lookup_signal : (_, _) t -> Signal.Uid.t -> Bits.t Base.Ref.t`
`val lookup_reg : (_, _) t -> Signal.Uid.t -> Bits.t Base.Ref.t`
```type 'a with_create_options = ?is_internal_port:(Signal.t -> Base.Bool.t) -> ?combinational_ops_database:Combinational_ops_database.t -> 'a```
`val create : (Circuit.t -> t_port_list) with_create_options`

construct a simulator from a circuit

`module Combine_error : sig ... end`
```val combine : ?port_sets_may_differ:Base.Bool.t -> ?on_error:(Combine_error.t -> Base.Unit.t) -> ('i, 'o) t -> ('i, 'o) t -> ('i, 'o) t```

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and `on_error` is called if a difference is found. By default, `on_error` raises.

The simulators should have the same input and output port sets, unless `port_sets_may_differ` is `true`, in which case only ports which exist on both simulators are checked.

`module With_interface (I : Interface.S) (O : Interface.S) : sig ... end`
`module Private : sig ... end`
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