1
GATE ECE 2017 Set 2
Numerical
+2
-0
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

2
GATE ECE 2017 Set 1
Numerical
+2
-0
A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is 3
GATE ECE 2017 Set 1
+2
-0.6
A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are QA QB = 00, 01, 10, and 11. Assume that XIN is held at a logic level throughout the operation of the FSM. When the FSM is initialized to the state QA QB = 100 and clocked, after a few clock cycles, it starts cycling through

A
all of the four possible states if XIN = 1
B
three of the four possible states if XIN = 0
C
only two of the four possible states if XIN =1
D
only two of the possible states if XIN = 0
4
GATE ECE 2016 Set 2
+2
-0.6
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. Which one of the following statements is correct?

A
Transitions from State A are ambiguously defined.
B
Transitions from State B are ambiguously defined.
C
Transitions from State C are ambiguously defined.
D
All of the state transitions are defined unambiguously.
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics
EXAM MAP
Joint Entrance Examination
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