# Simulation of Schematic as per provided in AD9856 datasheet in ADIsimPE?

I wanted to simulate, Evaluation board schematic as per provided in the AD9856 datasheet.

I am using ADIsimPE but in that, I am not getting AD9856 part details to place it. Also, I was unable to get AD8320 for the same.

I made a hardware interface of FPGA and AD9856 through SPI. It works as per mentioned in the datasheet for single tone frequency.

But in continuous mode when known data of 12 bit is provided to DDC, I am not getting properly modulated waveform at the IF connector.

I am using Ref Clock multiplier to make sampling frequency of 200 MHz from the oscillator of 50 MHz.

Data_I send on a frequency of 9.8208 MHz by making TxEnable high for the same and Data_Q sent at same frequency using Tx_Enable  signal LOW.

If anyone has screenshots of results of QPSK modulated data then please share.

• Hi,

As for the continuous mode, the data sheet indicates that "Do not engage continuous mode simultaneously with the REFCLK multiplier function. This corrupts the CIC interpolating filter, forcing unrecoverable mathematical overflow that can only be resolved by issuing a RESET command. The problem is due to the PLL failing to be locked to the reference clock while nonzero data is being clocked into the interpolation stages from the data inputs. The recommended sequence is to first engage the REFCLK multiplier function (allowing at least 1 ms for loop stabilization) and then engage continuous mode via software."

Best regards,

Mark

• I got these type of results at the output of AD9856.

SPI communication for AD9856 is done through FPGA.

Single tone operation working as mentioned in the datasheet of AD9856. But for Continuous mode, i am not able to observe phase change for IQ data.

I have written code in VHDL to make communication between FPGA and AD9856.

Some part of the code which is needful for AD9856 is as follows.

Please suggest me, if I am wrong somewhere.

----------------------------------------------------------------------------------
--Process Counter of 12 bit
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if rising_edge(CLK_10_M) then
if(data_count=11)then
data_count<=0;
else
data_count<=data_count+1;
end if;
end if;
end if;
end process;

----------------------------------------------------------------------------------
--Process-Data Storing in a single bit signal according to Tx Enable signal
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if rising_edge (CLK_10_M) then
if((data_count mod 2) = 0 ) then
DUC_TxENB_sgl <='1';
data_iq_1 <=I_Data_6_bit(data_count/2);
elsif ((data_count mod 2) = 1 ) then
DUC_TxENB_sgl <='0';
data_iq_1 <=Q_Data_6_bit(data_count/2);
end if;
end if;
end if;
end process;

----------------------------------------------------------------------------------
--Process- Assigning values of 12 clock cycles to a 12-bit vector
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if rising_edge (CLK_10_M) then
data_IQ_12_bit(data_count)<=data_iq_1;
end if;
end if;
end process;

process (CLK_10_M)
begin
if locked = '1' then
if rising_edge (CLK_10_M) then
duc_reset_sgl_d <= duc_reset_sgl;
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Process-: Splitting of 12 bit data
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if falling_edge (CLK_10_M) then
if(data_count=0) then
data_12_bit<=data_IQ_12_bit;
end if;
end if;
end if;
end process;

-----------------------------------------

--FIN = 2 FIQ

-------------------------------------

process (CLK_20M)
begin
if locked = '1' then
if rising_edge (CLK_20M) then
DUC_data<=data_12_bit;
end if;
end if;
end process;
IQ_data_out <= data_iq_1;
----------------------------------------------------------------------------------
--ProcessTo observe I data indivisually
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if rising_edge (CLK_10_M) then
data_i_1 <=I_Data_6_bit(0);
I_Data_6_bit <= I_Data_6_bit(0) & I_Data_6_bit(5 downto 1);
end if;
end if;
end process;
data_i_1_out<= data_i_1;

----------------------------------------------------------------------------------
--Process To observe Q data indivisually
----------------------------------------------------------------------------------
process (CLK_10_M)
begin
if locked = '1' then
if rising_edge (CLK_10_M) then
data_q_1 <=Q_Data_6_bit(0);
Q_Data_6_bit <= Q_Data_6_bit(0) & Q_Data_6_bit(5 downto 1);
end if;
end if;
end process;
data_q_1_out <= data_q_1;
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