1 /*
4  * Author:
5  *
6  * Created:
7  * Description:  BF561 startup file
8  *
9  * Modified:
10  *               Copyright 2004-2006 Analog Devices Inc.
11  *
12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License as published by
16  * the Free Software Foundation; either version 2 of the License, or
17  * (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, see the file COPYING, or write
26  * to the Free Software Foundation, Inc.,
27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28  */
31 #include <asm/blackfin.h>
32 #if CONFIG_BFIN_KERNEL_CLOCK
33 #include <asm/mach/mem_init.h>
34 #endif
36 .global __rambase
37 .global __ramstart
38 .global __ramend
39 .extern ___bss_stop
40 .extern ___bss_start
41 .extern _bf53x_relocate_l1_mem
43 #define INITIAL_STACK   0xFFB01000
45 .text
47 ENTRY(__start)
48 ENTRY(__stext)
49         /* R0: argument of command line string, passed from uboot, save it */
50         R7 = R0;
51         /* Set the SYSCFG register:
52          * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
53          */
54         R0 = 0x36;
55         SYSCFG = R0;
56         R0 = 0;
58         /* Clear Out All the data and pointer Registers */
59         R1 = R0;
60         R2 = R0;
61         R3 = R0;
62         R4 = R0;
63         R5 = R0;
64         R6 = R0;
66         P0 = R0;
67         P1 = R0;
68         P2 = R0;
69         P3 = R0;
70         P4 = R0;
71         P5 = R0;
73         LC0 = r0;
74         LC1 = r0;
75         L0 = r0;
76         L1 = r0;
77         L2 = r0;
78         L3 = r0;
80         /* Clear Out All the DAG Registers */
81         B0 = r0;
82         B1 = r0;
83         B2 = r0;
84         B3 = r0;
86         I0 = r0;
87         I1 = r0;
88         I2 = r0;
89         I3 = r0;
91         M0 = r0;
92         M1 = r0;
93         M2 = r0;
94         M3 = r0;
96         /* Turn off the icache */
97         p0.l = (IMEM_CONTROL & 0xFFFF);
98         p0.h = (IMEM_CONTROL >> 16);
99         R1 = [p0];
100         R0 = ~ENICPLB;
101         R0 = R0 & R1;
103         /* Anomaly 05000125 */
104 #ifdef ANOMALY_05000125
105         CLI R2;
106         SSYNC;
107 #endif
108         [p0] = R0;
109         SSYNC;
110 #ifdef ANOMALY_05000125
111         STI R2;
112 #endif
114         /* Turn off the dcache */
115         p0.l = (DMEM_CONTROL & 0xFFFF);
116         p0.h = (DMEM_CONTROL >> 16);
117         R1 = [p0];
118         R0 = ~ENDCPLB;
119         R0 = R0 & R1;
121         /* Anomaly 05000125 */
122 #ifdef ANOMALY_05000125
123         CLI R2;
124         SSYNC;
125 #endif
126         [p0] = R0;
127         SSYNC;
128 #ifdef ANOMALY_05000125
129         STI R2;
130 #endif
132         /* Initialise UART - when booting from u-boot, the UART is not disabled
133          * so if we dont initalize here, our serial console gets hosed */
134         p0.h = hi(UART_LCR);
135         p0.l = lo(UART_LCR);
136         r0 = 0x0(Z);
137         w[p0] = r0.L;   /* To enable DLL writes */
138         ssync;
140         p0.h = hi(UART_DLL);
141         p0.l = lo(UART_DLL);
142         r0 = 0x0(Z);
143         w[p0] = r0.L;
144         ssync;
146         p0.h = hi(UART_DLH);
147         p0.l = lo(UART_DLH);
148         r0 = 0x00(Z);
149         w[p0] = r0.L;
150         ssync;
152         p0.h = hi(UART_GCTL);
153         p0.l = lo(UART_GCTL);
154         r0 = 0x0(Z);
155         w[p0] = r0.L;   /* To enable UART clock */
156         ssync;
158         /* Initialize stack pointer */
159         sp.l = lo(INITIAL_STACK);
160         sp.h = hi(INITIAL_STACK);
161         fp = sp;
162         usp = sp;
164         /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
165         call _bf53x_relocate_l1_mem;
166 #if CONFIG_BFIN_KERNEL_CLOCK
167         call _start_dma_code;
168 #endif
170         /* Code for initializing Async memory banks */
172         p2.h = hi(EBIU_AMBCTL1);
173         p2.l = lo(EBIU_AMBCTL1);
174         r0.h = hi(AMBCTL1VAL);
175         r0.l = lo(AMBCTL1VAL);
176         [p2] = r0;
177         ssync;
179         p2.h = hi(EBIU_AMBCTL0);
180         p2.l = lo(EBIU_AMBCTL0);
181         r0.h = hi(AMBCTL0VAL);
182         r0.l = lo(AMBCTL0VAL);
183         [p2] = r0;
184         ssync;
186         p2.h = hi(EBIU_AMGCTL);
187         p2.l = lo(EBIU_AMGCTL);
188         r0 = AMGCTLVAL;
189         w[p2] = r0;
190         ssync;
192         /* This section keeps the processor in supervisor mode
193          * during kernel boot.  Switches to user mode at end of boot.
194          * See page 3-9 of Hardware Reference manual for documentation.
195          */
197         /* EVT15 = _real_start */
199         p0.l = lo(EVT15);
200         p0.h = hi(EVT15);
201         p1.l = _real_start;
202         p1.h = _real_start;
203         [p0] = p1;
204         csync;
209         p1.h = 0x0;
210         [p0] = p1;
211         csync;
213         raise 15;
214         p0.l = .LWAIT_HERE;
215         p0.h = .LWAIT_HERE;
216         reti = p0;
217 #if defined(ANOMALY_05000281)
218         nop; nop; nop;
219 #endif
220         rti;
222 .LWAIT_HERE:
223         jump .LWAIT_HERE;
225 ENTRY(_real_start)
226         [ -- sp ] = reti;
227         p0.l = lo(WDOGA_CTL);
228         p0.h = hi(WDOGA_CTL);
230         w[p0] = r0;     /* watchdog off for now */
231         ssync;
233         /* Code update for BSS size == 0
234          * Zero out the bss region.
235          */
237         p1.l = ___bss_start;
238         p1.h = ___bss_start;
239         p2.l = ___bss_stop;
240         p2.h = ___bss_stop;
241         r0 = 0;
242         p2 -= p1;
243         lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
244 .L_clear_bss:
245         B[p1++] = r0;
247         /* In case there is a NULL pointer reference
248          * Zero out region before stext
249          */
251         p1.l = 0x0;
252         p1.h = 0x0;
253         r0.l = __stext;
254         r0.h = __stext;
255         r0 = r0 >> 1;
256         p2 = r0;
257         r0 = 0;
258         lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
259 .L_clear_zero:
260         W[p1++] = r0;
262         /* pass the uboot arguments to the global value command line */
263         R0 = R7;
264         call _cmdline_init;
266         p1.l = __rambase;
267         p1.h = __rambase;
268         r0.l = __sdata;
269         r0.h = __sdata;
270         [p1] = r0;
272         p1.l = __ramstart;
273         p1.h = __ramstart;
274         p3.l = ___bss_stop;
275         p3.h = ___bss_stop;
277         r1 = p3;
278         [p1] = r1;
280         /*
282          */
286         r2.l = 0x2000;
287         r2.h = 0x0000;
288         r1 = r1 + r2;
289         sp = r1;
290         usp = sp;
291         fp = sp;
292         call _start_kernel;
293 .L_exit:
294         jump.s  .L_exit;
296 .section .l1.text
297 #if CONFIG_BFIN_KERNEL_CLOCK
298 ENTRY(_start_dma_code)
299         p0.h = hi(SICA_IWR0);
300         p0.l = lo(SICA_IWR0);
301         r0.l = 0x1;
302         [p0] = r0;
303         SSYNC;
305         /*
306          *  Set PLL_CTL
307          *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
308          *   -      = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
309          *   -      = output delay (add 200ps of delay to mem signals)
310          *   -      = input delay (add 200ps of input delay to mem signals)
311          *   -      = PDWN      : 1=All Clocks off
312          *   -      = STOPCK    : 1=Core Clock off
313          *   -      = PLL_OFF   : 1=Disable Power to PLL
314          *   -      = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
315          *   all other bits set to zero
316          */
318         p0.h = hi(PLL_LOCKCNT);
319         p0.l = lo(PLL_LOCKCNT);
320         r0 = 0x300(Z);
321         w[p0] = r0.l;
322         ssync;
324         P2.H = hi(EBIU_SDGCTL);
325         P2.L = lo(EBIU_SDGCTL);
326         R0 = [P2];
327         BITSET (R0, 24);
328         [P2] = R0;
329         SSYNC;
331         r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
332         r0 = r0 << 9;                    /* Shift it over,                  */
333         r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
334         r0 = r1 | r0;
335         r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
336         r1 = r1 << 8;                    /* Shift it over                   */
337         r0 = r1 | r0;                    /* add them all together           */
339         p0.h = hi(PLL_CTL);
341         cli r2;                          /* Disable interrupts              */
342         ssync;
343         w[p0] = r0.l;                    /* Set the value                   */
344         idle;                            /* Wait for the PLL to stablize    */
345         sti r2;                          /* Enable interrupts               */
347 .Lcheck_again:
348         p0.h = hi(PLL_STAT);
349         p0.l = lo(PLL_STAT);
350         R0 = W[P0](Z);
351         CC = BITTST(R0,5);
352         if ! CC jump .Lcheck_again;
354         /* Configure SCLK & CCLK Dividers */
355         r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
356         p0.h = hi(PLL_DIV);
357         p0.l = lo(PLL_DIV);
358         w[p0] = r0.l;
359         ssync;
361         p0.l = lo(EBIU_SDRRC);
362         p0.h = hi(EBIU_SDRRC);
363         r0 = mem_SDRRC;
364         w[p0] = r0.l;
365         ssync;
367         p0.l = (EBIU_SDBCTL & 0xFFFF);
368         p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
369         r0 = mem_SDBCTL;
370         w[p0] = r0.l;
371         ssync;
373         P2.H = hi(EBIU_SDGCTL);
374         P2.L = lo(EBIU_SDGCTL);
375         R0 = [P2];
376         BITCLR (R0, 24);
377         p0.h = hi(EBIU_SDSTAT);
378         p0.l = lo(EBIU_SDSTAT);
379         r2.l = w[p0];
380         cc = bittst(r2,3);
381         if !cc jump .Lskip;
382         NOP;
383         BITSET (R0, 23);
384 .Lskip:
385         [P2] = R0;
386         SSYNC;
388         R0.L = lo(mem_SDGCTL);
389         R0.H = hi(mem_SDGCTL);
390         R1 = [p2];
391         R1 = R1 | R0;
392         [P2] = R1;
393         SSYNC;
395         RTS;
396 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
398 ENTRY(_bfin_reset)
399         /* No more interrupts to be handled*/
400         CLI R6;
401         SSYNC;
403 #if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
404         p0.h = hi(FIO_INEN);
405         p0.l = lo(FIO_INEN);
406         r0.l = ~(PF1 | PF0);
407         w[p0] = r0.l;
409         p0.h = hi(FIO_DIR);
410         p0.l = lo(FIO_DIR);
411         r0.l = (PF1 | PF0);
412         w[p0] = r0.l;
414         p0.h = hi(FIO_FLAG_C);
415         p0.l = lo(FIO_FLAG_C);
416         r0.l = (PF1 | PF0);
417         w[p0] = r0.l;
418 #endif
420         /* Clear the IMASK register */
423         r0 = 0x0;
424         [p0] = r0;
426         /* Clear the ILAT register */
427         p0.h = hi(ILAT);
428         p0.l = lo(ILAT);
429         r0 = [p0];
430         [p0] = r0;
431         SSYNC;
433         /* make sure SYSCR is set to use BMODE */
434         P0.h = hi(SICA_SYSCR);
435         P0.l = lo(SICA_SYSCR);
436         R0.l = 0x20;
437         W[P0] = R0.l;
438         SSYNC;
440         /* issue a system soft reset */
441         P1.h = hi(SICA_SWRST);
442         P1.l = lo(SICA_SWRST);
443         R1.l = 0x0007;
444         W[P1] = R1;
445         SSYNC;
447         /* clear system soft reset */
448         R0.l = 0x0000;
449         W[P0] = R0;
450         SSYNC;
452         /* issue core reset */
453         raise 1;
455         RTS;
456 ENDPROC(_bfin_reset)
458 .data
460 /*
461  * Set up the usable of RAM stuff. Size of RAM is determined then
462  * an initial stack set up at the end.
463  */
465 .align 4
466 __rambase:
467 .long   0
468 __ramstart:
469 .long   0
470 __ramend:
471 .long   0
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