Cluster-based architecture for fault-tolerant quantum computation

Keisuke Fujii    Katsuji Yamamoto Department of Nuclear Engineering, Kyoto University, Kyoto 606-8501, Japan
February 24, 2021
Abstract

We present a detailed description of an architecture for fault-tolerant quantum computation, which is based on the cluster model of encoded qubits. In this cluster-based architecture, concatenated computation is implemented in a quite different way from the usual circuit-based architecture where physical gates are recursively replaced by logical gates with error-correction gadgets. Instead, some relevant cluster states, say fundamental clusters, are recursively constructed through verification and postselection in advance for the higher-level one-way computation, which namely provides error-precorrection of gate operations. A suitable code such as the Steane seven-qubit code is adopted for transversal operations. This concatenated construction of verified fundamental clusters has a simple transversal structure of logical errors, and achieves a high noise threshold for computation by using appropriate verification procedures. Since the postselection is localized within each fundamental cluster with the help of deterministic bare controlled- gates without verification, divergence of resources is restrained, which reconciles postselection with scalability.

pacs:
03.67.Lx, 03.67.Pp, 03.67.-a

I Introduction

In order to implement reliable computation in physical systems, either classical or quantum, the problem of noise should be overcome. Particularly, fault-tolerant schemes have been developed based on error correction in quantum computation Shor95 ; CaldShor96 ; Shor96 ; Stea96 ; DiViShor96 ; Stea97 ; Stea98 ; Gottesman97 . In the usual quantum error correction (QEC), error syndromes are detected on encoded qubits, and the errors are corrected according to them. The noise thresholds for fault-tolerant computation are calculated to be about depending on the QEC protocols and noise models Stea97 ; Stea98 ; Gottesman97 ; Stea99 ; Stea03 ; Kitaev97 ; Preskill98 ; Knill98 ; Gottesman98 ; AB-O99 . A main motivation for QEC comes from the fact that in the circuit model the original qubits should be used throughout computation even if errors occur on them.

On the other hand, more robust computation may be performed in measurement-based quantum computers GC99 ; ZLC00 ; OWC ; Niel03 ; Tame07 ; Knill05a ; Knill05b . Teleportation from old qubits to fresh ones is made by measurements to implement gate operations, and the original qubits are not retained. An interesting fault-tolerant scheme with error-correcting teleportation is proposed based on encoded Bell pair preparation and Bell measurement, which achieves high noise thresholds Knill05a ; Knill05b . The cluster model or one-way computer OWC should also be considered for fault-tolerant computation. A highly entangled state, called a cluster state, is prepared, and gate operations are implemented by measuring the qubits in the cluster with feedforward for the postselection of measurement bases. This gate operation in the cluster model may be viewed as the one-bit teleportation ZLC00 . A promising scheme for linear optical quantum computation is proposed, where deterministic gates are implemented by means of the cluster model Niel04 . Fault-tolerant computation is built up for this optical scheme by using a clusterized version of the syndrome extraction for QEC Stea97 . The noise thresholds are estimated to be about for photon loss and for depolarization Niel06 . The threshold result is also argued by simulating the QEC circuits with clusters Rausen03 ; ND05 ; AL06 . Furthermore, topological fault-tolerance in cluster-state computation is investigated in a two-dimensional nearest-neighbor architecture, where a high noise threshold is obtained in spite of its strong physical constraint Raussendorf07 . Some direct approaches are, on the other hand, considered for the fault-tolerant one-way computation FY07 ; Silva07 ; JF09 , though there seems to be a problem for scalability.

In this paper we present a systematic and comprehensive description of an architecture for fault-tolerant quantum computation, namely the cluster-based architecture, which has been proposed recently to reconcile postselection with scalability by virtue of one-way computation FY09 . Specifically, the fault-tolerant computation is implemented by concatenated construction and verification of logical cluster states via one-way computation with postselection. A number of cluster states are constructed in parallel with error detection, and the unsuccessful ones are discarded, selecting the clean cluster states. The error-correcting teleportation (or its cluster version) Knill05a ; Knill05b ; Silva07 ; JF09 requires a high-fidelity preparation of Bell state. It is also considered that improved ancilla preparation increases the noise threshold Reichardt04 ; Eastin07 . In the present cluster-based architecture FY09 , even gate operations as logical cluster states are prepared and verified by postselecting the lower-level computation to reduce the errors efficiently (see also Ref. FY07 for an early idea). This is quite distinct from the usual circuit-based QEC architectures, including the error-correcting teleportation, where the errors are corrected after noisy gate operations.

While high-fidelity state preparation is achieved by postselection, huge resources are generally required due to the exponentially diminishing net success probability according to the computation size. This is a serious obstacle for scalability in the postselecting schemes Knill05a ; Knill05b ; FY07 . Here, we succeed in overcoming this problem in postselection by presenting a systematic method of concatenation to construct logical cluster states through verification, where the unique feature of the cluster-model computation is fully utilized. As described in detail later, the necessary postselections are minimized and localized by dividing a whole cluster state into some fundamental clusters with the help of controlled- (C) gates without verification, say bare C gates. This enables the off-line gate operations prior to the computation as the verified logical cluster states, and provides a scalable concatenation with postselection in the cluster-model computation. The concatenated construction of verified clusters is implemented with transversal (bitwise) operations by adopting a suitable code such as the Steane seven-qubit code, which belongs to a class of stabilizer codes of Calderbank-Shor-Steane (CSS) CaldShor96 ; Stea96 ; Gottesman98 . The logical measurements of Pauli operators as well as the Clifford gates, , and C, are implemented transversally on such a quantum code. The non-Clifford gate is even operated for universal computation by preparing a specific qubit and making a transversal measurement FY07 ; Silva07 . By exploiting this good transversal property, the cluster-based architecture has a simple structure of logical errors in concatenation to estimate readily the noise threshold. A high noise threshold can be achieved by using appropriate verification procedures with postselection. Furthermore, the resources usage is moderate, being comparable to or even less than those of the circuit-based QEC architectures.

The rest of the paper is organized as follows. In Sec. II we briefly review the usual fault-tolerant quantum computation with circuit-based QEC. In Sec. III we introduce the main concept of cluster-based architecture by considering a simple model preliminarily. In Sec. IV we present a detailed description of an efficient architecture for the concatenated construction of verified logical clusters. The fundamental clusters and verification protocols are suitably adopted there, namely the hexa-cluster, code states, single and double verifications. Then, performance of the architecture is analyzed in Secs. V, VI and VII, with respect to the noise threshold and resources usage. Sec. VIII is devoted to summary and conclusion. In the Appendix A we explain how to produce the cluster diagrams to construct the fundamental clusters with single and double verifications.

Ii Circuit-based fault-tolerant architecture

We first review the usual fault-tolerant architecture based on the circuit-model computation with QEC. In comparison, this will be helpful to understand the distinct feature of the cluster-based fault-tolerant architecture, which will be investigated in the succeeding sections.

It is well known that by using QEC codes we can protect quantum information from errors which are caused by interaction with environment. Specifically, by adopting the stabilizer codes we can perform syndrome detection for recovery operation simply by measuring the stabilizer operators. Several QEC gadgets have been proposed to implement the stabilizer measurement in a fault-tolerant way DiViShor96 ; Stea97 ; Knill05a . A QEC gadget was first proposed by DiVincenzo and Shor, where cat states are used as ancillae for the syndrome measurement DiViShor96 . Subsequently, a relatively simple type of QEC gadget was proposed by Steane Stea97 , where encoded ancilla states are used to extract the syndrome with transversal operations. Especially, in the case of CSS code the logical code states can be used as ancilla states. For example, the following circuit executes the and error syndrome extractions by using the ancilla states, (1)

where the code blocks are illustrated as though for a three-qubit code for simplicity. In order to extract reliable error information, the syndrome extraction is repeated for some times. An optimized way to extract the syndrome information was also proposed in Ref. Plenio97 , where the subsequent syndrome extraction is conditionally performed according to the preceding syndrome information. Another interesting QEC gadget based on teleportation was proposed by Knill Knill05a , which is illustrated as follows: (2)

Here, the encoded data qubit is teleported to the fresh encoded qubit of the ancilla Bell state. The outcome of the encoded Bell measurement to complete the teleportation provides sufficiently the syndrome information, namely error-detecting or error-correcting teleportation. Thus, it is not necessary to repeat the syndrome extraction in this QEC gadget. The outcome of the Bell measurement is properly propagated to the subsequent computation as the Pauli frame Knill05a ; Niel06 .

Concatenated computation with QEC gadgets can be employed to achieve high accuracy for logical gate operations. In the usual fault-tolerant architectures based on the circuit-model computation Kitaev97 ; Knill98 ; AB-O99 , the concatenation is implemented by replacing a physical (lower-level) gate operation recursively with a logical (upper-level) one followed by QEC gadgets such as the circuits (1) and (2). It is illustrated for a controlled-NOT (CNOT) gate as follows: (3)

Here, we note that any logical gate operation should be followed by the QEC gadgets for fault-tolerant computation. We may call this type of concatenation in terms of logical circuits the circuit-based concatenation or circuit-based fault-tolerant architecture.

Iii Cluster-based fault-tolerant architecture

iii.1 Main concept

The cluster-based architecture pursues logical cluster states with high fidelity for reliable computation, whereas the circuit-based architecture concerns logical circuits with high accuracy as described in the preceding section. (Here, the terms “circuit-based” and “cluster-based” refer to the type of fault-tolerant concatenation. They do not specify the physical-level computation.) In the cluster model, quantum computation is implemented through measurements of the logical qubits in cluster states. Thus, high fidelity cluster states directly mean the ability to perform quantum computation with high accuracy. It is, however, not a trivial task to prepare such large entangled states with high fidelity as cluster states of logical qubits encoded in a concatenated QEC code. This may be done by adopting postselection (or multi-partite entanglement purification). That is, logical cluster states are constructed through verification process; they are discarded if infection of errors is found. It is expected generally that as the size of an entangled state gets large, the probability to pass the postselection decreases substantially. Thus, we have to design suitably the cluster-based architecture so as to make it scalable, while the postselection is made successfully. This dilemma between postselection and scalability in concatenation can be overcome by utilizing the unique feature of the cluster-model computation FY09 . The key elements are as follows:

Fundamental clusters with certain topologies, which are used to compose a whole cluster state to implement a desired computation.

Verification protocols, as parts of cluster states, to postselect the successful one-way computation for the construction of fundamental clusters.

Transversal bare C gates without verification, which are used to connect the fundamental clusters deterministically to construct the whole cluster state scalably.

We need not verify the whole of a cluster state by postselection, which would have resulted in divergence of resources due to the diminishing success probability. Instead, at each concatenation level we divide the whole cluster state (one-way computation) into the fundamental clusters (gate operations and ancillae). The fundamental clusters are deterministically connected by the bare C gates which operate transversally on a suitable code such as the Steane seven-qubit code. As a result, the postselection is localized within each fundamental cluster, which reduces the resource usages dramatically, though maintaining fault-tolerance of computation.

iii.2 Preliminary model

We consider preliminarily a simple model to illustrate the cluster-based architecture. At the same time, we introduce cluster diagrams, which are designed to describe properly the architecture.

We take one fundamental cluster as as follows: (4)

Henceforth we suitably define level- fundamental clusters as cluster states of level- qubits in concatenation of a QEC code. (Level-0 qubits are physical ones.) In this model the level- fundamental cluster (4) consists of two level- qubits connected with a C gate. We construct this level- fundamental cluster through a verification protocol as given in the following circuit: (5)

The two-qubit cluster is formed from the two level- logical qubits (1⃝) through the C gate operation (2⃝). The errors which are introduced to these two qubits before and during the C gate operation are detected by using a sort of the Steane’s QEC gadget (3⃝) with the ancilla qubits (4⃝). This verification protocol is implemented with postselection to obtain the level- fundamental cluster (4) with higher fidelity (5⃝).

In the cluster-based architecture, the entanglement operation with verification to construct the level- fundamental cluster is implemented by one-way computation on a certain cluster state which is made by combining the level- fundamental clusters with the transversal bare C gates. Specifically, the process (5) to obtain the fundamental cluster (4) is described in terms of a cluster diagram as follows: (6)

Here, the elements corresponding to those in the circuit (5) are labeled the same numbers 1⃝5⃝. We occasionally use the two-dimensional diagrams such as (6) to abbreviate the three-dimensional arrays to represent the whole cluster states by omitting the coordinate for the code blocks according to the encoding rules as explained below. [The whole three-dimensional array of (6) will be illustrated later.] The wavy lines in the diagram (6) indicate the bare C gates acting transversally on the level- qubits composing the level- fundamental clusters. The output qubits (5⃝) are denoted by as the verified level- fundamental cluster. The operation for encoding and transferring the level- code state is described by symbolically: (7)

Here, the level- qubits surrounded by the dotted line form the level- code state (cluster) . They are teleported upon measurements to another block of qubits as by a Hadamard operation with bare C gates (one-bit teleportation). The encoding operation of the level- code state is also described by symbolically for the later use: (8)

By applying the encoding (7), the full three-dimensional array of the diagram (6) is obtained with the axes corresponding to the code blocks, logical qubits and time as follows: (9)

Here, we observe that the level- fundamental cluster (4) is constructed through the verification by using level- fundamental clusters (4) and 4 level- logical qubits which are suitably connected with level- bare C gates.

As seen in the diagrams (7) and (8), the level- code states and are used for the encoding operations. They are given as the cluster states of level- qubits, which are similar to the fundamental cluster (4). [See the diagrams (12) and (13) in the next section.] We can prepare these cluster states for and by combining some copies of the level- fundamental cluster (4) with the level- bare C gates. (Here, we do not present their preparation explicitly for this preliminary model.) An alternative option is to include the level- code states and in the set of level- fundament clusters, as will be adopted in the next section for an efficient construction of fundamental clusters with high fidelity.

The circuit (5) is executed in the diagram (6) or (9) by measuring the the level- qubits except for the output qubits. Then, the syndrome information is extracted from the measurement outcomes (3⃝ and 4⃝). If this level- syndrome is found to be correct, we keep the output qubits (5⃝) as the verified level- fundamental cluster. Otherwise, we discard the unsuccessful outputs. This one-way computation completes one concatenation; the level- fundamental cluster as the entangled set of output level- qubits (’s) has been constructed and verified by using the level- fundamental clusters with bare C gates.

We produce many copies of the fundamental cluster by performing the above procedure recursively up to a certain logical level high enough to achieve the expected accuracy. Then, we construct the whole cluster state to implement a desired computation by combining these copies of the fundamental cluster with the transversal bare C gates. The logical error of the transversal bare C gate on the concatenated code also becomes sufficiently small at the highest level. Thus, given the clean enough fundamental clusters at the highest level, the one-way computation is operated fault-tolerantly on the whole cluster state. In this preliminary model, however, the noise threshold will be rather low, since the verification protocol is not optimal, and some of the qubits are connected doubly to the bare C gates. A more efficient architecture will be described in the next section, which achieves a high noise threshold .

iii.3 Unique features

We should mention that the role of bare C gates in the cluster-based architecture provides the essential distinction from the circuit-based architecture. The postselection with QEC gadgets can really achieve high accuracy for computation. However, in the circuit-based concatenation the postselection of gate operations should be performed in the ongoing computation (even if the error-detecting teleportation is utilized with off-line preparation of ancilla states Knill05a ). Thus, if errors are detected, the computation should be restarted from the beginning, which results in divergence of resources usage. This is because in the circuit-based architecture any logical gate operation is necessarily followed by QEC gadgets at each concatenation level, as seen in Sec. II.

Instead, in the cluster-based architecture bare C gates, which are not accompanied by QEC gadgets, are partially used for the one-way computation to implement the construction process, while fault-tolerance can be ensured by the verification and postselection of fundamental clusters. The logical cluster states are really postselected off-line and locally since the whole cluster is divided into the fundamental clusters with the help of bare C gates. When clean enough fundamental clusters are just constructed, we connect them with bare C gates deterministically, and then start the computation. The fundamental clusters, which represent the gate operations, have been constructed successfully in advance by removing sufficiently the errors via the postselection in the lower-level one-way computation, before starting the computation at the higher level. Thus, we may call this verification process as preselection or error-precorrection of gate operations. Here, it should be noted that the postselection for the whole cluster state or computation, without the use of bare C gates, increases exponentially the resources according to the computation size. The present architecture certainly succeeds in reconciling postselection with scalability, which would not be achieved without the cluster-model computation.

The cluster-based architecture also exploits a good transversal property by adopting a suitable code such as the Steane seven-qubit code. That is, the operations on the physical qubits are all transversal, and really limited after the verification process at the lowest (physical) level. In fact, as seen in the diagram (6), any direct operation is not implemented on the output qubits (’s) through the verified construction of fundamental cluster. The desired entanglement among them to form the fundamental cluster at the next level is rather generated via one-bit teleportation in the one-way computation. Thus, they inherit transversally the errors on the constituent physical-level qubits, up to the Pauli frame information from the one-way computation for cluster construction. Then, these output qubits composing the fundamental clusters undergo the transversal bare C gates and measurements at the next level for the first time. This transversal property provides a simple structure of logical errors in concatenation to estimate readily the noise threshold. In this respect, the cluster-based architecture presents a practical way to construct large entangled states, including the concatenated code states and fundamental clusters, the errors of which are described in a good approximation by the homogeneous errors on the constituent physical-level qubits Eastin07 . The details will be demonstrated in the following sections.

Iv Concatenated construction of verified cluster states

We now introduce an efficient architecture for fault-tolerant concatenation by adopting a set of suitable fundamental clusters and elaborate verification protocols. It is really designed to achieve high noise threshold by taking full advantage of the present cluster-based scheme. As seen in the diagram (6), some of the qubits are connected doubly to the bare C gates for the cluster construction in the preliminary model. This lowers the noise threshold substantially. Thus, the topologies of the fundamental clusters should be chosen so as to limit suitably the use of bare C connections (at most one bare C gate to each qubit) and redundant qubits for the cluster construction. It should also be noted that the errors on the resultant fundamental clusters are not detected after the construction is completed. This requires that the verification protocols should detect fully the first-order errors except for some of the errors introduced by the final few operations, which are inevitably left on the output states.

iv.1 Fundamental clusters

We adopt the following states as the level- fundamental clusters:

 |h(l)⟩,|0(l)⟩,|+(l)⟩. (10)

They are depicted in terms of the cluster diagrams as (11) (12) (13)

where the circles denote the level- qubits, and the boxed qubits are measured for Hadamard operations to obtain and . The hexa-cluster is a cluster state of six level- qubits which are connected linearly with C gates. This hexa-cluster represents an elementary unit of gate operations as seen later. The level- concatenated code states and are also taken as the fundamental clusters in this architecture. They are used as ancillae for encoding and syndrome detection.

iv.2 Single and double verifications

The level- fundamental clusters are constructed by operating the C gates on the level- qubits. These gate operations inevitably introduce errors on the output states. Thus, as seen in Sec. III, we verify and postselect the output states for the high fidelity construction. Specifically, we detect the errors efficiently by combining two verification gadgets, namely single and double verifications.

The C gate operation with single verification is given in terms of a circuit as (14)

where each dashed line with index indicates that seven level- wires are contained there. The single verification is the same as the protocol (5) for the model in Sec. III. The error on the level- qubit is detected by the syndrome extraction after the C gate operation. Furthermore, the preceding error on the level- qubit is detected by the syndrome extraction for the other level- qubit since it is propagated through the C gate as a error.

The cluster diagram for the single verification (14) is given with the fundamental clusters as (15)

where the ’s denote the encoding of for the syndrome extraction in the circuit (14). By considering the encoding (8), the single-verification diagram (15) is fully illustrated in terms of a cluster state of level- qubits as (16)

which may be compared with the diagram (9) in the preliminary model. Here, we observe that the level- C gate operation with single verification, as given in the circuit (14) and diagram (15), is implemented by using ’s, ’s and level- bare C gates.

In order to remove sufficiently the errors in the final stage of construction, we implement the double verification, which may be viewed as a sophistication of the Steane’s QEC gadget in the circuit (1). The C gate operation with double verification is described as follows: (17)

Here, the error verification through a CNOT gate is followed by the error verification through a C gate for high fidelity. Furthermore, the error propagation from the primary ancilla qubit to the data qubit through the two-qubit gate (CNOT or C) is prohibited in the leading order by inspecting the primary with the secondary . In fact, this double verification with the primary and secondary ancilla states has been applied recently to implement a high-performance recurrence protocol for entanglement purification FY09EP , where its optimality for detecting the first-order errors is discussed. We also note that the single and double verifications in (14) and (17) both remove the preceding errors through the C gate by the syndrome extractions for the two level- qubits.

Similar to the single-verification diagram (15), the circuit (17) for the double verification is implemented by a cluster diagram as follows: (18)

The full diagram for (18) is generated by considering the encoding of in (8), similarly to the single-verification diagram (16). We realize in the diagram (18) that the level- C gate operation with double verification is implemented by combining ’s and ’s with level- bare C gates.

iv.3 Concatenated cluster construction

The level- fundamental clusters are constructed from the level- ones via one-way computation. In order to achieve high fidelity, the C gate operations with single and double verifications are combined by using the bare C gates in a suitable way; (i) each qubit has at most one bare C connection (wavy line), and (ii) the output qubits to form the level- fundamental clusters have no bare C connection, and they are doubly verified in the final stage of construction. Specifically, the level- hexa-cluster is constructed as follows: (19)

The 6 ’s are transferred by the encoding (7), and they are entangled through 2 C gates with single verification (15) and 3 C gates with double verification (18) to form the (the output 6 qubits at the level ). This one-way computation to construct the is implemented by measuring the level- qubits, except those for the output ’s, in the three-dimensional diagram for (19). [The full diagram is generated with the code-block axis supplemented according to the encodings (7) and (8), as the diagrams (9) and (16).] The level- syndromes are extracted through the measurements of the ancilla encoded qubits. If all the level- syndromes are correct, the entangled set of six level- qubits survive as a verified .

Since the cluster diagrams such as (19) look somewhat complicated, we introduce suitably the reduced diagrams by omitting the time axis and qubits measured in the one-way computation. The hexa-cluster construction (19) is described as follows: (20)

Here, the single and double lines indicate the single and double verifications, respectively, and it is understood that the single verifications are always done before the double verifications. We construct similarly the fundamental clusters and as (21)

where the boxed level- qubits are measured transversally in the basis for Hadamard operations. We see that in these reduced diagrams all the qubits have at least one double-line connection, that is they are doubly verified in the final stage of construction. We can produce systematically the construction processes such as (19) from the reduced diagrams. The details are described in the Appendix A.

At the beginning of concatenation, the construction of the level-2 fundamental clusters by the physical-level computation is somewhat different from the constructions at the higher levels. This is because the verified level-1 fundamental clusters are not available by definition from the lower-level construction. It may be suitable to adopt the circuit-model computation at the physical level since both CNOT and C gates are deterministically available. The level-1 and are first encoded and verified against the and errors by measuring the and stabilizers, respectively. They are, however, not clean enough for the present purpose. We secondly verify the and errors on the and , respectively, as follows: (22)

This operation is the same as the multi-partite entanglement purification DAB03ADB05 . Then, we construct the level-2 fundamental clusters , and from these verified level-1 qubits and by implementing the circuits (14) and (17) with the bare C gates () according to the reduced diagrams (20) and (21). It is also possible to perform the physical-level one-way computation by means of the cluster diagrams to implement the relevant circuits for the level-2 construction. Additional errors are, however, introduced lowering slightly the noise threshold since the extra operations are required for the CNOT gate operations in the one-way computation. This will be considered explicitly in Sec. VII.

iv.4 Universal computation

The fundamental clusters are constructed through verification up to the highest logical level to achieve the fidelity required for a given computation size. Then, we can perform accurately the computation with Clifford gates by combining the highest-level hexa-clusters with the transversal bare C gates and performing the Pauli basis measurements of the level- qubits in the cluster states. Furthermore, we can implement even non-Clifford gates for universal computation as explained below.

In the cluster model the operation is implemented by the measurement in the basis with to be selected according to the outcome of preceding measurements OWC . The non-Clifford gates, e.g., the gate = , however, do not operate transversally even on the Steane seven-qubit code. Then, in order to implement the gate with a transversal measurement, we make use of the equivalence as follows: (23)

As a result, the operation can be implemented by the preparation of the state and the measurement with the or operation (the selection of measurement basis or ). The preparation of is reduced to that of based on the relation

 Z(−π/4)|+⟩=eiϕHS|π/8⟩, (24)

where is a certain phase. In this way we can implement the , , and C gates as a universal set by the transversal Pauli basis measurements of the level- qubits, including , in the level- cluster states FY07 ; Silva07 .

The level-1 is encoded by the usual method Knill98 ; Knill05a . Then, similarly to the other fundamental clusters the upper-level () is encoded with the lower-level , as shown in the following reduced diagram: (25)

where the circle indicates the transfer of through a rotation, similarly to the and encoding operations. The logical failure of , however, cannot be detected in the construction of because it has also the correct syndrome. Thus, this small mixture of is not reduced by the concatenation, though the constructed is kept on the code space by verification, retaining the logical fidelity as the . This slightly noisy () is even useful to obtain the desired high fidelity at the highest level by using the magic state distillation with Clifford operations BK05 ; Reichardt05 .

V Noise threshold

We have described in the previous section how to construct the verified fundamental clusters in concatenation, which enables us to implement universal computation fault-tolerantly. In the following sections we investigate the performance of this cluster-based architecture, including a high noise threshold by postselection and reasonable resources usage for scalability.

The construction of fundamental clusters is performed via the one-way computation at the lower level. This provides readily the threshold condition for the cluster-based architecture: The error probability for the measurement of each logical qubit, which composes the verified fundamental clusters, should be reduced arbitrarily by raising the concatenation level. The errors in measuring the logical qubits are twofold; (i) the errors on the logical qubits themselves, and (ii) the errors on the Pauli frames, which are propagated as by-products of one-way computation OWC . The errors of (ii) are thus given by induction as some multiple of those of (i) in the leading order. We also note, as discussed in Sec. III, that the cluster-based architecture exploits a good transversal property on a suitable code, which provides, in collaboration with the postselection, a simple concatenation structure of the logical errors in the verified fundamental clusters. Here, we estimate the noise threshold by considering these features of the cluster-based architecture. In this calculation we adopt the noise model as follows:

A two-qubit gate is followed by errors with probabilities (, and ).

The physical qubits and are prepared as mixed-states with an error probability :

 |0⟩ → (1−pp)|0⟩⟨0|+pp|1⟩⟨1|, (26) |+⟩ → (1−pp)|+⟩⟨+|+pp|−⟩⟨−|. (27)

The measurement of a physical qubit in the () basis is described by positive-operator-valued measure (POVM) elements with an error probability :

 M+A = (1−pM)E+A+pME−A, (28) M−A = (1−pM)E−A+pME+A, (29)

where are the projectors to the eigenstates of the Pauli operator , respectively.

v.1 Homogeneous errors in verified clusters

We first consider the errors on the level-0 (physical-level) qubits encoded in the level-2 fundamental clusters. Although the correlated errors are introduced in the encoding process of the level-1 qubits, they are detected and discarded by postselection sufficiently through the single and double verifications in the circuits (14) and (17) for the level-2 cluster construction. These verification protocols are implemented by the transversal operations. Thus, it is reasonably expected that the level-0 qubits encoded in these verified level-1 qubits, which compose the level-2 fundamental clusters, have independently and identically distributed (homogeneous) depolarization errors in the leading order Eastin07 . Specifically, the homogeneous error probabilities () for the level-0 qubits are determined by those for the physical two-qubit gates which are used transversally for the double verification in the final stage of construction. This is illustrated in the circuit (17) as (30)

providing the homogeneous errors,

 ϵX=pXI,ϵY=pYI,ϵZ = 2pZI, (31)

up to the higher-order contributions. The errors preceding the double verification, including the preparation error with , are fully detected and discarded by postselection in the leading order, as discussed below the circuit (17).

The verified level-2 fundamental clusters are connected with the transversal bare C gates to construct the level-3 fundamental clusters as shown in the diagram (19). After the one-way computation with postselection, the output level-2 qubits are left successfully, composing the level-3 fundamental clusters. Here, it should be noted that the output level-2 qubits, ’s in the diagram (19), are never touched directly in the level-3 cluster construction. Instead, the entanglement by the verified C gates is transferred via teleportation (one-way computation) transversally to the output level-2 qubits to form the verified level-3 fundamental clusters. Thus, each constituent level-0 qubit in these entangled level-2 qubits inherits transversally the homogeneous errors in Eq. (31) after the double verification in the level-2 cluster construction. The above argument is extended recursively to the verified level- fundamental clusters (). As a result, the errors in the verified fundamental clusters (before the bare C connections in the next-level construction) are reasonably described in terms of the homogeneous errors on the level-0 qubits. This fact really simplifies the error structure in the cluster-based architecture. Furthermore, the Pauli frame errors are removed in the leading order for the output qubits through the double verification. Thus, the cluster-based architecture provides a scalable way to construct a concatenated code state whose errors are well approximated by the homogeneous errors, which was assumed in Ref. Eastin07 .

v.2 Noise threshold calculation

We next consider the errors for the measurement of the logical qubits in the one-way computation to construct the verified fundamental clusters. The level- clusters with the homogeneous errors on their constituent level-0 qubits are used for the level- cluster construction. As seen in the previous section, e.g., the diagram (16), some pairs of level- qubits in these level- clusters are connected by the bare C gates. As a result, extra errors are added transversally to the constituent level-0 qubits through the bare C connection, as shown in the following diagram: (32)

Then, the homogeneous errors after the bare C connection are given in the leading order as

 ϵ′X = ϵX+∑B=I,X,Y,ZpXB, (33) ϵ′Y = ϵY+∑B=I,X,Y,ZpYB, (34) ϵ′Z = ϵZ+ϵX+ϵY+∑B=I,X,Y,ZpZB. (35)

Now we are ready to calculate the error probability for the measurement of the bare-connected level- qubit which is implemented in concatenation by the transversal measurements of the constituent lower-level qubits. Consider first the level-1 qubits composing the level-2 fundamental clusters, which are measured in the level-1 one-way computation for the level-3 cluster construction. Note here that the level-0 qubits (constituents of the level-1 qubits) are not assigned the Pauli frames in the circuit-model computation at the physical level to construct the level-2 fundamental clusters. (Even if the cluster-model computation is adopted at the physical level, the Pauli frame error can be neglected in a good approximation, which is left only as the second-order error contribution after the double verification.) Thus, the measurement of the level-1 qubit is affected by the errors on the level-0 qubits and the physical measurement error . The logical error probability for the measurement of the bare-connected level-1 qubit is then calculated in the leading order on the Steane seven-qubit code with distance 3 as

 p(1)q≃7C2(ϵ′Z+ϵ′Y+pM)2≡7C2(p(0)q)2, (36)

where is defined as the error probability for the measurement of the bare-connected level-0 qubit. It is apparent here that by choosing properly the physical basis the errors for the and measurements are arranged to be smaller than for the measurement, i.e., .

The outcomes of the measurements of the level-1 qubits are propagated to the neighboring qubits by updating the Pauli frames according to the rule of one-way computation OWC . Then, the errors on the measurement outcomes with the probability are accumulated during the computation. The blocks of seven output level-1 qubits (level-2 qubits) to form the level-3 fundamental clusters are, however, doubly verified in the final stage of one-way computation. Thus, the propagation of the preceding measurement errors as the Pauli frame error is prohibited by postselection in the leading order for these output level-1 qubits, as discussed in the circuit (17):

 p(1)Pauli∼(p(1)q)2. (37)

Subsequently, the level-2 one-way computation is performed by using the level-3 fundamental clusters to construct the level-4 fundamental clusters, where the constituent level-2 qubits are measured. Some of the level-2 qubits are connected with the transversal bare C gates for the first time in this computation. The measurement of the (bare-connected) level-2 qubit is executed by measuring the (bare-connected) level-1 qubits transversally. The seven level-1 measurement outcomes together with the seven level-1 Pauli frames determine the level-2 measurement outcome. Then, by considering Eq. (37) the error probability for measuring the level-2 qubit after the bare C connection is given in the leading order as

 p(2)q≃7C2(p(1)q+p(1)Pauli)2≃7C2(p(1)q)2. (38)

As for the logical error left on the Pauli frame of each output qubit after the cluster construction, similarly to Eq. (37), it is reduced by the double verification as

 p(l−1)Pauli∼(p(l−1)q)2(l≥2). (39)

Thus, the error probability for measuring the level- qubit is calculated in concatenation as

 p(l)q≃7C2(p(l−1)q)2≃(7C2p(0)q)2l/7C2. (40)

The threshold condition is then given from Eq. (40) as

 p(0)q=Dpg<1/7C2, (41)

and the noise threshold is estimated as

 pth≃(7C2D)−1, (42)

where represents the mean error probability for physical operations (). Typically with for and Knill05b , where , the noise threshold is estimated approximately as .

v.3 Numerical simulation

We have made numerical calculations to confirm the above estimation of the error probability for measuring the logical qubit and the noise threshold for computation by simulating the construction of fundamental clusters. Figure 1: The error probabilities ϵA/(pg/15) (A=X,Y,Z) for each level-0 qubit are plotted as functions of the physical error probability pg together with their leading values ϵX(pg/15)=ϵY/(pg/15)=1 and ϵZ/(pg/15)=2.

First, we have constructed the level-2 fundamental clusters according to the diagrams (20) and (21) by implementing the C operations with single and double verifications for the level-1 encoded qubits in the circuits (14) and (17) with bare C gates (transversal operation of physical C gates). Then, we have checked the error probabilities () for each level-0 qubit which is contained in the output level-1 qubits as the verified level-2 fundamental clusters. In Fig. 1 are plotted as functions of the physical error probability , where , and Knill05b are specifically adopted. In the case of they are in good agreement with the leading values and in Eq. (31). On the other hand, in the case of become larger due to the higher-order contributions, which are thus significant for . It has been also checked for that these errors are almost independent among the level-0 qubits; the correlated errors are one order of magnitude smaller than the independent ones even when the higher-order contributions are significant for . We have then evaluated the error probability for measuring the output level-1 qubit (component of the level-2 fundamental cluster) after operating the bare C gate on it. It is plotted in Fig. 2 as a function of . Figure 2: The error probability p(1)q for measuring the level-1 qubit after the bare CZ connection is plotted as a function of the physical error probability pg. The error probabilities p(1)Pauli for the Pauli frames (X,Y,Z) of the level-1 qubit are also plotted as functions of pg in comparison with p(1)q. The upper-most line indicates p(0)q in comparison to infer the threshold.

Next, we have constructed the level-3 fundamental clusters by simulating the one-way computation for the level-1 qubits (level-2 cluster states) in the diagrams such as (19) or their full three-dimensional versions. Then, we have calculated the error probabilities for the Pauli frames () of the level-1 qubit which is contained in the output level-2 qubit (component of the level-3 fundamental cluster). They are plotted in Fig. 2 as functions of in comparison with the error probability for measuring the level-1 qubit. This result really confirms that is suppressed substantially by the double verification, to be of the second order of , as shown in Eq. (37). Figure 3: The error probability p(2)q for measuring the level-2 qubit after the bare CZ connection is plotted as a function of the physical error probability pg, together with the leading term 7C2(p(1)q)2 (dotted line). The upper-most line indicates p(1)q in comparison to infer the threshold.

By using these values of and for the level-1 qubit, we have calculated the error probability for measuring the output level-2 qubit (component of the level-3 fundamental cluster) after the bare C connection. It is plotted as a function of in Fig. 3 together with the leading term (dotted line) as given in Eq. (38). (The error effect for due to the bare C connection is already taken into account transversally as a contribution in .) Here, it is found that for near the threshold the level-2 qubit error becomes significantly higher than its leading value (dotted line) due to the higher-order contributions including the Pauli frame error. The logical error probability, however, decreases through concatenation as for . This certainly indicates that the noise threshold is about , which is in reasonable agreement with the leading-order estimate in Eq. (42). The noise threshold of the present architecture is considerably higher than those of the usual circuit-based architectures with the Steane seven-qubit code. It is also comparable to those of the two architectures, error-correcting and postselecting ones Knill05a .

Vi Resources usage

The physical resources (qubits and gates) are calculated by counting the numbers of hexa-clusters, ancilla code states and bare C gates which are used in the diagrams for the construction of fundamental clusters. In this calculation we present recursion relations of the resources required for the components corresponding to the single verification, double verification, hexa-cluster , ancilla qubits and , respectively.

The single verification in the diagram (15) or its full version (16) uses 17 ’s, 2 ’s and 2 level- transversal bare C gates, that is

 R(l)S = 1×7R(l)h+2(R(l)++R(l)b)(l≥2), (43)

where

 R(l)b=7l (44)

indicates the resources for a level- transversal bare C gate (the number of physical C gates). Similarly, the resources for the double verification, which uses ’s, 8 ’s and and level- bare C gates in the diagram (18), are given as

 R(l)D=3×7R(l)h+8(R(l)++R(l)b)+2R(l)b(l≥2). (45)

Furthermore, the resources used to construct the level- fundamental clusters , and are counted from the reduced diagrams (20) and (21) as

 R(l+1)α = ∑β=S,D,0,bnβαR(l)βp(l+1)α(α=h,0,+;l≥1), (46)

with the numbers of the respective level- components

 (nSh,nDh,n0h,nbh) = (2,3,6,10), (47) (nS0,nD0,n00,nb0) = (6,7,11,26), (48) (nS+,nD+,n0+,nb+) = (5,7,10,24), (49)

and the success probabilities for the clusters to pass the verification process with postselection. Here, the bare C gates are used in the processes, (i) the encodings with (), and (ii) the connections between the outputs after the verifications and the inputs to the subsequent verifications, where is subtracted for the final outputs (). Thus, the number of the level- bare C gates is given by , i.e., , and . The bare C gates are also used in the verification diagrams, which are properly counted in and . The level-1 resources are given in the circuits (14), (17) and (22) as

 R(1)S = 3R(1)b+2R(1)0, (50) R(1)D = 9R(1)b+8R(1)0, (51) R(1)0 = R(1)+=69/p(1)0. (52)

Here, is counted as follows. The Steane seven-qubit code state is encoded into 7 physical qubits by using 9 CNOT gates Stea98 . This code state is preliminarily verified through 3 stabilizer measurements, each of which consumes 1 ancilla qubit and 4 CNOT gates. At this stage resources are used for each preliminarily verified code state. Then, the code sate is secondly verified according to the circuit (22), where 2 preliminarily verified code states and 7 (transversal) CNOT gates are used. Thus, the number of resources used to prepare the level-1 code state amounts to including the success probability .

The success probabilities have been evaluated in the numerical simulation for the cluster construction. In Fig. 4 we plot especially () as functions of the physical error probability for the levels . The level-1 appears to be rather high since the physical-level computation is implemented in the circuits with less operations. Then, the level-2 decreases substantially due to the low fidelity of the level-2 fundamental clusters for the level-3 cluster construction. However, the success probabilities almost approach unity at the levels 4 and higher as the error probability for the logical qubit is reduced rapidly for below the threshold. Figure 4: The success probabilities p(l)0 are plotted as functions of the physical error probability pg for the levels l=1,2,3,4.

The resources are evaluated by using the above recursion relations with the success probabilities simulated numerically, depending on the computation size , where the highest level is given as to achieve the accuracy . The results of () are shown in Fig. 5 for the present architecture of verified logical clusters (LC) with and , which are compared with the resources for the circuit-based Steane’s QEC scheme with Stea03 . Each step in these graphs indicates the rise of the highest level by one. We find that the present architecture really consumes much less resources than the Steane’s QEC scheme for (checked numerically also for ). This indicates that the overhead costs paid for the verification process with postselection in the cluster construction are worth enough to save the total resources usage by reducing rapidly the logical error probability. Thus, the present cluster-based architecture is quite efficient with respect to both noise threshold and resources usage, compared with the usual circuit-based QEC schemes with the Steane seven-qubit code. Figure 5: Resources for the present architecture of verified logical clusters (LC) with pg=10−2 and 10−3, which are compared with those for the Steane’s QEC scheme with pg=10−3.

We also compare the present architecture with the postselecting and error-correcting architectures Knill05a . The postselecting architecture makes use of the usual circuit-based non-determinism for fault-tolerant gate operation, which is different from the error-precorrection in the cluster-based architecture. It is thus lacking in scalability by itself, requiring the construction of a large QEC code state at a certain level with the decoding of the lower-level error-detection code, in order to implement the standard fault-tolerant computation at the higher levels. The resources usage of the postselecting architecture amounts to be quite large as for the overhead cost of the large QEC code state. On the other hand, the noise threshold and resources usage for the error-correcting architecture with the Fibonacci scheme are both comparable to those for the present cluster-based architecture with the Steane seven-qubit code.

Vii Miscellaneous

We further discuss some issues concerning the performance of the cluster-based architecture.

vii.1 Memory error effect

The memory errors may be significant in the cluster-based architecture without recovery operation. The qubits to form the clusters are not touched directly (but via one-bit teleportation) through the concatenated constructions after the level-1 verification. Then, the memory errors accumulate until they are measured in the upper-level construction. The memory errors are added as , where denotes the probability of memory error with the effective waiting time for one measurement, and is the number of waiting time steps at each concatenation level (e.g., for the hexa-cluster). The noise threshold is thus estimated roughly as

 pth∼[7C2{1+log2(log10N)nτm}]−1, (53)

depending on the computation size with the highest level . For example, for and (), which will be tolerable for practical computations. In order to overcome essentially the memory error accumulation, the fundamental clusters as two-colorable graph states may be refreshed at each level by using a purification protocol DAB03ADB05 ; Goyal06 .

vii.2 One-way computation at the physical level

We may use the one-way computation even at the physical level, instead of the circuit computation, for the construction of level-2 fundamental clusters. The level-1 qubits are encoded through the verification by the cluster versions of the circuits in (22). Then, the level-2 hexa cluster is constructed through the single and double verifications as given in the reduced diagram in (20) by combining the physical qubits and level-1 code states with the transversal bare C gates: (54)

The level-2 code states are constructed similarly according to the reduced diagrams in (21). The homogeneous errors for the resultant level-1 qubits (components of the level-2 clusters) are estimated in the first order by inspecting the double verification process in the final stage, where extra C gates are required for the CNOT gate operations inducing additional errors: , , . The noise threshold is slightly lowered as with in Eq. (42).

vii.3 Application of other QEC codes

So far we have considered only the Steane seven-qubit code in the present architecture. Here, we briefly discuss application of some other QEC codes, say code . If the code is a self-dual CSS code or a CSS code which has high symmetry such as the Bacon-Shor subsystem code, the cluster-based architecture can be applied straightforwardly by taking the hexa-cluster and the graph state equivalents of the code states of as the fundamental clusters. The behavior of logical errors is, however, somewhat different, depending on the distance of as seen in the following two examples.

We first consider the four-qubit error detection code . The Fibonacci scheme can be used for the code to generate deterministically the logical measurement outcomes from the physical ones in one-way computation. Then, the cluster-based concatenation can be carried out with the error detection code almost in the same way as with the Steane’s seven-qubit code. In this case, we may reduce the resources to prepare the level-2 fundamental clusters with high success probability, since the number of error locations is smaller than that for the Steane seven-qubit code Knill05a ; Aliferis . As a trade-off the error probability for the Pauli frame becomes , while the error probability for measuring the level-1 qubit is . Thus, the Pauli frame provides a more significant error contribution near the threshold than the case of the Steane seven-qubit code with .

We next consider the Golay code, which is a 23-qubit self-dual CSS code with distance 7. In this case, although we have to pay much more resources at the lowest level, the logical errors are reduced substantially as and Stea03 ; Cross07 . Thus, it will be possibility to improve the noise threshold of the cluster-based architecture by using the Golay code.

We further mention that even with the Steane seven-qubit code the present architecture has a room to improve its performance. The optimal decoding (adaptive concatenation) technique Poulin06Fern08 , which boosts the correctable error of the Steane seven-qubit code up to , is readily available to improve the noise threshold by generating efficiently the logical measurement outcomes in one-way computation.

Viii Conclusion

We have investigated an efficient architecture for fault-tolerant quantum computation, which is based on the cluster model of encoded qubits. Some relevant logical cluster states, fundamental clusters, are constructed through verification without recovery operation in concatenation, which provides the error-precorrection of gate operations for the one-way computation at the higher level. A suitable code such as the Steane seven-qubit code is adopted for transversal operations. This construction of fundamental clusters provides a simple transversal structure of logical errors in concatenation, and achieves a high noise threshold by using appropriate verification protocols, namely the single and double verifications. Since the postselection is localized within each fundamental cluster with the help of deterministic bare C gates without verification, divergence of resources is restrained, which reconciles postselection with scalability. Detailed numerical simulations have really confirmed these desired features of the cluster-based architecture. Specifically, the noise threshold is estimated to be about , and the resources usage is much less than those of the usual circuit-based QEC schemes with the Steane seven-qubit code. This performance is comparable to that of the error-correcting architecture with the Fibonacci scheme. Some means may hopefully be applied for the cluster-based architecture to improve its performance, including the error-detecting code with the Fibonacci scheme, other self-dual CSS codes such as the Golay code, which are more robust for logical encoding than the Steane seven-qubit code, and the adoptive concatenation or optimal decoding.

Acknowledgements.
This work was supported by the JSPS Grant No. 20.2157.

Appendix A Diagrams for cluster construction

We can produce systematically the diagrams for cluster construction from the reduced ones (20) and (21), according to the following rules: (i) Replace the single edge with the single verification (15). (ii) Replace the double edge with the double verification (18) so that the double verifications are always placed at the right side (namely later in time) of the single verifications. (iii) Put the encodings on the input qubits at the leftmost (initially in time). (iv) Apply the bare C gate (wavy line) to connect the output qubit of the preceding verification to the input qubit of the following verification. In the case that the double verification is followed by the other double verification, we cut off the leftmost qubit of the following verification by measurement before connecting these double verifications, in order to remove the redundant rotation. This prescription is illustrated in the following diagram: (55)

The cluster diagram (19) for is generated according to these rules (i)–(iv). The cluster states for and are constructed similarly in the following diagrams, where the pairs of the same characters such as (a)-(a) are actually connected by the bare C gates: (56) (57)

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