 This was reputed to have been due to the timing constants in the ZX8301 chip being optimised for the flat-screen CRT display originally intended for the QL.Internally, the QL comprised the CPU, two ULAs (ZX8301 and ZX8302) and an Intel 8049 microcontroller known as the IPC, or "Intelligent Peripheral Controller".The ZX8301 or "Master Chip" implemented the video display generator and also provided DRAM refresh.