 The removal of the need to consider concurrency control structures within a sieve block can speed up development time and results in safer code.The system is designed for hierarchical based systems with homogeneous or heterogeneous CPU cores which have local memories, connected via DMA engines or similar memory transfer models.Sieve has been shown successfully operating on multi-core x86 systems, the Ageia PhysX Physics Processing Unit, and the IBM Cell microprocessor.