and the Series 32000 architecture was developed instead. Although the new instruction set architecture was not VAX-11 compatible, it did retain its highly "orthogonal" design philosophy. That is, every instruction could be used with any type of data. Articles of the time also referred to this as "symmetrical". The original processor family consisted of the NS16032 CPU and a NS16C032 low-power variant, both having a 16-bit data path and so requiring two machine cycles to load a single 32-bit word. Both could be used with the NS16082 memory management unit, which provided 24-bit virtual memory support for up to 16 MB physical memory. The NS16008 was a cut-down version with an 8-bit external data path and no virtual memory support, which had a reduced pin count and was thus somewhat easier to implement. At the same time, National also announced two future versions, the NS32032 and NS32132. The former was essentially a version of the NS16032 with a 32-bit external data bus, allowing it to read data at twice the rate. This was project to be released in 1984. The NS32132 was a version with a 29-bit internal addresses and 32-bit external, allowing it to address a complete 4 GB of memory. It was to be released in 1985. All of these could also be used with the NS16081 floating point unit. Architecture The processors have 8 general-purpose 32-bit registers, plus a series of special-purpose registers: Frame pointer Stack pointer (one each for user and supervisor modes) Static base register, for referencing global variables Link base register for dynamically linked modules (object orientation) Program counter A typical processor status register, with a low-order user byte and a high-order system byte. (Additional system registers not listed). The instruction set is very much in the CISC model, with 2-operand instructions, memory-to-memory operations, flexible addressing modes, and variable-length byte-aligned instruction encoding. Addressing modes can involve up to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions is much lower than that of contemporary RISC processors. Unlike some other processors, autoincrement of the base register is not provided; the only exception is a "top of stack" addressing modes that pop sources and push destinations. Uniquely, the size of the displacement is encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements.