and the other does not. This is so that the compiler has a way to move instructions around when trying to fill delay slots. SPARC V7 does not have multiplication or division instructions, but it does have MULSCC, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy. SPARC architecture licensees The following organizations have licensed the SPARC architecture: Afara Websystems Bipolar Integrated Technology (BIT) Cypress Semiconductor European Space Research and Technology Center (ESTEC) Fujitsu (and its Fujitsu Microelectronics subsidiary) Gaisler Research HAL Computer Systems Hyundai LSI Logic Matra Harris Semiconductors (MHS) Matsushita Electrical Industrial Co. Meiko Scientific Metaflow Technologies Philips Electronics Prisma Ross Technology Solbourne Computer Systems & Processes Engineering Corporation (SPEC) TEMIC Weitek Implementations Notes: Operating system support SPARC machines have generally used Sun's SunOS, Solaris, or OpenSolaris including derivatives illumos and OpenIndiana, but other operating systems have also been used, such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux. In 1993, Intergraph announced a port of Windows NT to the SPARC architecture, but it was later cancelled. In October 2015, Oracle announced a "Linux for SPARC reference platform". Open source implementations Several fully open source implementations of the SPARC architecture exist: LEON, a 32-bit radiation-tolerant, SPARC V8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL. OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement. S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed