the DCUs provide the means to perform memory scrubbing, it is the SCU that controls the process. The SCU contains approximately 0.23 million transistors, all of them for logic, on a die measuring approximately 130 mm². I/O unit The POWER1's I/O interfaces are implemented by the I/O unit, which contains an I/O channel controller (IOCC) and two serial link adapters (SLAs). The IOCC implements the Micro Channel interface and controls both I/O and DMA transactions between the Micro Channel adapters and the system memory. The two SLAs each implement a serial fibre optic link, which are intended to connect RS/6000 systems together. The optical links were not supported at the time of the RS/6000's release. The I/O unit contains approximately 0.5 million transistors, with 0.3 million used for logic and 0.2 million used for memory, on a die measuring approximately 160 mm². See also Instruction set architectures: IBM POWER Instruction Set Architecture, PowerPC, Power ISA Processors: RISC Single Chip, RAD6000, POWER2, POWER3, POWER4, POWER5, POWER6, POWER7, POWER8, POWER9, Power10 Computer Systems: RS/6000, Scalable POWERparallel Related technology: PowerPC 601, RS64 References Great Microprocessors of the Past and Present (V 13.4.0) Further reading Relevant parts: Chapter 3 (how the POWER architecture is meant to be implemented), Chapters 4 and 5 (describes the POWER1). IBM microprocessors Superscalar microprocessors 32-bit microprocessors