in some DSPs such as the TMS320C30. Fixed-point unit (FXU) The FXU is responsible for decoding and executing all fixed-point instructions and floating-point load and store instructions. For execution, the FXU contains the POWER1's fixed-point register file, an arithmetic logic unit (ALU) for general instructions, and a dedicated fixed-point multiply and divide unit. It also contains instruction buffers that receive both fixed- and floating-point instructions from the ICU, passing on the floating-point instructions to the FPU, and a 128-entry two-way set-associative D-TLB for address translation. The FXU contains approximately 0.5 million transistors, with 0.25 million used for logic and 0.25 used for memory, on a die measuring approximately 160 mm². Floating-point unit (FPU) The POWER1's floating point unit executes floating-point instructions issue by the ICU. The FPU is pipelined and can execute single precision (32-bit) and double precision (64-bit) instructions. It is capable of performing multiply-add instructions, which contributed to the POWER1's high floating point performance. In most processors, a multiply and an add, which is common in technical and scientific floating-point code, cannot be executed in one cycle, as in the POWER1. Use of fused multiply–add also means that the data is only rounded once, improving the precision of the result slightly. The floating-point register file is also located on the FPU chip. It contains 32 64-bit floating-point registers, six rename registers and two registers that are used by divide instructions. Data-cache unit (DCU) The POWER1 has a 64 KB data cache implemented through four identical data-cache units (DCU), each containing 16 KB of data cache. The cache and the buses that connect the DCU to the other chips are ECC protected. The DCUs also provide the interface to the memory. If two DCUs are present (RIOS.9 configuration), the memory bus is 64 bits wide, and if four DCUs are present (RIOS-1 configuration), the memory bus is 128 bits wide. The memory interface portion of the DCUs provide three features that improves the reliability and availability of the memory: memory scrubbing, ECC and bit steering. Each DCU contains approximately 1.125 million transistors, with 0.175 million used for logic and 0.95 million used for SRAM, on a die measuring approximately 130 mm² (11.3 × 11.3 mm). Storage-control unit (SCU) The POWER1 is controlled by the SCU chip. All communications between the ICU, FXU and DCU chips as well as the memory and I/O devices is arbitrated by the SCU. Although