may also be divided by an integer multiple before being input to the phase comparator. This allows the synthesis of frequencies that are N/M times the reference frequency. This can be accomplished in a different manner by periodically changing the integer value of an integer-N frequency divider, effectively resulting in a multiplier with both whole number and fractional component. Such a multiplier is called a fractional-N synthesizer after its fractional component. Fractional-N synthesizers provide an effective means of achieving fine frequency resolution with lower values of N, allowing loop architectures with tens of thousands of times less phase noise than alternative designs with lower reference frequencies and higher integer N values. They also allow a faster settling time because of their higher reference frequencies, allowing wider closed and open loop bandwidths. Delta sigma synthesizer A delta sigma synthesizer adds a randomization to programmable-N frequency divider of the fractional-N synthesizer. This is done to shrink sidebands created by periodic changes of an integer-N frequency divider. PLL References Egan, William F. 2000. Frequency Synthesis by Phase-lock, 2nd Ed., John Wiley & Sons, Fractional N frequency synthesizer with modulation compensation U.S. Patent 4,686,488, Attenborough, C. (1987, August 11) Programmable fractional-N frequency synthesizer U.S. Patent 5,224,132, Bar-Giora Goldberg, (1993, June 29) See also Heterostructure barrier varactor CPU multiplier References Communication circuits