superscalar CPU. It contains three major execution units, a fixed-point unit (FXU), a branch unit (BPU) and a floating point unit (FPU). Although the POWER1 is a 32-bit CPU with a 32-bit physical address, its virtual address is 52 bits long. The larger virtual address space was chosen because it was beneficial for the performance of applications, allowing each one to have a large 4 GB address range. The POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction and data caches. The instruction cache, referred to as the "I-cache" by IBM, is 8 KB in size and is two-way set associative with a line size of 64 bytes. The I-cache is located on the ICU chip. The data cache, referred to as the "D-cache" by IBM, is 32 KB in size for RIOS.9 configurations and 64 KB in size for RIOS-1 configurations. The D-cache is four-way set associative with a line size of 128 bytes. The D-cache employs a store-back scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory. The store-back scheme is used to prevent the CPU from monopolizing access to the memory. Although the POWER1 was a high-end design, it was not capable of multiprocessing, and as such was disadvantaged, as the only way performance could be improved was by clocking the CPU higher, which was difficult to do with such a large multi-chip design. IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity of SP1 supercomputers based on the POWER1. As the POWER1 was the basis of the POWER2 and P2SC microprocessors, the lack of multiprocessing was passed on to these later POWER processors. Multiprocessing was not supported until the introduction of the POWER3 in 1998. Physical description The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of an instruction-cache unit (ICU), a fixed-point unit (FXU), a floating point unit (FPU), a number of data-cache units (DCU), a storage-control unit (SCU) and an I/O unit. Due to its modular design, IBM was able to create two configurations by simply varying the number of DCUs, RIOS-1 and a RIOS.9. The RIOS-1 configuration