has four DCUs, the intended amount, and was clocked at up to 40 MHz, whereas the RIOS.9 CPU had two DCUs and was clocked at lower frequencies. The chips are mounted on the “CPU planar”, a printed circuit board (PCB), using through-hole technology. Due to the large number of chips with wide buses, the PCB has eight planes for routing wires, four for power and ground and four for signals. There are two signal planes on each side of the board, while the four power and ground planes are in the center. The chips that make up the POWER1 are fabricated in a 1.0 µm CMOS process with three layers of interconnect. The chips are packaged in ceramic pin grid array (CPGA) packages that can have up to 300 pins and dissipate a maximum of 4 W of heat each. The total number of transistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.9 million, with 2.04 million used for logic and 4.86 million used for memory. The die area of all the chips combined is 1,284 mm². The total number of signal pins is 1,464. Chips Instruction-cache unit (ICU) The ICU contains the instruction cache, referred to as the "I-cache" by IBM and the branch processing unit (BPU). The BPU contains the program counter, the condition code register and a loop register. The ICU contains 0.75 million transistors with 0.2 million used for logic and 0.55 million used for SRAM. The ICU die measures approximately 160 mm² (12.7 × 12.7 mm). The BPU was capable of dispatching multiple instructions to the fixed and floating point instructions queues while it was executing a program flow control instruction (up to four simultaneously and out of order). Speculative branches were also supported by using a prediction bit in the branch instructions, with the results discarded before being saved if the branch was not taken. The alternate instruction would be buffered and discarded if the branch was taken. Consequently, subroutine calls and interrupts are dealt with without incurring branch penalties. The condition code register has eight field sets, with the first two reserved for fixed and floating point instructions and the seventh for vector instructions. The rest of the fields could be used by other instructions. The loop register is a counter for "decrement and branch on zero" loops with no branch penalty, a feature similar to those found