in single registers. It has a 6 stage long integer pipelines and a 15 stage long floating point pipeline. Its assortment of registers consists of 32 128-bit VLIW SIMD registers (naming/renaming), one 64-bit accumulator and two 64&-bit general data registers, 8 16-bit fix function registers, 16 8-bit controller registers. The processor also has two 64-bit integer ALUs, a 128bit Load-Store Unit (LSU), a Branch Execution Unit (BXU) and a 32-bit VU1 FPU coprocessor (which acted as a sync controller for the VPU0/VPU1) containing a MIPS base processor core with 32 64-bit FP registers and 15 32-bit integer registers. The ALUs are 64-bit, with a 32-bit FPU that isn't IEEE 754 compliant. The custom instruction set 107 MMI (Multimedia Extensions) was implemented by grouping the two 64-bit integer ALUs. Both the integer and floating-point pipelines are six stages long. To feed the execution units with instructions and data, there is a 16 KB two-way set associative instruction cache, an 8 KB two-way set associative non blocking data cache and a 16 KB scratchpad RAM. Both the instruction and data caches are virtually indexed and physically tagged while the scratchpad RAM exists in a separate memory space. A combined 48 double entry instruction and data translation lookaside buffer is provided for translating virtual addresses. Branch prediction is achieved by a 64-entry branch target address cache and a branch history table that is integrated into the instruction cache. The branch mispredict penalty is three cycles due to the short six stage pipeline. Vector processing units The majority of the Emotion Engine's floating point performance is provided by two vector processing units (VPU), designated VPU0 and VPU1. These were essentially DSPs tailored for 3D math, and the forerunner to hardware vertex shader pipelines. Each VPU features 32 128-bit vector SIMD registers (holding 4D vector data), 16 16-bit fixed-point registers, four floating point multiply-accumulate (FMAC) units, a floating point divide (FDIV) unit and a local data memory. The data memory for VPU0 is 4 KB in size, while VPU1 features a 16 KB data memory. To achieve high bandwidth, the VPU's data memory is connected directly to the GIF, and both of the data memories can be read directly by the DMA unit. A single vector instruction consists of four 32-bit single-precision floating-point values which are distributed to the four single-precision (32-bit) FMAC units for processing. This scheme is similar to the SSEx extensions by