KDF9 was an early British 48-bit computer designed and built by English Electric (which in 1968 was merged into International Computers Limited (ICL)). The first machine came into service in 1964 and the last of 29 machines was decommissioned in 1980 at the National Physical Laboratory. The KDF9 was designed for, and used almost entirely in, the mathematical and scientific processing fields in 1967, nine were in use in UK universities and technical colleges. The KDF8, developed in parallel, was aimed at commercial processing workloads. The KDF9 was an early example of a machine that directly supported multiprogramming, using offsets into its core memory to separate the programs into distinct virtual address spaces. Several operating systems were developed for the platform, including some that provided fully interactive use through PDP-8 machines acting as smart terminal servers. A number of compilers were available, notably both checkout and globally optimizing compilers for Algol 60. Architecture The logic circuits of the KDF9 were entirely solid-state. The KDF9 used transformer-coupled diode–transistor logic, built from germanium diodes, about 20,000 transistors, and about 2,000 toroid pulse transformers. They ran on a 1 MHz clock that delivered two pulses of 250 ns separated by 500 ns, in each clock cycle. The maximum configuration incorporated 32K words of 48-bit core storage (192K bytes) with a cycle time of 6 microseconds. Each word could hold a single 48-bit integer or floating-point number, two 24-bit integer or floating-point numbers, six 8-bit instruction syllables, or eight 6-bit characters. There was also provision for efficient handling of double-word (96-bit) numbers in both integer and floating point formats. However, there was no facility for byte or character addressing, so that non-numerical work suffered by comparison. Its standard character set was a version of the Friden Flexowriter paper tape code that was oriented to Algol 60, and included unusual characters such as the Algol subscript 10. However, each other I/O device type implemented its own subset of that. Not every character that could be read from paper tape could be successfully printed, for example. Registers The CPU architecture featured three register sets. The Nest was a 16-deep pushdown stack of arithmetic registers, The SJNS (Subroutine Jump Nesting Store) was a similar stack of return addresses. The Q Store was a set of 16 index registers, each of 48 bits divided into Counter (C), Increment (I) and Modifier (M) parts of 16 bits each. Flags