cache block is flushed onto the bus and state changes to Shared. On a BusRdX, the cache block is flushed onto the bus and state changes to Invalid. A BusUpgr is not possible. Note that by being in the Modified state in one particular processor, a cache block has to be in the Invalid state in all other processor(s), as the Modified state is allowed in either none or only one processor. This effectively negates the possibility of a BusUpgr on the bus, which would require this block to be in the Shared state in one of the processor(s) that, as seen above, issues a PrWr. Usage This protocol is similar to the one used in the SGI 4D machine. Variants Modern systems use variants of the MSI protocol to reduce the amount of traffic in the coherency interconnect. The MESI protocol adds an "Exclusive" state to reduce the traffic caused by writes of blocks that only exist in one cache. The MOSI protocol adds an "Owned" state to reduce the traffic caused by write-backs of blocks that are read by other caches. The MOESI protocol does both of these things. See also Coherence protocol MESI protocol MOSI protocol MOESI protocol MESIF protocol References Cache coherency