of compatible CPUs, it complicates multicycle CPUs (with no pipeline), faster CPUs with longer-than-expected pipelines, and superscalar CPUs (which can execute instructions out of order.) See also Branch delay slot Branch predication Branch table Conditional (programming) Control flow Indirect branch Program counter Subroutine Spaghetti code Notes References External links Free IA-32 and x86-64 documentation, provided by Intel The PDP-11 FAQ The ARM instruction set Control flow Instruction processing Machine code de:Branch (Maschinenbefehl)