(I) state, either the cache block was never fetched from the memory or it was invalidated. When there is a processor read (PrRd), the state changes from invalid (I) to shared (S), thereby generating a bus read (BusRd). At the same time, if it is a processor write request (PrWr), then the state of the block changes to modified (M) along with a snooped write request (BusRdX). Once the block is in the Owned (O) state, then a processor read (PrRd) does not generate any snooped signal and the block remains in the same state. Whereas, a write request from the processor (PrWr) results in changing the state of the block from owned (O) to modified (M) along with generating a snooped write request (BusUpgr). When the block is in the Modified (M) state, neither a processor read (PrRd) nor a processor write (PrWr) request generates a snooped signal since the block already indicates that the most recent and correct value resides only in that cache. Hence, it does not change the state and stays in modified (M) state. While the block is in the Shared (S) state and there is processor read (PrRd) request, since the value of the cache block is the same in every other processor and in the main memory, there is no bus signal that is generated after a processor read (PrRd). A bus write request (BusUpgr) is generated once there is a processor write (PrWr) request to a block in the shared (S) state because the cache block is now no longer valid in all the other caches and the state of the block changes from shared (S) to being modified (M). Bus Transactions Considering the behavior of the finite state machine to snooped bus transactions, if the cache block is in Invalid (I) state then no snooped bus request will affect the block in any way, so even if it is a bus read (BusRd) or bus write request from a processor that has or does not have the block (BusRdX or BusUpgr), the block remains in the same invalid (I) state and does not generate any further actions. When the cache block is in the Shared (S) state and there is a snooped bus read (BusRd) transaction, then the block stays in the same state and generates no more transactions as all the cache blocks have the same value including the main