state, it writes back to the main memory while changing the status of the block to shared (S). But in the case of MOSI protocol, where we have an additional state (owner), whenever another processor requests for a read operation, the block changes from modified to the owned (O) state and so retains the dirty block of cache, thereby removing the need to write back to the main memory immediately. This deferral can save bus traffic and main memory writes in certain sequences of transactions. Consider for example if a cache is M for processor 1, then processor 2 reads from it, and then processor 1 writes again to it. In MSI, the MS transition of processor 1 from the read leads to one memory write, and then the SM transition leads to a BusUpgr. On MOSI, the MO transition generates no traffic, and the OM transition also generates one BusUpgr as before. MOSI therefore dispensed the initial memory write back and associated bus traffic which MSI would do. Comparison to MESI Protocol Both MESI (also known as Illinois) and MOSI protocols, are extensions of the MSI protocol to improve different functionalities. MOSI focuses on reducing write backs and MESI attempts to reduce the number of bus transactions required after a read and write request from another processor. The exclusive (E) state in MESI protocol implies that the cache block is valid, clean (same value as in the main memory) and cached only in one cache whereas the owned (O) state in MOSI protocol implies that the cache block is valid, potentially dirty, writable and could be present in more than one cache (all caches have the same value). References See also Coherence protocol MSI protocol MESI protocol MOESI protocol Cache coherency