The MOSI protocol is an extension of the basic MSI cache coherency protocol. It adds the Owned state, which indicates that the current processor owns this block, and will service requests from other processors for the block. Overview of States Following are the permitted states of a given cache line: Modified (M) - Only one cache has a valid copy of the block and the value is likely to be different from the one in main memory. It has almost the same meaning as a dirty state in a write back cache except for the difference that modified state also implies exclusive ownership of that block. Dirty state just means that the value of the block is different from the one in main memory, whereas, modified implies that the value is different than that of the main memory and that it is cached in only one location. Owned (O) - Multiple caches may hold the most recent and correct value of a block and the value in main memory may or may not be correct. At a time, only one cache can have the owned state for a block. All the other caches with the same block must be in shared state. Shared (S) - Cache block is valid, could be shared by multiple caches, and may or may not have the same value as the main memory. Other processors can read from this, but do not have write permissions. Invalid (I) - Cache block is invalid. For any given pair of caches, the permitted states of a given cache line are as follows: Operations In MOSI protocol, each cache has the following requests: PrRd - Processor request to read a cache block. PrWr - Processor request to write into a cache block. BusRd - Snooped request indicating that there is a read request to a cache block made by another processor. BusRdX - Snooped request indicating that there is a write request to a cache block made by another processor that does not have the block. BusUpgr - Snooped request depicting that there is a write request to a cache block made by another processor that already has the block in its cache. Flush - Snooped request after which the cache block is placed on the bus for a cache to cache transfer. Processor Transactions Looking at the case for processor transactions, when the block is in the Invalid