the block is in the "S" state, the cache must notify any other caches that might contain the block in the "S" state that they must evict the block. This notification may be via bus snooping or a directory, as described above. Then the data may be locally modified. If the block is in the "I" state, the cache must notify any other caches that might contain the block in the "S" or "M" states that they must evict the block. If the block is in another cache in the "M" state, that cache must either write the data to the backing store or supply it to the requesting cache. If at this point the cache does not yet have the block locally, the block is read from the backing store before being modified in the cache. After the data is modified, the cache block is in the "M" state. For any given pair of caches, the permitted states of a given cache line are as follows: State Machine Processor requests to the cache include: PrRd: Processor request to read a cache block. PrWr: Processor request to write a cache block. In addition, there are bus side requests. These include: BusRd: When a read miss occurs in a processor’s cache, it sends a BusRd request on the bus and expects to receive the cache block in return. BusRdX: When a write miss occurs in a processor’s cache, it sends a BusRdX request on the bus which returns the cache block and invalidates the block in the caches of other processors. BusUpgr: When there's a write hit in a processor's cache, it sends a BusUpgr request on the bus to invalidate the block in the caches of other processors. Flush: Request that indicates that a whole cache block is being written back to the memory. State Transitions: Invalid: On a PrRd, BusRd is issued and state changes to Shared. On a PrWr, BusRdX is issued and state changes to Modified. On a BusRd, BusRdX or a BusUpgr an invalid block remains Invalid. Shared: On a PrRd, the block remains in the Shared state. On a PrWr, BusUpgr is issued and state changes to Modified. On a BusRd, the block remains in the Shared state. On a BusRdX or BusUpgr, the block transitions to Invalid. Modified: On a PrRd or PrWr, the block remains in the Modified state. On a BusRd, the