sensitive instructions are a subset of the set of privileged instructions: Handling critical instructions The conditions for ISA virtualization expressed in Theorem 1 may be relaxed at the expense of the efficiency property. VMMs for non-virtualizable ISAs (in the Popek and Goldberg's sense) have routinely been built. The virtualization of such architectures requires correct handling of critical instructions, i.e., sensitive but unprivileged instructions. One approach, known as patching, adopts techniques commonly used in dynamic recompilation: critical instructions are discovered at run-time and replaced with a trap into the VMM. Various mechanisms, such as the caching of emulation code or hardware assists, have been proposed to make the patching process more efficient. A different approach is that of paravirtualization, which requires guest operating systems to be modified (ported) before running in the virtual environment. Instruction sets of common architectures This section presents some relevant architectures and how they relate to the virtualization requirements. PDP-10 The PDP-10 architecture has a few instructions which are sensitive (alter or query the processor's mode) but not privileged. These instructions save or restore the condition codes containing USER or IOT bits: JSR: jump to subroutine JSP: jump and save program counter PUSHJ: push down and jump JRST: jump and restore System/370 All sensitive instructions in the System/370 are privileged: it satisfies the virtualization requirements. Motorola MC68000 The Motorola MC68000 has a single unprivileged sensitive instruction: MOVE from SR This instruction is sensitive because it allows access to the entire status register, which includes not only the condition codes but also the user/supervisor bit, interrupt level, and trace control. In most later family members, starting with the MC68010, the MOVE from SR instruction was made privileged, and a new MOVE from CCR instruction was provided to allow access to the condition code register only. IA-32 (x86) The IA-32 instruction set of the Pentium processor contains 18 sensitive, unprivileged instructions. They can be categorized in two groups: Sensitive register instructions: read or change sensitive registers or memory locations such as a clock register or interrupt registers: SGDT, SIDT, SLDT SMSW PUSHF, POPF Protection system instructions: reference the storage protection system, memory or address relocation system: LAR, LSL, VERR, VERW POP PUSH CALL FAR, JMP FAR, INT n, RETF STR MOV (segment registers) The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allows x86 processors to meet the Popek and Goldberg virtualization requirements. IA-64 The effort