The K5 is AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was closer to the Pentium regarding performance, although faster clock-for-clock compared to the Pentium. Technical details The K5 was based upon an internal highly parallel Am29000 RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility and the in-house-developed test suite proved invaluable on later projects. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating-point unit. The branch target buffer was four times the size of the Pentium's and register renaming helped overcome register dependencies. The chip's speculative execution of instructions reduced pipeline stalls. It had a 16 KB four-way set-associative instruction cache and an 8 KB data cache. The floating-point divide and square-root microcode were mechanically proven. The floating-point transcendental instructions were implemented in hardware and were faithful to true mathematical results for all operands. Performance The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, and in part due to the design itself, which had many levels of logic for the process technology of the day, hampering clock scaling. Additionally, while the K5's floating-point performance was regarded as superior to that of the Cyrix 6x86, it was slower than that of the Pentium, although offering more reliable transcendental function results. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the earlier Am486 and later AMD K6 enjoyed. Features Models There were two revisions of the K5 architecture, internally called the SSA/5 and the 5k86, both released with the K5 label. The original set of "SSA/5" CPUs had its branch prediction unit disabled and additional internal waitstates added; these issues were remedied with the "5k86", resulting in up to 30% better performance clock for clock. The "SSA/5" line ran from 75 to 100 MHz; the "5k86" line ran from 90 to 133 MHz.