latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches. Multi-level caches generally operate by checking the fastest cache, level 1 (L1), first; if it hits, the processor proceeds at high speed. If that smaller cache misses, the next fastest cache, level 2 (L2), is checked, and so on, before accessing external memory. As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. Price-sensitive designs used this to pull the entire cache hierarchy on-chip, but by the 2010s some of the highest-performance designs returned to having large off-chip caches, which is often implemented in eDRAM and mounted on a multi-chip module, as a fourth cache level. In rare cases, such as in the mainframe CPU IBM z15 (2019), all levels down to L1 are implemented by eDRAM, replacing SRAM entirely (for cache, SRAM is still used for registers). The ARM-based Apple M1 has a 192 KiB L1 cache for each of the four high-performance cores, an unusually large amount; however the four high-efficiency cores only have 128 KiB. The benefits of L3 and L4 caches depend on the application's access patterns. Examples of products incorporating L3 and L4 caches include the following: Alpha 21164 (1995) has 1 to 64 MiB off-chip L3 cache. IBM POWER4 (2001) has off-chip L3 caches of 32 MiB per processor, shared among several processors. Itanium 2 (2003) has a 6 MiB unified level 3 (L3) cache on-die; the Itanium 2 (2003) MX 2 module incorporates two Itanium 2 processors along with a shared 64 MiB L4 cache on a multi-chip module that was pin compatible with a Madison processor. Intel's Xeon MP product codenamed "Tulsa" (2006) features 16 MiB of on-die L3 cache shared between two processor cores. AMD Phenom II (2008) has up to 6 MiB on-die unified L3 cache. Intel Core i7 (2008) has an 8 MiB on-die unified L3 cache that is inclusive, shared by all cores. Intel Haswell CPUs with integrated Intel Iris Pro Graphics have 128 MiB of eDRAM acting essentially as an L4 cache. Finally, at the other end of the memory hierarchy, the CPU register file itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software—typically by