"Energy Efficient Small Form Factor" version has a reduced 35 W TDP. The Socket AM2 version also does not require a minimum voltage of 1.1 volts to operate, whereas all socket 754 Semprons with Cool'n'Quiet did. In 2006, AMD was selling both Socket 754 and Socket AM2 Sempron CPUs concurrently. In the middle of 2007 AMD appears to have dropped the 754 line and is shipping AM2 and S1 Semprons. Features table CPU features table Models for Socket A (Socket 462) Thoroughbred B/Thorton (130 nm) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 256 KiB, full speed MMX, 3DNow!, SSE Socket A (EV6) Front side bus: 166 MHz (FSB 333) VCore: 1.6 V First release: July 28, 2004 Clockrate: 1500 MHz – 2000 MHz (2200+ to 2800+) Barton (130 nm) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 512 KiB, full speed MMX, 3DNow!, SSE Socket A (EV6) Front side bus: 166 MHz – 200 MHz (FSB 333 – 400) VCore: 1.6 – 1.65 V First release: September 17, 2004 Clockrate: 2000–2200 MHz (Sempron 3000+, Sempron 3300+) Models for Socket 754 Paris (130 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 256 KiB, full speed MMX, 3DNow!, SSE, SSE2 Enhanced Virus Protection (NX bit) Integrated 72-bit (Single channel, ECC capable) DDR memory controller Socket 754, 800 MHz HyperTransport VCore: 1.4 V First release: July 28, 2004 Clockrate: 1800 MHz (3100+) Stepping: CG (Part No.: *AX) Palermo (90 nm SOI) Early models (stepping D0) are downlabeled "Oakville" mobile Athlon64 L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 128/256 KiB, full speed MMX, 3DNow!, SSE, SSE2 SSE3 support on E3 and E6 steppings AMD64 on E6 stepping Cool'n'Quiet (Sempron 3000+ and higher) Enhanced Virus Protection (NX bit) Integrated 72-bit (Single channel, ECC capable) DDR memory controller Socket 754, 800 MHz HyperTransport VCore: 1.4 V First release: February 2005 Clockrate: 1400–2000 MHz 128 KiB L2-Cache (Sempron 2600+, 3000+, 3300+) 256 KiB L2-Cache (Sempron 2500+, 2800+, 3100+, 3400+) Steppings: D0 (Part No.: *BA), E3 (Part No.: *BO), E6 (Part No.: *BX) Models for Socket 939 Palermo (90 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 128/256 KiB, full speed MMX, 3DNow!, SSE, SSE2, SSE3, AMD64 (E6 Steppings Only), Cool'n'Quiet, NX bit Integrated 144-bit (Dual channel, ECC capable) DDR memory controller Socket 939, 800 MHz HyperTransport VCore: 1.35/1.4 V First release: October 2005 Clockrate: 1800–2000 MHz