immunity. In addition, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacing PROMs and EEPROMs in space systems. Multi-level cell In February 2008, Intel and STMicroelectronics revealed the first multilevel (MLC) PRAM array prototype. The prototype stored two logical bits in each physical cell, in effect 256 Mb of memory stored in a 128 Mb physical array. This means that instead of the normal two states—fully amorphous and fully crystalline—an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area. In June 2011, IBM announced that they had created stable, reliable, multi-bit phase-change memory with high performance and stability. SK Hynix had a joint developmental agreement and a technology license agreement with IBM for the development of multi-level PRAM technology. Intel's 90 nm device Also in February 2008, Intel and STMicroelectronics shipped prototype samples of their first PRAM product to customers. The 90 nm, 128 Mb (16 MB) product was called Alverstone. In June 2009, Samsung and Numonyx B.V. announced a collaborative effort in the development of PRAM market-tailored hardware products. In April 2010, Numonyx announced the Omneo line of 128-Mbit NOR-compatible phase-change memories. Samsung announced shipment of 512 Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010. ST 28 nm, 16 MB array In December 2018 STMicroelectronics presented design and performance data for a 16 MB ePCM array for a 28 nm fully depleted silicon on insulator automotive control unit. In-memory computing More recently, there is significant interest in the application of PCM for in-memory computing. The essential idea is to perform computational tasks such as matrix-vector-multiply operations in the memory array itself by exploiting PCM's analog storage capability and Kirchhoff's circuit laws. PCM-based in-memory computing could be interesting for applications such as deep learning inference which do not require very high computing precision. In 2021, IBM published a full-fledged in-memory computing core based on multi-level PCM integrated in 14 nm CMOS technology node. Challenges The greatest challenge for phase-change memory has been the requirement of high programming current density (>107 A/cm², compared to 105...106 A/cm² for a typical transistor or diode). The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature,