or wave soldering). This was made worse by the requirement to have lead-free manufacturing requiring higher soldering temperatures. A manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place. The special gates used in flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The resistivity of the memory element in PRAM is more stable; at the normal working temperature of 85 °C, it is projected to retain data for 300 years. By carefully modulating the amount of charge stored on the gate, flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles the memory density, reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent advances have removed this problem. Because flash devices trap electrons to store information, they are susceptible to data corruption from radiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation. PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode or a BJT provides the greatest amount of current for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. Chalcogenide resistance is necessarily larger than that of a diode, meaning operating voltage must exceed 1 V by a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the total reverse bias leakage current from the unselected bit lines. In transistor-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete dopants as the p-n junction width scales down. Thin film-based selectors allow higher densities, utilizing < 4 F2 cell area by stacking memory layers horizontally or vertically. Often the isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Chalcogenide-based threshold switches have been demonstrated as a viable selector for high-density PCM arrays 2000 and later In August 2004, Nanochip licensed PRAM technology for use in