128 KiB L2-Cache (Sempron 3000+, 3400+) 256 KiB L2-Cache (Sempron 3200+, 3500+) Steppings: E3 (Part No.: *BP), E6 (Part No.: *BW) Models for Socket AM2 Manila (90 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 128/256 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit (Dual channel) DDR2 memory controller Socket AM2, 800 MHz HyperTransport VCore: 1.25/1.35/1.40 V (1.20/1.25 V for Energy Efficient SFF version) First release: May 23, 2006 Clockrate: 1600–2200 MHz 128 KiB L2-Cache (Sempron 2800+, 3200+, 3500+) 256 KiB L2-Cache (Sempron 3000+, 3400+, 3600+, 3800+) Stepping: F2 (Part No.: *CN, *CW) Sparta (65 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 256/512 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit (Dual channel) DDR2 memory controller Socket AM2, 800 MHz HyperTransport VCore: 1.20/1.40 V First release: August 20, 2007 Clockrate: 1900–2300 MHz 256 KiB L2-Cache (Sempron LE-1100, LE-1150) 512 KiB L2-Cache (Sempron LE-1200, LE-1250, LE-1300) Stepping: G1 (Part No.: *DE), G2 (Part No.: *DP) Brisbane (65 nm SOI) Models for Socket AM3 Sargas (45 nm SOI) Chip harvests from Regor with one core disabled Core Speed (MHz) – 2600–2900 Max Temps (C): 63 VCore: 1.35 V TDP: 45 W L1 Cache Size (KB) 128 L2 Cache Size (KB) 1024 CPU Arch : 1 CPU – 1 Cores – 1 Threads CPU EXT : MMX(+) 3DNow!(+) SSE SSE2 SSE3 SSE4A x86-64 AMD-V, Cool'n'Quiet, NX bit Integrated 128-bit (Dual Channel) DDR2 + DDR3 Memory Controller Socket AM3, 2000 MHz HyperTransport Steppings: C2, C3 Models for Socket S1 (638) Keene (90 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 256 or 512 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit (Dual channel) DDR2 memory controller Socket S1, 800 MHz HyperTransport VCore: 0.950-1.25 V First release: May 17, 2006 Clockrate: 1000–2000 MHz 256 KiB L2-Cache (Sempron 2100+, 3400+) 512 KiB L2-Cache (Sempron 3200+, 3500+, 3600+) Stepping: F2 (Part No.: *CM) Sable (65 nm SOI) L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 512 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit (Dual channel) DDR2 memory controller Socket S1, 1600 MHz HyperTransport VCore: 0.950-1.25 V First release: January 8, 2009 Clockrate: 2000–2100 MHz 25w 512 KiB L2-Cache Models for ASB1 package (BGA) Huron (65 nm SOI)