for a laptop); the total cache memory size is not unusually large (the total is more important for throughput) for a laptop, and much larger total (e.g. L3 or L4) sizes are available in IBM's mainframes. Current research Early cache designs focused entirely on the direct cost of cache and RAM and average execution speed. More recent cache designs also consider energy efficiency, fault tolerance, and other goals. There are several tools available to computer architects to help explore tradeoffs between the cache cycle time, energy, and area; the CACTI cache simulator and the SimpleScalar instruction set simulator are two open-source options. Multi-ported cache A multi-ported cache is a cache which can serve more than one request at a time. When accessing a traditional cache we normally use a single memory address, whereas in a multi-ported cache we may request N addresses at a time where N is the number of ports that connected through the processor and the cache. The benefit of this is that a pipelined processor may access memory from different phases in its pipeline. Another benefit is that it allows the concept of super-scalar processors through different cache levels. See also Branch predictor Cache (computing) Cache algorithms Cache coherence Cache control instructions Cache hierarchy Cache placement policies Cache prefetching Dinero (cache simulator by University of Wisconsin System) Instruction unit Locality of reference Memoization Memory hierarchy Micro-operation No-write allocation Scratchpad RAM Sum-addressed decoder Write buffer Notes References External links Memory part 2: CPU caches an article on lwn.net by Ulrich Drepper describing CPU caches in detail Evaluating Associativity in CPU Caches – Hill and Smith (1989) – introduces capacity, conflict, and compulsory classification Cache Performance for SPEC CPU2000 Benchmarks – Hill and Cantin (2003) – This reference paper has been updated several times. It has thorough and lucidly presented simulation results for a reasonably wide set of benchmarks and cache organizations. Memory Hierarchy in Cache-Based Systems – by Ruud van der Pas, 2002, Sun Microsystems – a nice introductory article to CPU memory caching A Cache Primer – by Paul Genua, P.E., 2004, Freescale Semiconductor, another introductory article An 8-way set-associative cache written in VHDL Understanding CPU caching and performance an article on Ars Technica by Jon Stokes IBM POWER4 processor review an article on ixbtlabs by Pavel Danilov What is Cache Memory and its Types! Memory Caching a Princeton University lecture Central processing unit Computer memory