read during the VBLANK period. Registers in the TIA allow the programmer to control the positioning of the graphical objects and their color. The TIA also provides two channels of one-bit sound. Each channel provides for 32 pitch values and 16 possible bit sequences. There is a 4 bit volume control. Lastly, the TIA has inputs for reading up to four analog paddle controllers using potentiometers and for two joystick triggers. Drawing the display As the registers hold data for only a single line of the display, creating a full screen requires the game program to update the registers on the fly, a process known as "racing the beam". To start the process, the game program running on the MOS Technology 6502-based CPU loads the TIA's registers with the data needed to draw the first line of the display. The TIA then waits until the television is ready to draw the line (under the command of the TIA's associated analog hardware) and read out the registers to produce a signal for that line. During the horizontal blanking period between lines, the 6502 quickly changes the TIA's registers as needed for the next line. This process continues down the screen. This is made more difficult because the MOS Technology 6507 in the 2600 is a pin-reduced version of the 6502 with no support for hardware interrupts. Generally the analog side of the display system generates an interrupt when it finishes drawing a raster line and is getting ready for the next one. The interrupt triggers the code needed to update the screen, and then returns to the "main" program. The 6507 left these pins off of the CPU to save money, however it does have a "RDY" pin to insert wait states into CPU bus cycles. The TIA was specifically designed to use the RDY pin to synchronize the CPU with the raster line timing of the video generated by the TIA: when the CPU writes to a certain register address of the TIA, the TIA lowers its RDY output signal until the beginning of the next line, a "wait for sync" command. This suspends the operation of the CPU until the start (color clock cycle 0) of the next line, providing a measure of automatic synchronization. The intended use of this mechanism is for the CPU to set up the TIA registers for the following line before the TIA reaches