up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controllers, multiple I/O-devices such as DUART, GPIO and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet, RapidIO or PCIe interfaces. The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications. P4080 – Includes eight e500mc cores, each with 32/32kB instruction/data L1 caches and a 128 kB L2 cache. The chip has dual 1 MB L3 caches, each connected to a 64-bit DDR2/DDR3 memory controller. The chip contains a security and encryption module, capable of packet parsing and classification, and acceleration of encryption and regexp pattern matching. The chip can be configured with up to eight Gigabit and two 10 Gigabit Ethernet controllers, three 5 GHz PCIe ports and two RapidIO interfaces. It also has various other peripheral connectivity such as two USB2 controllers. It is designed to operate below 30 W at 1.5 GHz. The processor is manufactured on a 45 nm SOI process and begun sampling to customers in August 2009. To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech to create a virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008. Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported 6WIND's packet processing software to the P4080. P5 The P5 series is based on the high performance 64-bit e5500 core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the CoreNet fabric. The P5 series processors share the same physical package and are also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID,