In computer science, false sharing is a performance-degrading usage pattern that can arise in systems with distributed, coherent caches at the size of the smallest resource block managed by the caching mechanism. When a system participant attempts to periodically access data that is not being altered by another party, but that data shares a cache block with data that is being altered, the caching protocol may force the first participant to reload the whole cache block despite a lack of logical necessity. The caching system is unaware of activity within this block and forces the first participant to bear the caching system overhead required by true shared access of a resource. Multiprocessor CPU caches By far the most common usage of this term is in modern multiprocessor CPU caches, where memory is cached in lines of some small power of two word size (e.g., 64 aligned, contiguous bytes). If two processors operate on independent data in the same memory address region storable in a single line, the cache coherency mechanisms in the system may force the whole line across the bus or interconnect with every data write, forcing memory stalls in addition to wasting system bandwidth. In some cases, the elimination of false sharing can result in order-of-magnitude performance improvements. False sharing is an inherent artifact of automatically synchronized cache protocols and can also exist in environments such as distributed file systems or databases, but current prevalence is limited to RAM caches. Example #include <iostream> #include <thread> #include <new> #include <atomic> #include <chrono> #include <latch> #include <vector> using namespace std; using namespace chrono; #if defined(__cpp_lib_hardware_interference_size) // default cacheline size from runtime constexpr size_t CL_SIZE = hardware_constructive_interference_size; #else // most common cacheline size otherwise constexpr size_t CL_SIZE = 64; #endif int main() { vector<jthread> threads; int hc = thread::hardware_concurrency(); for( int nThreads = 1; nThreads <= hc; ++nThreads ) { latch latSync( nThreads ); atomic_uint sync( nThreads ); // as much atomics as would fit into a cacheline struct { atomic_char atomics[CL_SIZE] alignas(CL_SIZE); } cacheLine; atomic_int64_t nsSum( 0 ); // sum of both thread execution times for( int t = 0; t != nThreads; ++t ) threads.emplace_back( [&]( atomic_char &a ) { latSync.arrive_and_wait(); // synch beginning of thread execution on kernel-level if( sync.fetch_sub( 1, memory_order::relaxed ) != 1 ) // fine-synch on user-level while( sync.load( memory_order::relaxed ) ); auto start = high_resolution_clock::now(); for( size_t r = 10'000'000; r--; ) a.fetch_add( 1,