memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards. In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC. A single-level cell (SLC) flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles. A single-level cell represents a 1 when almost empty and a 0 when almost full. There is a region of uncertainty (a read margin) between the two possible states at which the data stored in the cell cannot be precisely read. Multi-level cell The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate. The higher error rate necessitates an error-correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 flash controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read. The most commonly used algorithm is Bose–Chaudhuri–Hocquenghem (BCH code). Other drawbacks of MLC NAND are lower write speeds, lower number of program/erase cycles and higher power consumption compared to SLC flash memory. Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC. MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a flash file system, which is designed around the limitations of flash memory, such as using wear leveling to extend the useful lifetime of the flash device. The Intel 8087 used two-bits-per-cell technology for its microcode ROM, and in 1980 was one of the first devices on the market to use multi-level ROM cells. Intel later demonstrated 2-bit multi-level cell (MLC) NOR flash in 1997. NEC demonstrated quad-level cells in 1996, with a 64Mbit flash memory chip storing 2 bits per cell. In 1997, NEC demonstrated a dynamic random-access memory (DRAM) chip with quad-level cells, holding a capacity of 4Gbit. STMicroelectronics also demonstrated quad-level cells in 2000, with