Aldec, Inc. is a privately owned electronic design automation company based in Henderson, Nevada that provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. As a member of Accellera and IEEE Standards Association Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog). Aldec provides a hardware description language (HDL) simulation engine for other EDA tools such as Altium Designer and bundles special version of its tools with FPGA vendors software such as Lattice. History Aldec was founded in 1984 by Dr. Stanley M. Hyduke. In 1985 the company released its first product: MS-DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD. Sensing growing popularity of Microsoft Windows, ALDEC ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit. In 1996 Aldec signed agreement with Xilinx that allowed distribution of Xilinx-only version of Active-CAD under the Foundation name. While VHDL and Verilog were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and is still available (as of 2020). In 2000 ALDEC released high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms. In 2001 ALDEC added hardware to its product line: HES (Hardware Embedded Simulation) Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware. Year 2003 marks the release of Riviera-PRO supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage.) Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005. In 2006 Riviera-PRO was the first simulator supporting Open IP Encryption Initiative by Synplicity. Stimulated by requests from Verilog users, ALDEC released in 2007 an advanced, user-configurable lint tool implementing