matching networks require single chip packaging. Wafer-level packaging is implemented before wafer dicing, as shown in Fig. 3(a), and is based on anodic, metal diffusion, metal eutectic, glass frit, polymer adhesive, and silicon fusion wafer bonding. The selection of a wafer-level packaging technique is based on balancing the thermal expansion coefficients of the material layers of the RF MEMS component and those of the substrates to minimize the wafer bow and the residual stress, as well as on alignment and hermeticity requirements. Figures of merit for wafer-level packaging techniques are chip size, hermeticity, processing temperature, (in)tolerance to alignment errors and surface roughness. Anodic and silicon fusion bonding do not require an intermediate layer, but do not tolerate surface roughness. Wafer-level packaging techniques based on a bonding technique with a conductive intermediate layer (conductive split ring) restrict the bandwidth and isolation of the RF MEMS component. The most common wafer-level packaging techniques are based on anodic and glass frit wafer bonding. Wafer-level packaging techniques, enhanced with vertical interconnects, offer the opportunity of three-dimensional integration. Single-chip packaging, as shown in Fig. 3(b), is implemented after wafer dicing, using pre-fabricated ceramic or organic packages, such as LCP injection molded packages or LTCC packages. Pre-fabricated packages require hermetic cavity sealing through clogging, shedding, soldering or welding. Figures of merit for single-chip packaging techniques are chip size, hermeticity, and processing temperature. Microfabrication An RF MEMS fabrication process is based on surface micromachining techniques, and allows for integration of SiCr or TaN thin film resistors (TFR), metal-air-metal (MAM) capacitors, metal-insulator-metal (MIM) capacitors, and RF MEMS components. An RF MEMS fabrication process can be realized on a variety of wafers: III-V compound semi-insulating, borosilicate glass, fused silica (quartz), LCP, sapphire, and passivated silicon wafers. As shown in Fig. 4, RF MEMS components can be fabricated in class 100 clean rooms using 6 to 8 optical lithography steps with a 5 μm contact alignment error, whereas state-of-the-art MMIC and RFIC fabrication processes require 13 to 25 lithography steps. As outlined in Fig. 4, the essential microfabrication steps are: Deposition of the bias lines (Fig. 4, step 1) Deposition of the electrode layer (Fig. 4, step 2) Deposition of the dielectric layer (Fig. 4, step 3) Deposition of the sacrificial spacer (Fig. 4, step 4) Deposition of seed layer and subsequent electroplating (Fig. 4, step 5) Beam patterning, release and critical point drying (Fig. 4, step 6) With the