rules created by STARC - Japanese consortium of major silicon vendors. In 2008, releases ALINT: Design Rule Checker (STARC – Japanese Consortium of 11 ASIC Companies) 2010, releases Support for VHDL IEEE 1076-2008. In 2010, Aldec's Active-HDL wins Best FPGA Design & Simulation Tool in China In 2011, Aldec delivers UVM 1.0, OVM 2.1.2 & VMM 1.1.1a Support, releases 4 MHz Design Emulator, and wins Best FPGA Design & Verification Platform Provider in China. In 2012, Aldec enters SoC/ASIC Prototyping Market with HES-7 and jointly launches OSVVM, VHDL Verification. In 2013, Aldec releases Spec-TRACER Requirements Lifecycle Management In 2015, Aldec Releases ALINT-PRO with CDC Verification. In 2016, Aldec releases TySOM Product Line for Embedded Development using SoC FPGAs In 2020, Releases Support for VHDL IEEE 1076-2019. Products Software Active-HDL - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Special versions of the software that support just one FPGA vendor are available, e.g. Active-HDL Lattice Edition. Only available on MS Windows platform. Riviera-PRO - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera-PRO extends Active-HDL's simulation features with support for advanced verification methodologies such as linting, functional coverage, OVM and UVM, hardware acceleration, and prototyping. Riviera-PRO is a new generation of the tool known as Riviera-Classic and is available in 32-bit and 64-bit on MS Windows and Linux. HES-DVM - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design and hardware/software co-simulation (useful in Embedded System development). ALINT-PRO - single framework for design rule checker/linting and CDC analysis. ALINT-PRO is able to conduct extensive textual analysis of individual Verilog, VHDL and SystemVerilog design sources and advanced checks of the entire design hierarchy. Multiple sets of highly configurable, predefined rules are available and new, custom rules can be created using provided API. Built-in Phase-Based Linting methodology allows faster, more efficient checking of rules. ALINT-PRO smoothly supports running the rule checks for designs that target FPGA implementation using Xilinx, Intel, Microsemi, and Lattice technologies with minimal setup Spec-TRACER - unified requirements life-cycle management application designed specifically for FPGA and ASIC designs. Facilitates requirements capture, management, analysis, traceability and reporting; integrates with Windows-based HDL design and simulation tools.