The Xbox 360 technical specifications describe the various components of the Xbox 360 video game console. The console features a port on the top when vertical (left side when horizontal) to which a custom-housed hard disk drive unit can be attached in sizes of either 20, 60, 120, 250, 320, 500 GB; and as of April 2015 all 2.5" SATA Hard Drives up to 2 TB, the user can use the format option from system settings to utilize the new HDD. Inside, the Xbox 360 uses the triple-core IBM designed Xenon as its CPU, with each core capable of simultaneously processing two threads, and can therefore operate on up to six threads at once. Graphics processing is handled by the ATI Xenos, which has 10 MB of eDRAM. Its main memory pool is 512 MB in size. Central processing unit Xbox 360 took a different approach to hardware compared to its predecessor. The XCPU, named Xenon at Microsoft and "Waternoose" at IBM, is a custom triple-core 64-bit PowerPC-based design by IBM. The CPU emphasized high floating point performance through multiple FPU and SIMD vector processors in each core. The SIMD vector processor (VMX128) was modified for the Xbox to include a dot-product instruction. The dot-product instruction took far less latency than discrete instructions. The VMX128 was also modified by the addition of direct 3D (D3D) compressed data format. This led to an approximate 50 percent savings in required band-width and memory footprint making the CPU having a theoretical peak performance of 115.2 GFLOPS, being capable of 9.6 billion dot products per second. Each core of the CPU was capable of simultaneous multithreading and was clocked at 3.2 GHz. However, to reduce CPU die size, complexity, cost, and power demands, the processor used in-order execution in contrast to the Intel Coppermine 128-based Pentium III used in the original Xbox, which used more complex out-of-order execution. The original chip used a 90 nm process, although a newer 65 nm process SOI revision was implemented on later models, which was in-turn superseded by a 45 nm combined CPU and GPU chip. A 21.6 GB/s front side bus, aggregated 10.8 GB/s upstream and downstream, connected Xenon with the graphics processor/northbridge. Xenon was equipped with an 8th way set associative 1 MB Level 2 cache on-die running at half CPU clock speed. This cache was shared amongst the three CPU cores. Each core had separate