takes as an input a schematic diagram and the extracted view from a layout. It then generates a netlist from each one and compares them. Nodes, ports, and device sizing are all compared. If they are the same, LVS passes and the designer can continue. LVS tends to consider transistor fingers to be the same as an extra-wide transistor. Thus, 4 transistors (each 1 μm wide) in parallel, a 4-finger 1 μm transistor, or a 4 μm transistor are viewed the same by the LVS tool. The functionality of .lib files will be taken from SPICE models and added as an attribute to the .lib file. Other cell-based methodologies "Standard cell" falls into a more general class of design automation flows called cell-based design. Structured ASICs, FPGAs, and CPLDs are variations on cell-based design. From the designer's standpoint, all share the same input front end: an RTL description of the design. The three techniques, however, differ substantially in the details of the SPR flow (Synthesize, Place-and-Route) and physical implementation. Complexity measure For digital standard-cell designs, for instance in CMOS, a common technology-independent metric for complexity measure is gate equivalents (GE). See also Integrated Circuits Circuit Design Semiconductor Very-large-scale integration (VLSI) References External links VLSI Technology— This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design Oklahoma State University— This site contains support material for a complete System on Chip standard cell library that utilizes public-domain and Mentor Graphics/Synopsys/Cadence Design System tools The standard cell areas in a CBIC are built-up of rows of standard cells, like a wall built-up of bricks Virginia Tech— This is a standard-cell library developed by the Virginia Technology VLSI for Telecommunications (VTVT) Electronic design automation Logic gates